TW476145B - Chip scale stack package and method of fabricating the same - Google Patents
Chip scale stack package and method of fabricating the same Download PDFInfo
- Publication number
- TW476145B TW476145B TW089112571A TW89112571A TW476145B TW 476145 B TW476145 B TW 476145B TW 089112571 A TW089112571 A TW 089112571A TW 89112571 A TW89112571 A TW 89112571A TW 476145 B TW476145 B TW 476145B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor wafer
- metal
- wafer
- insulating layer
- patent application
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 117
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims abstract description 79
- 239000000853 adhesive Substances 0.000 claims abstract description 13
- 230000001070 adhesive effect Effects 0.000 claims abstract description 13
- 235000012431 wafers Nutrition 0.000 claims description 135
- 238000000034 method Methods 0.000 claims description 41
- 238000005538 encapsulation Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 7
- 238000007906 compression Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000005520 cutting process Methods 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 abstract description 4
- 238000007789 sealing Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 37
- 239000010931 gold Substances 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
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Description
476145 五、發明說明(1) 鳘jm <發明之領域> 本發明之發明領域係有關於晶片層疊封裝結構及製造 §亥晶片層疊封裝結構的方法,尤其是本發明與一封裝結構 相關,其中至少層疊兩個半導體晶片以完成一大小實際上 對應該傳統半導體晶片之尺寸,及製造該晶片層疊的方 法。 <相關技術之說明> 今日,由於記憶體晶片的容量增加率正快速成長。在 這一方面,128M PRAM已大量生產,而在未來256M的DRAM 也大將大量生產。 用於增加記憶體晶片的方法中包含如高度整合,在半 導體裝置的設定區域中裝入更多的晶胞等已在習知技術中 提出。但是,發展出此項技術必需相當長的時間,而且該 技術需要高的精確度以形成所需要的線寬等。為了符合這 些問題’最近以粗略發展出該層疊技術,應用技術可以相 當簡單的方式實現高度整合。 π層疊”一詞使用在半導體工業中意指經由在垂直方向 加熱至少兩半導體’而使得半導體晶片的容量增加兩倍。 經由層疊技術’例如,可由兩個64M DRAM裝置架構一 1 2 8M的DRAM裝置,或者是由兩個128M的⑽―裝置架構 出一 256M 的 DRAM。 在基本上的層疊封裝結構之例子中(其中使用層疊技 術生產者)’使用將架線架的内導線連結到定位結合墊片
476145 案號 89Π2571 修— 五、發明說明( 之^上表面 線,由包 片的側邊 在依 有相同結 其他導線 因此影響 但是 裝結構厚 的外導線 長。而且 合,由於 為了 第1圖中 上半導體 使得其表 下'導_線.架 2a的夕卜端 封體4鑄I 來。 而―且 點,此將 首先 產生裂縫 J:- 數 搞 兩 度 經 j 不 解 所 晶 面 結 的半導體晶片中。内導線經金屬線連接内導 體鑄模該整個結構,其方式為使得在半導體晶 個出導線架的外導線。 上述方式結構的封裝結構中,必需層疊另一具 的封裝結構。另言之,向上定位的封裝結構的 合到向下定位之封裝結構導線架的中間部位, 封.裝結構之間的電連結。 習知技術的層疊封裝結構必需承受整個層疊封 增加的缺點。但是因為信號必需從上封裝結構 下封裝結構的導線架,導致信號傳送路徑過 由於上及下封裝結構的導線經由焊接彼此耦. 適當的焊接將導致不良的連結。 決這些缺點,提出另一項的層疊封裝結構,如 示者。參見第1圖,形成表面具有結合墊片的 片la及下半導體晶片lb,配置這些半導體晶片 在一段預定的距離處彼此相對。上導線架2 a及 由金屬線3彼此相連結。另一方面,上導線架 合下導線架2 b的中間部位。所得到的結構由包 >其方式可使得下導線架2b的外線架曝露出 ,第1圖所示之傳統層疊封裝結構仍會有 於下文中加以說明。 一信號傳送路徑縮短,如果在一半 則必需將兩半導體晶片同時去除。
項缺 體晶 片中
476145 案號 89112571 "月 > 日 修正 .乂—— 五、發明說明(3) 而且,由於定位對應的導線架,使得彼此相對,可由 於在兩導線架之-間的容差而增加缺陷比率。而且5因為使 用错射將兩丰#體晶片結合社一·起·’所以焦要維修作滅° 而且,當記憶體晶片的尺寸改變時,由於包封體鑄模對應 的半導體晶片,當驅動上及下導線架時,必需有效地散 熱。即是說,因為無法足夠地安裝熱沉,所以散熱程度有 限。 另外,因為對應的因為對應的半導體晶片完全由包封 體鑄模,當驅動上下半導體晶片時無法有效散熱,及因為 無法足量的安裝熱沉,所以散熱度不夠。 <發明之總論> 因此,本發明的目的係在於解決上述習知技術中所產 生的問題,而且本發明的另一目的為提供晶片層疊封裝結 構,其可防止產生信號干擾,且縮短信號傳送路徑,而不 會增加整個厚度,本發明也包含製造該晶片層疊封裝結構 的方法。 本發明的另一〜目的為提供一種晶片層疊封裝結構,其 中在層疊之半導體晶片之間的電信號連結可經一簡單的程 序實現,而不必使用高成本的雷射裝置,及製造該晶片層 疊封裝結構的方法。 本發明的另一目的為提供一晶片層疊封裝結構,其中 對應的半導體晶片彼此互相耦合,其方式可令彼此可以簡 單的方式分開,而且有可能最大晶片層疊封裝結構在只有 一半導體晶片有裂紋時即將整個結構全部去除的缺點,本 476145 五、發明說明(4) 發明尚相關於製造該晶片層疊封裝結 、 本發明尚有一目的為提供曰^ 田、方法 得熱沉連接到-板上,在此可改日;:=結構,其可使 關於製造該晶月層疊封裝結構的方=了特性,本發明尚相 為了達到上述說明的目的,依撼 裝結構的方法為: 依據本發明之晶片層疊封 本發明係相關於一種半導I#曰y昆田 造方法。配置兩半導/曰Γ ::片層豐封裝結構及其製 I 冷日日片,使得這些半導俨曰士人 墊片形成表面互相相對。在絕緣層作用到;片二 合墊片形成表面上,且在絕緣声 旦日日片的、,、口 1=1中ΐ層之兩側邊曝露出來的金屬軌線係 位在3亥牙孔中,因此可將絕緣層互相結合在一 軌線也彼此連結。金屬線的一端連接曝露在絕緣層處= 屬軌線丄=由包封體鑄模半導體晶片的兩側邊,使得金 線的另一端曝露出來。 ' 、 > f ^ ^面不使用金屬軌線的話也可以使用圖樣帶。者 絕緣層彼此互相結合時,圖樣帶的-端電性連接到:屬; 導電黏著劑介接在該半導體晶片之間。可將一U2 上半導體晶片的一表面上。 /儿作用在 下:上述說明之晶片層疊封裝結構的製造方法現在說明於 在將、%緣層作用在具有多個半導體晶片之晶圓的表 m 第8頁 476145 五、發明說明(5) 面伋、’經由蝕刻絕緣層,可曝露出各半導體晶片的 片。連接到結合墊片的金屬軌線在絕緣層上形成。 經由沿標記線切割晶圓後,該晶圓分成對應的半導 片此後,兩半導體晶片的絕緣層進行熱壓縮。因 的金屬執線層彼此電性連結。外側連結端子的一端 軌線,=連接後,由一包封體將對應半導體晶片之 尺寸鑄模,其方式可令外側連結端子的其他端曝露 如果該連接中,該外侧連結端子包含金屬線, 對應的絕緣層彼此結合在一起時,金屬線的一端連 軌線的某些部位,丨該部位係曝露在絕緣層的側邊者 側連結端包含圖樣代時,使用金屬執線之間的附著 圖樣帶的端邊。使用包封體結合半導體晶片兩側邊 體晶片之間的空間。在執行鑄模程序之前,可在對 導體晶片之間介接一ACA。另一方面,可將一熱沉與 半導體晶片之一表面。 應用本發明的特徵,因為使用金屬軌線,而非 架,可使得信號干擾達到最小。由於不使用導線架 要使用高昂的雷射裝置以連接導線架。而且,由於 在層疊之半導體晶片的侧邊去除包封體,而使得口 之半導體晶片的側邊進行包封體鑄模,所以層聶/半 片彼此之間可加以分開。而且,當曝露出各^飓 表面時’有可能將〆熱’/冗、纟σ合到該表面。 一 由下文中的說明町更進一步了解本發明 點,閱Ί買時並請參考附圖 、 結合墊 然後, 體晶 此對應 與金屬 〜 兩晶片 出來。 首先, 接金屬 。當外I· 劑結合 及半導 應的半 ^合上 導線 ,不需 只經由 有層疊 導體晶 晶片的 及優 476145 五、發明說明(6) <較佳具體實施例之詳細描述> 下文說明較佳實施例,其例子顯示在附圖中。可能的 j ’各附圖中相同的標示表示相同的組件。 施例 第2圖至第22圖表不依據本發明第—之 封裝結構的製造程序。 /1 ^《且 此曰:ί,如第2圖所示,晶圓10具有多個半導體晶片, 圓士置於-轉台上。然後,如第3圖中所示者,當轉動 :^ ’經由轉動方式而將-絕緣材料塗佈在晶圓i 〇上, 了一具有預定厚度的絕緣層2〇作用在晶圓1〇的表面上, 如第4圖中所示者。 露出ΐί執:H圖所示,經由蚀刻絕緣層2°,而形成曝 金^ 。然後,在絕緣層2°上由上圖樣 金屬層,而况積该金屬層。第6圖之平面圖 3〇的結構。在第6圖中,將金屬軌線連接到結合塾 β 上。此時,在絕緣層20的中心部位,—部份的金 有去除而是留了下來。留在絕緣層20之中心部位上=^ 層之部位31用於提供電源或接地。 金屬 接同一結合墊片i!,此έ士人埶y ^ m蜀層甲邊下的部位連 用。s二 」 合塾片也用於提供電力或接地之 面,弟7圖為沿第6圖所示之截面圖,复中顯-J屬軌線30連接到用於電發信目的的:8、不 所示的1截面圖,其中顯示金二中 =片的=位31,此部位連接用於提供電力及接地之用二結
476145 ————— 案號 89112571 々年"月 > 日 修正 五、發明說明(7) N時,最好,架構上沒有單層外鄺,而是為Λ 1 / N i / A u 三層的結構。鋁(A 1 )與作為結合墊片1 1之材料的厚度直接 接觸,且以鎳(N 1 )作為防擴散層,可防止鋁及金互相反 應。金(Au)在往後的程序中將快速擴散,因此,可得到可 靠的結合。另一方面,最好沉積厚度分別為5 0 0 0埃,2 0 0 0 埃及5 0 0 0埃的銘,鎳及金,尤其是,金屬執線3 0的整個厚 度必需控制在10,000〜20,000埃之間。而且,可不使用上 述說明的材料及三層結構,在下列材料中選擇本發明的金 屬執線30,其包含Al/Ni/Al、A1/Pd/Al、Α1/Ρΐ/Αιι、 Al/Cu/Ni/Cr/Au、A1/Cli/Ni/Co/Au、A1/Ni/Au/Sn、 A—1/Ni/Cr/Au/Sn 、及Al/Co/Au/Sn 。 此時,沿線切割晶圓1 0,而將晶圓分為對應的半導體 晶片,如兩個半導體晶片4 0、41。其次,執行用於結合兩 個半導體晶片4 0及4 1。 可應用兩種不同的方法執行該結合程序。 在第一線方法中,如第1 1圖所示,使用一電漿清潔對 應之半導體晶片40、41的金屬軌線30,由此,由金製造之 金屬執線3 0的表面將活化。在此狀態下,如第9圖中所示 者,上半導體晶片40翻轉,且置於下半導體晶片41之上。 金屬轨線3 0之動作表面則必需如第1 2圖所示進行結合。最 後,兩金屬軌線3 0完全彼此互相結合。如第1 0圖中所示 者,絕緣層2 0也可以彼此互相結合。此後,必需硬固化整 個所得到的結構以固定結合邊界面。最好熱處理為3 0 0
476145 五、發明說明(8) 第二種方法中該絕緣層無法軟固化。在此第二種方法 中,在絕緣層黏著劑5 0經由熱壓縮而作用在絕緣層2 0之間 去除在黏著劑5 0中的氣泡,且將金屬軌線3 〇彼此結合。此 後’由固化整個所得到的結構,由黏著劑5 〇而將上半導體 晶片40及下半導體晶片4 1彼此互相結合。 當假設使用第一種方法時,對應之半導體晶片4 〇及4 1 的兩側,將一者層疊在另一者上方,且使用接地工具予以 接地,在此從絕緣層20中曝露出金屬軌線3〇。然後,如第 1 7圖中所示者金屬軌線3 0中的曝露部位進行細钱刻,且 然後周期存在金屬軌線3 〇之曝露部位上的外來物質。否 則’如第1 8圖中所示者,在接地工具6 〇處,可進行一接地 操作,而使得接地劑射入在對應半導體晶片4〇及41兩侧上 的噴嘴7 0。 、此後,如第1 9圖中所示者,金屬線80的一端作為外側 連結编子,且打線到金屬軌線3 〇的曝露部位。然後,如第 2〇圖中所示者,在將整個所得到的結構豎立後,將夾具㈣ 與上半導體晶片40及下半導體晶片41的表面接觸後,將包 ,肢100作用在上半導體晶片4〇及下半導體晶片41之間。 3,如第22圖所示,經由去除該夾具90,包封體100仍 /、、上半導體晶片40及下半導體晶片41的兩側邊,其中該 ,半導體晶片上下層疊,而且彼此結合在一起。結果,上 :,體晶片40的上表面及下半導體晶片41的下表面仍曝露 Λ此日^ ’金屬線8 0曝露到將安裝到板上之包封體1 〇 〇
476145 五、發明說明(9) 差_二實施例 第2 3圖表示依據本發明第二择 寸層疊封裝結構的截面視圖,且/24 1之半導體晶片尺 例中使用之圖樣帶的平面圖。 θ ·'、;本發明第二實施 圖樣帶110作為外侧連結端子,i 屬圖樣可配置在絕緣層上,此為習知拮、2恶足以使得金 依據此方式配置圖樣帶110,此圖樣帶:^知—者^因為 一般與金屬線80相結合,必需採用另一種方法貫施例 最重要的是,如第24圖中所示者,脸〇 應金屬圖樣由連結膠帶固定且彼此互相連:樣上的〜 =樣邊係定…^ 30之間,其方式為應用一熱壓縮處理,使得金 圖樣帶110的金屬圖樣彼此電連接。為了簡化與金屬、7軌 30之間的電連結,最好將圖樣帶丨〇 〇的金屬圖樣部位鍍、〃 金。 又 同時,當配置熱壓縮處理時,在絕緣層2〇之間產生一 空間。在此裝態下,使用包封體1 0 〇,而將絕緣層2 〇之 所產生的空間及上半導體晶片40,下半導體晶片41的兩3侧 邊鑄模,只曝露出圖樣帶1 〇 0的其他端邊。
在依據本發明第二實施例的方法中,因為沒有使用金 屬線,所以可省略打線的處理步驟,且可將作為外侧連纤 端子的圖樣帶100在半導體晶片40、41彼此互相結合時, 結合到金屬軌線30中。 第三實施例
476145 五、發明說明(1〇) 曰曰 卿曰第2 5圖之截面視圖顯示依據本發明第三實施例的半導 體^片尺寸層疊封裝結構。如第25圖中所示者,此實施例 的結構與第二實施例的結構類似,其中均使用圖樣帶 1曰1 〇 ’而與第二實施例不同的是在本實施例中當上半導責 曰曰片4 〇及下半導體晶片4 1彼此結合在一起時,在半導體 片4 0、4 1之間灌入非等向導電黏著劑(ACA)丄2 〇。 即在絕緣層2 0之間灌入ac A 1 2 0,且在絕緣層3 〇之間 置入圖樣帶1 〇 〇的一端。在此狀態下,經由固化整個所尸 到的結構,圖樣帶110的金屬圖樣可經ACA 12〇電連接于 軌線120,其中該ACA由一導電材料製造。依據此方式,其 如上文中所說明為可應用機械連接將半導體晶片4〇、U ς 此相結合,而且同時,可電單一的程序,而使得兩半^ 晶片彼此電連接。 —版 名四貫絲例 m 曰第26圖之截面視圖示依據本發明第四實施例的半 :二尺寸層疊封裝結構。士σ第26圖中所示者,此實施例= =構同於第一實施例中的結構,唯將一上表面具有一作出 部位,一下壓任何的熱沉連接到40的上表面上了而且^欣 二及第三實施例中,因為上半導體晶片弟 來,可將-熱沉連接到其上方。 上表面曝露出 如上所述,依據本發明,此實施例的優 互相層疊的上半導體晶片及下半導體晶片的結 經由金屬軌線介接而連接到外侧連結端子, 一 的傳遞路徑,而且,由於使用金屬軌線之故,q 日日方的干擾
476145
五、發明說明(11) 達到最小。 而且,因為不使用導線架’所以有可能使用簡單的執 塵細私序層豐半導體晶片而不需要成本高昂的雷射設“、、 而且,因為包封體只在層疊之半導體晶片的兩側鐘 模,當在經由在側邊去除包封體,而只在一半導體晶片轉 產生裂紋時,可去除將具有裂紋之半導體晶片。版日日 中 而且,由於曝露出各半導體晶片的表面,可去除散埶 特性,且可該熱沉連接到該曝露的表面上。 、“、、 f外,經由由包封體鑄模對應之半導體晶片的侧邊, 有可月b防止 '屋氣彳笔層疊的封裝體中洩漏出去。 者需佳實施例說明本發明,但嫺熟本技術 明沾ίϊί 貫施例加以更改及變更,而不偏離本發 、;、月神及觀點。其中上述的說明係用於說明本發明, Θ限制本@日月’本發明係由下文的中請專利範圍所限制。 476145 圖式簡單說明 第1圖示傳統層疊封裝結構之截面圖。 第2圖至第2 2圖以規則的方式顯示依據本發明第一實 施例一晶片尺寸層疊封裝結構的製造程序。 第2 3圖之截面圖表示依據本發明第二實施例之晶片尺 寸層疊封裝結構的截面圖。 第24圖之平面圖表示在本發明第二實施例的圖樣帶; 第2 5圖之截面圖表示依據本發明第三實施例之晶片層 疊封裝結構的截面圖。 第2 6圖表示依據本發明第四實施例之晶片層疊封裝結 構的截面圖。 圖式中元件名稱與符號 10 :晶圓 I 0 0 :包封體 11 :結合墊片 II 0 :圖樣帶 120 •金屬軌線 la 上 半 導 體片 lb 下 半 導 體片 20 絕 緣 層 2 a 上 導 線 架 2b 下 導 線 架 3 ·金屬線 3 0 :金屬軌線 31 :金屬層中留下的部位
第16頁 476145 圖式簡單說明 4 0、41 :半導體晶片 50 :黏著劑 6 0 :接地工具 7 0 :喷嘴 金屬線 80
Claims (1)
- 476145 ————…案號 89112571 特//月 > 日 修正 六、申請專利範圍 14 ·一種半導體晶片層疊封裝結構包含: 上半導體晶片及下半導體晶.片,各具有結合墊片形成 表面’此表面彼此相對;與 作用到上半導體晶片及下半導體晶片之結合墊片形成 表面上的數個絕緣層,各絕緣層上形成穿孔,以曝露出結 合墊片, 其特徵在於:絕緣層係彼此結合在一起,且此半導體 晶片層疊封裝結構更包括: 沉積在絕緣層之穿孔上的數個金屬執線,這些金屬執 線並電連接到結合墊片上; 一端連接到金屬軌線白勺數個夕卜側連結端子,以及 , 數個包封體,用於鑄模上半導體晶片及下半導體晶片 的側邊,其中該上半導體晶片及半導體晶片互相形成上下 之層疊,其方式可使該數個外侧連結端子的其他終端曝露 出來。 2. 如申請專利範圍第1項之+導體晶片層豐封裝結 構,其中該外側連結端子包含金屬線,此金屬線打線到曝 露在絕緣層側邊的金屬軌線上。 3. 如申請專利範圍第1項之半導體晶片層疊封裝結 構,其中該外侧連結端子包含直接連接到金屬軌線上的圖 樣帶。- 4. 如申請專利範圍第3項之半導體晶片層疊封裝結 構,其中一包封體或一不等向導電黏著劑灌入由絕緣層之 間形成的一空間中。 476145 一―——〜 tE 89112571 ..........._ 11 .....g 六、申請專利範圍 Ικ女〇申請專利範圍第1項或第2項或第3項或第4項中任 I 一項之半導體晶片層疊封裝結構,其中其中該熱沉連接到 上半導體晶片的表面上。 6.如申請專利範圍第1項之半導體晶片層疊封裝結 構,其中各金屬執線係從下列各項中選擇出來,包含 Al/Ni/Aii、A1/Pcl/Au、A1/I)t/Au、A 1 / C:u/N ι / Cu./Au、 Al/Cu/Ni/Co/Ai]、A1/Ni/Au/Sn、A1/Ni./Cu/Au/Sn、以及 A 1 / C o / A u / S η o7 · —種製造一半導體晶片層疊封裝結構的方法,該方 法具有下列步驟: 將一絕緣層作用到一晶圓的表面上,其中該晶圓具有 多個半導體晶片,蝕刻該絕緣層及因此曝露出各半導體晶 片的結合墊片, 其特徵在於:是種方法更包括下列步驟: 在絕緣層上沉積一金屬層,上圖樣該金屬層,且隨後 形成金屬軌線,其中該金屬軌線的一端連接曝露的結合墊 片,而其他端則向對應之絕緣層的邊緣延伸;沿一標記線切割該晶圓,因此將該晶圓分割成對應的 半導體晶片,且在絕緣層的側邊曝露出金屬執線的其他線 端; 將上半導體晶片及下半導體晶片彼此相互耦合,從該 晶圓中切下該半導體晶片,且因此使得金屬軌線彼此相連 結, 將金屬線之一端連結至已曝露出來的金屬執線的另一476145 ___________________—____________案號 89112571 __________V n ^ El —^ i^ji-__________________ 六、申請專利範圍 端;以及 使用一包封體,而鑄模彼此相耦合之丄及下半導體晶 片的側邊。其方式可使得金屬線的其他線端及上及下半導 體晶片的相對表面曝露出來。 8, 如申請專利範圍第7項之方法,其中該耦合的步驟 包含下列步驟: 軟固化上及下半導體晶片的絕緣層; 熱壓縮該絕緣層及該金屬軌線;以及 硬固化絕緣層。 9. 如申請專利範圍第8項之方法,其中在壓縮步驟 前,該耦合的步驟尚包含下列步驟: . 使用電漿清潔金屬執線,因此可活化該金屬執線。 1 0.如申請專利範圍第7項之方法,其中該耦合的步驟 包含下列步驟: 以黏著劑為介質而使得上及下半導體晶片的絕緣層相 結合;以及 固化該絕緣層及黏著劑。 1 1.如申請專利範圍第7項之方法,其中尚包含下列步 驟: 在分割晶圓成為對應的半導體晶片後,研磨對應的半 導體晶片之側邊。 1 2.如申請專利範圍第1 1項之方法,其中在研磨對應 半導體晶片的侧邊後’該力法尚ώ含步驟為. 執行該微細蝕刻程序,以去除存在金屬軌線之其他線476145 ————案E.…89112571 令?年7月夕日 修正 ^、申請專利範圍 端上的外在物質,其中該金屬轨線係曝露在絕緣層的側 邊。 1 3,如申請專利範圍第7項之方法,其中在研磨對應之< 半導體晶片的侧邊後,該方法尚包含步驟為: 將.熱沉連接到上半導體晶片的一表面上。 1. 4. 一種製造一半導體晶片層疊封裝結構的方法,該 方法具有下列步驟: 將一絕緣層作用到一晶圓的表面上,其中該晶圓具有 多個半導體晶片,蝕.刻該絕緣層及因此曝露出.各半導體晶 片的結合墊片; 其特徵在於:是種方法更包括下列步驟: , 在絕緣層上沉積一金屬軌線,上圖樣該金屬軌線,且 因此形成連接到該曝露之結合墊片上的金屬軌線上; 沿一標記線切割該晶圓; 熱壓縮該絕緣層及圖樣帶,其狀態為圖樣帶介接於從 晶圓切割下來之上半導體晶片及下半導體晶片的金屬執線 之間,因此電連接圖樣帶及金屬軌線的一端;以及 使用一包封體鑄模彼此相耦合之上半導體晶片及下半 導體晶片的側邊,及在絕緣層之間所形成的一空間,其方 式可使得圖樣帶的其他端的上及下半導體晶片的反向表面 曝露出來。 15.如申請專利範圍第14項之方法,其中在絕緣層之 間作用一不等向的導向黏著劑,執行一熱壓縮處理.,其狀 態為圖樣帶的一端***不等向導電黏著劑,且因此,圖樣 476145 —————案號 89112571 ..................如年,/ J__^:—曰— 修正 六、申請專利範圍 帶的其他端以不等向導電黏著劑作為介質而電性連接金屬 執線。 1 6。如申請專利範圍第1 4項之方法,其中在該步驟之 |後,該方法尚包含步驟為: 將一熱沉連接到上半導體晶片的一表面。
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- 2000-06-27 US US09/604,089 patent/US6589813B1/en not_active Expired - Fee Related
- 2000-06-27 TW TW089112571A patent/TW476145B/zh not_active IP Right Cessation
- 2000-06-28 JP JP2000195156A patent/JP4406497B2/ja not_active Expired - Fee Related
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2003
- 2003-04-28 US US10/423,872 patent/US6828686B2/en not_active Expired - Fee Related
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US11011418B2 (en) | 2005-08-11 | 2021-05-18 | Invensas Bonding Technologies, Inc. | 3D IC method and device |
US9716033B2 (en) | 2005-08-11 | 2017-07-25 | Ziptronix, Inc. | 3D IC method and device |
US11515202B2 (en) | 2005-08-11 | 2022-11-29 | Adeia Semiconductor Bonding Technologies Inc. | 3D IC method and device |
US10147641B2 (en) | 2005-08-11 | 2018-12-04 | Invensas Bonding Technologies, Inc. | 3D IC method and device |
US11289372B2 (en) | 2005-08-11 | 2022-03-29 | Invensas Bonding Technologies, Inc. | 3D IC method and device |
US11264345B2 (en) | 2015-08-25 | 2022-03-01 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US10262963B2 (en) | 2015-08-25 | 2019-04-16 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US11830838B2 (en) | 2015-08-25 | 2023-11-28 | Adeia Semiconductor Bonding Technologies Inc. | Conductive barrier direct hybrid bonding |
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US11552041B2 (en) | 2017-09-24 | 2023-01-10 | Adeia Semiconductor Bonding Technologies Inc. | Chemical mechanical polishing for hybrid bonding |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
US11804377B2 (en) | 2018-04-05 | 2023-10-31 | Adeia Semiconductor Bonding Technologies, Inc. | Method for preparing a surface for direct-bonding |
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US11728313B2 (en) | 2018-06-13 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Offset pads over TSV |
US11749645B2 (en) | 2018-06-13 | 2023-09-05 | Adeia Semiconductor Bonding Technologies Inc. | TSV as pad |
US11955445B2 (en) | 2018-06-13 | 2024-04-09 | Adeia Semiconductor Bonding Technologies Inc. | Metal pads over TSV |
US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
US11756880B2 (en) | 2018-10-22 | 2023-09-12 | Adeia Semiconductor Bonding Technologies Inc. | Interconnect structures |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
US11929347B2 (en) | 2020-10-20 | 2024-03-12 | Adeia Semiconductor Technologies Llc | Mixed exposure for large die |
Also Published As
Publication number | Publication date |
---|---|
US20030183945A1 (en) | 2003-10-02 |
KR100333384B1 (ko) | 2002-04-18 |
US6589813B1 (en) | 2003-07-08 |
KR20010004042A (ko) | 2001-01-15 |
US6828686B2 (en) | 2004-12-07 |
JP4406497B2 (ja) | 2010-01-27 |
JP2001035999A (ja) | 2001-02-09 |
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