TW440981B - Multiple line grids incorporating therein circuit elements - Google Patents
Multiple line grids incorporating therein circuit elements Download PDFInfo
- Publication number
- TW440981B TW440981B TW089103068A TW89103068A TW440981B TW 440981 B TW440981 B TW 440981B TW 089103068 A TW089103068 A TW 089103068A TW 89103068 A TW89103068 A TW 89103068A TW 440981 B TW440981 B TW 440981B
- Authority
- TW
- Taiwan
- Prior art keywords
- wire grid
- grid array
- item
- array package
- patent application
- Prior art date
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H05K1/00—Printed circuits
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- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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- H05K1/00—Printed circuits
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- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/10007—Types of components
- H05K2201/10045—Mounted network component having plural terminals
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- H—ELECTRICITY
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
經濟部智慧財產局員工消費合作社印製 v 4 4 Ο 9-β α 4 4 Π 9 8 11 Α7 -------Β7__ 五、發明說明(1 ) 發明領娀 本發明係有關積體電路封裝;且更特別地,係有關多 線柵陣列(MLGA)封裝,其於其間包含多線柵(MLGs),該 MLGs於其間併入諸如金屬線、電阻、感應器、電容器、 電晶艘或其等之混合之電路元件。 習知拮藜之描诫 現今於電子工業之最值得注意之設計趨熱之一係經由 電路元件之積體化及緻密化而其縮小化,被發展達成此目 的之此等技術之一者係表面置放技術(SMT),其係被作為 使1C元件置放於印刷電路板(pCBs)之成本有效率之方法。 數種使積體電路元件置放於電路板、晶片載體或其它組件 之不同技術係落於SMT之一般範疇。於此等技術中,區域 陣列(相對於周邊陣列)一般被用於以大程度之可靠性及製 造效率置放高I/O密度之封裝。區域陣列技術包含使用針 柵陣列(PGAs)、柱柵陣列(CGAs)及球柵陣列(BGAs)。最 近之BGA及CGA技術提供優於PGA方法之重大改良,其中 ,更高密度、可靠性及效率可對許多型式之封裝獲得之。 如其名稱所意含者’球栅陣列(BGAs)係使用電端子 之柵或陣列’如配置於1C封裝一側上之焊料球,以實現與 電路板之電接觸。陣列之焊料球於材料、尺寸(高度及寬 度)及間距(即,球與間之間隔)可依個別封裝而改變之。 此外’焊料球可以均勻或非均勻之陣列圖案排列,且某些 鉛可依所欲封裝性質而於某些區域内移除,其被稱為“去 集居(depopulation)’%焊料球典型上係使用鉛/錫最低鎔合 本紙張尺度適用中國國家標準(CNS)A4规格(210 * 297公爱) 4 j ,1. :^-------—訂---------線-W (請先«讀背面之注意事項再填寫本頁) A7 B7 五、發明說明(2) 金焊料球附接至板或模組,藉此,能無損及組件地移除及 修改。 (請先閱讀背面之注意Ϋ項再填寫本頁) 第1圖顯示倒裝片型之BGA封裝200於印刷電路板220 上之習知表面置放,其顯示焊料結合2〇3係形成於BGA之 球311及PCB220上之鉛202之間。 雖然上述BGA封裝於業界已成為具有高1/〇端子之半 導體元件之最普遍封裝另類方式之一者,但是,傳統之 BGA封裝係負坦數個問題,其間之一者係當1/〇密度增加 時’所需之焊料球之數量增加,其造成需使焊料球之尺寸 及其支撐物高度因而被降低,前者造成使適當之排列成行 變困難,且後者造成使其難以使晶片產生之熱被有效萃取 出。為減緩BGA封裝之上述問題,多線栅陣列(Mlga)封 裝已被引入’其被揭露於共同申請擁有之申請案美國序號 09/203,196號案(其名稱係“多線柵陣列封裝,,),其在此 被併入以供參考。 經氣部智·慧財產局員工消費合作社印製 但是’雖然最近於SMT之發展,縮小化之努力仍受諸 如電阻、電容器、感應器、電晶體或其等之混合之電路元 件(其一般係與1C元件一起被置於PCB上)之存在受阻。換 言之,若存在於PCB上之用以降低電路元件數目之方式可 被發現,則其能使進一步之縮小化變成可能。 基於降低存在於PCB上之電路元件之數目,其建議使 電路元件被包覆於封裝基材内(於BGA封裝之情況中)。但 是’於不具封包基材之倒裝片型之BGA封裝之情況中, 其上所述問題仍未被解決。 本紙張尺度適用中國國家標準(CNS>A4规格<210 * 297公釐) A7 經濟部智慧財產局員工消费合作社印製 44ο ^ ϋ ': 五'發明說明(3) 發明綜试 因此’本發明之主要目的係提供一種包含多線樹 (MLGs)之多線柵陣列(MLGA)封裝,該MLGs於其間併入 電路元件(例如,金屬線、電阻、電容器、感應器、電晶 體或其等之混合)。 依據本發明之方面,其提供一種多線柵陣列封裝包 含:包含一表面之半完成封裝,其巾第一金屬係形成 於該表面上用以連接數個輸入/輸出之端子;包含一上表 面之印刷電路板,其中第二金屬圖案係依據該第一金屬圊 案形成於該上表面上;及至少一多線柵,其係置於該半完 成封裝及該印刷電路板之間,其包含非導電體,其於其間 併入數電路元件及數個柱狀導體,每一導體係彼此呈電隔 離且被電連接至該電路元件、該第一及第二金屬圊案。 圖示簡要說明 本發明之上述及其它之目的及特徵由下述較佳實施例 及附圖之描述而變明顯,其中: 第1囷係傳統倒裝片型之球柵陣列封裝之透視圓; 第2圖顯示依據本發明之較佳實施例之置於印刷電路 板上之一種多線栅陣列封裝之載面圖; 第3圖描述依據本發明之第一較佳、實施例之多線栅之 一者之部份放大之載面圓; 第4圊例示依據本發明之第二較佳實施例之多線柵之 一者之部份放大之載面囷: 第5 A圖係ϋ從據本發明之第三較佳實施例之多線 本紙張尺度適用中國國家棵準(CNS)A4規格(210 x 297公釐)
,〕 ^--------It---------線,y. (請先閱讀背面之注意事項再填寫本頁) 6 AT B7 經 濟. 部 智 慧· 財 產 局 貝 工 消 费 合 作 社 印 製 五、發明說明(4 柵之一者之截面圊;且 第5B圊係第5A圖所示之多線柵之透視圖》 較佳實施例之詳細描述 於第2圖中,其提供依據本發明之較佳實施例之多線 柵陣列(MLGA)封裝100之截面圖,置於印刷電路板 (PCB)102上之MLGA封裝100包含含有數個線結合襯墊160 之1C組件170、具有數個導體116之多線柵(MLGs) 110之陣 列,及用以使1C組件170電連接至MLGs 110之陣列之藉由 堆疊數個基材層而形成之封裝基材。 封裝基材係非導電之基材,其提供上表面及下表面, 形成於下表面之第一圖案及形成於上表面之第二圖案。第 一及第二圖案係以使1C組件170之線結合襯墊160依據輸入 /輸出(I/O)端子設計被電連接至MLGs Π 0之陣列之方式設 計。 1C組件170被藉由於其間施用聚合黏著劑13〇(其於其 間包含銀於漿等)置於封裝基材之上部。金線140自1C組件 170之結合襯墊160以線結合至封裝基材120之第二圊案之 金屬化區域,以經由封裝基材120電連接MLGs 110陣列。 線結合之1C組件170以諸如模製化合物150之材料包覆以便 保護1C組件170免於不利環境之影響(諸如,濕氣等)。 於本發明之較佳實施例中,焊料淤漿124之第一圊案 依導體116之結構形成於封裝基材120之第一囷案上。焊料 淤漿124之第一圊案係藉由使用諸如篩網印刷之方法形成 。模製之1C組件170以使MLGs 110之導體116之端部與焊 本紙張尺度適用中國國家標準(CNS)A4规格(210 X 297公* ) — — — — — — — — — — — I— · I I ! — I— ,^ *111_111_ *;^ (請先閱讀背面之注意事項再填寫本頁) a7 ^ 4I\ 9 8 1_B7___ 五·、發明說明(5 ) 請 先 Μ 讀 背 S} 之 注 意 事 項 再 填 本 頁 料淤漿122之第二圖案排列校準之方式置於PCB 102上。 MLGs 110之導體116之端部經由使用焊料淤漿124之第一 圊案而電連接至封裝基材120之第一圖案。 於第3圖中’其描述依據本發明之一實施例之用於 MLGA封裝之MLG 110之部份放大載面圖。 MLG 110進一步包含柵體132,其係藉由層合數層狀 物112至115及諸如電阻117、金屬線118、電容及感應器Π9 之電路元件而於柵體132内積體化而形成。層狀物112至115 之每一者係由絕緣物料(諸如,陶瓷、聚合物、梦、陶曼 及聚合物之複合物等)形成。 於本發明之較佳實施例中,雖然電容器11丨係形成於 MLG 110之層112内,感應器119係形成於層1丨3至115内, 且電阻117及金属線118係形成於層Π5之頂部,但其可任 何形式之諸如電阻、金屬線、電容器、感應器或其等之混 合之電路元件可個別形成於層112至115内。 柱狀之導想116係由諸如焊料於聚之導趙物料製得, 且自栅體132之上表面及下表面向外突出,以便使封裝基 材120與PCB 102電連接。 經濟部智慧財產局員工消费合作社印製 參考第2圖’焊料淤漿之第二圖案以同於導體116之結 構於PCB 102上形成。焊料淤漿112之第二圊案係藉由使 用諸如筛網印刷之方法形成。 另外,於第4圊中’其顯示依據本發明之第二實施例 之MLG 410之部份放大之裁面圏。KMLG 410係相似於第 3圖所示之MLG 110,但柵體432被提供數個層412至415, 本紙張尺度適用中國國家榡準(CNS)A4規格(210 X 297公釐〉 經 濟. 部 智 慧’ 財 產 局 貝 工 消 費 合 社 印 製 A7 __B7___ 五、發明說明(6 ) 且於體上積體化之電路元件411,417, 418, 419係形成於主 體板430之頂部,且層狀物及主體板係由半導體(例如,石夕} 製得。 柱狀導體416係由諸如焊料淤漿之導體物料製得,且 自柵體432之上表面延伸至主體板430之下表面,以便使封 裝基材120與PCB 102電連接。 再者,於第5A及5B圖中,其顯示依據本發明第三較 佳實施例之MLG 510之部份放大截面围及第5A囷所示之 多線栅之透視圖。此MLG 510係相似於第3圓所示之MLG 110,但上層515被提供一組焊料雎塊530及一組金屬線518 ’以個別使每一焊料腫塊530與導體連接,如第5B圊所示 。於第三較佳實施例中,於上層515之頂部上形成之焊料 腫塊於尺寸上係不同於形成於導體516及較低層512上之焊 料腫塊517。再者’焊料腫塊530可以使其圊案不同於焊料 腫塊5 1 7之方式設計,以使其能與IC組件上之各種不同型 式之腫塊相容。此實施例於封裝IC組件(例如,倒裝片、 晶圓水平封裝等)係特別有利,其中IC上之腫塊係被置放 於周邊或同心置放之。 雖然本發明己以較佳實施例描述,但其它改質及改變 可於不偏離於下述申請專利範圍所述之本發明精神及範圍 下為之。 本紙張尺度適时關緖芈(CNS)A4规格咖x 297公8) 9 — — — — — — — — —---- 裝! — 訂·! 線 (請先閱讀背面之注意事項再填寫本頁) 4 4^0 -9-0-0 A7 4 40 98 1_b; 五、發明說明(7 ) 元件符號對照 100···多線柵陣列(MLGA) 封裝 102···印刷電路板(PCB) 110···多線柵(MLGs) 111···電容器 112至115·.·層狀物 116…導趙 117…電阻 118···金屬線 119···電容及感應器 120···封裝基材 122, 124…焊料淤漿 130···聚合黏著劑 132…栅體 140…金線 160···線結合襯塾 170…1C組件 410···多線柵(MLG) 411···電路元件 412至415…層狀物 416···柱狀導體 417, 418. 419…電路元件 430···主體板 432…樹想 510···多線柵(MLG) 512···較低層 515…上層 516…導體 517···焊料腫塊 518···金屬線 530…焊料腫塊 經濟部智慧財產局員工消費合作社印製 10 本紙張尺度適用中國國家標準(CNS>A4規格(210 * 297公;8 )
Claims (1)
- 440981 A8BSC8D8經濟部智慧財產局員工消費合作社印製1- 一種多線栅陣列其包含: 包含一表面#完成封裝體,其中第—金屬圖案 係形成於該表面上,用以連接數個輸入/輪出之端子· 包含一上表面之印刷電路板,其中第二金屬圊案 係依據該第一金屬圊案形成於該上表面上;及 至少一多線柵,其係置於該半完成封裝體及該印 刷電路板之間,其包含非導電體,其於其間併入數電 路元件及數個柱狀導體,每一導體係彼此呈電隔離且 被電連接至該電路元件、該第一及第二金屬圓案。 2_如申請專利範圍第】項之多線柵陣列封裝體其中該非 導體係藉由層合至少一層所形成。 3. 如申請專利範圍第2項之多線栅陣列封裝體其令該非 體層之每一者係個別具有至少一電路元件。 4. 如申請專利範圍第3項之多線柵陣列封裝體其中該電 路疋件係選自金屬線、電阻、電容器、感應器、電晶 趙或其等之混合。 5. 如申請專利範圍第4項之多線栅陣列封裝難,其中該非 導雜係由陶究、聚合物、石夕或陶究及聚合物之複合物 形成。 6’如申清專利範圍第5項之多線柵陣列封裝體其中該藉 由層狀物之層合而形成之該非導體進一步包含用以置 放該被層合之層狀物之模型趙。 7.如申请專利範圍第1項之多線柵陣列封裝體,其進一步 包含焊料之第一囷案$,其係形成於該半完成封裝體本紙張尺度刺中因困冢棵準(CNS>A4规g_<21G χ 297公着-jA8B8C8D8 ..^^-]—-- 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 之該第一金屬層與該多線柵之導體之端部之間。 8,如申請專利範圍第7項之多線柵陣列封裝體,其中該第 一圓案層係藉由篩網印刷方法形成。 9·如申請專利範圍第1項之多線柵陣列封裝體,其進一步 包含焊料之第二圊案層,其係形成於該印刷電路板之 該第二金屬圖案與該多線栅之該導體之另一端部。 10·如申請專利範圍第9項之多線柵陣列封裝體,其中該第 二圏案層係藉由篩網印刷方法形成。 11. 如申請專利範圍第1項之多線柵陣列封裝體,其中該半 完成封裝體包含封裝體本體,其係藉由層合數層狀物 及於該封裝體本體内積體化之積體電路組件而形成。 12. 如申請專利範圍第1項之多線柵陣列封裝體其中該多 線栅進一步包含第一組焊料腫塊及位於其上之金屬線 及位於其底部之第二組焊料腫塊,該第一組焊料腫塊 於尺寸上係不同於該第二組焊料腫塊。 13. 如申請專利範圍第12項之多線柵陣列封裝趙,其中該 第一組焊料腫塊之排列或圖案係不同於該第二組焊料 腫塊者》 14. 如申請專利範圍第13項之多線栅陣列封裝體其中該 半完成封裝體係倒裝片。 15. 如申請專利範圍第14項之多線柵陣列封裝體,其中該 半完成封裝體係晶圓水平封裝趙。 16. 如申清專利範圍第μ項之多線柵陣列封裝體,其中該 半成品化的封裝體進-步包含一具有多個線結合墊的 I--— — — — — — 111 — ·1111111 ^* — — — — — 1 — (請先閲讀背面之注意事項再填寫本頁)440981六、申請專利範圍 A8B8C8D8 c組與一具有一頂表面與一底表面的封裝基材該第 一金屬圊案係形成於該底表面’且該第二金屬圖案係 形成於該頂表面,該第一與該第二金屬圓案係被形成 ’而使得該1C組件的線結合墊係依據輸入/輸出端子設 計而電氣連接至該多線栅。 17.如申請專利範圍第16項之多線栅陣列封裝體,其中該 金線係自該IC組件的線結合塾線結合至該封裝基材之 第二金屬圖案之金屬化區域,以供經由該封裝基材電 氣連接該多線柵。 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4规格(210x297公釐) .^ (請先wtl背面之注意事項再填寫本頁)
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US09/451,450 US6320249B1 (en) | 1999-11-30 | 1999-11-30 | Multiple line grids incorporating therein circuit elements |
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US (1) | US6320249B1 (zh) |
EP (1) | EP1107312A2 (zh) |
JP (1) | JP3413147B2 (zh) |
TW (1) | TW440981B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030023125A (ko) * | 2001-09-12 | 2003-03-19 | 주식회사 글로텍 | 멀티플 라인 그리드를 이용한 반도체 패키지 |
US6900991B2 (en) * | 2001-12-03 | 2005-05-31 | Intel Corporation | Electronic assembly with sandwiched capacitors and methods of manufacture |
US6768650B2 (en) * | 2002-02-07 | 2004-07-27 | International Business Machines Corporation | Method and structure for reduction of impedance using decoupling capacitor |
JP2004119601A (ja) * | 2002-09-25 | 2004-04-15 | Fujitsu Ltd | 回路基板および電子機器 |
US20040125580A1 (en) * | 2002-12-31 | 2004-07-01 | Intel Corporation | Mounting capacitors under ball grid array |
US20050112842A1 (en) * | 2003-11-24 | 2005-05-26 | Kang Jung S. | Integrating passive components on spacer in stacked dies |
US7348661B2 (en) * | 2004-09-24 | 2008-03-25 | Intel Corporation | Array capacitor apparatuses to filter input/output signal |
US7553696B2 (en) * | 2006-08-29 | 2009-06-30 | International Business Machines Corporation | Method for implementing component placement suspended within grid array packages for enhanced electrical performance |
US9955582B2 (en) * | 2008-04-23 | 2018-04-24 | Skyworks Solutions, Inc. | 3-D stacking of active devices over passive devices |
US8530821B2 (en) | 2010-06-08 | 2013-09-10 | International Business Machines Corporation | Low distortion high bandwidth adaptive transmission line for integrated photonics applications |
US8723323B2 (en) * | 2012-07-12 | 2014-05-13 | Bae Systems Information And Electronic Systems Integration Inc. | Method for fabricating solder columns for a column grid array package |
DE202013011995U1 (de) * | 2013-01-22 | 2015-01-15 | Baumüller Nürnberg GmbH | Leiterplattenanordnung |
US9867295B2 (en) * | 2014-01-07 | 2018-01-09 | Dell Products L.P. | Ball grid array system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4803595A (en) * | 1986-11-17 | 1989-02-07 | International Business Machines Corporation | Interposer chip technique for making engineering changes between interconnected semiconductor chips |
US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
US6728113B1 (en) * | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
-
1999
- 1999-11-30 US US09/451,450 patent/US6320249B1/en not_active Expired - Fee Related
-
2000
- 2000-02-22 TW TW089103068A patent/TW440981B/zh active
- 2000-03-03 JP JP2000058865A patent/JP3413147B2/ja not_active Expired - Fee Related
- 2000-03-03 EP EP00104712A patent/EP1107312A2/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JP2001168233A (ja) | 2001-06-22 |
US6320249B1 (en) | 2001-11-20 |
EP1107312A2 (en) | 2001-06-13 |
JP3413147B2 (ja) | 2003-06-03 |
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