TW432873B - Photographing apparatus - Google Patents

Abstract

The present invention relates to a photographing apparatus in which the image information is stored in memory in the unit of each picture per unit after the photograph of object is taken, which comprises: a solid state photographing apparatus wherein a plurality of light receiving pixels is in column-row arrangement corresponding to specific color components, and the information charge of each light receiving pixel is stored independently according to each color component; the driving circuit to transfer the information charge of each light receiving pixel of the aforementioned solid state photographing apparatus to the output by the predetermined sequence to get the image signal; the signal processing circuit to generate the first till the third image data corresponding to the three primaries of light according to the aforementioned image signal; the digitizing circuit to digitize respectively the aforementioned first and the third image data to generate the first till the third digital data represented by one bit, and the control circuit which is connected to the memory to obtain the aforementioned first till third digital data in the aforementioned memory to read out and output the aforementioned first till third digital data stored in the aforementioned memory at the same time.

Description

^?873 ^ 五、發明說明（1) [發明所屬之技術領域] 本發明係關於以1畫面單位記憶攝取被攝體所得畫像 資料之攝像裝置。 [習用技術] 使用如CCD圖像感測器等固體攝像元件構成之靜態照 相機中’有内裝記憶卡或磁碟等記錄媒饉，將圖像資料記 錄在該等記錄媒體的構成。該時，為用較少容量之記錄媒 體能夠記憶更多畫像資料起見’有使用聯合照相專家組織 (以下簡稱為JPEG)演算法代表之各種數據壓縮技術。 第1圖係使用攝像元件之電子靜態照相機構成之方塊 圖，第2圖為說明該動作之時序圖。 攝像元件1係如CCD圖像感測器，包含有以行列配置之 複數移位暫存器。該複數個移位暫存器係對應於受光畫像 各列複數之垂直移位暫存器及配置於該複數個垂直移位暫 存器輸出側通常為一個的水平移位暫存器所構成。以行列 配置之複數個受光畫像安裝有以預定規則配列之三原色光 或該輔助色之濾色鏡，而且各受光像素則以其特定色成分 對應》驅動電路2係反應於後述CPU8之指令產生垂直轉送 時脈及水平轉送時脈，由該垂直轉送時脈及水平轉送時脈 以脈衝驅動攝像元件1。例如，依照排出時脈將全部受光 像素之情報電荷之暫時排出後，將經由預定期間L儲存攝 像元件1受光像素之情報電荷，以垂直轉送時脈由各受光 像素讀出於所對應之垂直移位暫存器*然後，由各垂 存器依行序轉送至其垂直方向，同時，亦以水平時脈以4^? 873 ^ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an imaging device that memorizes and captures image data obtained by a subject in units of one screen. [Conventional technology] A static camera using a solid-state imaging element such as a CCD image sensor is a structure in which a recording medium such as a built-in memory card or magnetic disk is used to record image data on these recording media. At this time, in order to be able to memorize more image data with a recording medium with a smaller capacity, various data compression techniques represented by the Joint Photographic Experts Organization (hereinafter referred to as JPEG) algorithm are available. Fig. 1 is a block diagram of an electronic still camera using an imaging element, and Fig. 2 is a timing chart illustrating the operation. The imaging element 1 is a CCD image sensor, and includes a plurality of shift registers arranged in rows and columns. The plurality of shift registers are composed of a plurality of vertical shift registers corresponding to each column of the received image and a horizontal shift register arranged on the output side of the plurality of vertical shift registers. A plurality of light-receiving images arranged in rows and columns are equipped with color filters of the three primary colors or the auxiliary colors arranged in a predetermined rule, and each light-receiving pixel corresponds to its specific color component. "Driver circuit 2 responds to the instructions of CPU8 described later when vertical transfer is generated. The clock and the horizontal transfer clock are used to drive the imaging element 1 by the vertical transfer clock and the horizontal transfer clock. For example, after the information charges of all light-receiving pixels are temporarily discharged in accordance with the discharge clock, the information charges of the light-receiving pixels of the imaging element 1 are stored through the predetermined period L, and the light-receiving pixels are read out at the corresponding vertical shifts in the vertical transfer clock. The bit register * is then transferred from each register to its vertical direction in sequence, and at the same time, the

C:\ProgramFiles\Pat_ent\310654.ptd 第 4 頁 4^873 五、發明說明（2) --- 二像素向水平方向轉送6因此，可從攝像元件1 ,輪出將 :畫面分之圖像情報以每行單位之連續躅像訊號\⑴輸 類比處理電路3係連接於攝影元件1，對從攝影元件^ 所輪入之圖像訊號Υβ⑴施以樣本持留’位準修正等之處 理，以產生所定形之圖像訊號Yi(t) ^ A/D變換電路4連接於 類比處理電路3，將從類比處理電路3輸入之圖像訊號、⑴ 以每一像素予以數位變換產生圖像資料Di(n) β數位處理^ 路5係連接於A/D變換電路4，對從A/d變換電路4輸入之圖 像資料施以色分離，色差矩陣等之處理，以產生含有 亮度資訊’色差資訊之圖像資料h⑷。 §己憶控制電路6係，連接於數位處理電路5及後述之幀 存儲器7，將從數位處理電路5輸入之圖像資料化⑴以畫 面，單位寫入幀存儲器7，同時，讀出記憶在幀存儲器7之 圖像資料匕⑷輸出。幀存儲器7具有可記憶適當數量畫面份 圏像資料D2⑷之容量，暫時記憶從記憶控制電路6寫入之圏 像資料D2⑷。 中央處理單位（以後簡稱為CPU )8根據控制程式控制各 部動作，同時，取進從記憶控制電路6輸出之圖像資料匕⑷ 實行壓縮處理β例如對軀動電路2即相應於攝像元件之曝 光狀態而設定資訊電荷之儲存時間，以適當電位獲得圖像 訊號Υ。⑴。又，對類比處理電路3及數位處理電路5即使各 處理時序同步於攝像元件1之動作，同時，設定各處理條 件。再者’對§己憶艘控制電路6，係於為施行塵縮處理之C: \ ProgramFiles \ Pat_ent \ 310654.ptd Page 4 ^ 873 V. Description of the invention (2) --- 2 pixels are transferred in the horizontal direction 6 Therefore, from the camera element 1, you can rotate out: the image divided by the screen The intelligence is connected to the photographic element 1 by the continuous image signal \ input analog processing circuit 3 of each line unit. The image signal 'β⑴ which is rotated from the photographic element ^ is subjected to sample hold' level correction, etc. Generates the shaped image signal Yi (t) ^ A / D conversion circuit 4 is connected to the analog processing circuit 3, and the image signal input from the analog processing circuit 3 is digitally transformed by each pixel to generate image data Di (n) β digital processing ^ The circuit 5 is connected to the A / D conversion circuit 4 and applies color separation, color difference matrix, etc. to the image data input from the A / d conversion circuit 4 to generate a color difference containing brightness information. Image data of information h⑷. § Jiyi control circuit 6 is connected to the digital processing circuit 5 and the frame memory 7 described later. The image data input from the digital processing circuit 5 is converted into frames and written into the frame memory 7 at the same time. The image data of the frame memory 7 is output. The frame memory 7 has a capacity capable of storing an appropriate number of frame image data D2, and temporarily stores the image data D2 '' written from the memory control circuit 6. A central processing unit (hereinafter simply referred to as a CPU) 8 controls the operations of various parts according to a control program, and simultaneously takes in image data output from the memory control circuit 6 and performs compression processing β, for example, exposure to the body circuit 2 corresponding to the imaging element State and set the storage time of the information charge to obtain the image signal at an appropriate potential. Alas. In addition, the analog processing circuit 3 and the digital processing circuit 5 set each processing condition at the same time, even if each processing timing is synchronized with the operation of the imaging element 1. Furthermore, the control circuit 6 for §Jiyi ship is for the purpose of performing the dust reduction process.

C:\PrograniFiles\Patent\310654.ptd 第 5 頁 ^aa873 ^ 五、發明說明（3) 各種演算時，其視其必要指示從幀存儲器7取進圖像資料 hoo。圖像資料記憶體9係連接於CPU8，在CPU8中記憶將固 像資料込⑴壓縮處理所成之壓縮資料C(n)。該圖像資料記憶 想9係使用例如不揮發型大容量快閃記憶體，可記錄複數 個畫面之壓縮資料C⑴。記憶於該圖像資料記憶體9之壓縮 資料C⑷於必要時讀出於CPU8，以壓縮資料C(n)之原狀，或 解凉·為圖像資料D2(n)後’向外部機器輪出。如述方式輸出 之壓縮資料C(n)或圖像資料D2⑴經與上述各處理相反之處理 後供給於顯示裝置及印字裴置》 於數位處理電路5產生之圖像資料〇2⑷通常具有對應於 A/D變換電路4構成之位元數，於取進圖像資料d2⑷之CPU8 也相應於其位元數構成輸入之介面及演算系統。因此，當 囷像資料h⑴之位元數增大時，CPU8之構成變為複雜，同 時’對圖像資料Dz⑷之各演算處理所需時間變長。同時， 就連接於CPU8之圖像資料記憶體9亦產生隨位元數增大而 須加大容量。因此，成為增加攝影褒置成本之原因。 [發明之概要] 本發明之目的’係在於提供一種簡化訊號處理系統， 以低成本可實現之攝像裝置者。 本發明之第1特徵係於攝取被攝體圈像，以每一畫面 單位記憶圖像資訊之攝像裝置中，具備：以行列配置對應 於特定色成分之複數個受光像素，在各受光像素依各色成 分獨立儲存的資訊電荷之固體攝像元件；將儲存於上述固 艘攝像元件之各受光像素之資訊電荷依序轉送輸出以獲得C: \ PrograniFiles \ Patent \ 310654.ptd Page 5 ^ aa873 ^ V. Description of the invention (3) During various calculations, it will take the image data hoo from the frame memory 7 according to its necessary instructions. The image data memory 9 is connected to the CPU 8, and the CPU 8 stores compressed data C (n) formed by compressing the fixed image data. The image data memory 9 uses a non-volatile large-capacity flash memory, which can record compressed data of multiple frames. The compressed data C stored in the image data memory 9 is read out to the CPU 8 as necessary, and the compressed data C (n) is in its original state, or it is released as an image data D2 (n). . The compressed data C (n) or image data D2 output as described above is supplied to the display device and the printing device after processing opposite to the above-mentioned processing. The image data generated by the digital processing circuit 5 usually has a value corresponding to The number of bits formed by the A / D conversion circuit 4 and the CPU 8 which takes in the image data d2⑷ also constitute an input interface and a calculation system corresponding to the number of bits. Therefore, as the number of bits of the image data h⑴ increases, the configuration of the CPU 8 becomes complicated, and at the same time, the time required for each calculation processing of the image data Dz⑷ becomes longer. At the same time, the image data memory 9 connected to the CPU 8 also needs to increase its capacity as the number of bits increases. Therefore, it becomes the cause of increasing the cost of photography installation. [Summary of the Invention] The object of the present invention is to provide a camera device that can simplify the signal processing system and can be realized at a low cost. A first feature of the present invention resides in an imaging device that captures a circle image of a subject and stores image information in each frame unit, and includes a plurality of light-receiving pixels corresponding to a specific color component arranged in rows and columns. The solid-state imaging element with information charges independently stored for each color component; the information charges of each light-receiving pixel stored in the solid-state imaging element are sequentially transferred and output to obtain

C:\ProgramFiles\Patent\310654.ptd 第 6 頁C: \ ProgramFiles \ Patent \ 310654.ptd page 6

432873432873

囷像訊號之驅動電故.& 三原色之第1至第3之蘭Ϊ上述圖像訊號，產生對應於先之 1至第3之\圖像資料之訊號處理電路；將上述第 於記憶體，以取進上;^位/=之二進位化電路，及連接 記憶體之同時，將記Λ 二進位資料記憶在上述 推讲隐在上述記憶體之上述第1至第3之二 進位資料予以讀出及輪出之控制電路者。 ώ夕if二從控制電路寫入記憶體可將二進位化電路產生 一進化資料。且在控制電路中不必施行壓縮處 理，故可大幅度簡化電路構成β 本發明之第2特徵係於攝取被攝體圖像，以每丨畫面單 位記憶圈像資訊之攝像裝置+ ’具備：以行列配置之複數 又光像素，及對各受先像素儲存資訊電荷之固體攝像元件 ’將储存在上述固體攝像元件各受光像素之資訊電荷依序 轉送輸出以獲得圖像訊號之驅動電路；根據上述圖像訊號 產生囷像資料之訊號處理電路；壓縮上述圖像資料以產生 壓縮資料之壓縮電路’及連接於記憶體以取進上述壓縮資 料記憶在上述記憶體之同時，讀出上述記憶體内之上述壓 縮資料予以輸出之控制電路，又，上述控制電路係相應於 上述壓縮資料對上述記憶艘之寫入速度設定上述驅動電路 之動作時序者。 因此，取進控制電路之圖像資料不須在途中記憶於幀 儲存器，變換成壓縮資料後’可由控制電路直接寫進記憶 體〇囷 The driving signal of the image signal. &Amp; The first to third colors of the three primary colors ΪThe above image signal generates a signal processing circuit corresponding to the first to the third image data; the above is stored in the memory ^ Bit / = binary binary circuit, and at the same time connected to the memory, memorize the Λ binary binary data in the above-mentioned deduction hidden in the above-mentioned first to third binary data Those who read and rotate the control circuit. If you write to the memory from the control circuit, the binary circuit can generate an evolutionary data. Furthermore, it is not necessary to perform compression processing in the control circuit, so the circuit configuration can be greatly simplified. The second feature of the present invention is the camera device that captures the subject image and stores the circle image information per unit of screen + 'It is equipped with: A plurality of light pixels arranged in rows and columns, and a solid-state imaging element that stores information charges to each of the preceding pixels. A driving circuit that sequentially transfers and outputs the information charges stored in the light-receiving pixels of the solid-state imaging element to obtain an image signal; A signal processing circuit for generating image data of image signals; a compression circuit for compressing the above-mentioned image data to generate compressed data; and a circuit connected to a memory to take the compressed data into the memory while reading out the memory The control circuit for outputting the compressed data, and the control circuit is to set the operation timing of the driving circuit corresponding to the write speed of the compressed data to the memory boat. Therefore, the image data taken into the control circuit does not need to be stored in the frame memory on the way, and after being converted into compressed data, it can be written directly into the memory by the control circuit.

繼87 3 五、發明說明（5^ ~ ' 本發明之第3之特徵係於攝取被攝體圖像，以每1畫面 單位取出圖像資訊之攝像裝置中，具備將光電變換產生之 資訊電荷分別以獨立儲存的複數個受光像素予以行列配 置’至少有一部分受光像素被遮光之固體择像元件；將儲 存於上述固艘攝像元件之各受光像素的資訊電荷依序轉送 輸出以獲得圖像訊號之驅動電路；依上述圖像訊號，產生 分別對應於上述複數個受光像素之圖像資料之訊號處理電 路；上述固體攝像元件之被遮光之上述一部分受光像素之 圖像資料產生高頻振動矩陣之矩陣產生電路，及參照上述 高頻振動矩陣將上述圖像資料予以二進位化之二進位化電 路者。 於是’相應攝像元件之動作狀況按各像素而任意變化 之暗電流成分做為高頻振動矩陣使用，故不須記憶大規模 高頻振動矩陣。 本發明之第4特徵係於攝取被攝體圏像，以每1畫面單 位取出圖像資訊之攝像裝置中，將光電變換產生之資訊電 荷分別以獨立儲存的複數之受光像素予以行列配置之同 時’對應於各受光像素以複數儲存像素幀轉送方式成行列 配置之固體攝像元件；將儲存於上述固體攝像元件各受光 像素之資訊電荷轉送至各垂直移位暫存器後，從各垂直移 位暫存器獲得依序轉送輸出圖像訊號之驅動電路；用以控 制從上述攝像元件各受光像素對各垂直移位暫存器轉送資 訊電荷之時序及自各垂直移位暫存器資訊電荷之轉送輸出 時序之時序控制電路；依上述圖像訊號，產生分別對應於Following 87 3 V. Description of the invention (5 ^ ~ 'The third feature of the present invention is that the imaging device that captures the image of the subject and fetches the image information every 1 frame unit has the information charge generated by photoelectric conversion. A plurality of light-receiving pixels stored separately are arranged in rows and columns' at least a part of the light-receiving pixels are blocked by a solid image selection element; the information charge of each light-receiving pixel stored in the solid-state image pickup element is sequentially transferred and output to obtain an image signal A driving circuit for generating a signal processing circuit corresponding to the image data of the plurality of light-receiving pixels according to the image signal; generating a high-frequency vibration matrix of the light-shielding image data of the part of the light-receiving pixels of the solid-state imaging element; A matrix generating circuit and a binary circuit that binarizes the above-mentioned image data with reference to the above-mentioned high-frequency vibration matrix. Therefore, the dark current component that arbitrarily changes the operation state of the corresponding imaging element for each pixel is used as the high-frequency vibration. The matrix is used, so there is no need to memorize large-scale high-frequency vibration matrices. A fourth feature of the present invention is ingestion In a camera device that takes out image information in one frame unit, the information charges generated by photoelectric conversion are arranged in rows and columns of light-receiving pixels that are stored independently, while corresponding to each light-receiving pixel in a plurality of storage pixels. The solid-state imaging elements arranged in rows and frames are transferred by the frame transfer method; the information charges stored in the light-receiving pixels of the solid-state imaging elements are transferred to the vertical shift registers, and sequentially transferred output images are obtained from the vertical shift registers. A signal driving circuit; a timing control circuit for controlling the timing of transferring information charges from each light-receiving pixel of the imaging element to each of the vertical shift registers and the timing of transferring and outputting information charges from each vertical shift register; Like signals, which are generated corresponding to

C:\ProgramFiles\Patent\3l0654.ptd 第 8 頁 432873 五、發明說明（6) --- 上述複數受光像素之每一圖像資料之訊號處理 上述圖像資料與一定判定基準值比較而予以二進及將 進位化電路者。上述時序控制電路係將自上述 一 各垂直移位暫存器轉送完了至上述資訊電荷開始二= 為止之期間内，保持預定時間間隔以對上述資訊： 以暗電流所發生之電荷者β 專付重整 於是，在儲存部各受光像素發生之腈電流變化以 振動加算於資訊電荷。然後，其任意暗電流成分重 像資料與一定基準值比較，成為二進位化結果可獲 頻振動處理同等效果^ ^ [發明之實施形態] 第1實施例 第3圖係顯示本發明攝像裝置之第1實施例之方塊圖。 攝像元件11係包含以行列配置之複數個受光像素及各 受光像素儲存之資訊電荷’依序轉送輸出之複數個移位暫 存器，依照驅動電路12之驅動時脈產生圖像訊號Υ{)⑴。驅 動電路12則產生成垂直轉送時脈及水平轉送時脈，由該垂 直轉送時脈及水平轉送時脈以脈衝驅動攝像元件n D該攝 像元件11及驅動電路12係與第1圚所示之攝像元件1及驅動 電路2 —致。 類比處理電路13對由攝像元件π輸入之圖像訊號 Y〇⑴’施行樣品持留等類比系訊號處理產生圖像訊號¥1⑴。 A/D變換電路14係從類比處理電路13輸入圖像訊號Yut)同步 於類比處理電路13之動作時序而予以數位變換以產生圖像C: \ ProgramFiles \ Patent \ 3l0654.ptd Page 8 432873 V. Description of the invention (6) --- The signal processing of each image data of the above-mentioned multiple light receiving pixels is processed by comparing the above image data with a certain judgment reference value. Those who enter and will carry the circuit. The above-mentioned timing control circuit keeps a predetermined time interval from the completion of the transfer of each of the vertical shift registers to the start of the above-mentioned information charge to two =, and pays for the above-mentioned information by the charge generated by the dark current β. The rearrangement is such that a change in the nitrile current occurring at each light receiving pixel in the storage portion is added to the information charge as a vibration. Then, the arbitrary dark current component ghost image data is compared with a certain reference value to obtain a binary result, and the equivalent effect of frequency vibration processing can be obtained. ^ [Embodiment of the Invention] FIG. 3 of the first embodiment shows the imaging device of the present invention. Block diagram of the first embodiment. The imaging device 11 includes a plurality of light receiving pixels arranged in rows and rows and a plurality of shift registers sequentially outputted by the information charges stored in the light receiving pixels, and generates image signals according to the driving clock of the driving circuit 12 ({) Alas. The driving circuit 12 generates a vertical transfer clock and a horizontal transfer clock. The vertical transfer clock and the horizontal transfer clock drive the imaging element n D by pulse. The imaging element 11 and the driving circuit 12 are as shown in the first figure. The imaging element 1 and the driving circuit 2 are the same. The analog processing circuit 13 performs analog signal processing such as sample hold on the image signal Y〇⑴ ′ input from the imaging element π to generate an image signal ¥ 1⑴. The A / D conversion circuit 14 inputs the image signal Yut from the analog processing circuit 13 and synchronizes with the operation timing of the analog processing circuit 13 to perform digital conversion to generate an image.

C:\ProgramFiles\Patent\310654.ptd 第 9 頁 432873 五，發明說明（Ό 資料01([〇。該類比處理電路12及A/D變換電路14之動作亦舆 第1圖所示類比處理電路3及A/D變換電路4之動作一致。 數位處理電路15係連接於A/D變換電路14，對由A/D變 換電路14輸入之圖像資料0!⑷施行色分離寒矩陣演算等處 理以產生對應於光之三原色之3色成分資料R(n)，G(n)， B(n)。例如：安裝在攝像元件11之遽色鏡如第4圏所示係 由白（W)，綠（G)，青（Cy)及黃（Y)構成時，以ff-Cy可取出 紅（R)成分，以W-Ye可取出藍（B)成分。C: \ ProgramFiles \ Patent \ 310654.ptd Page 9 432873 V. Description of the invention (Ό 01 料 01 ([〇. The operation of the analog processing circuit 12 and the A / D conversion circuit 14 is also the analog processing circuit shown in FIG. 1 The operations of 3 and A / D conversion circuit 4 are the same. Digital processing circuit 15 is connected to A / D conversion circuit 14 and performs processing such as color separation cold matrix calculation on the image data input from A / D conversion circuit 14! In order to generate the three-color component data R (n), G (n), and B (n) corresponding to the three primary colors of light. For example, the color mirror mounted on the imaging element 11 is shown by white (W) as shown in Figure 4 When it is composed of green (G), cyan (Cy) and yellow (Y), ff-Cy can take out the red (R) component, and W-Ye can take out the blue (B) component.

又，由Ye-G獲得R成分’Cy-G則可得B成分。為實行該 色演算處理於數位訊號處理電路15中，例如構成3行3列之 空間濾色鏡。由該數位處理電路15所得之色成分資料 R(n)，G(n)，B(n)分別具有對應於A/D變換電路14之位元 數。In addition, when the R component'Cy-G is obtained from Ye-G, the B component can be obtained. To implement this color calculation processing in the digital signal processing circuit 15, a spatial color filter of 3 rows and 3 columns is formed, for example. The color component data R (n), G (n), and B (n) obtained by the digital processing circuit 15 have the number of bits corresponding to the A / D conversion circuit 14, respectively.

二進位化電路16係將色成分資料R(n)，G(n)，B(n)予 以任意，設定之高頻振動型式為基準而做二進位化，如第 5圖所示，與驅動電路12之水平轉送時脈同步，產生將各 色成分分別以1位元表示之二進位資料r(n) ,g(；n)， b(n)。在此使用之高頻振動型式須記憶在二進位化電路 内藏記憶電路内預先決定之型式，或須記憶相應在攝像元 件11中任意產生暗電流成分之型式等而得之。該二進位化 電路16係與數位處理電路15成為一體可由使用數位處理電 路15之一部分，構成色成分資料R(n)，G(n)，B(n)與高頻 振動型式比較。又於該二進位化電路16中，僅實行色成分 資料R(n)，G(n)，B(n)與高頻振動型式之比較而不發生複The binarization circuit 16 arbitrarily sets the color component data R (n), G (n), and B (n). The set high-frequency vibration pattern is used as a reference to perform binarization. As shown in FIG. The horizontal transfer clock of the circuit 12 is synchronized to generate binary data r (n), g (; n), b (n) in which each color component is represented by 1 bit. The high-frequency vibration pattern used here must be memorized in a binary circuit, a pattern determined in advance in a built-in memory circuit, or a pattern corresponding to any dark current component arbitrarily generated in the imaging element 11 and the like. The binary circuit 16 is integrated with the digital processing circuit 15, and a part of the digital processing circuit 15 can be used to form the color component data R (n), G (n), and B (n) compared with the high-frequency vibration pattern. In the binary circuit 16, only the color component data R (n), G (n), and B (n) are compared with the high-frequency vibration pattern without complex.

C:\Program Files\Patent\310654.ptd 第 10 頁 411873 ^C: \ Program Files \ Patent \ 310654.ptd Page 10 411873 ^

雜的演算處理，故對處理之高速化有利。 CPU17係依控制程式控制各部之動作同時，取進二 進位化電路16輸出之3種二進位資料r(n)，g(n)，b(n)， 依序寫入圖像資料記憶趙18予以記憶。該3種二進位資料 r(n) ’g(n)，b(n)合計為3位元，在cm 之介面。又於二進位資料r(n)，w、地 μ S(n) ’ b(n)係於預先壓縮 無須於CPU17進行壓縮處理，故可大幅簡化演算處理。Miscellaneous calculus processing is beneficial to speeding up the processing. The CPU17 controls the operations of each part according to the control program. At the same time, it takes in the three binary data r (n), g (n), b (n) output by the binary circuit 16 and writes the image data memory in sequence. Zhao 18 Be memorized. The three kinds of binary data r (n) 'g (n) and b (n) add up to 3 bits, and the interface is in cm. In addition, the binary data r (n), w, and μ S (n) ′ b (n) are pre-compressed. There is no need to perform compression processing on the CPU 17, so the calculation processing can be greatly simplified.

又，有關於CPU17對驅動電路12之曝光控制或對類比處理 電路13及數位處理電路15之控制動作，係如第1囷所示與 CPU8為相同之動作。然後，對二進位化電路16，亦如對數 位處理電路15之控制動作，將訊號處理之時序同步於前段 電路’即同步於數位處理電路15。圖像資料記憶18係如第 1圖所示之圖像記憶電路9相同，連接於CPln7，依序記憶 取進於CPU17之二進位資料r(n)，g(n)，b(n)。The exposure control of the drive circuit 12 by the CPU 17 or the control processing of the analog processing circuit 13 and the digital processing circuit 15 is the same operation as that of the CPU 8 as shown in Fig. 1 (a). Then, the binary circuit 16 is also controlled by the digital processing circuit 15 to synchronize the timing of the signal processing with the previous stage circuit, that is, the digital processing circuit 15. The image data memory 18 is the same as the image memory circuit 9 shown in Fig. 1 and is connected to CPln7. It sequentially stores the binary data r (n), g (n), and b (n) taken into the CPU17.

記錄在圖像資料記憶體18之二進位資料r(n) ,g(n)， b(n)在必要時讀出於CPU17，並直接輸於外部機器。如上 述輸出之二進位資料r(n) ’g(n)，b(n)之顯示系統或印字 系統’雖較接收圖像資料D2(n>予以顯示或印字係於其再生 畫像之畫質劣化’唯依各成分施有高頻振動處理由深淡級 之模（gradation)顯示可獲得充分畫質。尤其攝像元件Μ 之受光像素數愈多，則可獲得更高畫質的再生畫面，故本 發明之效果極大。 如依本發明，可在圖像資料之訊號處理階段，將每— 色成分之資料予以二進位化結果’可簡化取進該二進化資The binary data r (n), g (n), and b (n) recorded in the image data memory 18bis are read out from the CPU 17 when necessary, and directly input to an external device. As shown above, the binary display data r (n) 'g (n), b (n)' s display system or printing system 'is better than the received image data D2 (n >) for display or printing based on the quality of its reproduced image. “Degradation” can be achieved only by applying high-frequency vibration processing to each component. Gradation display can achieve sufficient image quality. In particular, the greater the number of light-receiving pixels of the imaging element M, the higher the quality of the reproduced image. Therefore, the effect of the present invention is extremely great. According to the present invention, at the signal processing stage of the image data, the data of each color component can be binarized.

A32S7 3____ 五、發明說明（9) 料之CPU輸入介面。又’不須在CPU側施行資料之壓縮處 理，可簡化演算系統，同時亦可縮短訊號處理所需時間， 以對應高速動作。因此，可實現成本極低之攝像系統，以 適用簡易型監視用照相機及玩具等。 第2實施例 第6圖係顯示本發明攝像處置之第2實施例之方塊圖。 攝像元件21包含有複數個移位暫存器，以便以依序轉 送輸出以行列配置之複數個受光像素及各受光像素所儲存 之資訊電荷，依照驅動電路22之驅動時脈發生圖像訊號 Y〇⑴。該攝像元件21係與第1圈所示之攝像元件1 一致。驅 動電路22為產生垂直驅動時脈及水平驅動時，由該垂直無 動時脈及水平驅動時脈以脈衝驅動攝像元件11。該駆動電 路22之動作時序係設定於同步後述之CPU17對圖像資料記 憶體28之寫入時序者。 類比處理電路23係對由攝像元件21輸入之圖像訊號 Υ〇⑴施行類比系統之訊號處理後產生畫像訊號？!⑴。A/D變 換電路24係將從類比處理電路23輸入之圖像訊號？】⑴同步 於類比處理電路23之動作時序予以數位變換後，產生圖像 資料比⑷。該類比處理電路23及A/D變換電路24之動作亦與 第1圖所示類比處理電路3及A/D變換電路4之動作一致。 數位處理電路25連接於A/D變換電路24，對從A/D變換 電路24輸入之圖像資料D1(n)施行色分離及矩陣演算等處 理’例如對應於光之三原色產生色成分R(n)，G(n)， B(n)。換言之，因安裝於攝像元件21之濾色鏡係如第4圖A32S7 3____ V. Description of the invention (9) CPU input interface expected. Moreover, it is not necessary to perform data compression processing on the CPU side, which can simplify the calculation system, and also shorten the time required for signal processing to correspond to high-speed operations. Therefore, it is possible to realize an extremely low-cost camera system suitable for simple surveillance cameras and toys. Second Embodiment FIG. 6 is a block diagram showing a second embodiment of the imaging process of the present invention. The image sensor 21 includes a plurality of shift registers for sequentially transmitting and outputting a plurality of light-receiving pixels arranged in rows and rows and the information charges stored in the light-receiving pixels, and generating an image signal Y in accordance with the driving clock of the driving circuit 22 〇⑴. This imaging element 21 corresponds to the imaging element 1 shown in the first circle. The driving circuit 22 generates a vertical driving clock and a horizontal driving clock, and drives the imaging element 11 by the vertical non-clocking clock and the horizontal driving clock. The operation timing of the automatic circuit 22 is set at the writing timing of the image data memory 28 by the CPU 17 described later in synchronization. The analog processing circuit 23 generates an image signal after performing the analog signal processing on the image signal input from the imaging element 21? ! ⑴. Is the A / D conversion circuit 24 an image signal input from the analog processing circuit 23? ] Synchronization After digitally transforming the operation timing of the analog processing circuit 23, the image data ratio 产生 is generated. The operations of the analog processing circuit 23 and the A / D conversion circuit 24 are also consistent with the operations of the analog processing circuit 3 and the A / D conversion circuit 4 shown in FIG. The digital processing circuit 25 is connected to the A / D conversion circuit 24, and performs processing such as color separation and matrix calculation on the image data D1 (n) inputted from the A / D conversion circuit 24. For example, a color component R ( n), G (n), B (n). In other words, since the color filter mounted on the imaging element 21 is as shown in FIG. 4

432873 ^ 五、發明說明（10) 所示’以白（W)，綠（G)，青（Cy)及黃（Y)構成時，以ff_Cy 可取出紅（R)成分’以ff-Ye可取出藍（B)成分。又因Ye —G可 獲得R成分，Cy-G可獲得B成分。為實行該色演算處理於數 位訊號處理電路25係搆成如3行Χ3列之空間渡色鏡。由該 數位處理電路25獲得之色成分資料R(n)，G(n) ,Β(η)分別 具有對應於A/D變換電路24之位元數。 資料壓縮電路26對色成分R(n)，G(n)，B(n)施行壓縮 處理以產生削減位元數之壓縮資料r(n)，g(n) ,b(n)。該 壓縮處理，可採用高頻振動處理及誤差擴散處理。例如， 採用高頻振動處理時，係以任意設定之高頻振動型式為基 準使色成分資料R(n)，G(n)，B(n)二進位化，如第7圖所 示’同步於驅動電路22之水平轉送時脈產生分別以一位元 表示各色成分之各一位元之壓縮資料r(n)，g(n)，b(n)。 又，若採用誤差擴散處理時，係依一定基準值將色成分資 料R(n)，G(n)，B(n)二進位化，將該時發生之誤差分配於 周邊像素予以加算。採用該誤差擴散處理係如高頻振動處 理一樣，可得如第7圖所示之壓縮資料r(n) >g(n)， b(n)。又，於壓縮資料r(n) ’g(n)，b(n)，除以二進位表 示外’亦可以4進位（2位元），或8進位（3位元）以上方式表 示之。上述位元數，可考量電路動作速度或所要之再生畫 面畫質選擇即可。 CPU27係依控制程式控制各部動作，同時，取進由資 料壓縮電路26輸出之3種壓縮資料r(n)，g(n)，b(n)依序 窝進圖像資料記憶體28予以記憶之。在該CPU27中，係將432873 ^ V. Description of the invention (10) 'When composed of white (W), green (G), cyan (Cy) and yellow (Y), the red (R) component can be taken out with ff_Cy' can be taken with ff-Ye Take out the blue (B) component. In addition, the Ye component can obtain the R component, and the Cy-G component can obtain the B component. To implement this color calculation processing, a digital signal processing circuit 25 constitutes a space color mirror such as 3 rows × 3 columns. The color component data R (n), G (n), and B (η) obtained by the digital processing circuit 25 have the number of bits corresponding to the A / D conversion circuit 24, respectively. The data compression circuit 26 performs a compression process on the color components R (n), G (n), and B (n) to generate compressed data r (n), g (n), and b (n) that reduce the number of bits. The compression process may be a high-frequency vibration process and an error diffusion process. For example, when high-frequency vibration processing is used, the color component data R (n), G (n), and B (n) are binarized based on the arbitrarily set high-frequency vibration pattern, as shown in FIG. 7 'Synchronization At the horizontal transfer clock of the driving circuit 22, compressed data r (n), g (n), and b (n) of each bit representing each color component are generated by a bit. When the error diffusion process is used, the color component data R (n), G (n), and B (n) are binarized according to a certain reference value, and the errors occurring at that time are allocated to the surrounding pixels and added. Using this error diffusion processing, like high frequency vibration processing, compressed data r (n) > g (n), b (n) as shown in Fig. 7 can be obtained. In addition, in the compressed data r (n) 'g (n), b (n), in addition to the binary representation', it can also be expressed in the form of 4-bit (2 bits) or 8-bit (3 bits) or more. The number of bits mentioned above can be determined by considering the operating speed of the circuit or the desired quality of the reproduced picture. The CPU 27 controls the operations of each part according to the control program, and simultaneously takes in three types of compressed data r (n), g (n), and b (n) output by the data compression circuit 26 and sequentially stores them into the image data memory 28 for storage. Of it. In this CPU27, the system

C:\ProgramFiles\Patent\310654.ptd 第 13 頁 Μ ®7 3^ 一. 案號 8810^802C: \ ProgramFiles \ Patent \ 310654.ptd Page 13 Μ ®7 3 ^ I. Case No. 8810 ^ 802

二·^h£r 五、發明說明（11) 分別以一位元表示之壓蟑資料r(n)，g(n)，b(n)取進於輸 入介面後，直接寫入圈像資料記憶體28 此時之寫入時衝 係如第7圖所示。設定與驅動電路22水平轉送眸同步。因 此，CPU27無須對壓縮資料r(n) ’g(n)，b(n)進行壓縮處 理故可大幅度地簡化演算處理。又’有關CPU27對驅動電 硌22之曝光控制及類比處理電硌23及數位處理電路25之控 制動作，係進行如第1圈所示之CPU8同樣動作 對資料壓 縮電路26，亦如同對數位處理電路2 5之控制動作一樣，將 訊號處理時序同步於前段電路，即數位處理電硌25。圖像 資料記憶髏2 8係舆第1圖所示之圖像資料記憶襞分一樣，連 接於CPU27，依序取進CPU27之壓縮資料r(n)，g(n)，b(n) 記億。 記憶夺圏像資料記憶體28;壓縮資料r(n)，g(n)， b(n)係於必要時讀出於CPU27，並直接輸出於外部機器。 於上述輸出之壓縮資料r(n)，g(n)，b(n)毛類示系統或印 字系統，較接受圖像資料D2(n)齷示或印字時，其再生圖像 之畫質雖有劣化情況，然而因依各成分施有高頻振動處理 由深淡級之模擬顯示可獲得充分畫質。尤其攝像元件21之 受光像素愈多，可獲得詞更高畫質之再生畫面，故本發明 之效果很大。 如依本發明，係相應於壓縮資料之圈像資料記、憶體寫 入時序而騄動攝像无件，因此在訊處理過程中不需幀儲存 器。因鴣簡化裝置電路之構成，寸實現低成本之攝像系 统。2. ^ h £ r 5. Description of the invention (11) The cockroach data r (n), g (n), and b (n), respectively expressed in one bit, are taken into the input interface and directly written into the circle image data The memory 28 is written as shown in Figure 7 at this time. The setting is synchronized with the horizontal rotation of the driving circuit 22. Therefore, the CPU 27 does not need to perform compression processing on the compressed data r (n) 'g (n), b (n), so that the arithmetic processing can be greatly simplified. Also related to the CPU 27's exposure control of the drive electronics 22 and analog processing electronics 23 and the digital processing circuit 25, the same operations as the CPU 8 shown in the first circle to the data compression circuit 26, as well as the digital processing The control action of the circuit 25 is the same, and the signal processing timing is synchronized with the previous circuit, that is, the digital processing circuit 25. The image data memory 2 is the same as the image data memory shown in Figure 1. It is connected to the CPU27, and the compressed data r (n), g (n), and b (n) of the CPU27 are sequentially recorded. Billion. Memory capture image data memory 28; compressed data r (n), g (n), b (n) are read out to CPU 27 when necessary, and output directly to external equipment. The compressed data r (n), g (n), b (n) of the above-mentioned compressed data display system or printing system is better than the image quality of the reproduced image when the image data D2 (n) is displayed or printed. Although it may be deteriorated, high-frequency vibration processing is applied to each component to obtain sufficient image quality from the gradation simulation display. In particular, the more light-receiving pixels of the imaging element 21, the higher the quality of the reproduced picture can be obtained, so the effect of the present invention is great. According to the present invention, it is corresponding to the chronological data record and memory writing sequence of the compressed data, and the video is automatically recorded without parts. Therefore, a frame memory is not required during the message processing. Since the structure of the device circuit is simplified, a low-cost camera system is realized.

C:\Ptogmm Files\patent\310654.ptc 第14頁 2000.10.27.0J4 432873 ^ 五、發明說明（12) 又’係將圖像資料預先壓縮後通過CPU寫入圖像資料 記憶體’可簡化CPU之輸入介面，同時，可將演算系統簡 化，進一步降低成本。 第3實施例 第8圖係顯示本發明攝像裝置第3實施例之方塊圖。 攝像元件31係如第1圖所示攝像元件1 一樣之CCI)圖像 感測器’包含有行列配置之複數受先像素與依序轉送輸出 儲存在各受光像素内資訊電荷之複數個移位暫存器β行列 配置之複數受光像素係如第8圖所示安裝有光之三原色或 該等之輔助色依預定配列之濾色鏡，將各受光像素對應於 特定色成分。位於周邊領域之受光像素，係以光學上不透 明膜遮光’以構成可取出黑基準位準。又複數個移位暫存 器係以複數個垂直移位暫存器對應於受光像素之各列配 置，而將水平移位暫存器配置在複數個垂直移位暫存器輪 ΓΝ 以驅動電路3 2產生垂直轉送時脈及水平轉送時脈，將 垂直轉送時脈供於攝像元件31之垂直移位暫存器，而 平轉送時脈供於攝影元件31之水平移位暫存器。由此 分別獨立而儲存於複數個受光像素之資訊電荷以 序轉送輪出，可獲得1畫面份圖像資訊以丨行單位連 : 像訊號Yfl⑴。該圖像訊號，因被遮光受光像素 影元件31周邊的關係，係如第10圖所示，在水平掃 之開始（或終了）期間Κ顯示黑基準位準。 期間 類比處理電路33對由攝像元件31輪入之圖像C: \ Ptogmm Files \ patent \ 310654.ptc Page 14 2000.10.27.0J4 432873 ^ V. Description of the invention (12) It also 'compresses the image data in advance and writes it to the image data memory through the CPU' to simplify the CPU The input interface can also simplify the calculation system and further reduce costs. Third Embodiment FIG. 8 is a block diagram showing a third embodiment of the imaging device of the present invention. The image sensor 31 is a CCI like the image sensor 1 shown in FIG. 1) The image sensor 'contains a plurality of prior pixels arranged in rows and columns and sequentially transfers output to output a plurality of shifts of information charges stored in each light receiving pixel The plurality of light-receiving pixels arranged in the β-column of the register are as shown in FIG. 8, and the three primary colors of light or the auxiliary colors thereof are arranged according to a predetermined color filter, and each light-receiving pixel corresponds to a specific color component. The light-receiving pixels located in the surrounding area are shielded with an optically opaque film 'to constitute a removable black reference level. The plurality of shift registers are arranged with a plurality of vertical shift registers corresponding to the columns of the light-receiving pixels, and the horizontal shift registers are arranged in a plurality of vertical shift registers wheels ΓΝ to drive the circuit. 3 2 Generates a vertical transfer clock and a horizontal transfer clock, and supplies the vertical transfer clock to the vertical shift register of the imaging element 31, and the horizontal transfer clock to the horizontal shift register of the imaging element 31. Therefore, the information charges stored in the plurality of light-receiving pixels independently and sequentially are transmitted in turn, and one piece of image information can be obtained in a line unit: image signal Yfl⑴. This image signal, due to the surroundings of the light-receiving pixel shadow element 31, shows the black reference level during the beginning (or end) of the horizontal sweep as shown in FIG. During the analog processing circuit 33, the image rotated by the image sensor 31

/1 328T3 五、發明說明（13)/ 1 328T3 V. Description of the Invention (13)

進行樣品持留等類比系統之訊號處理，以產生圖像訊號 Y!⑴。A/D變換電路34使由類比處理電路33輸入之圖像訊號 Y1(t)同步於類比處理電路3 3之動作時序做數位之變換，以 產生圖像數據D1(t) «數位處理電路35連接於A/D變換電路34 對從A/D變換電路34輸入之圖像數據h⑴施以色分離及矩陣 演算等處理，產生對應於光三原色之3種色成分資料 R(n) ’G(n) ’B(n) »如安裴在攝像元件31之濾色鏡為白 0Π ’綠（G) ’青（Cy)及黃（Y)如第9圖所示構成時，以ff-Cy 取出紅（R)成分’以W-Ye取出藍（B)成分。又，以Ye-G得到 R成分，Cy-G可得B成分。為施行該色演算處理係於數位訊 號處理電路35中構成3行X3列之空間濾色鏡。自上述類比 處理電路32至數位處理電路35止之動作，係與第1圖所示 之類比處理電路3至數位處理電路5之動作一致。 矩陣產生電路36係如第1〇圖所示，依對應於圖像訊號 Y〇⑴之黑基準位準期間K設定時序之抽樣訊號，以每水平攆 描期間抽樣圖像資料匕⑷，將各抽樣值按預定數量重複配 列而產生高頻振動矩陣。即，在被遮光周邊領域之複數之 受光像素中，不會發生光電變換之資訊電荷，但儲存由暗Perform signal processing on analog systems such as sample hold to generate the image signal Y! ⑴. The A / D conversion circuit 34 synchronizes the image signal Y1 (t) input from the analog processing circuit 33 with the operation timing of the analog processing circuit 33 to perform digital conversion to generate image data D1 (t) «digital processing circuit 35 Connected to the A / D conversion circuit 34, the image data h⑴ input from the A / D conversion circuit 34 is subjected to processing such as color separation and matrix calculation to generate three color component data R (n) 'G ( n) 'B (n) »If Amber ’s color filter on the image sensor 31 is white 0Π' Green (G) 'Cyan (Cy) and Yellow (Y) As shown in Figure 9, take out the red with ff-Cy (R) component 'Take out the blue (B) component as W-Ye. The R component was obtained with Ye-G, and the B component was obtained with Cy-G. To implement this color calculation processing, a spatial filter of 3 rows by 3 columns is formed in the digital signal processing circuit 35. The operations from the analog processing circuit 32 to the digital processing circuit 35 described above correspond to the operations of the analog processing circuit 3 to the digital processing circuit 5 shown in FIG. As shown in FIG. 10, the matrix generating circuit 36 is based on the sampling signal corresponding to the black reference level period K of the image signal Y0. The sampling signal is set to sample image data at each horizontal scanning period. The sampled values are repeatedly arranged in a predetermined number to generate a high-frequency vibration matrix. That is, in a plurality of light-receiving pixels in the surrounding area that is shielded from light, the information charge of photoelectric conversion does not occur, but the

電流發生的電荷。該暗電流發生量係因有像素之參差，由 被遮光周邊領域之複數受光像素獲得之黑基準位準，直接 抽樣的結果，可獲得隨機資料。於是，將複數個抽樣值予 以重複配置在一行，可形成一行分之高頻振動矩陣。如此 產生之高頻振動矩陣，將個別資料τ⑷依序供於高頻振動 電路37。The electric charge generated by the current. The amount of dark current generated is the black reference level obtained from a plurality of light-receiving pixels in the surrounding area that is blocked due to pixel variations, and random data can be obtained as a result of direct sampling. Therefore, a plurality of sample values are repeatedly arranged in a row to form a high frequency vibration matrix in a row. The high-frequency vibration matrix thus generated supplies the individual data τ⑷ to the high-frequency vibration circuit 37 in order.

4S2S73 ..... 五、發明說明（14) 高頻振動電路37係將色成分資料R(n)，G(n)，B(n)依 自矩陣產生電路36供給之高頻振動資料τ(ιη)二進位化後， 如第7圖一樣’同步於驅動電路32水平轉送時脈，產生將 各色成分分別以1位元表示之壓縮資料r(n) ,g(n)， b (η)。在該高頻振動電路37中所用之高頻振動矩陣係在矩 陣產生電路36中以各行依暗電流成分產生，係相應於暗電 流成分變化’因此，可經常獲得與最適當頻振動陣列同等 效果。 時序控制電路38係依基準時脈控制各部動作。該時序 控制電路38同步於驅動電路32之動作時序，產生對應於圓 像訊號Yfl⑴之黑基準準位期間κ設定時序之抽樣訊號，供於 矩陣產生電路36 ^同時，對矩陣產生電路36，給予於各水 平掃描期間之開始時發出更新高頻振動矩陣之指令。再 者，時序控制電路3 8係對高頻振動電路37，係使色成分資 料R(n) G(n)，Β(π)之取進之時序同步於數位處理電路35 之輸出動作。又，該時序控制電路38驅動電路32之動作控 制與類比處理電路33至類比處理電路35止之動作控制係與 第1圖所示時序控制電路7之動作一致。 高頻振動電路37產生之壓縮資料r(n)，g(n)，b(n)記 錄於非揮發型記憶嫌或以磁碟片代表之大容量記錄媒體， 或供於顯示機器及印字機器„如上述輸出之壓縮資料 r(n)，g(n)，b(n)係使用相應於暗電流成分變化之高頻振 動矩陣予以二進位化，故不易受暗電流變化之影響，亦與 動作環境無關地再生穩定畫質之圖像。又，因不易受到暗 C:\ProgramFiles\Patent\310654.ptd 第 17 頁 432873 _ 案號88108802 Ϋΐ年A货AC?自 鉻砼 _ 五、發明說明U5) 電埤成分影饗之關係’可保持資訊電荷之長時間儲存於攝 像元件21’而可自由選擇從攝像元件2〗對各處理電路23， 24<讀出時序。 第11圖為矩陣產生電路36及高頻振動電路37之構成方 塊圖。 矩陣產生電路36係由暗電流檢測部41 ’峰值檢出部 43，差分檢測部44 ’矩陣部42及乘法器45構成《暗電流檢 出部41係相應於由時序控制電路38供給之抽樣訊號，實施 圖像資料Due之抽樣保持顯示黑基準位準部分。通常，攝 像元件31 4受光像素係於其周邊領域之至2〇像素乘遮光 故可由圖像訊號丫❶⑴之黑基準位準取出1〇至2〇像素分。矩 陣部42係將暗電流檢測部41檢測出之複數黑基準位準，以 周期性或任意配列為1行像素數分’以產生成高頻振動矩 陣。 峰值檢谢部43係依各水平掃描期間檢出暗電流徐測部 41檢測出的複數黑基準位準毒值並予以保持。差分檢測部 44係由各水平捧描期間内’以峰值檢測部43棟出之峰值與 前一個水平掃描期間内檢出之峰隹算出值差，依其計算結 果產生係數資料。然後，由乘法器45對矩陣部42產生之高 頻振動矩陣各高頻振動資料τ⑷’乘以差分檢測部44供給 之係數資料’以修整高頻振動矩陣β該修正係為修正攝像 元件31轉送資訊電荷時由時間差引起暗電流成分而作換 言之’從行列配置之複數受光像素轉送輸出時，依每一行 轉送時序之時間差而有蝽電流成分增加的關係，須對矩陣4S2S73 ..... V. Description of the invention (14) The high-frequency vibration circuit 37 is the high-frequency vibration data τ supplied from the matrix generating circuit 36 based on the color component data R (n), G (n), and B (n). (ιη) After binarization, as shown in FIG. 7, the clock is horizontally transmitted in synchronization with the driving circuit 32 to generate compressed data r (n), g (n), b (η) in which each color component is represented by 1 bit. ). The high-frequency vibration matrix used in the high-frequency vibration circuit 37 is generated by the dark current component in each row in the matrix generation circuit 36, and it corresponds to the change of the dark current component. Therefore, the same effect as that of the most suitable frequency vibration array can always be obtained . The timing control circuit 38 controls the operation of each part according to the reference clock. The timing control circuit 38 synchronizes with the operation timing of the driving circuit 32, and generates a sampling signal corresponding to the black reference level period κ setting timing of the circular image signal Yfl ， for the matrix generation circuit 36. At the same time, the matrix generation circuit 36 gives An instruction to update the high frequency vibration matrix is issued at the beginning of each horizontal scanning period. In addition, the timing control circuit 38 and the high-frequency vibration circuit 37 synchronize the timing of taking in the color component data R (n) G (n) and B (π) with the output operation of the digital processing circuit 35. The operation control of the timing control circuit 38 driving circuit 32 and the operation control of the analog processing circuit 33 to the analog processing circuit 35 are the same as the operation of the timing control circuit 7 shown in FIG. The compressed data r (n), g (n), and b (n) generated by the high-frequency vibration circuit 37 are recorded in a non-volatile memory or a large-capacity recording medium represented by a magnetic disk, or used for a display machine and a printing machine „The compressed data r (n), g (n), and b (n) output as described above are binarized using a high-frequency vibration matrix corresponding to the change in the dark current component, so they are not easily affected by the change in dark current. Reproduces images of stable quality regardless of the action environment. In addition, because it is not easy to be dark C: \ ProgramFiles \ Patent \ 310654.ptd Page 17 432873 _ Case No. 88108802 Year A Goods AC? Since Chrome _ V. Description of the Invention U5) The relationship between the electrical and electronic components' can be stored in the imaging element 21 for a long time to maintain the information charge and can be freely selected from the imaging element 2 to each processing circuit 23, 24 < the timing of reading. Figure 11 shows the matrix generation A block diagram of the configuration of the circuit 36 and the high-frequency vibration circuit 37. The matrix generation circuit 36 is composed of a dark current detection section 41 'a peak detection section 43, a differential detection section 44' a matrix section 42 and a multiplier 45, and a "dark current detection section" 41 corresponds to the sampling signal supplied by the timing control circuit 38 The implementation of the sampling of the image data due to display and display the black reference level part. Generally, the light receiving element of the camera element 314 is from its surrounding area to 20 pixels multiplied by shading, so it can be taken out from the black reference level of the image signal. 0 to 20 pixel points. The matrix section 42 is to generate a high-frequency vibration matrix by periodically or arbitrarily arranging a plurality of black reference levels detected by the dark current detection section 41 into a row of pixel points. The unit 43 is based on the dark current detected by the dark current measurement unit 41 during each horizontal scan. The complex black reference level poison value is detected and maintained. The differential detection unit 44 is generated by the peak detection unit 43 during each horizontal scanning period. The calculated difference between the peak value and the peak value detected during the previous horizontal scanning period generates coefficient data according to the calculation result. Then, the multiplier 45 multiplies each high-frequency vibration data τ⑷ 'of the high-frequency vibration matrix generated by the matrix portion 42 by the multiplier 45. The coefficient data provided by the differential detection unit 44 is used to modify the high-frequency vibration matrix β. This correction is to correct the dark current component caused by the time difference when the information element 31 transfers information charges. When the configured plurality of light-receiving pixels are transferred and output, there is a relationship that the current component increases according to the time difference of the transfer timing of each row.

43287 343287 3

部42輪出之高頻振動資料τ(η)乘以係數資料。 间頻振動電路37係由加法器46及二進位化部4了構成 。加法器46係對色成分資料以。，G(n)，Β(η)分別加算從 矩陣產生電路3 6輸入之高頻振動資料，並將各加算值供於 二進位化部47。二進位化部47係將對應於自加法器46輪入 之色成分資料R(n)，G(n)，Β(η)之加算值與一定判定值對 比，產生以2進位表示之對判定值加算值大小之壓縮資料 r(n)，g(n)，b(n)。由此，色成分資料R(n)對應於高頻振 動矩陣成為二進化。 在上述之實施形態中’係顯示將矩陣產生電路36及高 頻振動電路37從數位處理電路35予以獨立而設之例，但在 數位處理電路3 5之輸出階段亦可實行與矩陣電路3 6及高頻 振動電路37同一之處理。 如依本發明，相應於動作環境任意發生暗電流或分用 以產生高頻振動矩.陣的結果’不必多記高頻振動型式，可 對應於暗電流成分之偏差經常可獲得最適高頻振動型式。 因此’得以與裝置之動作環境無關地可再生經常穩定像質 之畫面。 又’圖像資料暗電流成分增加亦無妨的關係，可將從 攝像元件取出圖像訊號之時序寬度設定為較寬，則可自由 選擇對圓像訊號及圖像資料各處理電路之動作時序β因 此，可簡化電路構成，降低裝置之成本。 第4實施例 第12圖係本發明攝像裝置第4實施例之方塊圓，第13Multiply the high-frequency vibration data τ (η) by the coefficient data. The inter-frequency vibration circuit 37 is composed of an adder 46 and a binary unit 4. The adder 46 is for color component data. , G (n), B (η) are respectively added to the high-frequency vibration data input from the matrix generating circuit 36, and each added value is supplied to the binary unit 47. The binarization unit 47 compares the addition value of the color component data R (n), G (n), and B (η) corresponding to the rounds from the adder 46 with a certain judgment value, and generates a pair judgment represented by a binary. Compressed data r (n), g (n), b (n). As a result, the color component data R (n) becomes a double evolution corresponding to the high-frequency vibration matrix. In the above-mentioned embodiment, the example is shown in which the matrix generating circuit 36 and the high-frequency vibration circuit 37 are independently provided from the digital processing circuit 35, but the matrix processing circuit 3 5 can also be implemented in the output stage of the digital processing circuit 35. The processing is the same as that of the high-frequency vibration circuit 37. According to the present invention, a dark current or a distribution of a high-frequency vibration moment is generated arbitrarily in accordance with the operating environment. The result of the array 'does not need to remember many high-frequency vibration patterns, and it is possible to obtain the optimum high-frequency vibration corresponding to the deviation of the dark current component. Pattern. Therefore, it is possible to reproduce a picture with stable image quality regardless of the operating environment of the device. It is also possible to increase the dark current component of image data. The timing width of the image signal taken from the imaging element can be set to be wide, and the operation timing of each processing circuit of the circular image signal and image data can be freely selected. Therefore, the circuit configuration can be simplified and the cost of the device can be reduced. Fourth Embodiment FIG. 12 is a square circle of the fourth embodiment of the imaging device of the present invention.

432873 五、發明說明（17) 圖係說明其動作之時序圖β 杏^像元Λ51係梢轉送方式之咖圖像感測器，具有受 ί:二1S，水平轉送部51h及輪出部51d。受光 :川係由垂直方向連續之複數個移位暫存器所成，由該 移位暫存器之各位元分別構成受光像素。儲存部51s係由 連續於受光部51 i之移位暫存器之複數個移位暫存器所成 而由該移位暫存器之各位元分別構成儲存像素。水平轉送 部51h係以單一移位暫存器所成，儲存部51s之複數個移位 暫存器之輪出端則連接於該移位暫存器之各位元。輸出部 51d具有電性獨·立的電容量，接受從水平轉送部51h依序轉 送輸出之資訊電荷，將電荷量變換為電壓值輸出。又，攝 像元件51之受光部51i係如第14圖所示，對應於光之三原 色的複數個片段安裝依預定規則配列之濾色鏡，使各受光 像素對應於特定之色成分。在本實施形態中，係於單數行 交互配置G(綠）及R(紅）片段’而在雙數行則交互配置 B(藍）及G之各片段。432873 V. Description of the invention (17) The diagram is a sequence diagram to explain its operation. Β apricot ^ image element Λ51 is a coffee image sensor with a tip transfer method. It has a receiving unit: 2S, a horizontal transfer unit 51h, and a wheel output unit 51d. . Light receiving: The Sichuan system is formed by a plurality of shift registers which are continuous in the vertical direction, and each element of the shift register constitutes a light receiving pixel. The storage section 51s is formed by a plurality of shift registers successive to the shift register of the light receiving section 51 i, and each element of the shift register constitutes a storage pixel. The horizontal transfer unit 51h is formed by a single shift register, and the wheel out of the plurality of shift registers of the storage unit 51s is connected to each element of the shift register. The output section 51d has an independent electric capacity, and receives the information charges sequentially output from the horizontal transfer section 51h to convert the charge amount into a voltage value and output. In addition, as shown in Fig. 14, the light receiving section 51i of the image pickup element 51 is provided with a plurality of segments corresponding to the three primary colors of light, and a color filter arranged in accordance with a predetermined rule is installed so that each light receiving pixel corresponds to a specific color component. In this embodiment, G (green) and R (red) segments' are alternately arranged on the singular line, and B (blue) and G segments are alternately arranged on the even line.

於驅動電路52分別具有依共通基準時脈動作之垂直時 脈發生部52 v，儲存時脈發生部52 s及水平時脈發生部 52h。在垂直時脈發生部52v發生排出時脈φ(ΐ及垂直轉送 時脈Φν ’供於攝像元件51之受光部51i。因此可排出餘存 在受光部51i各受光像素之資訊電荷，之後，經預定時間L 後，重新儲存之資訊電荷，由受光部51i轉送至儲存部 51s。由儲存時脈發生部52s產生儲存轉送時脈，供於 攝像元件51之儲存部51s。由此，將受光部51i轉送輸出之Each of the driving circuits 52 includes a vertical clock generating section 52 v that operates in accordance with a common reference clock, a storage clock generating section 52 s, and a horizontal clock generating section 52 h. The discharge clock φ (ΐ and the vertical transfer clock Φν 'are supplied to the light receiving section 51i of the imaging element 51 in the vertical clock generating section 52v. Therefore, the information charges of the light receiving pixels remaining in the light receiving section 51i can be discharged. After time L, the information charge re-stored is transferred from the light receiving section 51i to the storage section 51s. The storage clock generating section 52s generates the storage transfer clock for the storage section 51s of the image sensor 51. Thus, the light receiving section 51i Forwarding output

A32873 五、發明說明（18)A32873 V. Description of Invention (18)

資訊電荷取進於儲存部51s，同時，從儲存部51s以1行單 位轉送至水平轉送部51h。又於儲存時脈產生部52s係依後 述時序控制電路57之指令，從完成取進資訊電荷於儲存部 51s時至開始向水平轉送部5ih轉送為止’將空下預定期間 E。因此，於該期間E時，有因暗電流產生之電荷（暗電流 電荷）混入儲存部51s保持之資訊電荷内者^在水平時脈產 生部52h產生水平轉送時脈φη，供於攝像元件51之水平轉 送部51h。於是，從儲存部515以1行單位轉送輸出之資訊 電荷係以_列轉送輪出於輪出部51d，從輸出部51d輪出之 一畫面分圖像資訊係1行單位連續之圈像訊號I⑴。該圖像 訊號Y〇⑴’係在期間E時在儲存部混入任意產生之暗電流電 荷，故如第15圖所示有暗電流成分作為補償予以加算。The information charge is taken into the storage section 51s, and at the same time, it is transferred from the storage section 51s to the horizontal transfer section 51h in one line unit. In addition, the storage clock generation unit 52s is vacated for a predetermined period E from the completion of taking in information charges in the storage unit 51s to the start of the transfer to the horizontal transfer unit 5ih according to the instructions of the timing control circuit 57 described later. Therefore, during the period E, the electric charge (dark current charge) generated by the dark current is mixed into the information charge held by the storage section 51s ^ The horizontal clock generation section 52h generates a horizontal transfer clock φη for the imaging element 51 Horizontal transfer section 51h. Therefore, the information charge transmitted and output in the unit of one line from the storage unit 515 is in the _row transfer wheel out of the output unit 51d, and one screen of image information is output from the output unit 51d. The image information is a continuous circle image signal in one row. I⑴. This image signal Y0⑴ ′ is mixed with an arbitrarily generated dark current charge in the storage section during the period E, so the dark current component is added as compensation as shown in FIG. 15.

類比處理電路53對從攝影元件51輪入之圖像訊號γ〇⑴ 施行樣品持留等之類比系統之訊號處理，以產生圖像訊號 乙⑴° A/D變換電路54係將由類比處理電路53輸入之圖像訊 號¥!⑴使之同步於類比處理電路53之動作時序，以作數位 變換’而產生圖像資料0!⑷。數位處理電路55係連接於a/d 變換電路54 ’對由A/D變換電路54輸入之圖像資料DUn)，施 行色分離及矩陣演算等處理’以產生對應於光之三原色之 3種色成分資料R(n) ’ G(n)，B(n)。若須對應於如第14圖 所示之濾色鏡時’可由單數列舆變數列各分配一像素方式 獲得R，G及B之各成分。又於各行中無法獲得之色成分， 可在其上下行獲得之色成分予以平均化而得之β為要施行 該色演算處理’在數位訊號處理電路55中，可構成3行Χ3The analog processing circuit 53 performs the signal processing of an analog system such as sample hold on the image signal γ〇⑴ from the photographic element 51 to generate an image signal. The A / D conversion circuit 54 will be input by the analog processing circuit 53 The image signal ¥! ⑴ is synchronized with the operation timing of the analog processing circuit 53 for digital transformation to generate image data 0! ⑷. The digital processing circuit 55 is connected to the a / d conversion circuit 54 'for image data DUn input from the A / D conversion circuit 54 and performs processing such as color separation and matrix calculation' to generate three colors corresponding to the three primary colors of light Composition information R (n) 'G (n), B (n). If it is necessary to correspond to the color filter shown in FIG. 14 ', each component of R, G, and B can be obtained by assigning a pixel to each of the singular and variable variables. In addition, color components that cannot be obtained in each line, and the color components that can be obtained in the upper and lower lines are averaged. Β is to be performed. The color calculation processing is performed in the digital signal processing circuit 55, which can be composed of 3 × 3.

C:\Program Files\Patent\310654.ptd 第 21 頁 五、發明說明（19) 列之空間濾色鏡。C: \ Program Files \ Patent \ 310654.ptd Page 21 V. The space color filter in column (19) of the invention description.

二進位化電路5 6係將從數位處理電路5 5輸入之色成分 資料R(n)，G(n)，B(n)與一定之判定基準值比較予以二進 位化，而產生二進位資料r(n)，g(n)，b(n) β該二進位資 料r(n)，g(n)，b(n)係同步於媒動電路52之水平轉送時脈 Φΐι，分別以1位元輸出。在該二進位化電路56中，將色成 分資料R(n)，G(n)，Β(η)與一定之判定基準值單純地比 較，依大小而產生二進位資料r(n)，g(n)，b(n)。然而， 於色成分資料R(n)，G(n)，B(n)中，含有攝像元件51之儲 存部51’s於期間3E内任意發生之暗電流電荷，故暗電流成 分與高頻振動矩陣有同等作用。 時序控制電路57係相應於控制全體裝置之CPU(未圖 示）指令而控制各部動作。該時序控制電路5 7從CPU接收儲 存控制指令時，對驅動電路52之儲存時脈發生部52s，設 定完成儲存部51s取進資訊電荷後，開始向水平轉送部51h 轉送為止之期間E »該期間E，係依圖像訊號γβ⑴之平均水 準設定’以使照圖像訊號YD⑴各色成分資料R(n)，G(n)， B(n)予以二進位化時，不會發生判定結果之偏倚βThe binary circuit 5 6 is a binary data which is obtained by comparing the color component data R (n), G (n), and B (n) input from the digital processing circuit 55 with a certain judgment reference value, thereby generating binary data. r (n), g (n), b (n) β The binary data r (n), g (n), b (n) are synchronized to the horizontal transfer clock Φΐι of the median circuit 52, which are respectively 1 Bit output. This binary circuit 56 simply compares the color component data R (n), G (n), B (η) with a certain determination reference value, and generates binary data r (n), g according to the size. (n), b (n). However, in the color component data R (n), G (n), and B (n), the storage portion 51's containing the imaging element 51 has a dark current charge arbitrarily generated in the period 3E, so the dark current component and the high-frequency vibration matrix Have the same effect. The timing control circuit 57 controls the operation of each unit in response to a CPU (not shown) instruction that controls the entire device. When the timing control circuit 57 receives a storage control command from the CPU, the storage clock generator 52s of the drive circuit 52 is set to set the period from when the storage unit 51s has taken in the information charge and then starts to transfer to the horizontal transfer unit 51h. E »This The period E is set according to the average level of the image signal γβ ', so that when the component image data R (n), G (n), and B (n) of the image signal YD⑴ are binarized, no judgment result will occur. Bias β

以二進位化電路56產生之壓縮資料r(n)，g(n)，b(n) 係記錄於非揮發型記憶體或以磁片等代表之大容量記錄媒 體’或供於顯示機器及印字機器。如上述輪岀之壓縮資料 r(n)，g(n)，b(n)能使用於與構成一畫面之像素數同等規 模之高頻振動矩陣，二進位化時再生之同等畫質圖像。 如依本發明，得以變更動作時序，而不必追加電路構The compressed data r (n), g (n), and b (n) generated by the binary circuit 56 are recorded in a non-volatile memory or a large-capacity recording medium represented by a magnetic disk or the like, or provided to a display device and Printing machine. For example, the compressed data r (n), g (n), and b (n) of the above rounds can be used in a high-frequency vibration matrix of the same size as the number of pixels constituting a screen. . According to the present invention, it is possible to change the operation timing without adding a circuit configuration.

C:\ProgramFiles\Pateiit\310654.ptd 第 22 頁 432873 五、發明說明（20) 成之狀態下’實現模擬高頻振動處理，以低成本實現攝像 系統。該攝像裝置可適用於簡易型監視用照相機及玩具 等。 、 又’因從攝像元件讀出資訊電荷之時序遲延，雖使圖 像資料含有之暗電流成分增加’可變更二進位化處理時之 判定基準值得容易地抵銷暗電流成分之增加。 [圖式之簡單說明] 第1圖係顢示f用攝像裝置之構成方塊圖。 第2圖係說明習用攝像裝置之動作時序圖。 第3圖係顯示第1實施例之構成方塊囷。 第4圖係顯示濾色銳構成例之模式圖。 第5圖係顯示二進位化資料之時序圈。 第6圖係顯示第2實施例之構成方塊圖。 第7圖係顯示壓縮資料之時序圖。 第8圖係顢示第3實施例之構成方塊圖。 第9圖係顯示濾色銳構成例之模式Μ。 第10圖係顯示抽樣訊號之時序圖。 第11圖係類示矩陣產生成電路及高頻振動電路之構成 方塊圖。 第12圓係顯示第4實施例之構成方塊圈。 第13圖係顯示第4實施例之動作時序圈。 第14圈係顯示濾色鏡構成例之棋式圖》 第15圓係顯示圖像訊號之睛電流成分波形圖。 [符號之說明]C: \ ProgramFiles \ Pateiit \ 310654.ptd Page 22 432873 V. Description of the invention (20) In the completed state, ‘realize high-frequency vibration simulation, and realize the camera system at low cost. This imaging device can be applied to simple surveillance cameras and toys. "Because the timing of the information charge read from the imaging element is delayed, although the dark current component contained in the image data is increased", the determination criterion at the time of binary processing can be changed to easily offset the increase of the dark current component. [Brief Description of the Drawings] FIG. 1 is a block diagram showing the configuration of the imaging device for f. FIG. 2 is a timing chart illustrating the operation of a conventional imaging device. Fig. 3 is a block diagram showing the constitution of the first embodiment. FIG. 4 is a schematic diagram showing an example of a sharp filter configuration. Figure 5 shows the timing circle of binary data. Fig. 6 is a block diagram showing the structure of the second embodiment. Figure 7 is a timing diagram showing the compressed data. Fig. 8 is a block diagram showing the structure of the third embodiment. FIG. 9 shows a mode M of an example of sharp filter configuration. Figure 10 is a timing diagram showing the sampling signal. Fig. 11 is a block diagram showing the structure of a matrix generating circuit and a high-frequency vibration circuit. The twelfth circle is a block circle constituting the fourth embodiment. Fig. 13 is a timing chart showing the operation sequence of the fourth embodiment. The 14th circle is a checker diagram showing an example of the color filter configuration. The 15th circle is a waveform diagram of the current component of the image signal. [Explanation of symbols]

C:\Program Files\Patent\310654.ptd 432873 案號邱108802 ?^年/£?月少7曰 修正 5*、發明說明 (21) 1，11，21，31，51 攝像元件 2, 1 之，22, 32, 52 驅動電路 3, 1 3, 23, 33, 53 類比處理電路 4, 14, 24, 34, 54 A/D變換電路 5, 1 5, 25, 35, 55 數位處理電路 6 記憶體控制電路 7 幘記憶體 8, 17, 27 CPU 9, 18, 28 圖像資料記憶體 16, 26, 36 矩陣產生電路 37 高頻振動電路 38, 57 時序控制電路 41 暗電路檢測部 42 矩陣部 43 峰值檢測部 44 差分檢測部 45 乘法器 46 加法器 47 二進位化部 5 Id 輸出部 51h 水平轉送部 51i 受光部 51s 儲存部 52v 垂蕈時脈發生部 52h 水平時脈發生部 52s 儲存時脈發生部C: \ Program Files \ Patent \ 310654.ptd 432873 Case No. Qiu 108802 ^ year / £? Month 7th amendment 5 *, invention description (21) 1, 11, 21, 31, 51 camera element 2, 1 of ， 22, 32, 52 Driving circuit 3, 1 3, 23, 33, 53 Analog processing circuit 4, 14, 24, 34, 54 A / D conversion circuit 5, 1 5, 25, 35, 55 Digital processing circuit 6 Memory Body control circuit 7 Memory 8, 17, 27 CPU 9, 18, 28 Image data memory 16, 26, 36 Matrix generation circuit 37 High-frequency vibration circuit 38, 57 Timing control circuit 41 Dark circuit detection section 42 Matrix section 43 Peak detection section 44 Differential detection section 45 Multiplier 46 Adder 47 Binary section 5 Id Output section 51h Horizontal transfer section 51i Light receiving section 51s Storage section 52v Weeping clock generation section 52h Horizontal clock generation section 52s Stored clock Occurrence department

C:\PFOgiam FiIesWteiitV310654rptc 第 24 頁 2000.10.27. G24C: \ PFOgiam FiIesWteiitV310654rptc Page 24 2000.10.27. G24

Claims (1)

^3287 3 ^ ----- 案號88108802_好年々月知曰 條正 1 '--」" · — ' " f 'λ、申請專利範固 I 一種攝像裝置，談攝像裝置係在攝取被攝體圖像，以 每1畫两單位纪憶圖像資料之攝俸裝置中，具備： 以行列配對應於特定色成分之複數個受光像素， 在各受光像素依各色成分獨立儲存的資訊電荷之固艘 褫像元件； 將儲存於上述阖體攝像元件之务受光像素之資訊 電荷，依序轉送輸出以獲得圈像訊號之驅動電略； 依上述圖像訊號產生對應於先之三原色之第丨至第 3之圖像資料之訊號處理電路； 將上述第1至第3之圖像資料分別予以二進位化， 以產生各別以1位元表示之第1至第3之二進位資料之二 進位化電路，及 連接於記偉體，以取進上述第1至第3之二進位資 料而記憶在上述記憶體之同時，將記憶在上述記憶體 之上述第1至第3之二進位資料予以讀出而輸出之控制 電路等者。 2.如申請專利範圍第1項記載之攝像裝置，其中係於上述 二進位化電路包含高頻振動處理者。 3* 一種攝像裝置，該攝像裝置係在攝取被攝體阖像，以 每1畫面單位記億圏像資料之攝像裝置中，具備： 以行列配置複數之受光像素，對各受光像素餺存 資訊電荷之固體攝像元件： 將上述©髏攝像元件各受光像素儲存之資訊電荷 依轉送輸出以獲得鼢像訊號之联動電路；^ 3287 3 ^ ----- Case No. 88108802_Good Year's Day and Month Knowing Article 1 "-" " ·-'" f' λ, patent application Fangu I A camera device, talking about the camera device A photographing device that captures an image of a subject and draws two units of chronicle image data per one includes: arranging a plurality of light-receiving pixels corresponding to a specific color component in rows and columns, and independently storing the light-receiving pixels according to each color component Information charge of the fixed image element; The information charge of the light receiving pixel stored in the above-mentioned body imaging element is sequentially transmitted and output to obtain the driving signal of the circle image signal; the corresponding three primary colors are generated according to the above image signal Signal processing circuits for the image data of the 丨 to the 3rd; Binary the image data of the 1st to the 3rd to generate the 1st to the 3rd digit represented by 1 bit respectively The data binary circuit and the circuit connected to Jiwei body, in order to take in the above-mentioned first to third binary data and memorize it in the above-mentioned memory, and then memorize it in the above-mentioned first to third of the memory Binary data is read and output Control circuit, etc. 2. The imaging device according to item 1 of the scope of patent application, wherein the binary circuit includes a high-frequency vibration processor. 3 * An image pickup device which captures the image of the subject and records the image data of one hundred million images per one screen unit, and includes: a plurality of light receiving pixels arranged in rows and columns, and information is stored for each light receiving pixel Charged solid-state imaging element: A linkage circuit that transfers the information charge stored in each photo-receiving pixel of the above-mentioned imaging element to obtain an image signal; 峨87 3E 87 3 依上述圖像訊號產生圖像資料之訊號夷理電路； 壓縮上逮圈像資料產生壓縮資料之壓縮電路，及 連接於記憶體，以取進上述壓縮資料記偉在上述 纪憶鎳之同時，讀出記憶在上述記憶體内之上述塵縮 資料予以輸出之掠制電路，而且 上述控制電路係相應於上迷壓縮資料對上述記愧 艘之寫入速度設定上述媒動電路之動作時序者。 4，如申請利專利範薗第3項記載之攝像裝置，其中，上述 控制電路係相應於將上述壓縮資料窝入上迷記憶體之 寫入速度設定上述驅動電路之動作時序與上述訊號處 理電路之動作時序者。 5· —種攝像裝置，該攝像裝置係在攝取被攝艟阃像，以 每1畫面單位記憶圖像資料之攝像裝置中，具備： 以行列配置且以光電變換產生資訊電荷分別獨立 储存的複數個受光像素’至少有一部分受光像素被遮 光之固體攝像元件； 將上述固體攝像元件各受光像素儲存的資訊電荷 以預定幀序轉送輸出而得到鷗像訊號之驅動電路； 依上述圏像訊號’產生對應於上述複數各受光像 素之圖像資枓之訊號處理電路； 依對應於上述固體攝像元件被遮光之上述一部分 之受光像素之圈像資料產生高頻振動矩陣之矩陣生成 電路，及 參照上述高頻振動矩陣將上述圖像資料予以二進A signal processing circuit for generating image data according to the above image signal; a compression circuit for generating compressed data by compressing the upper circle image data, and a circuit connected to the memory to take in the compressed data and record it at the same time as the above-mentioned Ji Ni A fetching circuit for outputting the dust shrinkage data stored in the memory, and the control circuit is to set the operation timing of the media motion circuit corresponding to the writing speed of the compressed data to the shame ship. 4. For the camera device described in item 3 of the patent application, wherein the control circuit is to set the operation timing of the drive circuit and the signal processing circuit corresponding to the writing speed of embedding the compressed data into the memory of the fan. The sequence of actions. 5 · —A kind of image pickup device, which is an image pickup device that captures a photographic image and stores image data in each frame unit, and includes: a plurality of information arranged in rows and columns and independently generated by photoelectric conversion to store information charges. A light-receiving pixel 'at least a part of the light-receiving pixel is a solid-state image pickup element; the information charge stored in each light-receiving pixel of the solid-state image pickup element is transmitted and output in a predetermined frame order to obtain a gull image signal driving circuit; generated according to the aforementioned image signal' A signal processing circuit corresponding to the image data of each of the plurality of light-receiving pixels; a matrix generation circuit for generating a high-frequency vibration matrix based on the circle image data of the light-receiving pixels corresponding to the part of the solid-state imaging element that is shielded from light; Frequency vibration matrix binarizes the above image data 432§7§432§7§ 仇化之二進位化電路者。 6，如申請專利範面第5項記載之攝像裝置，其中，上述矩 陣產生電路译具有：將上述圈像資料以對應於上述固 饈攝像元件遮光區域之時序取進以產生暗電流資料之 暗電流檢測部’及配列上述暗笮流資料以產生至少一 行分高頻振動矩陣之矩陣部者。 7. 如申請專利範固第6項記載之攝像裝置，其中，上逑矩 陣產生電路係再具備：以行單位檢測it上述暗電流資 料之最大值之♦值檢昶出部，及依每一行檢出上述最 大值差分之差分檢測岀部，且相應於上述差分檢測出 電路之檢測結果修正上述高頻振動矩陣者。 / 8. —種攝像裝置’該攝像裝置係在褥取被攝體圖像，以 每一畫面單位記憶圖像資料之攝像裝置中，具備： 以行列配置且以光電變鉍產生資訊電荷分別獨立 鍺存的複數之受光像素之同時’對應各受光像素為行. 列配置之複數儲存像素之幀轉送方式之固艟攝像元件 將上述固艘攝像元件各受光像素所儲其之資訊電 荷轉送至各垂直移位暫存器後，從各垂直移位暫存器 以預定之順序轉送輪出而獲得獼像訊號之驅動電路； 用以控制挺上述攝像元件各受光像素對各垂直移 位暫存器轉送資訊電荷之畸序及由各垂直移位暫存器 資訊電荷之轉送輸出時序之時序控制電路， 依上述圖像訊號，產生分別對應於上述複數受光Vengeful two carry the circuit. 6. The imaging device as described in item 5 of the patent application, wherein the matrix generation circuit has the following information: the circle image data is taken in at a timing corresponding to the light-shielding area of the fixed camera element to generate dark current data. A current detection unit and a matrix unit that arranges the dark current data to generate at least one line of a high-frequency vibration matrix. 7. The imaging device as described in item 6 of the patent application, wherein the upper matrix generating circuit is further provided with: a value detection unit for detecting the maximum value of the above dark current data in units of rows, and each row A differential detection unit that detects the maximum difference and corrects the high-frequency vibration matrix according to a detection result of the differential detection circuit. / 8. —A kind of camera device 'The camera device is an image pickup device that takes an image of a subject on a mattress and stores image data in each frame unit, and includes: arranged in rows and columns and generating information charges independently by photoelectric conversion of bismuth At the same time, the plurality of light-receiving pixels stored in germanium correspond to each light-receiving pixel as a row. The solid-state image pickup element of the frame transfer method of the plurality of storage pixels arranged in a row transfers the information charge stored in each light-receiving pixel of the above-mentioned image pickup element to each After the vertical shift register, a driving circuit is obtained from each of the vertical shift registers in a predetermined order to obtain the image signal; it is used to control the vertical shift registers of the light receiving pixels of the image pickup element. A timing control circuit that transfers the abnormal order of the information charge and the timing of the transfer output of the information charge of each vertical shift register, according to the above-mentioned image signal, generates a plurality of corresponding light receiving 432873 案號8S108802_年A月彡修正_ 六、申請專利範圍 像素產生圖像資料之訊號處理電路；及 將上述圖像資料與一定判定基準值比較而予以二 進位化之二進位化電路，而且 上述時序控制電路，係在對各垂直移位暫存器轉 送完上述資訊電荷至將上述資訊電荷開始轉送輸岀止 之期間内，保持預定時間間隔且於上述資訊電荷重疊 由暗電流發生之電荷者。 a.如申請專利範園第8項記載之攝像裝置，其中*上述固 體攝像元件係包含對應於上述複數受光像素，而配置 由光之三原色所成之複數片段之遽色鏡者。432873 Case No. 8S108802_A month 年 Amendment_ VI. Signal processing circuit for applying patents to generate image data for pixels; and a binary circuit for comparing the above image data with a certain judgment reference value and binarizing it, and The above-mentioned timing control circuit is a period in which the information charge is transferred from each vertical shift register to the time when the information charge starts to be transferred, and the predetermined time interval is maintained and the information charge overlaps with the charge generated by the dark current. By. a. The imaging device described in item 8 of the patent application park, wherein * the solid-state imaging element includes a chromatic mirror corresponding to the above-mentioned plurality of light-receiving pixels and having a plurality of fragments formed by three primary colors of light.