TW430809B - Semiconductor memory device having twisted bit-line structure - Google Patents

Semiconductor memory device having twisted bit-line structure

Info

Publication number
TW430809B
TW430809B TW087114551A TW87114551A TW430809B TW 430809 B TW430809 B TW 430809B TW 087114551 A TW087114551 A TW 087114551A TW 87114551 A TW87114551 A TW 87114551A TW 430809 B TW430809 B TW 430809B
Authority
TW
Taiwan
Prior art keywords
bit line
semiconductor memory
memory device
line structure
complementary
Prior art date
Application number
TW087114551A
Other languages
English (en)
Inventor
Sang-Seok Kang
Jong-Hyoung Lim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW430809B publication Critical patent/TW430809B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18Bit line organisation; Bit line lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225Shielding layers formed together with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/50Peripheral circuit region structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
TW087114551A 1998-05-12 1998-09-02 Semiconductor memory device having twisted bit-line structure TW430809B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980016966A KR100278656B1 (ko) 1998-05-12 1998-05-12 트위스트된비트라인구조를갖는반도체메모리장치

Publications (1)

Publication Number Publication Date
TW430809B true TW430809B (en) 2001-04-21

Family

ID=19537250

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087114551A TW430809B (en) 1998-05-12 1998-09-02 Semiconductor memory device having twisted bit-line structure

Country Status (4)

Country Link
US (1) US6140704A (zh)
JP (1) JP4513074B2 (zh)
KR (1) KR100278656B1 (zh)
TW (1) TW430809B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112349318A (zh) * 2019-08-07 2021-02-09 美光科技公司 具有位线噪声抑制方案的存储器装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259621B1 (en) * 2000-07-06 2001-07-10 Micron Technology, Inc. Method and apparatus for minimization of data line coupling in a semiconductor memory device
US6500706B1 (en) 2001-03-19 2002-12-31 Taiwan Semiconductor Manufacturing Company Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM
DE10124752B4 (de) * 2001-05-21 2006-01-12 Infineon Technologies Ag Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen
US6894231B2 (en) * 2002-03-19 2005-05-17 Broadcom Corporation Bus twisting scheme for distributed coupling and low power
DE10229163B3 (de) * 2002-06-28 2004-02-05 Infineon Technologies Ag Speicherbaustein mit gekreuzten Bitleitungen und Verfahren zum Auslesen
US7274612B2 (en) 2003-09-19 2007-09-25 International Business Machines Corporation DRAM circuit and its operation method
KR100541818B1 (ko) * 2003-12-18 2006-01-10 삼성전자주식회사 반도체 메모리 장치의 라인 배치구조
US9997242B2 (en) * 2016-10-14 2018-06-12 Arm Ltd. Method, system and device for non-volatile memory device state detection

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105134B2 (ja) * 1987-08-28 1995-11-13 三菱電機株式会社 半導体記憶装置
US5144583A (en) * 1989-01-09 1992-09-01 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device with twisted bit-line structure
JP2953708B2 (ja) * 1989-07-31 1999-09-27 株式会社東芝 ダイナミック型半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
JP2792211B2 (ja) * 1990-07-06 1998-09-03 日本電気株式会社 半導体記憶装置
JP3440335B2 (ja) * 1993-08-18 2003-08-25 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置
JP3672946B2 (ja) * 1993-11-30 2005-07-20 株式会社ルネサステクノロジ 半導体記憶装置
US5485419A (en) * 1994-05-23 1996-01-16 Campbell; John P. Memory device column address selection lead layout
US5949698A (en) * 1998-02-20 1999-09-07 Micron Technology, Inc. Twisted global column decoder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112349318A (zh) * 2019-08-07 2021-02-09 美光科技公司 具有位线噪声抑制方案的存储器装置
CN112349318B (zh) * 2019-08-07 2024-05-07 美光科技公司 具有位线噪声抑制方案的存储器装置

Also Published As

Publication number Publication date
US6140704A (en) 2000-10-31
JP4513074B2 (ja) 2010-07-28
KR100278656B1 (ko) 2001-02-01
KR19990084898A (ko) 1999-12-06
JPH11328949A (ja) 1999-11-30

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees