TW368731B - Manufacturing method for self-aligned local-interconnect and contact - Google Patents

Manufacturing method for self-aligned local-interconnect and contact

Info

Publication number
TW368731B
TW368731B TW086119492A TW86119492A TW368731B TW 368731 B TW368731 B TW 368731B TW 086119492 A TW086119492 A TW 086119492A TW 86119492 A TW86119492 A TW 86119492A TW 368731 B TW368731 B TW 368731B
Authority
TW
Taiwan
Prior art keywords
self
interconnect
contact
manufacturing
aligned
Prior art date
Application number
TW086119492A
Other languages
English (en)
Inventor
shi-wei Sun
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW086119492A priority Critical patent/TW368731B/zh
Priority to US09/035,347 priority patent/US5899742A/en
Priority to DE19814869A priority patent/DE19814869C2/de
Priority to JP10092062A priority patent/JP2999172B2/ja
Priority to FR9804236A priority patent/FR2772985B1/fr
Application granted granted Critical
Publication of TW368731B publication Critical patent/TW368731B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
TW086119492A 1997-12-22 1997-12-22 Manufacturing method for self-aligned local-interconnect and contact TW368731B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW086119492A TW368731B (en) 1997-12-22 1997-12-22 Manufacturing method for self-aligned local-interconnect and contact
US09/035,347 US5899742A (en) 1997-12-22 1998-03-05 Manufacturing method for self-aligned local interconnects and contacts simultaneously
DE19814869A DE19814869C2 (de) 1997-12-22 1998-04-02 Herstellungsverfahren für selbstausgerichtete lokale interne Verbindungen und Kontakte
JP10092062A JP2999172B2 (ja) 1997-12-22 1998-04-03 自己整合された局所的相互接続及びコンタクトを行うための製造方法
FR9804236A FR2772985B1 (fr) 1997-12-22 1998-04-06 Procede de fabrication pour des interconnexions locales et des contacts auto-alignes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086119492A TW368731B (en) 1997-12-22 1997-12-22 Manufacturing method for self-aligned local-interconnect and contact

Publications (1)

Publication Number Publication Date
TW368731B true TW368731B (en) 1999-09-01

Family

ID=21627462

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086119492A TW368731B (en) 1997-12-22 1997-12-22 Manufacturing method for self-aligned local-interconnect and contact

Country Status (5)

Country Link
US (1) US5899742A (zh)
JP (1) JP2999172B2 (zh)
DE (1) DE19814869C2 (zh)
FR (1) FR2772985B1 (zh)
TW (1) TW368731B (zh)

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US6033962A (en) * 1998-07-24 2000-03-07 Vanguard International Semiconductor Corporation Method of fabricating sidewall spacers for a self-aligned contact hole
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US6486060B2 (en) * 1998-09-03 2002-11-26 Micron Technology, Inc. Low resistance semiconductor process and structures
US6759315B1 (en) 1999-01-04 2004-07-06 International Business Machines Corporation Method for selective trimming of gate structures and apparatus formed thereby
US6207514B1 (en) * 1999-01-04 2001-03-27 International Business Machines Corporation Method for forming borderless gate structures and apparatus formed thereby
KR100281124B1 (ko) * 1999-01-20 2001-01-15 김영환 반도체소자 및 그의 제조방법
US6150223A (en) * 1999-04-07 2000-11-21 United Microelectronics Corp. Method for forming gate spacers with different widths
US6177304B1 (en) * 1999-04-26 2001-01-23 Chartered Semiconductor Manufacturing Ltd. Self-aligned contact process using a poly-cap mask
KR100518530B1 (ko) * 1999-06-17 2005-10-04 삼성전자주식회사 보더리스 콘택홀을 갖는 반도체 소자 및 그 제조방법
US6630718B1 (en) 1999-07-26 2003-10-07 Micron Technology, Inc. Transistor gate and local interconnect
US6228761B1 (en) * 1999-10-14 2001-05-08 Advanced Micro Devices, Inc. Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide
US6225216B1 (en) * 1999-10-15 2001-05-01 Advanced Micro Devices, Inc. Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide
US6441418B1 (en) 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction
US6551923B1 (en) * 1999-11-01 2003-04-22 Advanced Micro Devices, Inc. Dual width contact for charge gain reduction
US6245651B1 (en) * 2000-01-12 2001-06-12 Intenational Business Machines Corporation Method of simultaneously forming a line interconnect and a borderless contact to diffusion
US6274409B1 (en) * 2000-01-18 2001-08-14 Agere Systems Guardian Corp. Method for making a semiconductor device
US6376298B1 (en) * 2000-01-31 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Layout method for scalable design of the aggressive RAM cells using a poly-cap mask
US6335249B1 (en) 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
US6534389B1 (en) 2000-03-09 2003-03-18 International Business Machines Corporation Dual level contacts and method for forming
KR100370129B1 (ko) 2000-08-01 2003-01-30 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
US6426263B1 (en) * 2000-08-11 2002-07-30 Agere Systems Guardian Corp. Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain
US6392922B1 (en) * 2000-08-14 2002-05-21 Micron Technology, Inc. Passivated magneto-resistive bit structure and passivation method therefor
US6535413B1 (en) * 2000-08-31 2003-03-18 Micron Technology, Inc. Method of selectively forming local interconnects using design rules
US6835985B2 (en) * 2000-12-07 2004-12-28 Chartered Semiconductor Manufacturing Ltd. ESD protection structure
US6680514B1 (en) * 2000-12-20 2004-01-20 International Business Machines Corporation Contact capping local interconnect
KR100408414B1 (ko) * 2001-06-20 2003-12-06 삼성전자주식회사 반도체 소자 및 그 제조방법
US6730553B2 (en) * 2001-08-30 2004-05-04 Micron Technology, Inc. Methods for making semiconductor structures having high-speed areas and high-density areas
US6673715B2 (en) * 2001-10-24 2004-01-06 Micron Technology, Inc. Methods of forming conductive contacts
KR100400319B1 (ko) * 2001-11-01 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 콘택 제조방법
US6783995B2 (en) * 2002-04-30 2004-08-31 Micron Technology, Inc. Protective layers for MRAM devices
US6940134B2 (en) * 2002-07-02 2005-09-06 International Business Machines Corporation Semiconductor with contact contacting diffusion adjacent gate electrode
ITTO20021118A1 (it) * 2002-12-24 2004-06-25 St Microelectronics Srl Dispositivo mos e procedimento di fabbricazione di
KR100517555B1 (ko) * 2003-01-02 2005-09-28 삼성전자주식회사 살리사이드층을 포함하는 반도체 소자 및 그 제조방법
US7126200B2 (en) * 2003-02-18 2006-10-24 Micron Technology, Inc. Integrated circuits with contemporaneously formed array electrodes and logic interconnects
JP2004266001A (ja) * 2003-02-28 2004-09-24 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US7119024B2 (en) * 2003-07-10 2006-10-10 Micron Technology, Inc. Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device
JP4340248B2 (ja) * 2005-03-17 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体撮像装置を製造する方法
US20070093055A1 (en) * 2005-10-24 2007-04-26 Pei-Yu Chou High-aspect ratio contact hole and method of making the same
US8222746B2 (en) * 2006-03-03 2012-07-17 Intel Corporation Noble metal barrier layers
US7670946B2 (en) * 2006-05-15 2010-03-02 Chartered Semiconductor Manufacturing, Ltd. Methods to eliminate contact plug sidewall slit
KR100889313B1 (ko) * 2007-07-20 2009-03-18 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8536656B2 (en) * 2011-01-10 2013-09-17 International Business Machines Corporation Self-aligned contacts for high k/metal gate process flow
US20130193516A1 (en) * 2012-01-26 2013-08-01 Globalfoundries Inc. Sram integrated circuits and methods for their fabrication
US9721956B2 (en) * 2014-05-15 2017-08-01 Taiwan Semiconductor Manufacturing Company Limited Methods, structures and devices for intra-connection structures
US9799567B2 (en) * 2014-10-23 2017-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming source/drain contact
CN108389906B (zh) * 2017-02-03 2023-01-10 联华电子股份有限公司 高压金属氧化物半导体晶体管元件
KR102451171B1 (ko) * 2018-01-25 2022-10-06 삼성전자주식회사 반도체 소자

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EP0362571A3 (en) * 1988-10-07 1990-11-28 International Business Machines Corporation Method for forming semiconductor components
US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
DE69211329T2 (de) * 1992-03-27 1996-11-28 Ibm Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur
DE4219529C2 (de) * 1992-06-15 1994-05-26 Itt Ind Gmbh Deutsche Verfahren zur Herstellung von Halbleiterbauelementen in CMOS-Technik mit "local interconnects"
US5541427A (en) * 1993-12-03 1996-07-30 International Business Machines Corporation SRAM cell with capacitor
US5654589A (en) * 1995-06-06 1997-08-05 Advanced Micro Devices, Incorporated Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application
JPH0955440A (ja) * 1995-08-17 1997-02-25 Sony Corp 半導体装置及び半導体装置の製造方法
JP2765544B2 (ja) * 1995-12-26 1998-06-18 日本電気株式会社 半導体装置の製造方法
US5668065A (en) * 1996-08-01 1997-09-16 Winbond Electronics Corp. Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects
US5807779A (en) * 1997-07-30 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process

Also Published As

Publication number Publication date
DE19814869C2 (de) 2001-10-04
FR2772985B1 (fr) 2000-05-26
FR2772985A1 (fr) 1999-06-25
JP2999172B2 (ja) 2000-01-17
JPH11191623A (ja) 1999-07-13
DE19814869A1 (de) 1999-07-01
US5899742A (en) 1999-05-04

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MM4A Annulment or lapse of patent due to non-payment of fees