TW348301B - Method for the production of a DRAM cell arrangement - Google Patents

Method for the production of a DRAM cell arrangement

Info

Publication number
TW348301B
TW348301B TW086111372A TW86111372A TW348301B TW 348301 B TW348301 B TW 348301B TW 086111372 A TW086111372 A TW 086111372A TW 86111372 A TW86111372 A TW 86111372A TW 348301 B TW348301 B TW 348301B
Authority
TW
Taiwan
Prior art keywords
cell arrangement
dram cell
whose
production
produced
Prior art date
Application number
TW086111372A
Other languages
English (en)
Inventor
Rosener Wolfgang
Risch Lothar
Hofmann Franz
Stengl Reinhard
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of TW348301B publication Critical patent/TW348301B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
TW086111372A 1996-09-13 1997-08-08 Method for the production of a DRAM cell arrangement TW348301B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19637389A DE19637389C1 (de) 1996-09-13 1996-09-13 Verfahren zur Herstellung einer DRAM-Zellenanordnung

Publications (1)

Publication Number Publication Date
TW348301B true TW348301B (en) 1998-12-21

Family

ID=7805577

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086111372A TW348301B (en) 1996-09-13 1997-08-08 Method for the production of a DRAM cell arrangement

Country Status (5)

Country Link
US (1) US6037209A (zh)
EP (1) EP0925607B1 (zh)
DE (2) DE19637389C1 (zh)
TW (1) TW348301B (zh)
WO (1) WO1998011604A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19805712A1 (de) * 1998-02-12 1999-08-26 Siemens Ag Speicherzellenanordnung und entsprechendes Herstellungsverfahren
EP0945901A1 (de) * 1998-03-23 1999-09-29 Siemens Aktiengesellschaft DRAM-Zellenanordnung mit vertikalen Transistoren und Verfahren zu deren Herstellung
KR100396387B1 (ko) * 1998-03-24 2003-09-03 인피니언 테크놀로지스 아게 저장 셀 장치 및 그 제조 방법
JP3390704B2 (ja) * 1999-08-26 2003-03-31 株式会社半導体理工学研究センター 強誘電体不揮発性メモリ
JP3655175B2 (ja) * 2000-06-30 2005-06-02 株式会社東芝 半導体記憶装置の製造方法
US6566219B2 (en) 2000-09-22 2003-05-20 Infineon Technologies Ag Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening
US7355230B2 (en) * 2004-11-30 2008-04-08 Infineon Technologies Ag Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
KR101116360B1 (ko) 2010-06-04 2012-03-09 주식회사 하이닉스반도체 매립비트라인을 구비한 반도체장치 및 그 제조 방법
US8786014B2 (en) * 2011-01-18 2014-07-22 Powerchip Technology Corporation Vertical channel transistor array and manufacturing method thereof
KR101902486B1 (ko) 2012-05-16 2018-11-13 삼성전자주식회사 Ｍｏｓ 트랜지스터
JP2021174911A (ja) * 2020-04-28 2021-11-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357131A (en) * 1982-03-10 1994-10-18 Hitachi, Ltd. Semiconductor memory with trench capacitor
JPS6021558A (ja) * 1983-07-15 1985-02-02 Mitsubishi Electric Corp バイポ−ラ型半導体集積回路装置
GB2297648B (en) * 1991-08-31 1996-10-23 Samsung Electronics Co Ltd Semiconductor device
JP3043135B2 (ja) * 1991-09-26 2000-05-22 新日本製鐵株式会社 不揮発性半導体メモリの製造方法
WO1993012542A1 (en) * 1991-12-13 1993-06-24 Symetrix Corporation Layered superlattice material applications
KR960009998B1 (ko) * 1992-06-08 1996-07-25 삼성전자 주식회사 반도체 메모리장치의 제조방법
KR0140657B1 (ko) * 1994-12-31 1998-06-01 김주용 반도체 소자의 제조방법
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US5793076A (en) * 1995-09-21 1998-08-11 Micron Technology, Inc. Scalable high dielectric constant capacitor
US5554557A (en) * 1996-02-02 1996-09-10 Vanguard International Semiconductor Corp. Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell

Also Published As

Publication number Publication date
DE19637389C1 (de) 1997-10-16
DE59706513D1 (de) 2002-04-04
EP0925607A1 (de) 1999-06-30
WO1998011604A1 (de) 1998-03-19
US6037209A (en) 2000-03-14
EP0925607B1 (de) 2002-02-27

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees