TW348301B - Method for the production of a DRAM cell arrangement - Google Patents
Method for the production of a DRAM cell arrangementInfo
- Publication number
- TW348301B TW348301B TW086111372A TW86111372A TW348301B TW 348301 B TW348301 B TW 348301B TW 086111372 A TW086111372 A TW 086111372A TW 86111372 A TW86111372 A TW 86111372A TW 348301 B TW348301 B TW 348301B
- Authority
- TW
- Taiwan
- Prior art keywords
- cell arrangement
- dram cell
- whose
- production
- produced
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19637389A DE19637389C1 (de) | 1996-09-13 | 1996-09-13 | Verfahren zur Herstellung einer DRAM-Zellenanordnung |
Publications (1)
Publication Number | Publication Date |
---|---|
TW348301B true TW348301B (en) | 1998-12-21 |
Family
ID=7805577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086111372A TW348301B (en) | 1996-09-13 | 1997-08-08 | Method for the production of a DRAM cell arrangement |
Country Status (5)
Country | Link |
---|---|
US (1) | US6037209A (zh) |
EP (1) | EP0925607B1 (zh) |
DE (2) | DE19637389C1 (zh) |
TW (1) | TW348301B (zh) |
WO (1) | WO1998011604A1 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19805712A1 (de) * | 1998-02-12 | 1999-08-26 | Siemens Ag | Speicherzellenanordnung und entsprechendes Herstellungsverfahren |
EP0945901A1 (de) * | 1998-03-23 | 1999-09-29 | Siemens Aktiengesellschaft | DRAM-Zellenanordnung mit vertikalen Transistoren und Verfahren zu deren Herstellung |
KR100396387B1 (ko) * | 1998-03-24 | 2003-09-03 | 인피니언 테크놀로지스 아게 | 저장 셀 장치 및 그 제조 방법 |
JP3390704B2 (ja) * | 1999-08-26 | 2003-03-31 | 株式会社半導体理工学研究センター | 強誘電体不揮発性メモリ |
JP3655175B2 (ja) * | 2000-06-30 | 2005-06-02 | 株式会社東芝 | 半導体記憶装置の製造方法 |
US6566219B2 (en) | 2000-09-22 | 2003-05-20 | Infineon Technologies Ag | Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening |
US7355230B2 (en) * | 2004-11-30 | 2008-04-08 | Infineon Technologies Ag | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
KR101116360B1 (ko) | 2010-06-04 | 2012-03-09 | 주식회사 하이닉스반도체 | 매립비트라인을 구비한 반도체장치 및 그 제조 방법 |
US8786014B2 (en) * | 2011-01-18 | 2014-07-22 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
KR101902486B1 (ko) | 2012-05-16 | 2018-11-13 | 삼성전자주식회사 | Mos 트랜지스터 |
JP2021174911A (ja) * | 2020-04-28 | 2021-11-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357131A (en) * | 1982-03-10 | 1994-10-18 | Hitachi, Ltd. | Semiconductor memory with trench capacitor |
JPS6021558A (ja) * | 1983-07-15 | 1985-02-02 | Mitsubishi Electric Corp | バイポ−ラ型半導体集積回路装置 |
GB2297648B (en) * | 1991-08-31 | 1996-10-23 | Samsung Electronics Co Ltd | Semiconductor device |
JP3043135B2 (ja) * | 1991-09-26 | 2000-05-22 | 新日本製鐵株式会社 | 不揮発性半導体メモリの製造方法 |
WO1993012542A1 (en) * | 1991-12-13 | 1993-06-24 | Symetrix Corporation | Layered superlattice material applications |
KR960009998B1 (ko) * | 1992-06-08 | 1996-07-25 | 삼성전자 주식회사 | 반도체 메모리장치의 제조방법 |
KR0140657B1 (ko) * | 1994-12-31 | 1998-06-01 | 김주용 | 반도체 소자의 제조방법 |
DE19519160C1 (de) * | 1995-05-24 | 1996-09-12 | Siemens Ag | DRAM-Zellenanordnung und Verfahren zu deren Herstellung |
US5793076A (en) * | 1995-09-21 | 1998-08-11 | Micron Technology, Inc. | Scalable high dielectric constant capacitor |
US5554557A (en) * | 1996-02-02 | 1996-09-10 | Vanguard International Semiconductor Corp. | Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell |
-
1996
- 1996-09-13 DE DE19637389A patent/DE19637389C1/de not_active Expired - Fee Related
-
1997
- 1997-07-28 US US09/254,696 patent/US6037209A/en not_active Expired - Lifetime
- 1997-07-28 EP EP97936561A patent/EP0925607B1/de not_active Expired - Lifetime
- 1997-07-28 DE DE59706513T patent/DE59706513D1/de not_active Expired - Fee Related
- 1997-07-28 WO PCT/DE1997/001580 patent/WO1998011604A1/de active IP Right Grant
- 1997-08-08 TW TW086111372A patent/TW348301B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE19637389C1 (de) | 1997-10-16 |
DE59706513D1 (de) | 2002-04-04 |
EP0925607A1 (de) | 1999-06-30 |
WO1998011604A1 (de) | 1998-03-19 |
US6037209A (en) | 2000-03-14 |
EP0925607B1 (de) | 2002-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
HK1003545A1 (en) | Method of making a dram storage cell with vertical transistor | |
ATE222403T1 (de) | Dram-speicherzelle mit vertikalem transistor und verfahren zur herstellung derselben | |
JPS5723261A (en) | Semiconductor memory | |
WO2002011200A8 (de) | Halbleiterspeicher-zellenanordnung und verfahren zu deren herstellung | |
TW348301B (en) | Method for the production of a DRAM cell arrangement | |
JPS57111061A (en) | Semiconductor memory unit | |
RU95107653A (ru) | Полупроводниковое запоминающее устройство с конденсаторами, образованными над и под транзистором ячейки памяти, и способ его изготовления | |
ATE348406T1 (de) | Herstellungsverfahren für eine grabenkondensator- dram-zelle | |
DE3885185D1 (de) | Vertikal-Trench-Transistor-/Kapazitätsspeicherzellen-Struktur und Herstellungsverfahren dafür. | |
EP0344447A3 (en) | Pillar dram cell | |
MY118306A (en) | Self- aligned diffused source vertical transistors with stack capacitors in a 4f- square memory cell array | |
KR890004474B1 (en) | Semiconductor memory device | |
MY117480A (en) | Semiconductor memory device and manufacturing method thereof | |
TW331041B (en) | Semiconductor memory device | |
TW430794B (en) | Ferroelectric memory device and method for operating thereof | |
TW324857B (en) | Strong dielectric memory apparatus capable of decreasing array noise and power consumption | |
DE59109236D1 (de) | DRAM-Zellenstruktur mit Kondensator über Bitleitung und Verfahren zu deren Herstellung | |
ATE131314T1 (de) | Kompakte halbleiterspeicheranordnung und verfahren zu deren herstellung. | |
ATE181450T1 (de) | Sram-speicherzelle | |
TW228594B (zh) | ||
GB1530056A (en) | Semiconductor data storage matrices | |
WO2001041186A3 (de) | Dreitransistor-dram-zelle und dazugehöriges herstellungsverfahren | |
EP0073019A3 (en) | Memory device and process for manufacturing the same | |
JPS6417462A (en) | Read-only memory device | |
KR960008530B1 (en) | Dram cell |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |