TW324824B - Monocrystalline synchronous DRAM system - Google Patents
Monocrystalline synchronous DRAM systemInfo
- Publication number
- TW324824B TW324824B TW086110025A TW86110025A TW324824B TW 324824 B TW324824 B TW 324824B TW 086110025 A TW086110025 A TW 086110025A TW 86110025 A TW86110025 A TW 86110025A TW 324824 B TW324824 B TW 324824B
- Authority
- TW
- Taiwan
- Prior art keywords
- monocrystalline
- synchronous dram
- address
- dram system
- cell array
- Prior art date
Links
- 230000001360 synchronised effect Effects 0.000 title abstract 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19224596A JP3185672B2 (ja) | 1996-07-22 | 1996-07-22 | 半導体メモリ |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW324824B true TW324824B (en) | 1998-01-11 |
Family
ID=16288087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW086110025A TW324824B (en) | 1996-07-22 | 1997-07-15 | Monocrystalline synchronous DRAM system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5852586A (zh) |
| JP (1) | JP3185672B2 (zh) |
| KR (1) | KR100253449B1 (zh) |
| TW (1) | TW324824B (zh) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3871813B2 (ja) * | 1998-08-10 | 2007-01-24 | 株式会社ルネサステクノロジ | マルチポートメモリ、データプロセッサ及びデータ処理システム |
| JP3271591B2 (ja) * | 1998-09-30 | 2002-04-02 | 日本電気株式会社 | 半導体記憶装置 |
| US6373778B1 (en) | 2000-01-28 | 2002-04-16 | Mosel Vitelic, Inc. | Burst operations in memories |
| US6191997B1 (en) | 2000-03-10 | 2001-02-20 | Mosel Vitelic Inc. | Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. |
| US6928026B2 (en) | 2002-03-19 | 2005-08-09 | Broadcom Corporation | Synchronous global controller for enhanced pipelining |
| KR100625294B1 (ko) * | 2004-10-30 | 2006-09-18 | 주식회사 하이닉스반도체 | 전원 공급 제어 회로 및 전원 공급 회로의 제어 방법 |
| JP4703220B2 (ja) * | 2005-03-04 | 2011-06-15 | 株式会社東芝 | 半導体記憶装置 |
| KR100732194B1 (ko) | 2005-10-17 | 2007-06-27 | 삼성전자주식회사 | 메모리 모듈과 메모리 시스템 및 그 제어방법 |
| JP2007183816A (ja) * | 2006-01-06 | 2007-07-19 | Elpida Memory Inc | メモリ制御装置 |
| TWI447728B (zh) * | 2011-03-03 | 2014-08-01 | Mstar Semiconductor Inc | 動態隨機存取記憶體之控制方法及控制器 |
| KR102451156B1 (ko) | 2015-12-09 | 2022-10-06 | 삼성전자주식회사 | 메모리 모듈 내에서 랭크 인터리빙 동작을 갖는 반도체 메모리 장치 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5587962A (en) * | 1987-12-23 | 1996-12-24 | Texas Instruments Incorporated | Memory circuit accommodating both serial and random access including an alternate address buffer register |
| JP2742220B2 (ja) * | 1994-09-09 | 1998-04-22 | 松下電器産業株式会社 | 半導体記憶装置 |
| US5594702A (en) * | 1995-06-28 | 1997-01-14 | National Semiconductor Corporation | Multi-first-in-first-out memory circuit |
| US5537353A (en) * | 1995-08-31 | 1996-07-16 | Cirrus Logic, Inc. | Low pin count-wide memory devices and systems and methods using the same |
| US5666321A (en) * | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
| US5652733A (en) * | 1996-04-29 | 1997-07-29 | Mosaid Technologies Inc. | Command encoded delayed clock generator |
-
1996
- 1996-07-22 JP JP19224596A patent/JP3185672B2/ja not_active Expired - Fee Related
-
1997
- 1997-07-10 US US08/891,193 patent/US5852586A/en not_active Expired - Lifetime
- 1997-07-15 TW TW086110025A patent/TW324824B/zh active
- 1997-07-21 KR KR1019970034019A patent/KR100253449B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1040677A (ja) | 1998-02-13 |
| KR100253449B1 (ko) | 2000-05-01 |
| US5852586A (en) | 1998-12-22 |
| KR980010801A (ko) | 1998-04-30 |
| JP3185672B2 (ja) | 2001-07-11 |
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