TW293122B - - Google Patents

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Publication number
TW293122B
TW293122B TW085105311A TW85105311A TW293122B TW 293122 B TW293122 B TW 293122B TW 085105311 A TW085105311 A TW 085105311A TW 85105311 A TW85105311 A TW 85105311A TW 293122 B TW293122 B TW 293122B
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TW
Taiwan
Prior art keywords
memory cell
sense amplifier
columns
cell arrays
data
Prior art date
Application number
TW085105311A
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Chinese (zh)
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Nippon Electric Co
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Publication of TW293122B publication Critical patent/TW293122B/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Description

A7 B7 五、發明説明（，） 發明背軎 經濟部中央樣準局貝工消費合作社印製 發 明 領 城 本 發 明 有 關 於 一 種 半 導 體 記 億 元 件 9 持 別 是 一 種 具 有 共 用 型 威 測 放 大 器 之 動 態 隨 機 存 取 記 憶 體 (DRAM )元件 Ο 相 顒 技 術 說 明 在 第 一 個 已 往 技 術 之 DRAM元件 中 ， 使 用 單 層 鋁 之 技 術 製 造 > 設 置 許 多 區 塊 9 各 區 塊 有 兩 個 記 億 UO 早 元 陣 列 > 兩 列 感 測 放 大 器 9 及 在 兩 列 感 測 放 大 器 之 間 的 行 解 碼 器 0 各 感 測 放 大 器 直 接 連 至 一 資 料 放 大 器 9 資 料 放 大 器 則 連 至 一 輸 入 / 輸 出 缓 衝 器 0 因 此 由 於 感 測 放 大 器 各 列 與 資 料 放 大 器 之 間 的 連 線 可 以 縮 短 9 所 以 可 以 改 進 讀 取 速 度 待 性 及 讀 取 作 業 邊 限 特 性 9 此 將 於 稍 後 詳 述 〇 但 在 上 述 第 一 個已往技術之DRAM元件 中 9 因 為 對 於 每 一 個 區 塊 設 置 一 行 解 碼 器 > 於 是 積 體 性 降 低 Ο 在 第 二 m 已 往 技 術 之 DRAM元件 中 1 使 用 雙 層 鋁 之 技 術 製 造 9 感 測 放 大 器 各 列 以 共 用 型 感 測 放 大 器 形 成 9 且 設 置 一 行 解 碼 器 供 所 有 區 塊 共 用 1 於 是 增 加 了 積 體 性 9 此 亦 將 於 稍 後 詳 述 〇 但 在 上 述 第 二 個 己 往 技 術 之 DRAM元件 中 > 因 為 對 於 每 一 個 區 塊 設 置 一 行 解 碼 器 » 於 是 積 體 性 降 低 〇 在 第 二 痼 已 往 技 術 之 DRAM元件 中 使 用 雙 層 鋁 之 技 術 製 造 9 感 測 放 大 器 各 列 以 共 用 型 感 測 放 大 器 形 成 9 且 設 置 一 行 解 碼 器 供 所 有 區 塊 共 用 9 於 是 增 加 了 積 體 性 9 此 亦 將 於 稍 後 詳 述 〇 但 在 上 述 第 二 値 已 往 技 術 之 DRAM 之 元 件 中 » 因 為 有 幾列 測 放 大 器 是 用 於 兩 相 鄰 區 塊 間 9 所 以 必 須 要 有 選 擇 器 以 切 換 這 些 感 測 放 大 器 各 列 於 兩 相 鄰 區 塊 其 中 之 一 9 此 降 低 了 積 體 性 〇 發 明 本發明之目的在提供一種具有共用型感測放大器之高 本紙張尺度適用中國國家標準（CNS ) A4规格（hOXWJ公釐） i I I I - —1 n ^ 丨 --I I I·'—訂-------A 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（> ) 積體性半導體記憶元件。 根據本發明，在一半導體記憶元件中含有兩列非共用 型感測放大器，許多記憶單元陣列介於非共用型感測放 大器各列之間，許多共用型感測放大器各列介於兩列相 郯之共用型感測放大器之間，許多輸入/輸出（I/O)缓衝 器，及許多資料故大器，各資料媛衡器直接連至其中一 列感測放大器及1/ 0緩衝器其中唯一的一個。因為感測 放大器各列均直接連至資料放大器，所Μ其間的連線得 Μ縮短，使謓取速度特性與讀取作業邊限特性得Μ改進 。而且因為未設置選擇器Μ切換感測放大器各列，所Μ 可Μ增加積體性。 圖式籣诚 本發明由下面的說明與已往技術比較並參考附圖將更 加清楚瞭解，附圖中： 圖1為說明第一個已注技術DRAM元件之電路圖； 圖2為說明第二個已往技術DRAM元件之電路圖； 圖3為圖2元件之部分電路圖； 圖4為說明第二個已往技術DRAM元件之電路圖； 圖5為說明根據本發明之DRAM元件一實例之電路圖， K及 圖6為圖5元件之部分電路圖。 優撰g例說明 在說明優埋實例之前，將參考圖1,2,3與4解釋已往技 術之DRAM元件。 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I - -- 1^1 n^— —II 一 I - I (請先閱讀背面之注意事項再填寫本頁) P»— X 、-° 線 經濟部中央標準局員工消費合作社印製 A7 B7 _ 五、發明説明（，） 圈1中示出第一個已往技術之.DRAM元件，使用單層紹 之技術製造，記憶單元陣列^^1,^^2，..·^8分別用列位 址解碼器RD1,RD2,...RD8存取，且分別連至感測放大器 各列SA1.SA2, . . .SA8 °感測放大器各列SA1與SA3,SA3與 SA4.SA5與SA6.SA7與SA8, Μ及SA9與S/ΠΟ分別用行解瑪 器CD1,CD2.CD3與CD4存取。而且，感測放大器各列SA1, SA2.....SA8分别經由資料匯流排DB1.BD2,----DB8連至 訊差故大器，即資料放大器DAl,D/\2.....DA8°此外，資 料放大器D A1與D A 2連至一與I / 0端子I / 〇 1相連的I / 〇缓 衡器BF1;資料放大器DA3與DA4連至一與I/O端子1/〇2相 連的I/O缓衡器BF2;資料放大器DA5與DA6連至一與I/O 端子1/03相連的I/O鍰衝器BF3;資料放大器DA7與DA8刖 連至一與I/O端子1/04相連的I/O媛衡器BF1。 於是在圖1中，記憶單元陣列MCI與MC2,感测放大器 列SA1與SA2,列位址解碼器RD1與RD2M及行位址解碼器 CD1形成一區塊BK1供I/O端子1/01之用，記憶單元陣列 MC3與MC4,感测放大器列SA3與SA4,列位址解碼器RD3 與RD4M及行位址解碼器（D2形成一區塊BK2供I/O端子1/ 02之用；記憧簞元陣列MC5與MC6,感測放大器列SA5與 SA6,列位址解碼器RD5與RD6M及行位址解碼器CD3形成 一區塊BK3供I/O端子1/03之用；記憶單元陣列MC7與MC8 ,感测放大器列SA7與SA8,列位址解碼器RD7與RD8M及 以行位址解礴器CD4形成一區塊BK4供I/O端子1/04之用。 在圖1之DRAM元件中，因為感測放大器各列SA1,SA2, 本紙張尺度適用中國國家榡準（CNS ) Α4規格（210Χ297公嫠） --------{-裝-----α—訂-------^ 線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（4 ) ....SA8分別直接連至資料放大器DA1.DA2.....DA8,所 以資料匯流排DB1,DB2......DB8的長度可Μ縮短，使賁 料匯流排DB1,DB2,...DB8的寄生電容與電阻得降低，於 是譲取作業速度特性與謓取作業邊限特性得Μ改進。 但在圖1之DRAM元件中，因為設置了行位址解碼器CD1 ,CD2. CD3與CD4供區塊BK1,BK2,BK3與BK4之用，行位址 解碼器的数目太多，所Μ積體性下降。 圖2中示出第二個已往技術之DRAM元件，使用雙曆鋁 之技術製造，不用圓1的行位址解碼器CD1,CD2, CD3與 CD4,而設置單一行位址解碼器CD供所有區塊BK1.BK2, BK3與BK4供用，於是增加了積體性。 而且設置非共用型感測放大器各列SA1’與SA9’與共用 型感測放大器各列SA2’，SA3^____SA8’，而非圖1之感測 放大器各列SA1,SA2____SA8。即各非共用型感測放大器 各列SA1’與SA9'連至其中一記憶單元陣列如MCI與MC8。與 此相反，各共用型感測放大器各列SA2、SA3'...SA8U 連至記憶單元陣列MC1.MC2,...MC8其中兩個。比方說， 共用型感測放大器列SA2’連至兩個記憶翬元陣列MCI與 MC2 ° 更詳细地說，請參考圖3 ,示出圖2之非共用型感測 放大器列SA1’，記憶單元陣列MCI及共用型感測放大器 列SA2’，記憶單元陣列MCI包含字元線WL1,WL2,...WLb ，由列位址解碼器RD1,位元線BL11,BLU’，BL12,中BL12’ ....，與記憶單元 Clii，Cl12，...，Cl2i，Cl22，...Clmi 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) —裝.A7 B7 Fifth, the invention description (,) The invention backed by the Central Bureau of Economics of the Ministry of Economic Affairs of the Beigong Consumer Cooperative printed the invention leader. This invention relates to a semiconductor billion-element component. 9 is a dynamic randomizer with a shared power amplifier. Access memory (DRAM) device Ο phase-wise technical description In the first DRAM device of the past technology, it was manufactured using a single-layer aluminum technology > set up many blocks 9 each block has two billion UO early element arrays > Two-column sense amplifiers 9 and row decoders between the two-column sense amplifiers 0 Each sense amplifier is directly connected to a data amplifier 9 The data amplifier is connected to an input / output buffer 0 The connection between each column of the amplifier and the data amplifier can be shortened by 9 so the read speed waitability and read operation margin characteristics can be improved 9 which will be detailed later 〇 But in the first DRAM device of the previous technology mentioned above 9 because one row of decoders is provided for each block > the integration is reduced Ο In the DRAM device of the second m prior technology 1 is manufactured using the technology of double-layer aluminum 9 Each column of the sense amplifier is formed with a common sense amplifier 9 and a row of decoders is provided for all blocks to share 1 so that the integration is increased 9 This will also be detailed later. But in the second prior art mentioned above In the DRAM device > because a row of decoders is provided for each block »the integration is reduced. In the second DRAM device of the prior art, the technology of double-layer aluminum is used to manufacture 9 sense amplifier columns for a common sense The test amplifier forms 9 and sets a row of decoders for all blocks to share 9 so the integration 9 is increased. This will also be detailed later. However, Described in the second DRAM component of the previous technology »Because there are several columns of test amplifiers used between two adjacent blocks, there must be a selector to switch these sense amplifiers in each of the two adjacent blocks 9. This reduces the integration. The purpose of the present invention is to provide a high-end paper standard with a common sense amplifier that is applicable to the Chinese National Standard (CNS) A4 specification (hOXWJ mm) i III-— 1 n ^ 丨--III · '—Subscribe ------- A line (please read the notes on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (>) Body semiconductor memory device. According to the present invention, a semiconductor memory device contains two rows of non-shared sense amplifiers, many memory cell arrays are between the rows of the non-shared sense amplifiers, and many rows of shared sense amplifiers are between the two rows of phases Between the shared sense amplifiers of Tan, there are many input / output (I / O) buffers and many data amplifiers. Each data scale is directly connected to one of the sense amplifiers and 1/0 buffers. one of. Because each column of the sense amplifier is directly connected to the data amplifier, the connection between them is shortened, which improves the pickup speed characteristics and the read operation margin characteristics. Moreover, since the selector M is not provided to switch the columns of the sense amplifier, the integration can be increased. The invention will be more clearly understood by comparing the following description with the prior art and referring to the accompanying drawings. In the drawings: FIG. 1 is a circuit diagram illustrating the first technology-infused DRAM component; FIG. 2 is a diagram illustrating the second past Circuit diagram of a technical DRAM element; Figure 3 is a partial circuit diagram of the element of FIG. 2; FIG. 4 is a circuit diagram illustrating a second prior art DRAM element; FIG. 5 is a circuit diagram illustrating an example of a DRAM element according to the present invention, K and FIG. 6 are Figure 5 is a partial circuit diagram of components. Description of excellent examples Before explaining the excellent examples, the DRAM components of the prior art will be explained with reference to Figures 1, 2, 3 and 4. -4- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) I--1 ^ 1 n ^ — —II I-I (please read the precautions on the back before filling this page) P »— X,-° Line A7 B7 _ printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy _ V. Description of Invention (,) Circle 1 shows the first prior technology. DRAM components are manufactured using a single-layer technology, The memory cell arrays ^^ 1, ^^ 2,... ^ 8 are respectively accessed by column address decoders RD1, RD2, ... RD8, and are respectively connected to the columns of sense amplifiers SA1.SA2,... The SA1 ° sense amplifier columns SA1 and SA3, SA3 and SA4. SA5 and SA6. SA7 and SA8, M and SA9 and S / ΠΟ are accessed by the CDM, CD2, CD3 and CD4, respectively. Moreover, the columns SA1, SA2 ... SA8 of the sense amplifiers are respectively connected to the differential amplifiers through the data buses DB1.BD2, ---- DB8, namely the data amplifiers DAl, D / \ 2 ... .. DA8 ° In addition, the data amplifiers D A1 and DA 2 are connected to an I / O buffer BF1 connected to the I / O terminal I / 〇1; the data amplifiers DA3 and DA4 are connected to an I / O terminal 1 / 〇 2 Connected I / O buffer BF2; data amplifiers DA5 and DA6 are connected to an I / O punch BF3 connected to I / O terminal 1/03; data amplifiers DA7 and DA8 are connected to one and I / O terminals 1/04 connected I / O yuan scale BF1. Thus, in FIG. 1, memory cell arrays MCI and MC2, sense amplifier columns SA1 and SA2, column address decoders RD1 and RD2M, and row address decoder CD1 form a block BK1 for I / O terminal 1/01 For use, memory cell arrays MC3 and MC4, sense amplifier columns SA3 and SA4, column address decoders RD3 and RD4M, and row address decoder (D2 form a block BK2 for I / O terminal 1/02; Arrays MC5 and MC6, sense amplifier columns SA5 and SA6, column address decoders RD5 and RD6M and row address decoder CD3 form a block BK3 for I / O terminals 1/03; memory cell array MC7 and MC8, sense amplifier columns SA7 and SA8, column address decoders RD7 and RD8M and row address decoder CD4 form a block BK4 for I / O terminal 1/04. DRAM in FIG. 1 In the components, because the sense amplifiers are in each column SA1, SA2, the paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 gong) -------- {-装 ----- α- 定------- ^ Line (please read the precautions on the back before filling in this page) A7 B7 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention Instructions (4) .... SA8 are directly connected to Data amplifier DA1.DA2 .. ... DA8, so the length of the data bus DB1, DB2 ... DB8 can be shortened, so that the parasitic capacitance and resistance of the material bus DB1, DB2, ... DB8 can be reduced, so the fetching operation The speed characteristics and the operating margin characteristics have been improved by M. However, in the DRAM device of FIG. 1, because the row address decoders CD1, CD2, CD3, and CD4 are provided for blocks BK1, BK2, BK3, and BK4, The number of row address decoders is too large, so the integration decreases. Figure 2 shows the second prior art DRAM device, which is manufactured using the technology of dual calendar aluminum, without using the circle 1 row address decoder CD1, CD2, CD3 and CD4, and a single row address decoder CD is provided for all blocks BK1. BK2, BK3 and BK4, thus increasing the integration. Moreover, non-shared sense amplifier columns SA1 'and SA9' are provided Each column SA2 'and SA3 ^ ____ SA8' of the common sense amplifier are not SA1, SA2__SA8 of the sense amplifier of Fig. 1. That is, each column SA1 'and SA9' of each non-shared sense amplifier are connected to one of the memories Cell arrays such as MCI and MC8. In contrast, the columns SA2, SA3 '... SA8U of each common sense amplifier are connected to the memory cell arrays MC1.MC2, ... ..MC8 two of them. For example, the shared sense amplifier array SA2 'is connected to the two memory cell arrays MCI and MC2. For more details, please refer to FIG. 3, which shows the non-shared sense of FIG. 2. Sense amplifier row SA1 ', memory cell array MCI and shared sense amplifier row SA2', memory cell array MCI includes word lines WL1, WL2, ... WLb, which is composed of column address decoder RD1, bit line BL11, BLU ', BL12, Medium BL12' ..., with memory unit Clii, Cl12, ..., Cl2i, Cl22, ... Clmi This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling out this page) — Pack.

Je 線 A7 B7 snu2 五、發明説明（t )Je line A7 B7 snu2 5. Description of the invention (t)

Clra2, ...在字元線 WL1,WL2,..WIU 與位元線 BL11,BL11’ ,...BL12,BL12’，..的交點上存取。位元線 BL11,BL11’ 與BL13,BL13’，BL15,B15'...(未示出）達至非共用型感 测放大器列SAl'SAl’含有η级由一放大器如AMP11及-Y 開關如YSW11形成，YSW11由行位址解碼器CD的Υ開關信 號YSW1控制。另一方面，位元線BL12,BL12’，及BL14,BL 14’，BL16,BL16’，...（未示出）均連至共用型感測放大器 SA2’，SA2'亦含η级，各级Μ —放大器如AMP21及一Y開關 如YSW21形成。換句話說，記憶單元C 1 η , C 1 χ .......Clra2, ... is accessed at the intersection of the word lines WL1, WL2,... WIU and the bit lines BL11, BL11 ’, ... BL12, BL12’, .. Bit lines BL11, BL11 'and BL13, BL13', BL15, B15 '... (not shown) reach the non-shared sense amplifier column SAl'SAl' contains n-level by an amplifier such as AMP11 and -Y switch As YSW11 is formed, YSW11 is controlled by the Y switch signal YSW1 of the row address decoder CD. On the other hand, the bit lines BL12, BL12 ', and BL14, BL 14', BL16, BL16 ', ... (not shown) are all connected to the shared sense amplifier SA2', SA2 'also contains n-level, Various levels of M-amplifiers such as AMP21 and a Y switch such as YSW21 are formed. In other words, the memory cells C 1 η, C 1 χ .......

Clnu, ...均連至非共用型感測放大器列SA1',而記憶單 元C 1丨2 , C 1 2 2 , . . . C 1 m2 ,...則連至共用型感測放大器列 S A2 ' ° 非共同型感測放大器列如SA1*與記憶單元陣列MCI之 連接/斷接由一解碼器（未示出）所產生的移轉閘控制信 號如TG1加以控制。而且，共用型感测放大器列如SA2’ 與其上側記憶單元陣列如MCI之連接/斷接由解碼器（未 示出）所產生的移轉閘控制信號如TG2U加K控制。此外， 共用型感測放大器列如SA2·與其下側記憶單元陣列如MC 2之埋接/斷接由解碼器（未示出）所產生的移轉閘控制 信號如TG2L加Μ控制。 回到圖2,認憶單元陣列MCI與MC2,感測放大器各列 SA1’，SA2’，SA3',及列位址解碼器RD1與RD2形成一區塊 BK1供I/O端子1/〇丨之用；記憶單元陣列MC3與MC4,感測 放大器各列SA3’，SA4、SA5’，及列位址解碼器RD3與RD4 -7- 本紙張尺度適用中國囤家標準（CNS ) A4規格（210X297公羡1 ' --I-----ί 丨裝-----1—訂----I-J 線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局員工消費合作社印製 經濟部中央標準局員工消費合作杜印袋 A7 _____B7_ 五、發明説明（各） 肜成一區塊BK2供I/O端子1/02之用；記憶單元陣列MC5 與MC6,感測放大器各列SA5’，SA6',SA7',M及列位址解 碼器RD5與RD6形成一區塊BK3供I/O端子1/03之用；記憶 單元陣列MC7與MC8,感測放大器各列SA7’，SA5',SA9’， 及列位址解碼器RD7與RD8形成一區塊BK4供I/O端子1/04 之用。因此，區塊BK1與BK2中的資料在共用型感測放大 器列S A 3 ’中混合，且因此設置一選擇器S L 1 Μ鑑別區塊B K 1 中的資料與區塊ΒΚ2中的資料。而且區塊ΒΚ2與ΒΚ3中的 資料在共用型感測放大器列SA5'中混合，因此設置一選 擇器SL2以鑑別區塊ΒΚ2中的資料與區塊ΒΚ3中的資料。 另外，區塊ΒΚ3與ΒΚ4中的資料在共用型感测放大器列SA 7·中混合，且因此設置一選擇器SL3M鑑別區塊ΒΚ3中的 資料與區塊ΒΚ4中的資料。請注意選擇器SL1, SL2與SL3 均由一解碼器（未示出）控制。 此外，兩資料匯流排DB31與DB32及兩資料鑀衡器DA31 與DA32均連至選擇產SL1,兩資料匯流排DB51與DB52及 兩資料媛衡器DA51與DA52均連至選擇器SL2,兩資料匯 流排DB71與DB72及兩資料媛衡器DA71與DA72均連至選擇 器 SL3。 於是，在圖2的DARM元件中，埋擇器SL1,SL2與SL3的 存在及資料放大器的數目增加降低了積體性。 圖4中示出第三個已注技術之DRAM元件，將圖2的DRAM 元件修正減少資料放大器的數目。即資料故大器DA1,DA2 -8- 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） ------------^ ▲ I— (請先閱讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標準局員工消費合作社印製 A7 _B7 五、發明説明（7 ) ,D A 8分別位於記億單元陣列M C 1，H C 2 , M C 8的中 間。但在這種情況下，資料匯流排D Β 1，D Β 2 , D Β 3 1 , D Β 3 2 , DB4,DB51，DB52,DB6，DB71,DB72,DB8,及 DB9的長度增加， 結果寄生電容與電阻增加，因此讀取作業速度特性與讀 取作業邊限降低》 圖5中示出本發明一實例，記億單元陣列MC8,MCI與 MC2,威測放大器SA9',SA1·與SA2、及列位址解碼器RD8 ，R D 1與R D 2形成一區塊Β K 1供I / 0端子I / 0 1之用；記億單 元陣列MC2，MC3與MC4,慼測放大器SA3'與SA4·，及列位址 解碼器RD2.RD3與RD4形成一區塊BK2供I/O端子1/02之用 ;記憶單元陣列M C 4 , M C 5與M C 6 ,感測放大器S A 5 A S A 6 ·, 及列位址解碼器RD4,RD5與RD6形成一區塊M3供I/O端子 1/03之用；記億單元陣列MC6,MC7與MC8,感測放大器SA7· 與SA8',及列位址解碼器RD6，RD7與RD8形成一區塊BK4供 I / 〇端子I / 0 4之用。 圖5中，戲測放大器各列SA9',SA1，與SA2,僅用於I/O 端子1/01,因此，威測放大器各列SA9，，SA1，，與SA21分 別經由資料匯流排DB9, DB1與DB2連至資料放大器DA9, DA1與DA2,無需選擇器。資料放大器DA9.DA1與DA2均連 至I / 〇緩衝器B F 1。請注意兩値非共用型威測放大器各列 SA9’|5|SA1'作為一個共用型威測放大器使用。 而且US測放大器各列SA3,與，SA4,僅用於I/O端子1/〇2 。因此感測放大器各列S Α 3，與s A 4 _分別經資料匯流排D Β 3與DB4連至資料放大器DA3與DA4,不用選擇器。資料放 本紙張尺度適用中國國家揉準（CNS > A4規格（210X297公釐） ------„I裝-----：丨訂‘-----(線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 B7 _ 五、發明説明（* ) 大器DA3與DA4則連至I/O缓衝器BF2e 此外，感測放大器各列SA5·與SA6’僅用於I/O端子1/03 ，因此感测放大器各列SA5’與SA6·分別經資料匯流排DB5 與D B 6遽至資料放大器D A 5與D A 6，無需遘擇器。資料放大 器DA5與DA6則連至I/O缓衝器DF3。 此外，威潮放大器各列SA71與SA8·僅用於I/O端子1/04 ，所以威測放大器各列S A 7 ’與S A 8 ·分別經資料匯流排D B 7 與DB8連至資料放大器DA7與DA8,無需選擇器。資料放大 器DA7與DA8則連至I/O緩衝器BF4。 因為威測放大器各列SA1 · , SA2 ^____SA9’與1/ 〇端子 1/01,1/02,1/03，1/04之間的開僳是固定的，所以匾塊 BK1與BK2中的資料在記憶單元陣列MC2中混合；區塊BK2 與BK3中的資料在記億單元陣列MC4中混合；區塊BK3與 BK4中的資料在記憶單元陣列MC6中混合；區塊BK4與BK1 中的資料在記億單元陣列M C 8中混合。 更詳細地説，參考圖Β,其中示出圖5之共用型烕澜放大 器列SA2'，記億單元陣列MC2與共用型感測放大器列SA3· ，記憶單元陣列MC2含有由列位址解碼器RD2存取的字元 線 WLm+l,WLB+2,...WL2B,位元線 BL21，BL21’，BL22..... 及在字元線 WLin+1, ¥1^ + 2，...¥1^2|«與位元線81121，8121' 之間交點的記億單元 C2u，C2i2 C2ai ,C2 22，...C2bu，C2i«2，...0 位元線 BL21,BL21·與 BL23 ,BL23'BL25, BL25'，...（来示出）達至共用型IS測放大器 列SA3’，SA3_含η级，各级以一放大器如AMP31及一Y開開如 -1 0 _ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -------r--* I裝-- (請先閲讀背面之注意事項再填寫本頁) 訂· 線 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（9 ) YSW31形成，YSW31由行位址解碼器CD之Y開關信號YSW1控 制。另一方面，位元線 BL22, BL22’及 BL24,BL24’，BL26Clnu, ... are connected to the non-shared sense amplifier row SA1 ', and the memory cells C 1 丨 2, C 1 2 2,... C 1 m2, ... are connected to the shared sense amplifier row S A2 '° The connection / disconnection of the non-common sense amplifier series such as SA1 * and the memory cell array MCI is controlled by a transfer gate control signal generated by a decoder (not shown) such as TG1. Furthermore, the connection / disconnection of the shared sense amplifier array such as SA2 'and its upper memory cell array such as MCI is controlled by a transfer gate control signal generated by a decoder (not shown) such as TG2U plus K. In addition, the common sense amplifier array such as SA2 and its lower memory cell array such as MC 2 are embedded / disconnected by a transfer gate control signal generated by a decoder (not shown) such as TG2L plus M control. Returning to FIG. 2, the memory cell arrays MCI and MC2, the columns of sense amplifiers SA1 ', SA2', SA3 ', and the column address decoders RD1 and RD2 form a block BK1 for I / O terminals 1 / 〇 丨For use; memory cell arrays MC3 and MC4, sense amplifier columns SA3 ', SA4, SA5', and column address decoders RD3 and RD4 -7- This paper scale is applicable to the Chinese hoarding standard (CNS) A4 specification (210X297 Gongxian 1 '--I ----- ί 丨 install ----- 1--order ---- IJ line (please read the precautions on the back and then fill out this page) Employee consumption of the Central Bureau of the Ministry of Economic Affairs Cooperatives print the A7 consuming consumer cooperation du printing bag of the Central Bureau of Standards of the Ministry of Economics _____B7_ V. Description of the invention (each) A block BK2 for I / O terminals 1/02; memory cell arrays MC5 and MC6, sense amplifiers Columns SA5 ', SA6', SA7 ', M and column address decoders RD5 and RD6 form a block BK3 for I / O terminal 1/03; memory cell arrays MC7 and MC8, sense amplifier columns SA7' , SA5 ', SA9', and column address decoders RD7 and RD8 form a block BK4 for I / O terminal 1/04. Therefore, the data in blocks BK1 and BK2 is in the shared sense amplifier column SA 3 'medium mix A selector SL 1 Μ is set to identify the data in block BK 1 and the data in block BK2. And the data in blocks BK2 and BK3 are mixed in the shared sense amplifier row SA5 ', so set A selector SL2 is used to identify the data in the block BK2 and the data in the block BK3. In addition, the data in the blocks BK3 and BK4 are mixed in the shared sense amplifier row SA 7 ·, and therefore a selector SL3M is provided Identify the data in block Β3 and the data in block Κ4. Please note that selectors SL1, SL2 and SL3 are controlled by a decoder (not shown). In addition, two data buses DB31 and DB32 and two data weighers Both DA31 and DA32 are connected to SL1, two data buses DB51 and DB52 and two data scales DA51 and DA52 are connected to the selector SL2, two data buses DB71 and DB72 and two data scales DA71 and DA72 are connected to Selector SL3. Therefore, in the DARM device of FIG. 2, the presence of the buried selectors SL1, SL2, and SL3 and the increase in the number of data amplifiers reduce the integration. FIG. 4 shows the third DRAM device that has been injected. , Reduce the DRAM component correction of Figure 2 The number of material amplifiers. That is, the data is DA1, DA2 -8- This paper scale is applicable to the Chinese National Standard (CNS & A4 specifications (210X297 mm) ------------ ^ ▲ I— (Please read the precautions on the back and then fill out this page) A7 _B7 printed by the employee consumer cooperative of the Central Standards Bureau of the Ministry of Economics. 5. Description of the invention (7), DA 8 are located in the MC1, HC 2, MC 8 in the middle. However, in this case, the length of the data bus D B 1, D B 2, D B 3 1, D B 3 2, DB4, DB51, DB52, DB6, DB71, DB72, DB8, and DB9 increases, resulting in parasitic Capacitance and resistance increase, so the reading operation speed characteristics and reading operation margin decrease. "An example of the present invention is shown in FIG. 5, a billion-element cell array MC8, MCI and MC2, a power amplifier SA9 ', SA1 · and SA2, And the column address decoders RD8, RD 1 and RD 2 form a block Β K 1 for I / 0 terminal I / 0 1; the memory cell array MC2, MC3 and MC4, the test amplifier SA3 'and SA4 · , And column address decoders RD2. RD3 and RD4 form a block BK2 for I / O terminal 1/02; memory cell array MC 4, MC 5 and MC 6, sense amplifier SA 5 ASA 6 ·, and Column address decoders RD4, RD5 and RD6 form a block M3 for I / O terminal 1/03; Billion cell array MC6, MC7 and MC8, sense amplifiers SA7 · and SA8 ', and column address decoding The RD6, RD7 and RD8 form a block BK4 for I / O terminal I / 04. In Fig. 5, each row of test amplifiers SA9 ', SA1, and SA2 is only used for I / O terminals 1/01. Therefore, each row of prestige amplifiers SA9, SA1, and SA21 is via the data bus DB9, DB1 and DB2 are connected to data amplifiers DA9, DA1 and DA2, no selector is required. The data amplifiers DA9.DA1 and DA2 are both connected to the I / O buffer B F1. Please note that the two non-shared prestige amplifier columns SA9 ’| 5 | SA1 'are used as a shared prestige amplifier. And each column of US test amplifier SA3, and, SA4, are only used for I / O terminal 1 / 〇2. Therefore, the columns S A 3 and S A 4 _ of the sense amplifiers are connected to the data amplifiers DA3 and DA4 via the data buses D B3 and DB4, respectively, without a selector. The standard of the paper is suitable for Chinese national standards (CNS & A4 specifications (210X297mm) ------ "I installed -----: 丨 order '----- (line (please read first Note on the back and then fill out this page) A7 B7 _ Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs _ V. Description of the invention (*) The DA3 and DA4 are connected to the I / O buffer BF2e. In addition, each of the sense amplifiers Columns SA5 · and SA6 'are only used for I / O terminal 1/03, so each column of sense amplifiers SA5' and SA6 · goes through data buses DB5 and DB 6 to data amplifiers DA 5 and DA 6, respectively, without selection The data amplifiers DA5 and DA6 are connected to the I / O buffer DF3. In addition, the Weichao amplifier columns SA71 and SA8 are only used for I / O terminals 1/04, so the Weiwei amplifier columns SA 7 'and SA 8 · Connect to data amplifiers DA7 and DA8 via data buses DB 7 and DB8, respectively, without selectors. Data amplifiers DA7 and DA8 are connected to I / O buffer BF4. Because the prestige amplifier columns SA1 ·, SA2 ^ The opening between SA9 'and 1 / 〇 terminals 1/01, 1/02, 1/03, 1/04 is fixed, so the data in the plaques BK1 and BK2 are mixed in the memory cell array MC2 The data in blocks BK2 and BK3 are mixed in the memory cell array MC4; the data in blocks BK3 and BK4 are mixed in the memory cell array MC6; the data in blocks BK4 and BK1 are mixed in the memory cell array MC 8 In more detail, referring to FIG. B, which shows the shared type amplifier amplifier column SA2 ′ of FIG. 5, the billion cell array MC2 and the shared sense amplifier array SA3. The memory cell array MC2 contains the decoding by the column address The word lines WLm + 1, WLB + 2, ... WL2B, bit lines BL21, BL21 ', BL22 ..... and the word lines WLin + 1, ¥ 1 ^ + 2, ... ¥ 1 ^ 2 | «Billions of units C2u, C2i2, C2ai, C2 22, ... C2bu, C2i« 2, ... 0 bit line BL21, at the intersection between the bit lines 81121, 8121 ' BL21 · and BL23, BL23'BL25, BL25 ', ... (to be shown) reach the common IS test amplifier series SA3', SA3_ contains n levels, each level is opened with an amplifier such as AMP31 and a Y -1 0 _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ------- r-* I installed-(please read the precautions on the back before filling this page) · Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Line Economy System A7 B7 5. Description of the invention (9) YSW31 is formed. YSW31 is controlled by the Y switch signal YSW1 of the row address decoder CD. On the other hand, the bit lines BL22, BL22 ’and BL24, BL24’, BL26

,BL26'____(未示出）則連至共用型感測放大器S A 2 S A 2’亦含η级，各級Μ —放大器如AMP21及一Y開關如YSW21 形成。換句話說，記憶單元C2h,C221 ...02„11,..均連 至共用型感測放大器列SA3、記憶單元C212 ,C2,*,...C2 12____則連至共用型感測放大器列SA2 ’。 共用型感測放大器列SA3’與記憶單元陣列如MC2之連 接/斷接由解碼器（未示出）所產生之移轉閘控制信號TG 3U加Μ控制。並且，共用型感測放大器列SA2’與記憶單 元陣列MC2之連接/斷接由解碼器（未示出）所產生之移轉 閘控制信號如T G 2 L加W控制。 於是，在圖5之記憶單元陣列MC2, MC4,MC6與MC8中， 一半記憶單元連至一感測放大器列供一區塊或1/ 〇缓衝 器之用，另一半記憶單元則連至一感測放大器列供另一 區塊或I/O鍰衝器之用。 如上所述，根據本發明，因為感測放大器各列與資料 放大器之間的關係是固定的，感測放大器各列直接連至 資料放大器，所以其間的資料匯流排可以減少，因此寄 生電容與電阻得以降低而改進讀取作業速度特性與謓取 作業邊限。 -11- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------{-裝-------訂j------^線 (請先閲讀背面之注意事項再填寫本頁), BL26 '____ (not shown) is connected to the shared sense amplifier S A 2 S A 2' also contains n level, each level of M-amplifier such as AMP21 and a Y switch such as YSW21 are formed. In other words, the memory cells C2h, C221 ... 02 "11, ... are connected to the shared sense amplifier row SA3, and the memory cells C212, C2, *, ... C2 12____ are connected to the shared sense Amplifier column SA2 '. The connection / disconnection of the shared sense amplifier column SA3' and the memory cell array such as MC2 is controlled by the transfer gate control signal TG 3U generated by the decoder (not shown) plus M. Also, the shared type The connection / disconnection of the sense amplifier array SA2 'and the memory cell array MC2 is controlled by a transfer gate control signal generated by a decoder (not shown) such as TG 2 L plus W. Therefore, the memory cell array MC2 in FIG. 5 In MC4, MC6 and MC8, half of the memory cells are connected to a sense amplifier row for one block or 1 / 〇 buffer, and the other half of the memory cells are connected to a sense amplifier row for another block or The use of I / O detectors. As described above, according to the present invention, because the relationship between each row of the sense amplifier and the data amplifier is fixed, and each row of the sense amplifier is directly connected to the data amplifier, the data bus between them Rows can be reduced, so parasitic capacitance and resistance are reduced to improve reading Industry speed characteristics and margins of operation. -11- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) --------- {-installation ------- order j ------ ^ line (please read the notes on the back before filling this page)

Claims (1)

經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 1. 一種半導體記憶元件，包含： 第一與第二非共用型感測放大器各列（SA1’，SA9’）； 許多記憶單元陣列（MC1,MC2,,.,MC8)置於該第一與第 二并共用型感測放大器各列之間； 許多共用型感測放大器各列（SA2',SA3’.....SA8’） 接連在兩相鄰該記憶單元陣列之間； 許多輸入/輪出鑀衝器（BF1,BF2,...BF8); 許多資料放大器（DA1,DA2,...DA9),各直接連至該 非共用型感測放大器各列其中之一與該共用型感测故 大器各列及該輸入/輸出媛衝器其中唯一的一個。 2. 如申請專利範圍第1項之元件，並含： 許多第一位址解碼器（R D 1 , R D 2 , . . . R D 8 > ,各連至該 記憶單元陣列其中之一；及 一第二位置解碼器（CD)連至所有該記憶單元陣列。 3. —種半導體記憶元件，包含： 第一與第二非共用型感測放大器各列（SA1',SA9’）； 許多記憶單元陣列（MC1,MC2,...MC8)置於該第一與 第二非共用型感測放大器各列之間；Μ及 許多共用型感測放大器各列（SA2’，SA3’.....SA8 ') 連接於兩相鄰該記憶單元陣列之間； 該記憶單元陣列其中之一與鄰接該記憶單元陣列其 中之一的兩個該記憶單元陣列形成一區塊，供一輸入 / 輸出端子（1/01, 1/02,. ..1/08)之用。 4. 如申請專利範圍第3項之元件，其中Μ該記憶單元陣 -1 2- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） --------{-裝-----.—訂------^ ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 列其中之一之所有記憶單元及該二記憶單元陣列之各 半數記憶單元形成該一區塊。 5. 如申請專利範圍第3項之元件，其中該記憶單元陣列 之第一最外陣列（M C 1 ), 次於該第一最外陣列之其中 一該記憶單元陣列及一第二最外陣列（MC8)形成一區 塊供一輸人/輸出端子（1/01)之用。 6. —種半導體記憶元件，包含： Ν(Ν = 2,3,..)個輸人 / 輸出鍰衝器（BF1,BF2,..BF8)； 第一與第二非共用型感測放大器各列（SA1’，SA9·); 2H個記憶單元陣列（MC1,MC2,...MC8)置於該第一與 第二非共用型感測放大器各列之間，該記憶單元陣列 其中第一個連至該第一非共用型感測放大器列，該記 憶單元陣列其中第2N個連至該第二非共用型感測放大 器列； 2N個共用型感測放大器各列（542’，563,...568’）連 接於兩相鄰該記憶單元陣列之間；以及 (2H + 1)個資料放大器（DA1,DA2,...DA9)各經資料匯 流排（DB1,DB2,...DB9)«至該非共用型感测放大器各 列其中之一及該共用型感測放大器各列， 該資料放大器之第一，第二及第（2 N + 1)個連至該輸 入/輸出媛衝器之第一個， 該資料放大器之第Π-1)個與第i個（i=4,6.....2N) 連至該輸入/輸出鍰衡器之第ί/2個。 7. 如申請專利範圍第6項之元件，並含： -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公鼇） (請先閲讀背面之注意事項再填寫本頁) -I m^i n nn nn 一eJ1^11 ^^^1 n nn ml I nll« i ^^^1 · 申請專利範圍 N 2 A8 B8 C8 D8 一 之第 第中個 個其單 列一 i 陣 器 碼 解 2 D R 元 Ha s' 憶 己 言該至 遵 8 D R 列 " 元 單 憶 記 該 有 所 至 3 D C /(· 器 碼 解 (請先閲讀背面之注意事項再填寫本頁) j--裝-----—訂 經濟部中央標準局員工消費合作社印製 n nn tm 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）A8 B8 C8 D8 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs VI. Patent application 1. A semiconductor memory device, including: the first and second non-shared sense amplifier columns (SA1 ', SA9'); many Memory cell arrays (MC1, MC2, .., MC8) are placed between the columns of the first and second parallel sense amplifiers; the columns of many common sense amplifiers (SA2 ', SA3' ... .SA8 ') successively between two adjacent memory cell arrays; many input / wheel output punches (BF1, BF2, ... BF8); many data amplifiers (DA1, DA2, ... DA9), each It is directly connected to one of the columns of the non-shared sense amplifier and the only one of the columns of the shared sense amplifier and the input / output device. 2. For example, the components of the first item of the patent application scope, including: many first address decoders (RD 1, RD 2,... RD 8 >, each connected to one of the memory cell arrays; and one The second position decoder (CD) is connected to all the memory cell arrays. 3. A type of semiconductor memory element, including: the first and second non-shared sense amplifier columns (SA1 ', SA9'); many memory cells Arrays (MC1, MC2, ... MC8) are placed between the first and second non-shared sense amplifier columns; M and many shared sense amplifier columns (SA2 ', SA3' ... .SA8 ') is connected between two adjacent memory cell arrays; one of the memory cell arrays and the two memory cell arrays adjacent to one of the memory cell arrays form a block for an input / output terminal (1/01, 1/02, ..1 / 08). 4. For the component of patent application item 3, in which the memory cell array -1 2- This paper scale is applicable to the Chinese National Standard (CNS ) Α4 specification (210Χ297 mm) -------- {-installed -----.— order ------ ^ ^ (please read the precautions on the back before filling (Write this page) A8 B8 C8 D8 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 6. All the memory cells listed in one of the patent applications and half of the memory cells of the two memory cell arrays form this block. 5. For example, the device of claim 3, wherein the first outermost array (MC 1) of the memory cell array, one of the memory cell array and the second outermost array (MC8) next to the first outermost array ) Form a block for one input / output terminal (1/01). 6. A kind of semiconductor memory device, including: Ν (Ν = 2,3, ..) input / output percussion device ( BF1, BF2, .. BF8); each column of the first and second non-shared sense amplifiers (SA1 ', SA9 ·); 2H memory cell arrays (MC1, MC2, ... MC8) are placed in the first Between each row of the second non-shared sense amplifier, the first one of the memory cell array is connected to the first non-shared sense amplifier row, and the 2Nth of the memory cell array is connected to the second non-shared Type sense amplifier columns; 2N common sense amplifier columns (542 ', 563, ... 568') connected Between two adjacent memory cell arrays; and (2H + 1) data amplifiers (DA1, DA2, ... DA9) each through the data bus (DB1, DB2, ... DB9) «to the non-shared sense One of the columns of the sense amplifier and the columns of the shared sense amplifier, the first, second, and (2 N + 1) of the data amplifier are connected to the first of the input / output amplifier, the The Π-1) of the data amplifier and the ith (i = 4,6 ... 2N) are connected to the / 2th of the input / output balance instrument. 7. For example, the 6th component of the patent application, including: -13- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 male Ao) (please read the precautions on the back before filling this page) -I m ^ in nn nn a eJ1 ^ 11 ^^^ 1 n nn ml I nll «i ^^^ 1 · Patent application scope N 2 A8 B8 C8 D8 The first and second row of its single row i array code solution 2 DR Yuan Ha s' should remember to comply with the 8 DR column " Yuan Shan Yi Ji should have to 3 DC / (· device code solution (please read the precautions on the back before filling this page) j--install- ----— Ordered by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs n nn tm 4 This paper scale applies the Chinese National Standard (CNS) A4 specification (210X 297 mm)
TW085105311A 1995-04-25 1996-05-03 TW293122B (en)

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JP2792398B2 (en) * 1992-06-30 1998-09-03 日本電気株式会社 Semiconductor memory circuit

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