TW202338935A - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
- Publication number
- TW202338935A TW202338935A TW112100473A TW112100473A TW202338935A TW 202338935 A TW202338935 A TW 202338935A TW 112100473 A TW112100473 A TW 112100473A TW 112100473 A TW112100473 A TW 112100473A TW 202338935 A TW202338935 A TW 202338935A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- copper
- conductive layer
- bonding pad
- conductive
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims description 112
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 155
- 229910052802 copper Inorganic materials 0.000 claims abstract description 155
- 239000010949 copper Substances 0.000 claims abstract description 155
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims description 83
- 239000002055 nanoplate Substances 0.000 claims description 67
- 238000007747 plating Methods 0.000 claims description 63
- 239000002061 nanopillar Substances 0.000 claims description 54
- 239000013078 crystal Substances 0.000 claims description 30
- 230000001788 irregular Effects 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 364
- 239000004020 conductor Substances 0.000 description 40
- 238000012360 testing method Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 16
- 238000002161 passivation Methods 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 150000001768 cations Chemical class 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 239000000523 sample Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000002441 X-ray diffraction Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- 238000001887 electron backscatter diffraction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000003112 inhibitor Substances 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- -1 benzocyclobutenyl Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000002135 nanosheet Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/0355—Selective modification
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/0384—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/03845—Chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05563—Only on parts of the surface of the internal layer
- H01L2224/05564—Only on the bonding interface of the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0651—Function
- H01L2224/06515—Bonding areas having different functions
- H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0801—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0805—Shape
- H01L2224/08057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0805—Shape
- H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08123—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting directly to at least two bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/085—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/802—Applying energy for connecting
- H01L2224/80201—Compression bonding
- H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
- H01L2224/80379—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1011—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20102—Temperature range 0 C=<T<60 C, 273.15 K =<T< 333.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/201—Temperature ranges
- H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
在一實施例中,一種裝置包括介電層、導電通孔以及接合墊。介電層位於半導體基板的主動面上方。導電通孔位於介電層中,且導電通孔包括第一銅層,具有非均勻晶向。接合墊位於導電通孔上方和介電層中,且接合墊包括第二銅層,具有均勻晶向,接合墊的頂表面與介電層的頂表面共面。
Description
本發明實施例係關於一種半導體裝置及其形成方法,特別係有關於一種接合墊包括具有均勻晶向(grain orientation)的導電(銅)層的半導體裝置及其形成方法。
自積體電路(integrated circuit, IC)發展以來,由於各種電子部件(例如電晶體、二極體、電阻器、電容器等)的積體密度不斷提高,半導體產業經歷了持續的快速成長。在大多數情況下,積體密度的提高來自於最小特徵尺寸的反復減小,這允許將更多部件整合到給定區域中。隨著對小型化、更高速度、更大帶寬以及更低功耗和延遲的需求不斷增加,對封裝半導體裸晶(semiconductor dies)的更小、更具創造性的技術的需求也在增加。
堆疊式半導體裝置已成為進一步減小半導體裝置的物理尺寸的有效技術。在堆疊式半導體裝置中,主動電路(例如邏輯電路和記憶體電路)在不同的半導體晶圓上製造,兩個或多個半導體晶圓可以通過合適的接合(bonding)技術接合在一起,以進一步減小半導體裝置的形態因子(form factor)。
本揭露一些實施例提供一種半導體裝置。所述半導體裝置包括介電層、導電通孔(via)以及接合墊(bonding pad)。介電層位於半導體基板的主動面上方。導電通孔位於介電層中,且導電通孔包括第一銅層,具有非均勻晶向(grain orientation)。接合墊位於導電通孔上方和介電層中,且接合墊包括第二銅層,具有均勻晶向,接合墊的頂表面與介電層的頂表面共面。
本揭露一些實施例提供一種半導體裝置。所述半導體裝置包括第一積體電路裸晶(die)以及第二積體電路裸晶。第一積體電路裸晶包括第一介電層以及位於第一介電層中的第一接合墊,第一接合墊包括第一導電層和位於第一導電層上的第二導電層,第一導電層包括多個第一晶粒(grains),第二導電層包括多個第二晶粒,其中大部分第一晶粒不具有相同的晶格方向(lattice direction),且大部分第二晶粒具有相同的晶格方向。第二積體電路裸晶包括第二介電層以及位於第二介電層中的第二接合墊,第二介電層通過介電對介電鍵結(dielectric-to-dielectric bonds)直接接合到第一介電層,且第二接合墊通過金屬對金屬鍵結(metal-to-metal bonds)直接接合到第一接合墊。
本揭露一些實施例提供一種形成半導體裝置的方法。所述方法包括在介電層中圖案化互連開口(interconnect opening),介電層設置於半導體基板的主動面上方,互連開口具有通孔開口(via opening)和位於通孔開口上方的溝槽(trench)。所述方法也包括在互連開口中鍍覆(plating)第一銅層,第一銅層填充通孔開口並襯於(lining)溝槽內,第一銅層具有非均勻晶向。所述方法還包括在第一銅層上鍍覆第二銅層,第二銅層填充溝槽的剩餘部分,第二銅層具有均勻晶向。此外,所述方法包括平坦化第二銅層、第一銅層和介電層,直到第二銅層的頂表面與第一銅層的頂表面和介電層的頂表面共面。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然,這些實施例僅作為範例,而不該以此限定本揭露的範圍。例如,在說明書中敘述了一第一特徵形成於一第二特徵之上或上方,其可能包含第一特徵與第二特徵是直接接觸的實施例,亦可能包含了有附加特徵形成於第一特徵與第二特徵之間,而使得第一特徵與第二特徵可能未直接接觸的實施例。另外,在本揭露不同範例中可能使用重複的參考符號及/或標記,此重複係為了簡化與清晰的目的,並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
再者,空間相關用語,例如“在…下方”、“下方”、“較低的”、“在…上方”、“較高的”及類似的用語,是為了便於描述圖式中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。
根據各種實施例,通過接合積體電路裸晶(integrated circuit dies)形成裸晶堆疊(die stacks),且用於積體電路裸晶的接合墊(bonding pads)包括奈米孿晶銅層(nano-twinned copper layers)。與非奈米孿晶銅相比,奈米孿晶銅可以在更低溫度和更低壓力下混合(intermingle)。因此,在積體電路裸晶的接合過程中可使用低溫接合製程。使用低溫接合製程可以提高所得的裸晶堆疊的可靠性並提高裸晶整合(die integration)的容易程度(ease)。此外,與非奈米孿晶銅相比,奈米孿晶銅可以承受更大的拉伸應變並具有更大的電遷移(electromigration)。因此,接合墊之間的接合強度大,且接合強度不會因任何後續執行的熱退火製程而顯著降低。
第1圖至第8圖是根據一些實施例之一積體電路裸晶100之製造的中間階段的剖視圖。示出了一個裝置區域102D,且在裝置區域102D中形成一個積體電路裸晶100。積體電路裸晶100可以是邏輯裝置(例如中央處理單元(central processing unit, CPU)、圖形處理單元(graphics processing unit, GPU)、微控制器等)、記憶體裝置(例如動態隨機存取記憶體(dynamic random access memory, DRAM)裸晶、靜態隨機存取記憶體(static random access memory, SRAM)裸晶等)、功率管理裝置(例如功率管理積體電路(power management integrated circuit, PMIC)裸晶)、射頻(radio frequency, RF)裝置、感應器裝置、微機電系統(micro-electro-mechanical-system, MEMS)裝置、信號處理裝置(例如數位信號處理(digital signal processing, DSP)裸晶)、前端裝置(例如類比前端(analog front-end, AFE)裸晶)等或上述的組合(例如系統單晶片(system-on-a-chip, SoC)裸晶)。積體電路裸晶100可以在一個晶圓中形成,該晶圓包括多個裝置區域102D。裝置區域102D隨後被分割(singulated)以形成多個積體電路裸晶100。
在第1圖中,形成或提供一半導體基板102。半導體基板102可以是摻雜和未摻雜的矽基板、或者是絕緣體上半導體(semiconductor-on-insulator, SOI)基板的主動層。半導體基板102可以包括其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括矽鍺、磷化砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦及/或磷化砷化鎵銦;或上述的組合。也可以使用其他基板,例如多層或梯度基板。半導體基板102具有主動面(例如第1圖中朝上的表面),有時成為正面,和非主動面(例如第1圖中朝下的表面),有時稱為背面。
裝置104(由電晶體表示)形成在半導體基板102的主動面處。裝置104可以是主動裝置(例如電晶體、二極體等)、電容器、電阻器等。裝置104可以通過可接受的沉積、光微影和蝕刻技術在前端(front-end of line, FEOL)製程中形成。舉例來說,裝置104可以包括柵極結構以及源極/汲極區,其中柵極結構位於通道區上,源極/汲極區與通道區相鄰。通道區可以是半導體基板102的圖案化區。舉例來說,通道區可以是在半導體基板102中圖案化的半導體鰭片、半導體奈米片、半導體奈米線等的區域。當裝置104是電晶體時,它們可以是奈米結構場效應電晶體(nanostructure field-effect transistors, Nanostructure-FETs)、鰭式場效應電晶體(fin field-effect transistors, FinFETs)、平面電晶體等。
層間電介質(inter-layer dielectric)106形成在半導體基板102的主動面上方。層間電介質106圍繞並可以覆蓋裝置104。層間電介質106可以包括由例如磷矽玻璃(Phospho-Silicate Glass, PSG)、硼矽玻璃(Boro-Silicate Glass, BSG)、硼摻雜磷矽玻璃(Boron-Doped Phospho-Silicate Glass, BPSG)、未摻雜矽玻璃(undoped Silicate Glass, USG)等材料形成的一或多個介電層,其可以通過例如化學氣相沉積(chemical vapor deposition, CVD)等的沉積製程形成。接點108通過層間電介質106形成以電性和物理耦接裝置104。舉例來說,當裝置104是電晶體時,接點108可以耦接電晶體的柵極和源極/汲極區。接點108可以由合適的導電材料形成,例如鎢、鈷、鎳、銅、銀、金、鋁等或上述的組合,其可以通過例如物理氣相沉積(physical vapor deposition, PVD)或化學氣相沉積的沉積製程、例如電解或化學鍍的鍍覆(plating)製程等形成。
互連結構110形成在層間電介質106和接點108上方。互連結構110將裝置104互連以形成積體電路,且可以在後端(back-end of line, BEOL)製程中形成。互連結構110可以由例如介電層114中的金屬化圖案112形成。介電層114可以是例如低介電常數(low-k)介電層。金屬化圖案112可以包括金屬線(lines)和通孔(vias),其可以通過例如單鑲嵌製程、雙鑲嵌製程等的鑲嵌製程形成在介電層114中。金屬化圖案112可以由合適的導電材料形成,例如銅、鎢、鋁、銀、金、上述的組合等。金屬化圖案112通過接點108電性耦接到裝置104。
在第2圖中,一或多個鈍化層116形成在互連結構110上。鈍化層116可以由下列材料形成:一或多種合適的介電材料,例如氮氧化矽、氮化矽、低介電常數電介質例如碳摻雜氧化物、極低介電常數電介質例如多孔碳摻雜氧化矽等;聚合物,例如聚酰亞胺、阻焊劑、聚苯並噁唑(polybenzoxazole, PBO)、苯並環丁烯(benzocyclobutene, BCB)基的聚合物、模塑料(molding compound)等;類似物;或上述的組合。鈍化層116可以通過化學氣相沉積、旋塗、層壓等或上述的組合形成。在一些實施例中,鈍化層116包括氮化矽層。
測試墊122形成為延伸穿過鈍化層116以電性和物理耦接到互連結構110的上部金屬化圖案112。測試墊122用於裝置測試,且在積體電路裸晶100的正常操作期間可以不耦接到互連結構110。在一些實施例中,測試墊122由低成本導電材料(例如鋁)形成。測試墊122可以通過鑲嵌製程形成,例如單鑲嵌製程。
然後對積體電路裸晶100執行電路探針(Circuit probe, CP)測試以確定積體電路裸晶100是否是已知良品裸晶(known good die, KGD)。積體電路裸晶100通過使用探針執行測試。探針通過例如測試連接器電性和物理耦接到測試墊122。僅有是已知良品裸晶的積體電路裸晶100會經過後續處理和封裝,而未通過電路探針測試的裸晶則不被進一步處理。測試可以包括測試積體電路裸晶100的功能,或者可以包括測試基於積體電路裸晶100的設計而可能預期的已知開路或短路。在測試完成之後,探針被移除,且測試墊122上的任何多餘的可回焊(reflowable)材料可以通過例如蝕刻製程、化學機械拋光(chemical-mechanical polish, CMP)製程、研磨製程等來去除。
在第3圖中,介電層124形成在測試墊122和鈍化層116上。介電層124橫向地圍繞測試墊122,且掩埋測試墊122,使得測試墊122在積體電路裸晶100中保持隔離。介電層124可以由下列材料形成:聚合物,例如聚苯並噁唑、聚酰亞胺、苯並環丁烯基的聚合物等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽玻璃、硼矽玻璃、硼摻雜磷矽玻璃、原矽酸四乙酯(tetraethyl orthosilicate, TEOS)基的氧化物;類似物;或上述的組合。介電層124可以通過例如旋塗、層壓、化學氣相沉積等形成。在一些實施例中,介電層124由原矽酸四乙酯基的氧化矽形成。
在第4圖中,在介電層124和鈍化層116中圖案化互連開口(包括通孔開口126和溝槽128)。互連開口可以通過可接受的光微影和蝕刻技術形成。通孔開口126延伸穿過介電層124和鈍化層116,且暴露互連結構110的上部金屬化圖案112。溝槽128是延伸到介電層124中的凹槽。溝槽的第一子集(128A)設置於所示剖視圖中的相應通孔開口126上方,使得通孔開口126將溝槽128A連接到互連結構110的上部金屬化圖案112。溝槽的第二子集(128B)未設置於所示剖視圖中的相應通孔開口126上方。通孔開口126具有大深寬比(例如高度與寬度的比)。在一些實施例中,通孔開口126的深寬比在0.5至12的範圍內。溝槽128具有低深寬比。在一些實施例中,溝槽128的深寬比在0.2至3的範圍內。
在第5圖中,導電層130形成在通孔開口126中和溝槽128的下部。導電層130可以由導電材料形成,例如銅、鋁、鎢、鈷、金、上述的組合等,其可以通過例如電解或化學鍍的鍍覆製程、例如物理氣相沉積或化學氣相沉積的沉積製程等形成。
在一些實施例中,導電層130由銅形成,使得導電層130為銅層。銅層具有包括多個晶粒(grains)的多晶結構。晶粒具有非均勻取向(non-uniform orientation),使得大部分晶粒不具有相同的晶格方向(lattice direction)。具有非均勻晶向(grain orientation)的銅層可以稱為非孿晶銅層(non-twinned copper layer)。隨後將針對第9圖至第11圖描述導電層130的多晶結構。在其他實施例中,導電層130由另一種導電材料形成。
導電層130的厚度小,且被控制為使得導電層130填充通孔開口126但不填充溝槽128。具體地,導電層130形成的厚度足夠小以使得導電層130不完全填充溝槽128,但足夠大以使得導電層130完全填充通孔開口126。在一些實施例中,導電層130形成為1 µm至6 µm範圍內的厚度。
在本實施例中,導電層130通過保形(conformal)製程形成,使得溝槽128中的導電層130保形地襯於(lines)溝槽128的底部和側壁。如此一來,溝槽128的底部處的導電層130的厚度基本上等於(在製程變異範圍內)溝槽128的側壁處的導電層130的厚度。在另一個實施例中(隨後將針對第15圖至第17圖進行描述),導電層130通過自底向上(bottom-up)製程形成,使得溝槽128的底部處的導電層130的厚度大於溝槽128的側壁處的導電層130的厚度。
作為通過保形製程形成導電層130的示例,晶種層1301形成在介電層124上和互連開口(包括通孔開口126和溝槽128)中。在一些實施例中,晶種層1301為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層1301包括鈦層和位於鈦層上方的銅層。可以使用例如物理氣相沉積等來形成晶種層1301。然後在晶種層1301上鍍覆導電材料1302,例如前述材料中的一種。在一些實施例中,導電材料1302為通過電鍍製程形成的銅。電鍍製程具有大的鍍覆保形性(plating conformality),使得通孔開口126中的鍍覆速率基本上等於(在製程變異範圍內)溝槽128中的鍍覆速率。具體地,導電材料1302是通過將晶種層1301浸入鍍覆溶液中而形成。鍍覆溶液可以是例如硫酸電解液。鍍覆溶液包含導電材料1302的陽離子。將電流施加到鍍覆溶液以還原陽離子,從而形成導電材料1302。導電材料1302可用低鍍覆電流進行鍍覆(這允許電鍍製程具有大的鍍覆保形性),且可以短時間鍍覆(這減少了導電層130的厚度)。在一些實施例中,導電材料1302以1 A至5 A範圍內的鍍覆電流和80秒至300秒範圍內的持續時間進行鍍覆。使用在這些範圍內的鍍覆電流和持續時間鍍覆導電材料1302允許導電層130形成為期望的厚度(如之前描述的)。如隨後將更詳細描述的,通孔開口126中的導電層130的部分將形成導電通孔152(參見第7圖)。以大的鍍覆保形性來鍍覆導電材料1302也降低了在導電通孔152中形成空隙或裂縫的風險,特別是當通孔開口126具有大深寬比時。避免在導電通孔152中形成空隙或裂縫可降低導電通孔152的電阻,從而提高積體電路裸晶100的性能。
在第6圖中,導電層140形成在溝槽128的上部。導電層140可以由導電材料形成,例如銅、鋁、鎢、鈷、金、上述的組合等,其可以通過例如電解或化學鍍的鍍覆製程、例如物理氣相沉積或化學氣相沉積的沉積製程等形成。
在一些實施例中,導電層140由銅形成,使得導電層140為銅層。銅層具有包括多個晶粒的多晶結構。晶粒具有均勻取向(uniform orientation),使得大部分晶粒具有相同的晶格方向。具有均勻晶向(grain orientation)的銅層可以稱為奈米孿晶銅層(nano-twinned copper layer)。如隨後將更詳細描述的,溝槽128中的導電層140和導電層130的部分將形成接合墊154(參見第7圖)。形成具有均勻晶向的導電材料的接合墊154允許在低溫下執行接合製程並提高所得的接合的強度,從而增加積體電路裸晶100的可靠性。隨後將針對第9圖至第11圖描述導電層140的多晶結構。在其他實施例中,導電層140由另一種導電材料形成。更一般地,導電層140可以由具有多晶結構的任何導電材料形成。
導電層140的厚度大,且被控制為使得導電層140填充溝槽128(包括本實施例中的溝槽128A和溝槽128B)。具體地,導電層140形成的厚度足夠大以使得導電層140完全填充(並可能過度填充)溝槽128。在一些實施例中,導電層140形成為0.1 µm至6 µm範圍內的厚度。導電層140填充未被導電層130填充的溝槽128的剩餘部分。導電層140可以比導電層130厚。
作為形成導電層140的示例,將導電材料(例如前述材料中的一種)鍍覆在導電層130上。在一些實施例中,導電材料為通過電鍍製程形成的銅。具體地,導電材料是通過將導電層130浸入鍍覆溶液中而形成。鍍覆溶液可以是例如硫酸電解液。鍍覆溶液包含導電材料的陽離子。在一些實施例中,導電層130和導電層140使用相同的鍍覆溶液進行鍍覆。將電流施加到鍍覆溶液以還原陽離子,從而形成導電材料。導電材料可用高鍍覆電流進行鍍覆(這允許電鍍製程形成具有均勻晶向的導電材料),且可以長時間鍍覆(這增加了導電層140的厚度)。與導電層130相比,導電層140以更大的鍍覆電流和更長的持續時間進行鍍覆。在一些實施例中,導電材料以7 A至12 A範圍內的鍍覆電流和250秒至500秒範圍內的持續時間進行鍍覆。使用在這些範圍內的鍍覆電流和持續時間鍍覆導電材料允許導電層140形成為期望的厚度(如之前描述的),且使得鍍覆的導電材料具有均勻晶向。此外,因為溝槽128具有低深寬比,所以在導電層140中形成空隙或裂縫的風險較低,即使導電材料未以大的鍍覆保形性進行鍍覆。
在第7圖中,執行去除製程以去除導電層130和導電層140的多餘部分,這些多餘部分位於介電層124的頂表面之上,從而形成導電通孔152和接合墊154。在去除製程之後,導電層130具有留在通孔開口126中的部分(從而形成導電通孔152),且導電層130和導電層140具有留在溝槽128中的部分(從而形成接合墊154)。在一些實施例中,可以使用平坦化製程,例如化學機械拋光(CMP)、回蝕(etch-back)製程、上述的組合等。執行平坦化製程,直到導電層140的頂表面與導電層130的頂表面和介電層124的頂表面基本上共面(在製程變異範圍內)。在平坦化製程之後,介電層124和接合墊154的頂表面基本上共面(在製程變異範圍內)。介電層124和接合墊154的基本上共面的頂表面位於積體電路裸晶100的正面,其將用於後續接合製程。
如上所述,導電層130的厚度較小,而導電層140的厚度較大。正因為如此,導電通孔152包括導電層130的部分而不包括導電層140的任何部分。同理,接合墊154包括導電層130和導電層140兩者的部分。每個導電通孔152的導電層130與相應的上覆(overlying)接合墊154的導電層130是連續的。如上所述,導電層130以大的鍍覆保形性進行鍍覆。具體地,導電層130以比導電層140更大的鍍覆保形性來進行鍍覆。從導電通孔152中省略導電層140使得導電通孔152包括以大的鍍覆保形性鍍覆的導電層130,降低了在導電通孔152中形成空隙或裂縫的風險,特別是當導電通孔152具有高深寬比時。在導電層130是保形地形成的本實施例中,接合墊154中的導電層130的水平部分(例如在導電層140下方的部分)與接合墊154中的導電層130的垂直部分(例如在導電層140與介電層124之間的部分)具有基本上相同的厚度(在製程變異範圍內)。
在第8圖中,通過沿著劃線區域,例如在裝置區域102D與相鄰裝置區域(未單獨示出)之間執行單片化(singulation)製程156。單片化製程156可以包括鋸切製程、雷射切割製程等。單片化製程156將裝置區域102D與相鄰裝置區域分割。所得的單片化積體電路裸晶100來自裝置區域102D。在單片化製程156之後,半導體基板102、層間電介質106、互連結構110、鈍化層116和介電層124的單片化部分是橫向相連的(laterally coterminous)。
接合墊154將用於後續的接合製程。每個接合墊154包括導電層130和導電層140。如上所述,導電層130、140的材料具有包括多個晶粒的多晶結構。導電層130的晶粒具有非均勻取向。導電層140的晶粒具有均勻取向。以下將針對第9圖至第11圖描述導電層130、140的多晶結構,第9圖至第11圖示出導電層130、140的各種視圖。
第9圖示出一個接合墊154的部分,包括導電層130和導電層140。導電層140在其中包括多個奈米柱(nanocolumns)142。奈米柱142具有橫向尺寸D
1(寬度或長度)。在一些實施例中,一個奈米柱142的橫向尺寸D
1在200 nm至2000 nm的範圍內。奈米柱142在垂直方向上伸長並形成奈米級的柱。奈米柱142具有清晰且可區分的邊界,例如當在X射線繞射(X Ray Diffraction, XRD)圖像或電子背向散射繞射(Electron Back Scatter Diffraction, EBSD)圖像中觀察時。具體地,奈米柱142通過垂直邊界相互隔開。奈米柱142可以(或可以不)從導電層130的頂表面延伸到導電層140的頂表面。奈米柱142的邊緣基本上是垂直的,並且可以(或可以不)略微彎曲或傾斜,總體趨勢是從導電層130向上。
第9圖還示出一些奈米柱142的細節。示出了兩個奈米柱142的中間部分的細節。應理解的是,其他奈米柱142可以具有與所示奈米柱142類似的結構。根據一些實施例,每個奈米柱142包括多個奈米板(nanoplates)144,在垂直方向上堆疊而形成奈米柱142。奈米板144具有可清楚區分的界面,例如當在XRD圖像或EBSD圖像中觀察時。奈米板144的橫向尺寸D
1也是對應奈米柱142的橫向尺寸D
1。奈米板144具有厚度T
1。在一些實施例中,奈米板144的厚度T
1在5 nm至400 nm的範圍內。在剖視圖中,奈米板144是細長的,每個奈米板144的橫向尺寸D
1大於其對應的厚度T
1。在一些實施例中,一個奈米板144的比值(D
1/T
1)在5至40的範圍內。不同奈米板144的厚度T
1可以彼此不同。在一些實施例中,兩個相鄰奈米板144A、奈米板144B的厚度T
1A和T
1B的比值(即,T
1A/T
1B)在0.25至80的範圍內。不同奈米板144的厚度T
1可以彼此相同,使得比值(T
1A/T
1B)等於1.0。另外,一個奈米柱142中奈米板144的最大厚度與奈米板144的最小厚度之比值可以小於約80。一個奈米柱142中奈米板144的頂表面和底表面可以與相鄰奈米柱142中它們接觸的奈米板144的頂表面和底表面齊平、高於或低於它們(以隨機方式)。
在一些實施例中,所有奈米柱142都具有與相鄰奈米柱142的邊緣接觸的清楚可區分的邊緣(例如在XRD圖像或EBSD圖像中)。所述邊緣也基本上是垂直的。在其他實施例中,大多數奈米柱142具有清楚可區分的邊緣(基本上是垂直的)以將它們與相鄰奈米柱142分開,而少量(例如少於5%)的奈米板144可能延伸到相鄰奈米柱142中。舉例來說,兩個相鄰奈米柱142中的一些奈米板144可以彼此融合(merge),使得沒有可區分的邊緣將它們彼此分開。
第10圖示出導電層130的多晶結構和導電層140的多晶結構。具體地,示出了導電層140的單個奈米柱142的多晶結構。為了圖式清晰,省略了其他奈米柱142。
導電層130具有多晶結構,其中包括多個晶粒136。每個晶粒136具有與相鄰晶粒136的晶體結構不同及/或錯位以形成邊界的晶體結構。導電層130內的晶粒136可以具有彼此不同的形狀和彼此不同的尺寸。導電層130內的晶粒136的邊界是不規則的(隨機的、無重複圖案)且彼此不對齊,使得晶粒136的圖案不規則。晶粒136的不規則圖案分布在整個導電層130中。
導電層130的晶粒136具有非均勻取向。具體地,導電層130的晶粒136具有隨機的晶格取向。因此,導電層130的大部分晶粒136不具有相同的晶格方向。
每個奈米板144具有多晶結構,其中包括多個晶粒146。每個晶粒146具有與其相鄰晶粒146的晶體結構不同及/或錯位以形成邊界的晶體結構。每個奈米板144內的晶粒146可以具有彼此不同的形狀和彼此不同的尺寸。每個奈米板144內的晶粒146的邊界是不規則的(隨機的、無重複圖案)且彼此不對齊。每個奈米板144內的晶粒146的不規則圖案分布在整個奈米板144中。每個奈米板144內的頂部晶粒146的頂表面基本上彼此共面以形成奈米板144的基本上平坦的頂表面,其還與其上覆的奈米板144形成平面界面。在一些實施例中,奈米板144的頂部晶粒146的頂表面具有小於約5%的厚度T
1的高度變化。類似地,每個奈米板144內的底部晶粒146的底表面基本上彼此共面以形成奈米板144的基本上平坦的底表面。在一些實施例中,奈米板144的底部晶粒146的底表面具有小於約5%的厚度T
1的高度變化。奈米板144的側壁處的晶粒146的邊緣也基本上對齊以形成基本上垂直的邊緣。在一些實施例中,奈米板144的側壁處的晶粒146的邊緣的偏移量小於厚度T
1的約10%。因此,在剖視圖中,每個奈米板144可以具有矩形形狀並具有清晰可區分的邊界。奈米板144通過水平邊界相互隔開。
奈米板144的晶粒146具有均勻取向。具體地,奈米板144的大部分晶粒146可以具有相同的晶格方向,其可以在<111>晶面(crystal plane)中。在一些實施例中,超過85%(按體積計)的晶粒146是<111>取向,而其餘百分比(按體積計)的晶粒146則具有其他晶格取向。當奈米板144的大部分晶粒146具有相同的晶格方向且導電層130的大部分晶粒136不具有相同的晶格方向時,可以說奈米板144的晶粒146比導電層130的晶粒136具有更大的均勻性。
第11圖是接合墊154的一部分(特別是導電層140的一部分)的俯視圖。在導電層140中,多個奈米柱142相鄰排列並彼此連接。同一奈米柱142中的奈米板144在俯視圖中可以具有相同(或相似)的形狀和相同(或相似)的尺寸,這也分別是由這些奈米板144形成的各別的奈米柱142在俯視圖中的形狀和尺寸。
如第9圖至第11圖中所示,多個晶粒146共同形成奈米板144,其具有清晰的頂表面、清晰的底表面和清晰的邊緣,每一者都是由於外部晶粒146的外表面的對齊而形成的。多個奈米板144堆疊而形成一個奈米柱142。多個奈米柱142進一步排列而形成一個導電層140。在一些實施例中,所有奈米柱142在其中包括奈米板144。在其他實施例中,一些(例如超過約80%)的奈米柱142在其他包括奈米板144,且這些奈米柱142可以稱為堆疊式(stacked)奈米柱。
可能存在(或可能不存在)其中不具有堆疊的奈米板144的其他奈米柱142,且這些奈米柱142可以稱為非堆疊式奈米柱142。非堆疊式奈米柱142也具有其中包括多個晶粒146的多晶結構,但其中不具有將非堆疊式奈米柱142劃分為堆疊的奈米板的清晰界面,而是晶粒146的不規則圖案分布在整個非堆疊式奈米柱142中。在一些實施例中,非堆疊式奈米柱142從導電層130的頂表面延伸到導電層140的頂表面。導電層130具有與非堆疊式奈米柱142相似的結構,因此非堆疊式奈米柱142可以與導電層130融合而不會形成可區分的界面。在另一些其他實施例中,一些奈米柱142被劃分為上部和下部,且上部可以是非堆疊式奈米柱142,而對應的下部可以是堆疊式奈米柱142,反之亦然。
可以通過控制用於形成導電層130和導電層140的鍍覆製程的參數來形成導電層130、140的多晶結構。具體地,通過利用先前描述的鍍覆電流和持續時間來鍍覆導電層130、140允許導電層130、140形成為具有期望的多晶結構。
第12圖是根據一些實施例之一裸晶堆疊的剖視圖。裸晶堆疊包括以面對面方式接合的兩個積體電路裸晶100(包括第一積體電路裸晶100A和第二積體電路裸晶100B)。如此一來,第一積體電路裸晶100A的正面接合到第二積體電路裸晶100B的正面。裸晶堆疊可以是一積體電路封裝(例如系統整合晶片(system-on-integrated-chip, SoIC)封裝等)的部分。
作為接合製程的示例,可以通過混合接合將第一積體電路裸晶100A接合到第二積體電路裸晶100B。介電層124(包括介電層124A和介電層124B)通過介電對介電接合(dielectric-to-dielectric bonding)直接接合,而不使用任何黏合劑材料(例如裸晶附接膜(die attach film))。接合墊154(包括接合墊154A和接合墊154B)通過金屬對金屬接合(metal-to-metal bonding)直接接合,而不使用任何共晶材料(例如焊料)。所述接合可以包括預接合和退火。在預接合期間,施加小的壓力以將第一積體電路裸晶100A和第二積體電路裸晶100B彼此壓靠。預接合在低溫下進行,例如約室溫,例如15 °C至30 °C範圍內的溫度,且在預接合之後,介電層124A和介電層124B彼此接合。然後在隨後的退火步驟中提高接合強度,其中對介電層124A、124B和接合墊154A、154B進行退火。在退火之後,形成例如融熔鍵結(fusion bonds)的直接鍵結(direct bonds),將介電層124A接合到介電層124B。舉例來說,所述鍵結可以是介電層124A的材料與介電層124B的材料之間的共價鍵。接合墊154A與接合墊154B一一對應地連接。接合墊154A和接合墊154B可以在預接合之後物理接觸,或者可以在退火期間膨脹以進行物理接觸。另外,在退火期間,接合墊154A和接合墊154B的材料(例如銅)混合(intermingle),從而也形成金屬對金屬鍵結。因此,第一積體電路裸晶100A和第二積體電路裸晶100B之間所得的鍵結是混合鍵結(hybrid bonds),包括介電對介電鍵結和金屬對金屬鍵結。
接合墊154的頂表面包括奈米孿晶銅層(例如導電層140)的頂表面,使得各對(pairs)接合墊154的界面包含奈米孿晶銅。奈米孿晶銅層(例如導電層140)可以在比非孿晶銅層(例如導電層130)更低的溫度和更低的壓力下混合。如此一來,接合墊154A和接合墊154B可以在接合製程期間在低溫和低壓(例如低真空)下退火。此外,接合墊154A和接合墊154B可以在接合製程期間以短時間退火。所述接合製程為低溫接合製程。在本文中,低溫接合製程是在低於約300 °C的溫度和低於約1000 kgf/cm
2的壓力下執行的接合製程。在一些實施例中,在接合製程期間,介電層124A、124B和接合墊154A、154B在150 °C至250 °C範圍內的溫度下退火。使用低溫接合製程可以提高所得的裸晶堆疊的可靠性並提高裸晶整合的容易程度。此外,與非孿晶銅相比,奈米孿晶銅可以承受更大的拉伸應變並具有更大的電遷移。因此,接合墊154A、154B之間的接合強度大,且接合強度不會因任何後續執行的熱退火製程而顯著降低。
當接合墊154A、154B的材料在接合期間混合時,成對的接合墊154A、154B形成各別的接合墊結構158。具體地,當各對接合墊154A、154B的導電層130(包括導電層130A和導電層130B)接合時,它們融合以形成各別的接合層結構138。類似地,當各對接合墊154A、154B的導電層140(包括導電層140A和導電層140B)接合時,它們融合以形成各別的接合層結構148。接合墊結構158的接合墊154A、154B之間的界面(包括導電層130A、130B的界面和導電層140A、140B的界面)可能是無法區分的。所得的接合層結構148中的每一者在所有側面上被相應的接合層結構138包圍。
接合墊結構158的尺寸可以很小,這有助於在低溫接合製程期間增加鍵結強度。在一些實施例中,導電通孔152具有小於約8 µm的寬度W
1,例如在1 µm至8 µm的範圍內。在一些實施例中,接合墊154具有小於約10 µm的寬度W
2,例如在2 µm至10 µm的範圍內。在一些實施例中,導電通孔152具有大於約4 µm的高度H
1,例如在4 µm至12 µm的範圍內。在一些實施例中,接合墊154具有大於約2 µm的厚度T
2,例如在2 µm至6 µm的範圍內。在一些實施例中,接合層結構148具有大於約0.2 µm的厚度T
3,例如在0.2 µm至12 µm的範圍內。在一些實施例中,每個接合墊154的導電層140的厚度(例如約一半的厚度T
3)大於約0.1 µm,例如在0.1 µm至6 µm的範圍內。在一些實施例中,各對導電通孔152A、152B具有大於約8 µm的組合厚度T
4,例如在8 µm至24 µm的範圍內。厚度T
3相對於組合厚度T
4較小。在一些實施例中,比值(T
3/T
4)大於約0.025,例如在0.025至0.75的範圍內。在一些實施例中,接合墊結構158具有大於約4 µm的厚度T
5,例如在4 µm至12 µm的範圍內。厚度T
3相對於厚度T
5較小。在一些實施例中,比值(T
3/T
5)大於約0.05,例如在0.05至1的範圍內。
第13圖是根據一些實施例之一裸晶堆疊的剖視圖。此實施例類似於針對第12圖描述的實施例,除了不是所有的接合墊154都包括奈米孿晶銅層(例如導電層140)。具體地,形成在溝槽128A(參見第4圖至第6圖)中的接合墊154包括導電層130、140兩者的部分,但是形成在溝槽128B(參見第4圖至第6圖)中的接合墊154包括導電層130的部分而不包括導電層140的任何部分。接合墊154是否形成為包括導電層140的部分可以通過調整溝槽128的深寬比來控制,使得導電層140被鍍覆(參見第6圖)在具有高深寬比的溝槽128A中,但不被鍍覆在具有低深寬比的溝槽128B中。如此一來,溝槽128A中的接合墊154的厚度大於溝槽128B中的接合墊154的厚度。從一些接合墊154中省略奈米孿晶銅層(例如導電層140)可以降低製造成本,同時仍允許使用低溫接合。
第14圖是根據一些實施例之一裸晶堆疊的剖視圖。此實施例類似於針對第12圖描述的實施例,除了僅第一積體電路裸晶100A的接合墊154A包括奈米孿晶銅層(例如導電層140A),而第二積體電路裸晶100B的接合墊154B則不包括奈米孿晶銅層。通過將第二積體電路裸晶100B的導電層130B(參見第5圖)鍍覆到較大的寬度,使得導電層130B填充第二積體電路裸晶100B的溝槽128(包括溝槽128A和溝槽128B,參見第4圖至第6圖),可以從第二積體電路裸晶100B中省略奈米孿晶銅層。具體地,導電層130B形成的厚度足夠大以使得導電層130B完全填充(並可能過度填充)溝槽128。從第二積體電路裸晶100B中省略奈米孿晶銅層可以降低製造成本,同時仍允許使用低溫接合。當從第二積體電路裸晶100B中省略奈米孿晶銅層時,接合墊154B的導電層130B接合到接合墊154A的導電層130A、140A兩者。
前面描述的裸晶堆疊可以在所述積體電路裸晶100中的一者或兩者被分割(如第8圖所描述的)之前或之後形成。舉例來說,可以進行裸晶對裸晶接合,其中單片化的第一積體電路裸晶100A被接合到單片化的第二積體電路裸晶100B。類似地,可以進行裸晶對晶圓接合,其中單片化的第一積體電路裸晶100A被接合到包括未單片化的第二積體電路裸晶100B的晶圓。同樣地,可以進行晶圓對晶圓接合,其中包括未單片化的第一積體電路裸晶100A的第一晶圓被接合到包括未單片化的第二積體電路裸晶100B的第二晶圓。
第15圖至第17圖是根據一些其他實施例之一積體電路裸晶100之製造的中間階段的剖視圖。為了製造積體電路裸晶100,可以執行針對第1圖至第4圖描述的適當步驟,然後可以執行針對第15圖至第17圖描述的步驟來代替針對第5圖至第7圖描述的步驟,並且可以執行針對第8圖描述的適當步驟以完成積體電路裸晶100的製造。
在第15圖中,導電層130形成在通孔開口126中和溝槽128的下部。在本實施例中,導電層130通過自底向上(bottom-up)製程形成,使得溝槽128中的導電層130不會保形地襯於溝槽128的底部和側壁。因此,溝槽128的底部處的導電層130的厚度大於溝槽128的側壁處的導電層130的厚度。
作為通過自底向上製程形成導電層130的示例,晶種層1301形成在介電層124上和互連開口(包括通孔開口126和溝槽128)中。在一些實施例中,晶種層1301為金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層1301包括鈦層和位於鈦層上方的銅層。可以使用例如物理氣相沉積等來形成晶種層1301。然後在晶種層1301上鍍覆導電材料1302,例如前述材料中的一種。在一些實施例中,導電材料1302為通過電鍍製程形成的銅。電鍍製程具有低的鍍覆保形性,使得通孔開口126中的鍍覆速率大於溝槽128中的鍍覆速率。具體地,導電材料1302是通過將晶種層1301浸入鍍覆溶液中而形成。鍍覆溶液可以是例如硫酸電解液。鍍覆溶液包含導電材料1302的陽離子,且進一步包括促進劑、抑制劑和調平劑(leveler agent)。將電流施加到鍍覆溶液以還原陽離子,從而形成導電材料1302。在鍍覆溶液中包含促進劑、抑制劑和調平劑可降低鍍覆保形性,從而以自底向上的方式進行鍍覆。具體地,促進劑可增加通孔開口126中的鍍覆速率,而抑制劑和調平劑可降低溝槽128中的鍍覆速率。如此一來,導電材料1302由底部向上垂直地形成以填充通孔開口126和溝槽128的下部。在導電材料1302填充溝槽128的上部之前,可以使用定時製程(timed processes)來停止導電材料1302自底向上的鍍覆。以自底向上製程形成導電材料1302也降低了在導電通孔152中形成空隙或裂縫的風險。在一些實施例中,在介電層124的頂表面上方基本上沒有形成導電材料1302。
在第16圖中,導電層140形成在溝槽128的上部。導電層140可以通過與先前針對第6圖描述的類似製程(例如電鍍製程)來形成。
在第17圖中,執行去除製程以去除導電層130和導電層140的多餘部分,這些多餘部分位於介電層124的頂表面之上,從而形成導電通孔152和接合墊154。可以通過與先前針對第7圖描述的類似製程(例如平坦化製程)來進行去除。在導電層130是以自底向上的方式形成的本實施例中,接合墊154中的導電層130的水平部分(例如在導電層140下方的部分)可以比接合墊154中的導電層130的垂直部分(例如在導電層140與介電層124之間的部分)具有更大的厚度。
第18圖是根據一些實施例之一裸晶堆疊的剖視圖。此實施例類似於針對第12圖描述的實施例,除了導電層130是通過自底向上製程形成的。
第19圖是根據一些實施例之一裸晶堆疊的剖視圖。此實施例類似於針對第13圖描述的實施例,除了導電層130是通過自底向上製程形成的。
第20圖是根據一些實施例之一裸晶堆疊的剖視圖。此實施例類似於針對第14圖描述的實施例,除了導電層130是通過自底向上製程形成的。
本揭露實施例可以達到許多優點。形成至少一些接合墊154使得它們包括奈米孿晶銅層(例如導電層140),允許了在裸晶接合期間使用低溫接合製程。使用低溫接合製程可以提高所得的裸晶堆疊的可靠性並提高裸晶整合的容易程度。此外,與非孿晶銅相比,奈米孿晶銅可以承受更大的拉伸應變並具有更大的電遷移。因此,接合墊154之間的接合強度大,且接合強度不會因任何後續執行的熱退火製程而顯著降低。另外,從導電通孔152中省略導電層140使得導電通孔152包括以大的鍍覆保形性或自底向上製程鍍覆的導電層130,降低了在導電通孔152中形成空隙或裂縫的風險,特別是當導電通孔152具有高深寬比時。
在一個示例性實施例中,一種裝置包括:介電層,位於半導體基板的主動面上方;導電通孔,位於介電層中,且導電通孔包括第一銅層,具有非均勻晶向;以及接合墊,位於導電通孔上方和介電層中,且接合墊包括第二銅層,具有均勻晶向,接合墊的頂表面與介電層的頂表面共面。在所述裝置的一些實施例中,第二銅層包括多個銅奈米柱,每個銅奈米柱包括多個銅奈米板,銅奈米板沿遠離第一銅層延伸的垂直方向堆疊。在所述裝置的一些實施例中,銅奈米柱通過垂直邊界相互隔開。在所述裝置的一些實施例中,銅奈米板通過水平邊界相互隔開。在所述裝置的一些實施例中,第一銅層包括多個第一晶粒,具有分布在整個第一銅層中的不規則圖案,且所述銅奈米板中的每個銅奈米板包括多個第二晶粒,具有分布在整個銅奈米板中的不規則圖案。在所述裝置的一些實施例中,接合墊還包括第一銅層,其中第二銅層設置於第一銅層上方。
在一個示例性實施例中,一種裝置包括:第一積體電路裸晶,包括:第一介電層;以及第一接合墊,位於第一介電層中,且第一接合墊包括第一導電層和位於第一導電層上的第二導電層,第一導電層包括多個第一晶粒,第二導電層包括多個第二晶粒,其中大部分第一晶粒不具有相同的晶格方向,且大部分第二晶粒具有相同的晶格方向;以及第二積體電路裸晶,包括:第二介電層,通過介電對介電鍵結直接接合到第一介電層;以及第二接合墊,位於第二介電層中,且第二接合墊通過金屬對金屬鍵結直接接合到第一接合墊。在所述裝置的一些實施例中,大多數第二晶粒是<111>取向。在所述裝置的一些實施例中,第二接合墊包括第三導電層和位於第三導電層上方的第四導電層,第三導電層接合到第一導電層,第四導電層接合到第二導電層。在所述裝置的一些實施例中,第二接合墊包括第三導電層,第三導電層接合到第一導電層並接合到第二導電層。在所述裝置的一些實施例中,第一積體電路裸晶還包括:第三接合墊,位於第一介電層中,第三接合墊包括第三導電層,第三導電層包括多個第三晶粒,具有分布在整個第三接合墊中的不規則圖案。在所述裝置的一些實施例中,第一導電層是第一銅層,且第二導電層是第二銅層。
在一個示例性實施例中,一種方法包括:在介電層中圖案化互連開口,介電層設置於半導體基板的主動面上方,互連開口具有通孔開口和位於通孔開口上方的溝槽;在互連開口中鍍覆第一銅層,第一銅層填充通孔開口並襯於溝槽內,第一銅層具有非均勻晶向;在第一銅層上鍍覆第二銅層,第二銅層填充溝槽的剩餘部分,第二銅層具有均勻晶向;以及平坦化第二銅層、第一銅層和介電層,直到第二銅層的頂表面與第一銅層的頂表面和介電層的頂表面共面。在所述方法的一些實施例中,第二銅層的鍍覆電流大於第一銅層的鍍覆電流。在所述方法的一些實施例中,第二銅層的鍍覆時間比第一銅層的鍍覆時間長。在所述方法的一些實施例中,第二銅層的厚度大於第一銅層的厚度。在所述方法的一些實施例中,第一銅層包括多個第一晶粒,具有分布在整個第一銅層中的不規則圖案。在所述方法的一些實施例中,第二銅層包括多個銅奈米柱,每個銅奈米柱包括多個銅奈米板,所述銅奈米板中的每個銅奈米板包括多個第二晶粒,具有分布在整個銅奈米板中的不規則圖案。在所述方法的一些實施例中,平坦化第二銅層、第一銅層和介電層形成第一接合墊於介電層中,且所述方法更包括:將第二接合墊接觸第一接合墊;以及通過低溫接合製程將第一接合墊接合到第二接合墊。在所述方法的一些實施例中,其中低溫接合製程包括:在150 ℃至250 ℃的溫度範圍內對第一接合墊和第二接合墊進行退火。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解,且可輕易地以本揭露為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下,可對本揭露進行各個改變、置換或修改。
100:積體電路裸晶
100A:第一積體電路裸晶
100B:第二積體電路裸晶
102:半導體基板
102D:裝置區域
104:裝置
106:層間電介質
108:接點
110:互連結構
112:金屬化圖案
114:介電層
116:鈍化層
122:測試墊
124, 124A, 124B:介電層
126:通孔開口
128, 128A, 128B:溝槽
130, 130A, 130B:導電層
1301:晶種層
1302:導電材料
136:晶粒
138:接合層結構
140, 140A, 140B:導電層
142:奈米柱
144, 144A, 144B:奈米板
146:晶粒
148:接合層結構
152, 152A, 152B:導電通孔
154, 154A, 154B:接合墊
156:單片化製程
158:接合墊結構
D
1:橫向尺寸
H
1:高度
T
1, T
1A, T
1B, T
2, T
3, T
5:厚度
T
4:組合厚度
W
1, W
2:寬度
根據以下的詳細說明並配合所附圖式做完整揭露。須強調的是,根據本產業的一般作業,圖示並未按照比例繪製。事實上,可能任意的放大或縮小元件的尺寸,以做清楚的說明。
第1圖至第8圖是根據一些實施例之一積體電路裸晶之製造的中間階段的剖視圖。
第9圖至第11圖是根據一些實施例之接合墊的各種視圖。
第12圖是根據一些實施例之一裸晶堆疊(die stack)的剖視圖。
第13圖是根據一些實施例之一裸晶堆疊的剖視圖。
第14圖是根據一些實施例之一裸晶堆疊的剖視圖。
第15圖至第17圖是根據一些其他實施例之一積體電路裸晶之製造的中間階段的剖視圖。
第18圖是根據一些實施例之一裸晶堆疊的剖視圖。
第19圖是根據一些實施例之一裸晶堆疊的剖視圖。
第20圖是根據一些實施例之一裸晶堆疊的剖視圖。
130:導電層
136:晶粒
140:導電層
142:奈米柱
144:奈米板
146:晶粒
Claims (20)
- 一種半導體裝置,包括: 一介電層,位於一半導體基板的一主動面上方; 一導電通孔,位於該介電層中,該導電通孔包括一第一銅層,具有非均勻晶向;以及 一接合墊,位於該導電通孔上方和該介電層中,該接合墊包括一第二銅層,具有均勻晶向,該接合墊的頂表面與該介電層的頂表面共面。
- 如請求項1之半導體裝置,其中該第二銅層包括複數個銅奈米柱,該些銅奈米柱中的每一者包括複數個銅奈米板,該些銅奈米板沿遠離該第一銅層延伸的一垂直方向堆疊。
- 如請求項2之半導體裝置,其中該些銅奈米柱通過垂直邊界相互隔開。
- 如請求項2之半導體裝置,其中該些銅奈米板通過水平邊界相互隔開。
- 如請求項2之半導體裝置,其中該第一銅層包括多個第一晶粒,具有分布在整個該第一銅層中的不規則圖案,且該些銅奈米板中的每個銅奈米板包括多個第二晶粒,具有分布在整個該銅奈米板中的不規則圖案。
- 如請求項1之半導體裝置,其中該接合墊還包括該第一銅層,其中該第二銅層設置於該第一銅層上方。
- 一種半導體裝置,包括: 一第一積體電路裸晶,包括: 一第一介電層;以及 一第一接合墊,位於該第一介電層中,該第一接合墊包括一第一導電層和位於該第一導電層上的一第二導電層,該第一導電層包括多個第一晶粒,該第二導電層包括多個第二晶粒,大多數該些第一晶粒不具有相同的晶格方向,且大多數該些第二晶粒具有相同的晶格方向;以及 一第二積體電路晶粒,包括: 一第二介電層,通過介電對介電鍵結直接接合到該第一介電層;以及 一第二接合墊,位於該第二介電層中,該第二接合墊通過金屬對金屬鍵結直接接合到該第一接合墊。
- 如請求項7之半導體裝置,其中大多數該些第二晶粒係<111>取向。
- 如請求項7之半導體裝置,其中該第二接合墊包括一第三導電層和位於該第三導電層上方的一第四導電層,該第三導電層接合到該第一導電層,該第四導電層接合到該第二導電層。
- 如請求項7之半導體裝置,其中該第二接合墊包括一第三導電層,該第三導電層接合到該第一導電層並接合到該第二導電層。
- 如請求項7之半導體裝置,其中該第一積體電路裸晶還包括: 一第三接合墊,位於該第一介電層中,該第三接合墊包括一第三導電層,該第三導電層包括多個第三晶粒,具有分布在整個該第三接合墊中的不規則圖案。
- 如請求項7之半導體裝置,其中該第一導電層係一第一銅層,且該第二導電層係一第二銅層。
- 一種形成半導體裝置的方法,包括: 在一介電層中圖案化一互連開口,該介電層設置於一半導體基板的一主動面上方,該互連開口具有一通孔開口和位於該通孔開口上方的一溝槽; 在該互連開口中鍍覆一第一銅層,該第一銅層填充該通孔開口並襯於該溝槽內,該第一銅層具有非均勻晶向; 在該第一銅層上鍍覆一第二銅層,該第二銅層填充該溝槽的剩餘部分,該第二銅層具有均勻晶向;以及 平坦化該第二銅層、該第一銅層和該介電層,直到該第二銅層的頂表面與該第一銅層的頂表面和該介電層的頂表面共面。
- 如請求項13之形成半導體裝置的方法,其中該第二銅層的鍍覆電流大於該第一銅層的鍍覆電流。
- 如請求項13之形成半導體裝置的方法,其中該第二銅層的鍍覆時間比該第一銅層的鍍覆時間長。
- 如請求項13之形成半導體裝置的方法,其中該第二銅層的厚度大於該第一銅層的厚度。
- 如請求項13之形成半導體裝置的方法,其中該第一銅層包括多個第一晶粒,具有分布在整個該第一銅層中的不規則圖案。
- 如請求項13之形成半導體裝置的方法,其中該第二銅層包括複數個銅奈米柱,該些銅奈米柱中的每一者包括複數個銅奈米板,該些銅奈米板中的每個銅奈米板包括多個第二晶粒,具有分布在整個該銅奈米板中的不規則圖案。
- 如請求項13之形成半導體裝置的方法,其中平坦化該第二銅層、該第一銅層和該介電層形成一第一接合墊於該介電層中,且形成半導體裝置的方法更包括: 將一第二接合墊接觸該第一接合墊;以及 通過一低溫接合製程將該第一接合墊接合到該第二接合墊。
- 如請求項19之形成半導體裝置的方法,其中該低溫接合製程包括: 在150 ℃至250 ℃的溫度範圍內對該第一接合墊和該第二接合墊進行退火。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202263269989P | 2022-03-28 | 2022-03-28 | |
US63/269,989 | 2022-03-28 | ||
US17/841,223 | 2022-06-15 | ||
US17/841,223 US20230307392A1 (en) | 2022-03-28 | 2022-06-15 | Die Bonding Pads and Methods of Forming the Same |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202338935A true TW202338935A (zh) | 2023-10-01 |
Family
ID=87930657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112100473A TW202338935A (zh) | 2022-03-28 | 2023-01-06 | 半導體裝置及其形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20230307392A1 (zh) |
KR (1) | KR20230140328A (zh) |
DE (1) | DE102023103294A1 (zh) |
TW (1) | TW202338935A (zh) |
-
2022
- 2022-06-15 US US17/841,223 patent/US20230307392A1/en active Pending
- 2022-08-12 KR KR1020220101514A patent/KR20230140328A/ko unknown
-
2023
- 2023-01-06 TW TW112100473A patent/TW202338935A/zh unknown
- 2023-02-10 DE DE102023103294.1A patent/DE102023103294A1/de active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230307392A1 (en) | 2023-09-28 |
KR20230140328A (ko) | 2023-10-06 |
DE102023103294A1 (de) | 2023-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI624006B (zh) | 用於成品率改善的使用銅合金的混合鍵 | |
US8791011B2 (en) | Through-silicon via structure formation process | |
CN113540059A (zh) | 封装的半导体器件及其形成方法 | |
US20190131276A1 (en) | Die stack structure and method of fabricating the same | |
US20230343753A1 (en) | Integrated circuit packages and method of forming the same | |
US20110193197A1 (en) | Structure and method for making crack stop for 3d integrated circuits | |
TW202114111A (zh) | 封裝 | |
TWI705546B (zh) | 三維積體電路結構及其製造方法 | |
US11362069B2 (en) | Three-dimensional stacking structure and manufacturing method thereof | |
US11978716B2 (en) | Package | |
TW202002188A (zh) | 三維積體電路結構 | |
TWI807331B (zh) | 半導體結構及其製造方法 | |
US20230025094A1 (en) | Integrated circuit packages and methods of forming the same | |
TW202333249A (zh) | 半導體裝置及其形成方法 | |
TWI749920B (zh) | 半導體封裝及其形成方法 | |
US20210335627A1 (en) | Backside interconnect for integrated circuit package interposer | |
TW202338935A (zh) | 半導體裝置及其形成方法 | |
CN114864545A (zh) | 半导体装置的制造方法 | |
Bum et al. | Process development of multi-die stacking using 20 um pitch micro bumps on large scale dies | |
CN116487353A (zh) | 半导体器件及其形成方法 | |
TWI838115B (zh) | 裝置封裝體及其製造方法 | |
TWI792311B (zh) | 半導體裝置及其製造方法 | |
TWI836928B (zh) | 半導體封裝及其形成方法 | |
US11756891B2 (en) | Semiconductor device and method for manufacturing same | |
US20230377968A1 (en) | Redistribution layer metallic structure and method |