TWI705546B - 三維積體電路結構及其製造方法 - Google Patents
三維積體電路結構及其製造方法 Download PDFInfo
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- TWI705546B TWI705546B TW108137978A TW108137978A TWI705546B TW I705546 B TWI705546 B TW I705546B TW 108137978 A TW108137978 A TW 108137978A TW 108137978 A TW108137978 A TW 108137978A TW I705546 B TWI705546 B TW I705546B
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Abstract
本發明實施例公開三維積體電路結構及形成所述三維積體電路結構的方法。所述三維積體電路結構中的一者包括第一晶粒、多個第二晶粒以及介電結構。所述第二晶粒結合到所述第一晶粒。所述介電結構設置在所述第二晶粒之間。所述介電結構包括第一介電層及第二介電層。所述第一介電層具有側壁及底部,所述側壁的第一表面與所述底部的第一表面接觸所述第二介電層且形成第一角度。所述側壁的第二表面與所述底部的第二表面形成比所述第一角度小的第二角度。
Description
本發明實施例是有關於一種三維積體電路結構及其製造方法。
近年來,由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等)的集成密度持續提高,半導體行業已經歷快速成長。集成密度的這種提高在很大程度上歸因於最小特徵大小(minimum feature size)的連續減小,這使得更多元件能夠集成到給定區域中。
與先前的封裝相比,這些較小的電子元件需要的佔據面積較小。一些類型的半導體的封裝包括四方扁平封裝(quad flat pack,QFP)、引腳格陣列(pin grid array,PGA)、球格陣列(ball grid array,BGA)、覆晶晶片(flip chip,FC)、三維積體電路(three-dimensional integrated circuit,3DIC)、晶圓級封裝(wafer level package,WLP)以及疊層封裝(package on package,PoP)
裝置。一些3DIC是通過將晶片放置在半導體晶圓級上的晶片之上製備而成。3DIC提供提高的集成密度及其他優點,例如更快的速度及更高的頻寬,這是因為堆疊的晶片之間的內連線的長度減小。然而,存在相當多的對於3DIC的技術而言要處置的挑戰。
本發明實施例的一種三維積體電路結構包括第一晶粒、多個第二晶粒以及介電結構。所述第二晶粒結合到所述第一晶粒。所述介電結構設置在所述第二晶粒之間。所述介電結構包括第一介電層及第二介電層。所述第一介電層具有側壁及底部,所述側壁的第一表面與所述底部的第一表面接觸所述第二介電層且形成第一角度。所述側壁的第二表面與所述底部的第二表面形成比所述第一角度小的第二角度。
本發明實施例的一種三維積體電路結構包括第一晶粒、第二晶粒、第三晶粒、第一介電層及第二介電層。所述第二晶粒及所述第三晶粒結合到所述第一晶粒的表面。所述第一介電層及所述第二介電層設置在所述第二晶粒與所述第三晶粒之間。所述第一介電層包括位於所述第二介電層與所述第二晶粒之間的側壁。所述側壁包括面對所述第二介電層的第一表面及面對所述第二晶粒的第二表面。相對於所述第一晶粒的所述表面,所述第一表面的第一斜率小於所述第二表面的第二斜率。
本發明實施例的一種製造三維積體電路結構的方法包括
以下步驟。提供第一晶粒。將多個第二晶粒結合到所述第一晶粒上,其中在所述多個第二晶粒之間形成間隙。通過執行包括以下製程的至少一個循環而在所述間隙中填充介電材料:通過第一沉積製程,形成第一介電層,所述第一介電層在所述間隙的側壁的頂部部分處相對於在所述間隙的所述側壁的底部部分處具有較小的厚度;以及通過第二沉積製程,在所述間隙之上的所述第一介電層上形成第二介電層。移除所述介電材料的一部分以在所述多個第二晶粒之間形成介電結構,其中所述介電結構的頂表面實質上與所述多個第二晶粒的頂表面共面。
10、10A、10B:三維積體電路(3DIC)結構
100:第一晶粒
100a:表面
102:第一半導體基底
104:第一半導體裝置
106:第一內連結構
108:第一絕緣層
110:第一金屬特徵
110a:第一頂部金屬特徵
112:第一鈍化層
114:第一焊墊
200:第二晶粒
202:第二半導體基底
204:第二半導體裝置
206:第二內連結構
208:第二絕緣層
210:第二金屬特徵
210a:第二頂部金屬特徵
212:第二鈍化層
214:第二焊墊
220、304、BL、BS、F-1、F-2、F1-1、F2-1、F1-2、F2-2:介電層
302:重佈線層結構
306:導電層
308:焊墊
310:鈍化層
312:外部端子
312a:導電柱
312b:凸塊
BDL1:第一結合介電層
BDL2:第二結合介電層
BP1:第一結合焊墊
BP2:第二結合焊墊
BS1:第一結合結構
BS2:第二結合結構
BT1、BT2、BT3、BTP、BTP1、BTP1-1、BTP2-1:底部
BV1:第一結合通孔
BV2:第二結合通孔
d1、d2:水準距離
DS:介電結構
G1、G2、G3、G4、G5:間隙
H:高度
IBT1、IBT1-1、IBT2-1、ISW、ISW1、ISW1-1、ISW1-2、ISW2-1:內表面
LSF:最低表面
OBT1、OBT1-1、OSW1、OSW1-1、OSW2-1:外表面
SW1、SW2、SW3、SWP、SWP1、SWP1-1、SWP1-2、SWP2-1:側壁
t、t1、t2:厚度
TP:頂部
TSV:基底穿孔
U、U1、U2:單元
W:寬度
θ1、θ1’、θ2、θ2’:夾角
結合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的臨界尺寸。
圖1A到圖1H是根據一些實施例的在形成三維積體電路結構的示例性方法期間的各個中間結構的剖視圖。
圖2A是根據本公開一些實施例的3DIC結構的剖視圖,且圖2B是圖2A所示介電結構的局部放大圖。
圖3是根據本公開一些實施例的3DIC結構的剖視圖。
圖4A到圖4D是根據一些實施例的形成介電結構的第一介電層的局部放大剖視圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然,這些僅為實例而非旨在進行限制。舉例而言,在以下說明中,在第一特徵之上或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例,且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外,本公開可在各個實例中重複參考編號和/或字母。此種重複使用是為了簡明及清晰起見,且自身並不表示所討論的各個實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上(on)”、“在...之上(over)”、“上覆在...上(overlying)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。除了圖中所繪示的取向以外,所述空間相對性用語還旨在囊括裝置在使用或操作中的不同取向。設備可具有另外的取向(旋轉90度或處於其他取向),且本文所用的空間相對性描述語可同樣相應地作出解釋。
另外,為易於說明,本文中可能使用例如“第一”、“第二”、“第三”、“第四”等用語來闡述圖中所示相似或不同的元件或特徵,且所述用語可根據說明的存在或上下文的順序互換地使用。
也可包括其他特徵及製程。舉例而言,可包括測試結構以說明對三維(three dimensional,3D)封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試焊墊(test pad),以便能夠對3D封裝或3DIC進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用,以提高良率並降低成本。
圖1A到圖1H是根據一些實施例的在形成三維積體電路結構的示例性方法期間的各個中間結構的剖視圖。
參照圖1A,提供第一晶粒100。第一晶粒100可例如為應用專用積體電路(application-specific integrated circuit,ASIC)晶片、類比(analog)晶片、感測器晶片、無線及射頻晶片(wireless and radio frequency chip)、電壓調節器晶片(voltage regulator chip)或記憶體晶片。在一些實施例中,第一晶粒100可包括主動元件或被動元件。在一些實施例中,第一晶粒100包括第一半導體基底102、第一內連結構106及第一結合結構BS1。
第一半導體基底102包含元素半導體(例如,矽、鍺)和/或化合物半導體(例如,矽鍺、碳化矽、砷化鎵、砷化銦、氮
化鎵或磷化銦)。在一些實施例中,第一半導體基底102包括含矽材料。舉例而言,第一半導體基底102是絕緣體上矽(silicon-on-insulator,SOI)基底或矽基底。在各種實施例中,第一半導體基底102可採用平面基底、具有多個鰭的基底、奈米線形式的基底、或所屬領域中的一般技術人員已知的其他形式的基底。根據設計的要求而定,第一半導體基底102可為P型基底或N型基底且可在其中具有摻雜區。可針對N型裝置或P型裝置配置摻雜區。在一些實施例中,第一半導體基底102中可根據製程要求而具有基底穿孔。
第一半導體基底102包括界定至少一個主動區域的隔離結構,且在所述主動區域上/中設置有至少一個第一半導體裝置104。第一半導體裝置104包括一個或多個功能裝置。在一些實施例中,所述功能裝置包括主動元件、被動元件或其組合。在一些實施例中,所述功能裝置可包括積體電路裝置。所述功能裝置例如為電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置和/或其他相似裝置。在一些實施例中,第一半導體裝置104包括閘極介電層、閘極電極、源極區/漏極區、間隙壁等。
第一內連結構106設置在第一半導體基底102的第一側(例如,前側)之上。具體而言,第一內連結構106設置在第一半導體裝置104之上且電連接到第一半導體裝置104。在一些實施例中,第一內連結構106包括至少一個第一絕緣層108以及多個第一金屬特徵110。第一金屬特徵110設置在第一絕緣層108中且
彼此電連接。第一金屬特徵110的一部分(例如,第一頂部金屬特徵110a)被第一絕緣層108暴露出。在一些實施例中,第一絕緣層108包括位於第一半導體基底102上的層間介電(inter-layer dielectric,ILD)層、以及位於所述層間介電層之上的至少一個金屬間介電(inter-metal dielectric,IMD)層。在一些實施例中,第一絕緣層108包含氧化矽、氮氧化矽、氮化矽、低介電常數(低k)材料或其組合。第一絕緣層108可為單層式結構或多層式結構。在一些實施例中,第一金屬特徵110包括金屬插塞及金屬線。所述插塞可包括形成在層間介電層中的接觸件(contacts)以及形成在金屬間介電層中的通孔(vias)。所述接觸件形成在底部金屬線與下伏的第一半導體裝置104之間且與底部金屬線與下伏的第一半導體裝置104接觸。所述通孔形成在兩條金屬線之間且與這兩條金屬線接觸。第一金屬特徵110可包含鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合。在一些實施例中,可在每一個第一金屬特徵110與第一絕緣層108之間設置障壁層,以防止第一金屬特徵110的材料遷移到下伏的第一半導體裝置104。障壁層包含例如Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,第一內連結構106是通過雙鑲嵌製程形成。在一些替代實施例中,第一內連結構106是通過多個單鑲嵌製程形成。在又一些替代實施例中,第一內連結構106是通過電鍍製程形成。
在一些實施例中,視需要在第一內連結構106之上形成第一鈍化層112。第一鈍化層112覆蓋第一絕緣層108並暴露出第
一頂部金屬特徵110a的部分。在一些實施例中,第一鈍化層112包含氧化矽、氮化矽、苯並環丁烯(benzocyclobutene,BCB)聚合物、聚醯亞胺(polyimide,PI)、聚苯並噁唑(polybenzoxazole,PBO)或其組合,且由例如旋轉塗布、化學氣相沉積(chemical vapor deposition,CVD)製程等合適的製程形成。
在第一內連結構106之上形成第一焊墊114且第一焊墊114電連接到第一內連結構106。在一些實施例中,第一焊墊114進一步延伸到第一鈍化層112中以電連接到第一頂部金屬特徵110a。第一焊墊114與第一金屬特徵110可具有相同或不同的材料。在一些實施例中,第一焊墊114的材料可包括金屬材料,例如鋁、銅、鎳、金、銀、鎢或其組合。第一焊墊114可通過以下步驟來形成:形成通孔洞以暴露出第一頂部金屬特徵110a;通過合適的製程(例如電化學鍍覆製程、CVD製程、原子層沉積(atomic layer deposition,ALD)製程、PVD製程等)沉積金屬材料層以填充在開口中並覆蓋第一鈍化層112;以及接著將金屬材料層圖案化。在一些實施例中,第一焊墊114的厚度可介於例如1μm到3μm的範圍內。
第一結合結構BS1設置在第一半導體基底102的第一側(例如,前側)之上。具體而言,第一結合結構BS1設置在第一內連結構106或第一鈍化層112之上。在一些實施例中,第一結合結構BS1包括至少一個第一結合介電層BDL1及多個第一結合金屬特徵。在一些實施例中,第一結合介電層BDL1包含氧化矽、
氮化矽、聚合物或其組合。第一結合金屬特徵設置在第一結合介電層BDL1中且彼此電連接。在一些實施例中,第一結合金屬特徵可包括第一結合焊墊BP1以及第一結合通孔BV1。具體而言,如圖1A所示,第一結合焊墊BP1電連接到第一結合通孔BV1且因此電連接到第一頂部金屬特徵110a。第一結合金屬特徵可包含鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合。在一些實施例中,可在每一個第一結合金屬特徵與第一結合介電層BDL1之間設置障壁層(未示出)。所述障壁層例如包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,第一結合結構BS1是通過雙鑲嵌製程形成。在一些替代實施例中,第一結合結構BS1是通過多個單鑲嵌製程形成。在又一些替代實施例中,第一結合結構BS1是通過電鍍製程形成。
參照圖1B,提供多個第二晶粒200。第二晶粒200可例如為應用專用積體電路(ASIC)晶片、類比晶片、感測器晶片、無線及射頻晶片、電壓調節器晶片或記憶體晶片。第二晶粒200可為同一類型的晶粒或不同類型的晶粒。出於理解目的,在一些實施例的說明中,第二晶粒200可被稱為第二晶粒及第三晶粒。在一些實施例中,第二晶粒及第三晶粒用於指示設置在第一晶粒100上(或第一晶粒100之上)的晶粒,且第二晶粒及第三晶粒可為同一類型的晶粒或不同類型的晶粒。第二晶粒200及第一晶粒100可為同一類型的晶粒或不同類型的晶粒。在一些實施例中,第二晶粒200可包括主動元件或被動元件。
第二晶粒200可具有與第一晶粒100的結構相似的結構。在一些實施例中,第二晶粒200包括第二半導體基底202、第二內連結構206、第二焊墊214及第二結合結構BS2。因此,以下詳細示出第二晶粒200與第一晶粒100之間的差異,且在本文中不再對所述兩者之間的相似之處進行贅述。
第二半導體基底202在材料及配置方面可相似於第一半導體基底102。在一些實施例中,第二半導體基底202包括界定至少一個主動區域的隔離結構,且在所述主動區域上/中設置有至少一個第二半導體裝置204。第二半導體裝置204包括一個或多個功能裝置。在一些實施例中,所述功能裝置包括主動元件、被動元件或其組合。在一些實施例中,所述功能裝置可包括積體電路裝置。所述功能裝置例如為電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置和/或其他相似裝置。在一些實施例中,第二半導體裝置204包括閘極介電層、閘極電極、源極區/漏極區、間隙壁等。
在一些實施例中,第二晶粒200還包括基底穿孔TSV,基底穿孔TSV穿透過第二半導體基底202。在一些實施例中,當第二半導體基底202是含矽基底時,基底穿孔TSV被稱為“矽穿孔”。基底穿孔TSV電連接到第二內連結構206以及將形成的重佈線層結構302(圖1H所示)。在一些實施例中,基底穿孔TSV包括導電通孔。導電通孔包含銅、銅合金、鋁、鋁合金或其組合。在一些實施例中,每一個基底穿孔TSV還包括位於導電通孔與第
二半導體基底202之間的擴散障壁層。擴散障壁層包含Ta、TaN、Ti、TiN、CoW或其組合。
第二內連結構206可具有與第一內連結構106的結構相似的結構。在一些實施例中,第二內連結構206設置在第二半導體基底202的第一側(例如,前側)之上。具體而言,第二內連結構206設置在第二半導體裝置204之上且電連接到第二半導體裝置204。在一些實施例中,第二內連結構206包括至少一個第二絕緣層208及多個第二金屬特徵210。在一些實施例中,第二金屬特徵210包括金屬插塞及金屬線。第二金屬特徵210設置在第二絕緣層208中且彼此電連接。第二金屬特徵210的一部分(例如,第二頂部金屬特徵210a)被第二絕緣層208暴露出。
在一些實施例中,視需要在第二內連結構206之上形成第二鈍化層212。第二鈍化層212在材料及配置方面可相似於第一鈍化層112。第二鈍化層212覆蓋第二絕緣層208且暴露出第二頂部金屬特徵210a的部分。
第二焊墊214在材料及配置方面可相似於第一焊墊114。第二焊墊214形成在第二內連結構206之上且電連接到第二內連結構206。在一些實施例中,第二焊墊214進一步延伸到第二鈍化層212中,以電連接到第二頂部金屬特徵210a。
第二結合結構BS2可具有與第一結合結構BS1的結構相似的結構。在一些實施例中,第二結合結構BS2設置在第二內連結構206或第二鈍化層212的第一側(例如,前側)之上。在一
些實施例中,第二結合結構BS2包括至少一個第二結合介電層BDL2及多個第二結合金屬特徵。第二結合金屬特徵設置在第二結合介電層BDL2中且彼此電連接。在一些實施例中,第二結合金屬特徵包括第二結合通孔BV2以及第二結合焊墊BP2,第二結合通孔BV2電連接到第二內連結構206的第二頂部金屬特徵210a,第二結合焊墊BP2電連接到第二結合通孔BV2。
第二晶粒200與第一晶粒100之間的一個差異在於晶粒大小。第二晶粒200的大小不同於(例如,小於)第一晶粒100的大小。在本文中,用語“大小”是指長度、寬度和/或面積。舉例而言,如在圖1B的剖視圖中所示,第二晶粒200的寬度小於第一晶粒100的寬度。
仍參照圖1B,將第二晶粒200上下倒置並安裝到第一晶粒100的表面100a上。在一些實施例中,表面100a例如是第一晶粒100的前表面。在結合之後,表面100a也是第一晶粒100與第二晶粒200之間的結合表面。第二晶粒200電耦合到第一晶粒100。在一些實施例中,通過第一結合結構BS1及第二結合結構BS2將第二晶粒200與第一晶粒100面對面地結合在一起。在一些實施例中,在將第二晶粒200結合到第一晶粒100之前,將第二結合結構BS2與第一結合結構BS1對齊,使得第二結合焊墊BP2結合到第一結合焊墊BP1且第二結合介電層BDL2結合到第一結合介電層BDL1。在一些實施例中,可利用光學感測方法實現第一結合結構BS1與第二結合結構BS2的對齊。在實現對齊之後,通
過混合結合將第一結合結構BS1與第二結合結構BS2結合在一起,所述混合結合包括金屬對金屬結合及介電質對介電質結合。
如圖1B所示,在將第二晶粒200結合到第一晶粒100上之後,在第二晶粒200之間形成間隙G1(或者也稱為晶粒與晶粒之間的空間)。在一些實施例中,間隙G1形成在第二晶粒200的側壁以及第一晶粒100的表面100a之間。間隙G1具有側壁SW1及底部BT1。在一些實施例中,舉例而言,側壁SW1可實質上垂直於底部BT1。因此,間隙G1從底部到頂部可具有均勻的寬度。間隙G1的長寬比被定義為間隙G1的高度H對寬度W的比。在一些實施例中,間隙G1的長寬比可例如大於1。在一些實施例中,間隙G1的寬度W可小於20μm,且間隙G1的高度H可大於20μm。然而,本發明並非僅限於此。
參照圖1C到圖1F,闡述介電結構DS,其仲介電結構DS填充到第一晶粒100之上的第二晶粒200(第二晶粒200也可稱為第二晶粒及第三晶粒)之間的間隙G1中。在一些實施例中,如圖1C所示,在第一晶粒100之上形成介電層BL以覆蓋第二晶粒200以及覆蓋第二晶粒200之間的第一晶粒100,且接著形成間隙G2。介電層BL可形成在第二晶粒200的頂表面之上以及間隙G1的側壁SW1及底部BT1之上。在一些實施例中,介電層BL直接接觸間隙G1的側壁SW1及底部BT1,間隙G1的側壁SW1及底部BT1分別屬於第二晶粒200的側壁及第一晶粒100的表面100a。在一些實施例中,介電層BL可通過沉積製程形成,所述沉
積製程向間隙G1的表面提供良好的粘合且高效地提供合適的厚度。因此,可將要形成的介電結構DS穩定地粘合到第一晶粒100及第二晶粒200。在一些實施例中,介電層BL可通過電漿增強CVD(plasma enhanced CVD,PECVD)製程等共形地形成。換句話說,介電層BL可為共形層。本文中使用用語“共形”或“共形地”來闡述在第二晶粒之間的間隙的整個側壁表面上形成具有實質上均勻的厚度的材料。相反,使用用語“非共形”或“非共形地”來闡述在第二晶粒之間的間隙的整個側壁表面上形成具有不均勻的厚度的材料。“實質上均勻的厚度”是指厚度的變化小於約5%,且“不均勻的厚度”是指厚度的變化大於或等於5%。
在一些實施例中,介電層BL可包含氧化矽、氮化矽或其組合。在一些實施例中,介電層BL在包括第二晶粒200的頂表面以及間隙G1的側壁SW1及底部BT1的整個表面上的厚度可為實質上均勻的。在一些實施例中,介電層BL的厚度對間隙G1的高度H的比可介於例如0.1到0.3的範圍內。當介電層BL的厚度對間隙G1的高度H的比處於以上範圍內時,所形成的間隙G2的長寬比可小於間隙G1的長寬比。在實施例中,介電層BL的厚度可介於例如5μm到15μm的範圍內。
在一些實施例中,間隙G2可具有與間隙G1相似的輪廓。詳細而言,間隙G2具有側壁SW2及底部BT2,且側壁SW2可實質上垂直於底部BT2。也就是說,間隙G2的頂部寬度可實質上等於間隙G2的底部寬度。在一些實施例中,間隙G2的長寬比
被定義為間隙G2的高度對寬度的比,且間隙G2的長寬比可小於0.8。然而,本發明並非僅限於此。
參照圖1D及圖1E,執行形成第一介電層F-1及第二介電層F-2的循環。首先,如圖1D所示,通過第一沉積製程在第二晶粒200之間的間隙G2之上形成第一介電層F-1,且接著形成間隙G3。由於第一沉積製程,相對於在間隙G2的側壁SW2的底部部分(即,側壁SW2的更靠近第一晶粒100的表面100a的部分)處而言,第一介電層F-1在間隙G2的側壁SW2的頂部部分(即,側壁SW2的更靠近第二晶粒200的頂表面的部分)處具有較小的厚度。換句話說,第一介電層F-1在間隙G2的側壁SW2之上具有不均勻的厚度t,且厚度t隨著第一介電層F-1靠近間隙G2的底部BT2而增大。在一些實施例中,第一沉積製程可為非共形沉積製程,例如高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)製程等。HDP-CVD製程包括沉積及蝕刻循環。詳細而言,HDP-CVD製程可通過使沉積模式(例如PECVD方法)與濺鍍模式(例如偏壓濺鍍方法)交替來執行,其中沉積模式內的沉積速率大於濺鍍模式內的濺鍍速率。舉例而言,首先,如圖4A所示,執行沉積步驟,且間隙G的開口變窄。接著,如圖4B所示,執行蝕刻步驟,且間隙G的開口擴大。之後,如圖4C所示,執行沉積步驟,且間隙G的開口變窄。接著,如圖4D所示,執行蝕刻步驟,且間隙G的開口擴大。在一些實施例中,通過重複圖4A到圖4D所示沉積及蝕刻循環,可形成圖
1D所示第一介電層F-1。
在一些實施例中,間隙G2的頂部部分上的第一介電層F-1的厚度t1對間隙G2的底部部分上的第一介電層F-1的厚度t2的比可介於0.3到0.5的範圍內。在一些實施例中,間隙G3的長寬比可介於例如0.3到0.5的範圍內。
在一些實施例中,第一介電層F-1形成在第二晶粒200以及第二晶粒200之間的間隙G2之上的介電層BL上。在一些實施例中,第一介電層F-1形成在間隙G2的側壁SW2及底部BT2上。在省略介電層BL的一些替代實施例中,第一介電層F-1可直接形成在第二晶粒200以及第二晶粒200之間的間隙G1上。換句話說,介電層F-1實體地且直接地接觸第二晶粒200的頂表面及側壁SW1以及第一晶粒100的表面100a。
在一些實施例中,參照圖1D,間隙G3可具有與間隙G2不同的輪廓。在一些實施例中但不限於此,間隙G3的頂部TP(開口)寬於間隙G3的底部。詳細而言,間隙G3可形成有傾斜的側壁SW3而非垂直的側壁,其中側壁SW3的內表面與最靠近的第二晶粒200的側壁SW1之間的距離隨著側壁SW3越來越靠近間隙G3的頂部TP而減小。換句話說,側壁SW3不垂直於間隙G3的底部BT3(例如,側壁SW3與底部BT3不垂直),且在側壁SW3與底部BT3之間可形成大於90度的夾角θ1。相反地,如圖1C及圖1D所示,側壁SW2實質上垂直於間隙G2的底部BT2(例如,側壁SW2與底部BT2垂直),且形成在側壁SW2與底部BT2之
間的夾角θ2實質上等於例如90度。在一些實施例中,間隙G3的夾角θ1大於夾角θ2。也就是說,間隙G3的側壁的斜率大於間隙G2的側壁的斜率,且第二晶粒200之間的間隙的輪廓從間隙G2(間隙G2的輪廓相似於由於介電層BL的共形沉積而形成在第二晶粒200之間的初始間隙G1的輪廓)改變成間隙G3。
傳統上,當形成在晶粒之間的間隙的側壁垂直於間隙的底表面時,要沉積的材料可對間隙的頂部進行不期望地(undesirably)密封(即,在完全填充間隙之前對間隙的頂部進行密封),且此常常發生在具有高長寬比的間隙中。相反,在一些實施例中,第一介電層F-1通過非共形沉積製程形成,且形成間隙G3,間隙G3具有傾斜的側壁SW3且具有比間隙G3的底部寬的頂部。因此,要沉積的材料(例如第二介電層F-2的材料)將無法容易地對間隙G3的頂部TP進行密封。換句話說,第一介電層F-1為後續沉積製程提供更好的間隙輪廓。
在一些實施例中,第一介電層F-1的形成不僅提供用於部分地填充間隙的材料,而且還修改第二晶粒之間的間隙的輪廓。在一些實施例中,第一介電層F-1的材料可與介電層BL的材料不同或相同。第一介電層F-1的材料可包括氧化矽、氮化矽或其組合。在一些實施例中,第一介電層F-1的厚度可小於介電層BS的厚度。在一些實施例中,第一介電層F-1的厚度可介於例如0.5μm到2μm的範圍內。在一些替代實施例中,舉例而言,第一介電層F-1的厚度可等於或大於介電層BS的厚度。
參照圖1E,通過第二沉積製程在第一介電層F-1之上形成第二介電層F-2。在一些實施例中,第二沉積製程可為共形沉積製程,例如PECVD製程等。在一些實施例中,第二介電層F-2共形地形成在第二晶粒200之上以及第二晶粒200之間的第一介電層F-1上。在一些實施例中,第二介電層F-2形成在間隙G3的側壁SW3及底部BT3上。在第二沉積製程期間,舉例而言,間隙G3的側壁SW3上的第二介電層F-2的厚度是實質上均勻的。由於間隙G3的側壁SW3傾斜而非垂直,因此在完全填充間隙G3之前,要沉積的材料將無法容易地對間隙G3的頂部TP進行密封。因此,第二介電層F-2可填充間隙G3且填充在間隙G3中的第二介電層F-2不具有空隙。
在一些實施例中,第二介電層F-2被配置成完全填充間隙G3,且因此如圖1E所示,第二介電層F-2的最低表面LSF高於第二晶粒200的頂表面或者實質上與第二晶粒200的頂表面齊平。換句話說,第二晶粒200之間的空間被完全填充。在一些替代實施例中,第二介電層F-2的最低表面LSF可高於基底穿孔TSV的頂表面或者實質上與基底穿孔TSV的頂表面齊平。在一些替代實施例中,如果在執行形成第一介電層及第二介電層的一個循環之後,第二晶粒200之間的空間未被完全填充,則可再次執行形成第一介電層及第二介電層的至少一個循環直到空間被填滿。
在一些實施例中,第一介電層F-1的形成主要是用以形成具有傾斜的側壁的間隙,且第二介電層F-2的形成主要是用以
完全填充間隙。因此,第一介電層F-1的形成也可稱為間隙輪廓修改步驟,且第二介電層F-2的形成也可稱為間隙填充步驟。在一些實施例中,第二介電層F-2的厚度可大於第一介電層F-1的厚度。舉例而言,第二介電層F-2的厚度可介於5μm到15μm的範圍內。當厚度小於5μm時,間隙G3可不被完全填充,且當厚度大於15μm時,空隙可形成在第二介電層F-2中。然而,在一些替代實施例中,第二介電層F-2的厚度可小於或等於第一介電層F-1的厚度。在一些實施例中,第二介電層F-2的材料可與第一介電層F-1的材料不同或相同。第二介電層F-2的材料可包括氧化矽、氮化矽或其組合。
參照圖1F,執行平坦化製程,以在第二晶粒200之間的間隙G1中形成介電結構DS。在一些實施例中,通過使用基底穿孔TSV作為停止層,移除介電層BL、第一介電層F-1及第二介電層F-2的部分。另外,部分地移除第二晶粒200的第二半導體基底202以暴露出基底穿孔TSV。因此,第二半導體基底202的頂表面及介電結構DS的頂表面可與基底穿孔TSV的頂表面齊平。在一些實施例中,平坦化製程是化學機械研磨製程等。
在一些實施例中,如圖1F所示,介電結構DS從外到內包括介電層BL、第一介電層F-1及第二介電層F-2。在一些實施例中,介電層BL的頂表面、第一介電層F-1的頂表面及第二介電層F-2的頂表面實質上彼此齊平,且介電結構DS的頂表面實質上與第二晶粒200的頂表面齊平。在一些實施例中,舉例而言,介
電層BL是最外部介電層,第二介電層F-2是最內部介電層,且第一介電層F-1設置在介電層BL與第二介電層F-2之間。然而,本發明並非僅限於此。在一些替代實施例中,在最外部介電層與最內部介電層之間可設置有更多介電層。
在一些實施例中,介電層BL及第一介電層F-1被配置成容置隨後沉積的材料,且因此介電層BL及第一介電層F-1分別為U形。在一些實施例中,介電層BL直接接觸第二晶粒200的側壁。介電層BL具有底部BTP及側壁SWP,且側壁SWP從底部BTP的邊緣向上延伸。在一些實施例中,舉例而言,介電層BL共形地形成在第二晶粒200的側壁以及第二晶粒200之間的第一晶粒100的表面100a的一部分之上。由於第二晶粒200的側壁實質上垂直於第一晶粒100的表面100a,因此側壁SWP實質上垂直於底部BTP。在一些實施例中,舉例而言,介電層BL用於保護第二晶粒200。
在一些實施例中,第一介電層F-1與第二介電層F-2統稱為單元U。在一些實施例中,第一介電層F-1具有底部BTP1及側壁SWP1,側壁SWP1從底部BTP1的邊緣向上延伸。側壁SWP1具有內表面ISW1以及與內表面ISW1相對的外表面OSW1。內表面ISW1面對第二介電層F-2,且外表面OSW1面對第二晶粒200。側壁SWP1的內表面ISW1與最靠近的第二晶粒200之間的距離大於側壁SWP1的外表面OSW1到最靠近的第二晶粒200之間的距離。底部BTP1具有內表面IBT1以及與內表面IBT1相對的外表
面OBT1。底部BTP1的內表面IBT1與第一晶粒100的表面100a之間的距離大於底部BTP1的外表面OBT1到第一晶粒100的表面100a之間的距離。在一些實施例中,舉例而言,內表面IBT1是上表面,且外表面OBT1是下表面。側壁SWP1的內表面ISW1實體連接到底部BTP1的內表面IBT1,且側壁SWP1的外表面OSW1實體連接到底部BTP1的外表面OBT1。
內表面ISW1、IBT1接觸第二介電層F-2,且第一介電層F-1的內表面ISW1、IBT1是隨後在上面沉積材料(例如第二介電層F-2的材料)的表面。如圖1F所示,在側壁SWP1的內表面ISW1與底部BT1的內表面IBT1之間形成有夾角θ1。在側壁SWP1的外表面OSW1與底部BT1的外表面OBT1之間形成有夾角θ2。夾角θ1大於夾角θ2。在一些實施例中,夾角θ2實質上等於90度,且夾角θ1大於90度。
在另一方面,可通過第一介電層的內表面及外表面各自的斜率來闡述第一介電層的內表面及外表面。在一些實施例中,斜率被定義為側壁相對於第一晶粒100的表面100a的傾斜程度(梯度)。詳細而言,當側壁平行於第一晶粒100的表面100a時,斜率最小,且當側壁垂直於第一晶粒100的表面100a時,斜率最大。在一些實施例中,一側(例如,間隙的左側或右側)處的側壁SWP1設置在與側壁SWP1處於同一側處的一個第二晶粒200(例如,左側或右側處的第二晶粒200)與第二介電層F-2之間。相對於第一晶粒100的表面100a而言,側壁SWP1(例如,第一
側處的側壁SWP1)的內表面ISW1的斜率小於同一側壁SWP1的外表面OSW1的斜率。換句話說,相對於第一晶粒100的表面100a而言,第一介電層F-1的側壁SWP1的內表面ISW1比外表面OSW1更平緩地傾斜。在一些實施例中,當側壁SWP1的外表面OSW1實質上垂直於第一晶粒100的表面100a時,側壁SWP1的外表面OSW1的斜率最大。在一些實施例中,第一介電層F-1的側壁SWP1的外表面OSW1也是介電層BL的側壁SWP的內表面,且因此第一介電層F-1的側壁SWP1的內表面ISW1比介電層BL的側壁SWP的內表面更平緩地傾斜。在一些實施例中,舉例而言,底部BTP1的外表面OBT1及底部BTP1的內表面IBT1可實質上平行於第一晶粒100的表面100a。
在一些實施例中,由於內表面ISW1比第一介電層F-1的側壁SWP1的外表面OSW1更平緩地傾斜,因此下側壁SWP1(例如,側壁SWP1的更靠近第一晶粒100的一部分)的厚度t2大於上側壁SWP1的厚度t1。換句話說,側壁SWP1的內表面ISW1與外表面OSW1之間的厚度隨著側壁SWP1靠近底部BTP1而增大。下側壁SWP1的內表面ISW1與第二晶粒200的側壁之間的水準距離d1大於上側壁SWP1的內表面ISW1與同一第二晶粒200的側壁之間的水準距離d2。換句話說,側壁SWP1的內表面ISW1與第二晶粒200之間的距離隨著內表面ISW1靠近底部BTP1而增大。相反地,在共形地沉積的介電層BS中,下側壁SWP的厚度可與上側壁SWP的厚度實質上相同。換句話說,介電層BS的側
壁SWP的厚度可為實質上恒定的。另外,下側壁SWP的內表面與第二晶粒200的側壁之間的水準距離與上側壁SWP的內表面與同一第二晶粒200的側壁之間的水準距離實質上相同。也就是說,上側壁SWP的內表面與同一第二晶粒200的側壁之間的水準距離可為實質上恒定的。
在一些實施例中,第二介電層F-2設置在第一介電層F-1中及第一介電層F-1上。在一些實施例中,舉例而言,第二介電層F-2被配置成完全填充由第一介電層F-1形成的間隙G3,且因此第二介電層F-2是倒梯形的。詳細而言,第二介電層F-2具有頂表面、底表面及側壁表面。在一些實施例中,第二介電層F-2的側壁表面及底表面被第一介電層F-1包封,且第二介電層F-2的頂表面實質上與第二介電層F-2的頂表面齊平。在一些實施例中,介電層BL是最外部介電層,然而,在一些替代實施例中,可省略介電層BL。換句話說,單元U的第一介電層F-1可直接接觸第二晶粒200的側壁。另外,在一些實施例中,介電結構DS僅包括一個單元U,且因此第二介電層F-2完全填充間隙G3,然而,本發明並非僅限於此。在一些替代實施例中,介電結構DS可包括更多單元。
參照圖1G,在一些實施例中,在平坦化製程之後,進一步移除第二半導體基底202的部分以使得基底穿孔TSV從第二半導體基底202突出。接著,可在第二半導體基底202之上分別形成介電層220以包封基底穿孔TSV。在一些實施例中,舉例而言,
介電層220可通過沉積製程及後續平坦化製程形成。
參照圖1H,在第二晶粒200的第二側(例如,背側)及介電結構DS之上形成重佈線層結構302。重佈線層結構302包括交替地堆疊的至少一個介電層304與至少一個導電層306。在一些實施例中,重佈線層結構302電連接到第二晶粒200的基底穿孔TSV。在一些實施例中,介電層304包含感光材料,例如,聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合等。在一些實施例中,導電層306包含銅、鎳、鈦、其組合等。在一些實施例中,在導電層306與介電層304之間可設置有障壁層。障壁層例如包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,重佈線層結構302是通過雙鑲嵌製程形成的。在一些替代實施例中,重佈線層結構302是通過多個單鑲嵌製程形成的。在又一些替代實施例中,重佈線層結構302是通過電鍍製程形成的。
之後,在重佈線層結構302之上形成焊墊308。在一些實施例中,焊墊308是用於安裝導電連接件(例如,金屬柱、微凸塊等)的凸塊下金屬(under bump metallization,UBM)焊墊。焊墊308包含金屬或金屬合金。焊墊308包含鋁、銅、鎳或其合金。
然後,鈍化層310覆蓋介電層304及覆蓋焊墊308的邊緣部分,且暴露出焊墊308的中心部分。在一些實施例中,鈍化層310包含氧化矽、氮化矽、苯並環丁烯(BCB)聚合物、聚醯亞胺(PI)、聚苯並噁唑(PBO)或其組合。
接著,可形成外部端子312以電連接焊墊308。舉例而
言,在外部接觸焊墊308上形成排列成陣列的多個外部端子312(例如,導電球/凸塊)。在一些實施例中,外部端子312可為通過植球及回流製程形成的焊球。在一些實施例中,舉例而言,外部端子312可包括導電柱312a以及導電柱312a上的凸塊312b。在一些其他實施例中,外部端子312可為或可包括銅柱、受控塌陷晶片連接(C4)凸塊、微凸塊、銅層、鎳層、無鉛(lead free,LF)層、化學鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)層、Cu/LF層、Sn/Ag層、Sn/Pb、其組合等。應注意,可對外部端子312利用任何合適的外部端子以及用於形成外部端子的任何合適的製程。
在一些實施例中,在形成外部端子312之後,由此完成本申請的三維積體電路(3DIC)結構10。在一些實施例中,舉例而言,3DIC結構10可為小外廓積體電路(small outline integrated circuit,SOIC)結構。
隨著晶粒與晶粒之間的空間(晶粒之間的間隙)變窄,間隙填充製程是關鍵製程。傳統上,在重複執行沉積製程之後,在間隙被完全填充之前,間隙的頂部可能被所沉積的材料不期望地密封。因此,間隙中的所沉積的材料中形成有空隙。這常常在通過共形沉積(例如PECVD)填充具有高長寬比的間隙中看到。儘管非共形沉積製程(例如HDP-CVD)可更完全地填充間隙,但是HDP-CVD的沉積速率慢,且HDP-CVD的成本高。在一些實施例中,通過在共形沉積製程(例如,PECVD)之前或在共形沉積
製程之間執行非共形沉積製程(例如,HDP-CVD),可修改間隙的輪廓。也就是說,間隙的側壁的傾斜程度比第二晶粒之間的初始間隙的傾斜程度平緩,以使間隙的頂部保持比間隙的底部寬。因此,要沉積的材料將無法容易地對間隙的頂部進行密封,且間隙可被所沉積的材料完全填充而在間隙中的所沉積的材料不具有空隙。因此,通過對共形沉積製程與非共形沉積製程二者的益處進行組合,可完全地且高效地填充間隙,且3DIC結構的性能提高。
圖2A是根據本公開一些實施例的3DIC結構的剖視圖,且圖2B是圖2A所示介電結構的局部放大圖。圖2A所示3DIC結構與圖1H所示3DIC結構相似,由此使用相同的參考編號來指代相同的及類似的部件,且在本文中將不再對其予以贅述。圖1H所示3DIC結構與圖2A所示3DIC結構之間的差異在於介電結構的組成。舉例而言,在圖1H所示的實施例中,介電結構DS包括一個單元U。然而,在圖2A及圖2B所示的實施例中,在3DIC結構10A中,介電結構DS包括多個單元U1、U2。詳細而言,介電結構DS設置在第二晶粒200之間,且介電結構DS從外層到內層包括介電層BL、單元U1及單元U2。
在一些實施例中,舉例而言,單元U1設置在介電層BL上且部分地被介電層BL圍繞,且單元U2設置在單元U1上且部分地被單元U1環繞。在一些實施例中,介電層BL的材料、形成方法及配置與3DIC結構10中的介電層BL的材料、形成方法及配置相似。另外,單元U2是最內部單元,且因此,單元U2的材
料、形成方法及配置與3DIC結構10中的單元U的材料、形成方法及配置相似。因此,在本文中不再對其予以贅述。單元U1將在以下詳細闡述。
在一些實施例中,介電層BS是U形的,且介電層BS具有底部及側壁SWP,側壁SWP從底部的邊緣向上延伸。在一些實施例中,單元U1具有第一介電層F1-1及第二介電層F1-2,且單元U2具有第一介電層F2-1及第二介電層F2-2。第一介電層F1-1、F2-1是U形的,且每一第一介電層F1-1、F2-1具有底部BTP1-1、BTP2-1及側壁SWP1-1、SWP2-1,側壁SWP1-1、SWP2-1從底部BTP1-1、BTP2-1的邊緣向上延伸。底部BTP1-1、BTP2-1具有內表面IBT1-1、IBT2-1及與內表面IBT1-1、IBT2-1相對的外表面OBT1-1、OBT2-1。在一些實施例中,舉例而言,外表面OBT1-1、OBT2-1是下表面,且內表面IBT1-1、IBT2-1是上表面。相似地,側壁SWP1-1、SWP2-1具有內表面ISW1-1、ISW2-1及與內表面相對的外表面OSW1-1、OSW2-1。側壁SWP1-1、SWP2-1的內表面ISW1-1、ISW2-1實體連接到底部BTP1-1、BTP2-1的內表面IBT1-1、IBT2-1,且側壁SWP1-1、SWP2-1的外表面OSW1-1、OSW2-1實體連接到底部BTP1-1、BTP2-1的外表面OBT1-1、OBT2-1。在一些實施例中,單元U1的第二介電層F1-2是U形的,且第二介電層F1-2具有底部及側壁SWP1-2,側壁SWP1-2從底部的邊緣向上延伸。在一些實施例中,舉例而言,最內部單元U2的第二介電層F2-2是倒梯形的。
第一介電層F1-1、F2-1的內表面ISW1-1、ISW2-1是隨後在上面沉積材料(例如第二介電層F1-2、F2-2的材料)的側壁表面。在一些實施例中,側壁SWP1-1、SWP2-1的內表面ISW1-1、ISW2-1比側壁SWP1-1、SWP2-1的外表面OSW1-1、OSW2-1更平緩地傾斜。在一些實施例中,在側壁SWP1-1、SWP2-1的內表面ISW1-1、ISW2-1與底部BTP1-1、BTP2-1的內表面IBT1-1、IBT2-1之間形成有夾角θ1、θ1’。在一些實施例中,在側壁SWP1-1、SWP2-1的外表面OSW1-1、OSW2-1與底部BTP1-1、BTP2-1的外表面OBT1-1、OBT2-1之間形成有夾角θ2、θ2’。夾角θ1大於夾角θ2,夾角θ1’大於夾角θ2’。在一些實施例中,夾角θ1、θ1’大於90度。在一些實施例中,夾角θ2可實質上等於90度,即,介電層BS的側壁可為垂直的。在一些實施例中,夾角θ2可實質上等於夾角θ1,換句話說,第二介電層F1-2的側壁的外表面及內表面可實質上彼此平行。
在一些實施例中,相對於第一晶粒100的表面100a而言,第一介電層F1-1的側壁SWP1-1的內表面ISW1-1的斜率小於介電層BS的側壁SWP的內表面ISW的斜率。相似地,相對於第一晶粒100的表面100a而言,第一介電層F2-1的側壁SWP2-1的內表面ISW2-1的斜率小於單元U1中的第二介電層F1-2的側壁的內表面ISW1-2的斜率。換句話說,與介電層BS及第二介電層F1-2的側壁表面(即,側壁SWP、SWP1-2的內表面ISW、ISW1-2)相比,第一介電層F1-1、F2-1提供傾斜的側壁表面(即,側壁
SWP1-1、SWP2-1的內表面ISW1-1、ISW2-1),所述傾斜的側壁表面適用於第二介電層F1-2、F2-2的沉積製程。因此,通過在介電層BS與第二介電層F1-2之間以及在第二介電層F1-2、F2-2之間***第一介電層F1-1、F2-1,可使第二介電層F1-2、F2-2的材料容易地且精確地沉積到第二晶粒200之間的間隙中。
在一些實施例中,第二晶粒200之間的間隙G1的長寬比可為高的,且在依序沉積介電層BS、F1-1、F1-2、F2-1之後,所形成的間隙G2、G3、G4的長寬比實質上減小。舉例而言,間隙G1的長寬比可大於1.5,間隙G2的長寬比可小於1,間隙G3的長寬比可小於0.8,且間隙G4的長寬比可介於0.3到0.5的範圍內。在一些實施例中,間隙G1的頂部部分上的介電層BS的厚度可與間隙G1的底部部分上的介電層BS的厚度實質上相同,且所述厚度對間隙G1的頂部寬度的比可為0.1到0.2。在一些實施例中,間隙G2的頂部部分上的介電層F1-1的厚度小於間隙G2的底部部分上的介電層F1-1的厚度,且間隙G2的頂部部分上的介電層F1-1的厚度對間隙G2的頂部寬度的比可為0.2到0.3。在一些實施例中,間隙G3的頂部部分上的介電層F1-2的厚度可與間隙G3的底部部分上的介電層F1-2的厚度實質上相同,且間隙G3的頂部部分上的介電層F1-2的厚度對間隙G3的頂部寬度的比可為0.1到0.25。在一些實施例中,間隙G4的頂部部分上的介電層F2-1的厚度可與間隙G4的底部部分上的介電層F2-1的厚度實質上相同,且間隙G4的頂部部分上的介電層F2-1的厚度對間隙G4的頂
部寬度的比可為0.1到0.25。在一些實施例中,間隙G5的頂部部分中的介電層F2-2的寬度對間隙G5的頂部寬度的比可小於0.3。
在一些實施例中,第一介電層F1-1、F2-1可通過非共形沉積製程(例如HDP-CVD等)形成。介電層BS及第二介電層F1-2、F2-2可通過共形沉積製程(例如PECVD製程或其他合適的方法)形成。在一些實施例中,每一單元U1、U2通過非共形沉積製程以及在非共形沉積製程之後立即執行的共形沉積製程形成。在一些實施例中,單元U1、U2可通過交替地執行HDP-CVD製程與PECVD製程形成。在一些實施例中,介電層BS在單元U1、U2之前形成,且因此可在重複HDP-CVD製程及CVD製程的循環之前執行附加共形沉積製程(例如PECVD製程)。在一些實施例中,可形成夾層結構(sandwich structure)(即,介電層BS/第一介電層F1-1/第二介電層F1-2或第二介電層F1-2/第一介電層F2-1/第二介電層F2-2)作為CVD膜/HDP-CVD膜/CVD膜。在一些實施例中,介電層BS、第一介電層F1-1、F2-1及第二介電層F1-2、F2-2的材料可包括氧化矽、氮化矽或其組合。在一些實施例中,介電層BS、第一介電層F1-1、F2-1及第二介電層F1-2、F2-2的材料可相同或不同。
在一些實施例中,在介電層BL與最內部單元U2之間僅設置有一個單元U1,然而,本發明並非僅限於此。在一些替代實施例中,在介電層BL與最內部單元U2之間可設置有多個單元,且每一單元可具有與單元U1相似的配置。另外,在一些替代實施
例中,可省略介電層BL。詳細而言,如圖3所示,在3DIC結構10B中,介電結構DS由多個U1、U2構成,且最外部單元U1直接接觸第二晶粒200。換句話說,第一介電層F1-1直接接觸第二晶粒200的側壁。第一介電層F1-1的側壁SWP1-1的外表面OSW1-1也是第二晶粒200的側壁,且底部BTP1-1的外表面OBT1-1也是第一晶粒100的表面100a。因此,第一介電層F1-1的輪廓與第二晶粒200之間的間隙實質上相同。在一些實施例中,舉例而言,第一介電層F1-1的側壁SWP1-1的外表面OSW1-1實質上垂直於底部BTP1-1的外表面OBT1-1,且在外表面OSW1-1與外表面OBT1-1之間形成的夾角θ2實質上等於90°度。夾角θ1大於夾角θ2。相對於第一晶粒100的表面100a而言,側壁SWP1-1的內表面ISW1-1的斜率小於第一介電層F1-1的側壁SWP1-1的外表面OSW1-1的斜率。換句話說,與第二晶粒200的側壁表面相比,第一介電層F1-1提供適用於後續沉積製程的側壁表面(即,側壁SWP1-1的內表面ISW1-1)。
在一些實施例中,單元的第一介電層被配置成為依序沉積製程提供更好的間隙輪廓,且單元的第二介電層被配置成提供期望的厚度以填充晶粒之間的間隙。在一些實施例中,通過重複包括非共形沉積製程(例如,HDP-CVD)與共形沉積製程(例如,PECVD)的循環,可完全地且高效地填充第二晶粒之間的間隙,且可形成間隙而不具有空隙。因此,3DIC結構的性能提高。
儘管層的側壁被示出為直的側壁,但是本發明並非僅限
於此。在一些實施例中,在層的側壁與底部之間形成的隅角可為圓形的,然而,側壁與底部之間的角度可由層的側壁的切線與層的底部的切線形成。另外,應注意,儘管3DIC結構10、10A中的介電結構DS被示出為具有相似的配置,然而,本發明並非僅限於此。換句話說,3DIC結構可具有至少兩種介電結構DS,例如圖1H所示介電結構DS及圖2A所示介電結構DS。
傳統上,為將介電材料填充到晶粒之間的間隙中,可重複執行沉積製程(例如CVD製程)。然而,在重複執行沉積製程之後,間隙的頂部變窄,且因此在間隙被完全填充之前,間隙的頂部可能被所沉積的材料不期望地密封。因此,間隙中的所沉積的材料中形成有空隙,這會影響包括晶粒的3DIC結構的性能。在一些實施例中,通過在共形沉積製程(例如,PECVD)之前或在共形沉積製程之間執行非共形沉積製程(例如,HDP-CVD),間隙的側壁平緩地傾斜(即,間隙的頂部比底部寬)。因此,在間隙被實質上填充之前,所沉積的材料將無法容易地對間隙的頂部進行密封。因此,可將間隙填充材料填充到間隙中而在間隙中的填充材料不具有空隙,且包括晶粒的3DIC結構的性能提高。
根據一些實施例,一種三維積體電路結構包括第一晶粒、多個第二晶粒以及介電結構。所述第二晶粒結合到所述第一晶粒。所述介電結構設置在所述第二晶粒之間。所述介電結構包括第一介電層及第二介電層。所述第一介電層具有側壁及底部,所述側壁的第一表面與所述底部的第一表面接觸所述第二介電層
且形成第一角度。所述側壁的第二表面與所述底部的第二表面形成比所述第一角度小的第二角度。
根據一些實施例,所述側壁的所述第一表面與所述第二晶粒中的一者之間的距離隨著所述第一表面靠近所述底部而增大。
根據一些實施例,所述側壁的所述第一表面與所述第二表面之間的厚度隨著所述側壁的所述第一表面及所述第二表面靠近所述底部而增大。
根據一些實施例,所述第一介電層設置在所述第二介電層與所述多個第二晶粒之間。
根據一些實施例,所述第二角度實質上等於90度。
根據一些實施例,所述第一介電層的頂表面及所述第二介電層的頂表面實質上與所述多個第二晶粒的頂表面齊平。
根據一些實施例,所述第一介電層是U形的。
根據一些實施例,所述介電結構還包括位於所述第一介電層與所述多個第二晶粒之間的第三介電層,且所述第三介電層接觸所述側壁的所述第二表面及所述底部的所述第二表面。
根據一些實施例,所述介電結構包括交替地設置的多個第一介電層與多個第二介電層。
根據一些實施例,一種三維積體電路結構包括第一晶粒、第二晶粒、第三晶粒、第一介電層及第二介電層。所述第二晶粒及所述第三晶粒結合到所述第一晶粒的表面。所述第一介電
層及所述第二介電層設置在所述第二晶粒與所述第三晶粒之間。所述第一介電層包括位於所述第二介電層與所述第二晶粒之間的側壁。所述側壁包括面對所述第二介電層的第一表面及面對所述第二晶粒的第二表面。相對於所述第一晶粒的所述表面而言,所述側壁的所述第一表面的第一斜率小於所述側壁的所述第二表面的第二斜率。
根據一些實施例,所述側壁的所述第一表面與所述第二晶粒之間的距離隨著所述第一表面靠近所述第一晶粒的所述表面而增大。
根據一些實施例,還包括位於所述第一介電層與所述第二晶粒之間的第三介電層,其中所述第二表面接觸所述第三介電層。
根據一些實施例,所述第二表面實質上平行於所述第二晶粒的與所述第一晶粒的所述表面垂直的側壁。
根據一些實施例,所述第一表面與所述第二表面之間的距離隨著所述第一表面靠近所述第一晶粒的所述表面而增大。
根據一些實施例,還包括位於所述第一介電層與所述第二介電層之間的第三介電層,其中所述第三介電層共形地形成在所述第一介電層之上。
根據一些實施例,一種製造三維積體電路結構的方法包括以下步驟。提供第一晶粒。將多個第二晶粒結合到所述第一晶粒上,其中在所述多個第二晶粒之間形成間隙。通過執行包括以
下製程的至少一個循環而在所述間隙中填充介電材料:通過第一沉積製程,形成第一介電層,所述第一介電層在所述間隙的側壁的頂部部分處相對於在所述間隙的所述側壁的底部部分處而言具有較小的厚度;以及通過第二沉積製程,在所述間隙之上的所述第一介電層上形成第二介電層。移除所述介電材料的一部分以在所述多個第二晶粒之間形成介電結構,其中所述介電結構的頂表面實質上與所述多個第二晶粒的頂表面共面。
根據一些實施例,所述第一沉積製程是高密度電漿化學氣相沉積製程。
根據一些實施例,還包括在執行所述至少一個循環之前,在所述間隙之上共形地形成第三介電層。
根據一些實施例,移除所述介電材料的所述一部分是通過平坦化製程執行的。
根據一些實施例,執行所述至少一個循環包括執行多個循環。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、替代及
變更。
10:三維積體電路(3DIC)結構
100:第一晶粒
100a:表面
102:第一半導體基底
104:第一半導體裝置
106:第一內連結構
108:第一絕緣層
110:第一金屬特徵
110a:第一頂部金屬特徵
112:第一鈍化層
114:第一焊墊
200:第二晶粒
302:重佈線層結構
304、BS、F-1、F-2:介電層
306:導電層
308:焊墊
310:鈍化層
312:外部端子
312a:導電柱
312b:凸塊
BDL1:第一結合介電層
BP1:第一結合焊墊
BTP、BTP1:底部
BV1:第一結合通孔
DS:介電結構
SWP、SWP1:側壁
θ1、θ2:夾角
Claims (10)
- 一種三維積體電路結構,包括:第一晶粒;多個第二晶粒,結合到所述第一晶粒;以及介電結構,設置在所述多個第二晶粒之間且包括第一介電層及第二介電層,其中所述第一介電層具有側壁及底部,所述側壁的第一表面與所述底部的第一表面接觸所述第二介電層且形成第一角度,並且所述側壁的第二表面與所述底部的第二表面形成比所述第一角度小的第二角度。
- 如申請專利範圍第1項所述的三維積體電路結構,其中所述側壁的所述第一表面與所述第二晶粒中的一者之間的距離隨著所述第一表面靠近所述底部而增大。
- 如申請專利範圍第1項所述的三維積體電路結構,其中所述側壁的所述第一表面與所述第二表面之間的厚度隨著所述側壁的所述第一表面及所述第二表面靠近所述底部而增大。
- 如申請專利範圍第1項所述的三維積體電路結構,其中所述第一介電層的頂表面及所述第二介電層的頂表面實質上與所述多個第二晶粒的頂表面齊平。
- 如申請專利範圍第1項所述的三維積體電路結構,其中所述介電結構還包括位於所述第一介電層與所述多個第二晶粒之間的第三介電層,且所述第三介電層接觸所述側壁的所述第二表面及所述底部的所述第二表面。
- 如申請專利範圍第1項所述的三維積體電路結構,其中所述介電結構包括交替地設置的多個第一介電層與多個第二介電層。
- 一種三維積體電路結構,包括:第一晶粒;第二晶粒及第三晶粒,結合到所述第一晶粒的表面;以及第一介電層及第二介電層,設置在所述第二晶粒與所述第三晶粒之間,所述第一介電層包括位於所述第二介電層與所述第二晶粒之間的側壁,所述側壁包括面對所述第二介電層的第一表面及面對所述第二晶粒的第二表面,其中相對於所述第一晶粒的所述表面,所述側壁的所述第一表面的第一斜率小於所述側壁的所述第二表面的第二斜率。
- 如申請專利範圍第7項所述的三維積體電路結構,其中所述側壁的所述第一表面與所述第二晶粒之間的距離隨著所述第一表面靠近所述第一晶粒的所述表面而增大。
- 一種製造三維積體電路結構的方法,包括:提供第一晶粒;將多個第二晶粒結合到所述第一晶粒上,其中在所述多個第二晶粒之間形成間隙;通過執行包括以下製程的至少一個循環而在所述間隙中填充介電材料: 通過第一沉積製程,形成第一介電層,所述第一介電層在所述間隙的側壁的頂部部分處相對於在所述間隙的所述側壁的底部部分處具有較小的厚度;以及通過第二沉積製程,在所述間隙之上的所述第一介電層上形成第二介電層;以及移除所述介電材料的一部分,以在所述多個第二晶粒之間形成介電結構,其中所述介電結構的頂表面實質上與所述多個第二晶粒的頂表面共面。
- 如申請專利範圍第9項所述的方法,其中所述第一沉積製程是高密度電漿化學氣相沉積製程。
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