TW202332927A - Timing calibration method and system - Google Patents

Timing calibration method and system Download PDF

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TW202332927A
TW202332927A TW111141229A TW111141229A TW202332927A TW 202332927 A TW202332927 A TW 202332927A TW 111141229 A TW111141229 A TW 111141229A TW 111141229 A TW111141229 A TW 111141229A TW 202332927 A TW202332927 A TW 202332927A
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output
channel
test
clock
timing calibration
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TWI826083B (en
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董亞明
韓潔
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大陸商蘇州華興源創科技股份有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits

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  • Physics & Mathematics (AREA)
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Abstract

Disclosed in the present invention are a timing calibration method and system. The timing calibration method is used for performing timing calibration on test signals in a plurality of test channels of a digital test machine. The method comprises: gating any two test channels of a digital test machine, so as to output test signals; comparing, by using a window comparator, the test signals output by the two gated test channels, and outputting a comparison result to an FPGA; transmitting, to the FPGA and via a clock buffer, the test signal output by one of the two gated test channels, and taking the test signal as a sampling clock; the FPGA collecting the output result of the window comparator according to the sampling clock, and sending result information to a control terminal; and the control terminal adjusting a clock phase of the test signal in the corresponding test channel according to an output structure of the FPGA, so as to complete timing calibration of the test channel.

Description

時序校準方法和系統Timing calibration method and system

本發明涉及晶片測試領域，更具體地，涉及一種時序校準方法和系統。The present invention relates to the field of wafer testing, and more specifically, to a timing calibration method and system.

數位晶片測試機通常支援pattern（測試向量）測試，用於數位晶片通過測試pattern來判斷晶片功能是否正常，從而實現數位晶片大規模量產時的快速測試。Digital chip testing machines usually support pattern (test vector) testing, which is used for digital chips to determine whether the chip function is normal by testing the pattern, thereby enabling rapid testing of digital chips during mass production.

數位晶片測試機一般支援幾百個測試通道，每個測試通道輸出的數位信號都需要同時輸出到待測數位晶片的引腳處，即數位信號需要邊沿對齊，以保證輸出到待測數位晶片引腳處的信號間時序是正確的。要保證所有數位晶片測試機所有測試通道輸出的數位信號邊沿對齊，需要通過對數位信號時序校準來實現。Digital chip testers generally support hundreds of test channels. The digital signals output by each test channel need to be output to the pins of the digital chip under test at the same time. That is, the digital signals need to be edge aligned to ensure that they are output to the pins of the digital chip under test. The timing between signals at the feet is correct. To ensure edge alignment of the digital signals output by all test channels of all digital chip testing machines, it is necessary to calibrate the timing of the digital signals.

現有方法一般通過高速示波器來逐個判斷測試通道測試邊沿是否對齊，該方法需要額外的高速示波器，成本高使用不便；或者通過兩個通道輸出時鐘後的信號相與，再將相與的信號通過電容充電後採集電壓的方式測算邊沿是否對齊，該方法需要通過電容充電和ADC採樣導致測試時間較長。Existing methods generally use a high-speed oscilloscope to determine whether the test edges of the test channels are aligned one by one. This method requires an additional high-speed oscilloscope, which is costly and inconvenient to use; or the signals after the clock output are output through the two channels, and then the signal is passed through the capacitor. The method of collecting voltage after charging is used to measure whether the edges are aligned. This method requires capacitor charging and ADC sampling, which results in a long test time.

本發明的一個目的在於提供一種時序校準方法和系統，以解決現有技術存在的問題中的至少一個。An object of the present invention is to provide a timing calibration method and system to solve at least one of the problems existing in the prior art.

為達到上述目的，本發明採用下述技術方案：In order to achieve the above objects, the present invention adopts the following technical solutions:

本發明第一方面提供一種時序校準方法，用於對數位測試機的若干測試通道中的測試信號進行時序校準，該方法包括： 選通數位測試機的任意兩個測試通道，以輸出測試信號； 採用窗口比較器對選通的兩個測試通道輸出的測試信號進行比較，並將比較結果輸出到FPGA； 被選通的兩個測試通道其中之一輸出的測試信號經時鐘緩衝器傳輸到FPGA作為採樣時鐘； FPGA根據採樣時鐘採集窗口比較器的輸出結果，並將結果資訊發送給控制終端； 控制終端根據FPGA的輸出結構調整對應的測試通道中測試信號的時鐘相位，以完成對測試通道的時序校準。 A first aspect of the present invention provides a timing calibration method for timing calibration of test signals in several test channels of a digital testing machine. The method includes: Select any two test channels of the digital testing machine to output test signals; Use a window comparator to compare the test signals output by the two gated test channels, and output the comparison results to the FPGA; The test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer as the sampling clock; The FPGA collects the output results of the window comparator according to the sampling clock and sends the result information to the control terminal; The control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA to complete the timing calibration of the test channel.

可選地，該方法進一步包括：以所述採樣時鐘所在的測試通道作為校準基準通道，依次選通其他多個測試通道之一與所述窗口比較器連通作為被校準通道進行時序校準。Optionally, the method further includes: using the test channel where the sampling clock is located as a calibration reference channel, and sequentially selecting one of the other multiple test channels to be connected to the window comparator as the calibrated channel for timing calibration.

可選地，所述數位測試機的多個激勵信號測試通道連接繼電器網路的輸入端，所述繼電器網路的第一輸出端連接所述窗口比較器的第一輸入端，所述繼電器網路的第二輸出端連接所述窗口比較器的第二輸入端和所述時鐘緩衝器的輸入端，所述窗口比較器的輸出端連接所述FPGA的第一輸入端，所述時鐘緩衝器的輸出端連接所述FPGA的第二輸入端，所述FPGA的輸出端連接所述控制終端。Optionally, the plurality of excitation signal test channels of the digital testing machine are connected to the input end of the relay network, and the first output end of the relay network is connected to the first input end of the window comparator. The relay network The second output end of the path is connected to the second input end of the window comparator and the input end of the clock buffer, the output end of the window comparator is connected to the first input end of the FPGA, and the clock buffer The output terminal is connected to the second input terminal of the FPGA, and the output terminal of the FPGA is connected to the control terminal.

可選地，所述控制終端控制所述繼電器網路中的繼電器斷開或閉合，使被選通的兩個激勵信號測試通道分別輸出到所述繼電器網路的第一輸出端和第二輸出端。Optionally, the control terminal controls the relays in the relay network to open or close, so that the two gated excitation signal test channels are output to the first output end and the second output of the relay network respectively. end.

可選地，如果被校準通道產生的時鐘信號邊沿與基準通道產生的時鐘信號邊沿不對齊，所述控制系統控制所述數位測試機激勵信號測試通道調整被校準通道輸出的時鐘相位，直到被校準通道的時鐘相位與基準通道產生的時鐘信號邊沿對齊。Optionally, if the edge of the clock signal generated by the calibrated channel is not aligned with the edge of the clock signal generated by the reference channel, the control system controls the digital testing machine excitation signal test channel to adjust the clock phase output by the calibrated channel until it is calibrated. The clock phase of the channel is edge aligned with the clock signal generated by the reference channel.

可選地，利用二分查找法調整被校準通道輸出的時鐘相位。Optionally, use a binary search method to adjust the clock phase of the calibrated channel output.

可選地，若測得被校準通道比基準通道相位超前，則令被校準通道輸出延遲N nS，此時若測得被校準通道比基準通道相位滯後，則調整被校準通道輸出延遲為N/2 nS，此時若測得被校準通道比基準通道相位滯後，則被校準通道比基準通道相位超前在0~N/2 nS範圍，若測得被校準通道比基準通道相位超前，則被校準通道比基準通道相位超前在N/2~N nS範圍，其中N＞0。Optionally, if the measured phase of the calibrated channel is ahead of the reference channel, then the output of the calibrated channel is delayed by N nS. At this time, if the measured phase of the calibrated channel is lagging behind the reference channel, then the output delay of the calibrated channel is adjusted to N/ 2 nS. At this time, if the phase of the calibrated channel is measured to be lagging behind the reference channel, the calibrated channel is ahead of the reference channel in the range of 0~N/2 nS. If the phase of the calibrated channel is measured to be ahead of the reference channel, it is calibrated. The phase of the channel is ahead of the reference channel in the range of N/2~N nS, where N>0.

本發明第二方面提供一種執行上述時序校準方法的時序校準系統，該系統包括：數位測試機、控制終端和時序校準板卡； 所述時序校準板卡包括：繼電器網路、窗口比較器、時鐘緩衝器和FPGA； 其中，數位測試機包含多個激勵信號測試通道； 繼電器網路用於將數位測試機的多個激勵信號測試通道選通任意兩個激勵信號測試通道分別輸出到窗口比較器； 窗口比較器用於對選通後的兩個激勵信號測試通道輸出的時鐘信號進行比較，判斷兩個時鐘信號邊沿是否對齊，並將判斷結果輸出到FPGA； 時鐘緩衝器用於將所選通的激勵信號測試通道之一輸出的時鐘信號緩衝後輸出到FPGA作為採樣時鐘； FPGA用於根據採樣時鐘採集窗口比較器的比較結果，並將結果發送給控制終端； 控制終端用於控制激勵信號測試通道產生時鐘信號，判斷兩個激勵信號測試通道產生的時鐘信號是否邊沿對齊，並進行時序校準。 A second aspect of the present invention provides a timing calibration system that performs the above timing calibration method. The system includes: a digital testing machine, a control terminal and a timing calibration board; The timing calibration board includes: relay network, window comparator, clock buffer and FPGA; Among them, the digital test machine contains multiple excitation signal test channels; The relay network is used to select any two excitation signal test channels from the multiple excitation signal test channels of the digital testing machine and output them to the window comparator respectively; The window comparator is used to compare the clock signals output by the two excitation signal test channels after gating, judge whether the edges of the two clock signals are aligned, and output the judgment result to the FPGA; The clock buffer is used to buffer the clock signal output by one of the selected excitation signal test channels and output it to the FPGA as a sampling clock; FPGA is used to collect the comparison results of the window comparator according to the sampling clock and send the results to the control terminal; The control terminal is used to control the excitation signal test channel to generate clock signals, determine whether the clock signals generated by the two excitation signal test channels are edge aligned, and perform timing calibration.

可選地，所述繼電器網路和所述窗口比較器支援100~800MHz工作頻率。Optionally, the relay network and the window comparator support an operating frequency of 100~800MHz.

可選地，所述控制終端控制所述繼電器網路選通測試通道之一與所述時鐘緩衝器輸入端和所述高速窗口比較器第二輸入端連通用作校準基準通道，依次選通其他多個激勵信號測試通道之一與所述窗口比較器第一輸入端連通作為被校準通道進行時序校準。Optionally, the control terminal controls one of the relay network gating test channels to be connected to the input end of the clock buffer and the second input end of the high-speed window comparator to be used as a calibration reference channel, and the other channels are gating in turn. One of the plurality of excitation signal test channels is connected to the first input end of the window comparator as a calibrated channel for timing calibration.

本發明的有益效果如下：The beneficial effects of the present invention are as follows:

本發明所述技術方案，提供了一種時序校準方法和系統，該系統無需外接示波器等儀器即可實現時序校準，使用方便。本發明所述時序校準方法通過利用高速繼電器網路和時序校準板中的高速窗口比較器，可以快速實現數位測試機測試通道的時序校準，提高了時序校準效率，並且所有測試通道的校準精度能夠達到50ps以內，滿足校準精度要求。The technical solution of the present invention provides a timing calibration method and system, which can realize timing calibration without external instruments such as oscilloscopes and is easy to use. The timing calibration method of the present invention can quickly realize the timing calibration of the test channels of the digital testing machine by utilizing a high-speed relay network and a high-speed window comparator in the timing calibration board, thereby improving the timing calibration efficiency, and the calibration accuracy of all test channels can be Reaching within 50ps, meeting the calibration accuracy requirements.

下面結合圖式對本發明的具體實施方式作進一步詳細的說明。The specific embodiments of the present invention will be described in further detail below in conjunction with the drawings.

為了更清楚地說明本發明，下面結合優選實施例和圖式對本發明做進一步的說明。圖式中相似的部件以相同的圖式符號進行表示。本領域技術人員應當理解，下面所具體描述的內容是說明性的而非限制性的，不應以此限制本發明的保護範圍。In order to illustrate the present invention more clearly, the present invention will be further described below in conjunction with preferred embodiments and drawings. Similar parts in the drawings are represented by the same drawing symbols. Those skilled in the art should understand that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of the present invention.

如圖1所示，本發明一個實施例提供了一種時序校準系統，包括數位測試機1、控制終端2和時序校準板卡3。As shown in Figure 1, one embodiment of the present invention provides a timing calibration system, including a digital testing machine 1, a control terminal 2 and a timing calibration board 3.

其中，數字測試機1包含若干測試通道，每個測試通道中對應傳輸一個測試向量（Pattern），所述測試向量作為測試信號被數位測試機發送至待測產品引腳。常見的數位測試機1包含有512、768、1024個測試通道。即512個測試通道中對應傳輸512個測試向量。Among them, the digital test machine 1 includes several test channels, and each test channel correspondingly transmits a test vector (Pattern). The test vector is sent as a test signal by the digital test machine to the pin of the product under test. Common digital test machines 1 include 512, 768, and 1024 test channels. That is, 512 test vectors are transmitted correspondingly in 512 test channels.

控制終端2可以為電腦或雲端伺服器，主要用於控制時序校準流程的進行。The control terminal 2 can be a computer or a cloud server, and is mainly used to control the timing calibration process.

時序校準板卡3包括：高速繼電器網路31、高速窗口比較器32、時鐘緩衝器 33和FPGA 34。The timing calibration board 3 includes: a high-speed relay network 31, a high-speed window comparator 32, a clock buffer 33 and an FPGA 34.

其中，高速繼電器網路31用於選通數位測試機的任意兩個測試通道，使得被選通的兩個測試通道中的兩個測試向量分別輸出到高速窗口比較器32中。在一個具體示例中，所述高速繼電器網路31和所述高速窗口比較器32最大支援800MHz工作頻率。Among them, the high-speed relay network 31 is used to gate any two test channels of the digital testing machine, so that the two test vectors in the two gated test channels are output to the high-speed window comparator 32 respectively. In a specific example, the high-speed relay network 31 and the high-speed window comparator 32 support a maximum operating frequency of 800MHz.

高速窗口比較器32用於對選通後的兩個測試通道輸出的測試向量信號進行比較，判斷兩個測試向量信號的邊沿是否對齊，並將判斷結果輸出到FPGA 34；The high-speed window comparator 32 is used to compare the test vector signals output by the two test channels after gating, judge whether the edges of the two test vector signals are aligned, and output the judgment result to the FPGA 34;

時鐘緩衝器 33用於將其中一個測試通道產生的測試向量信號緩衝後輸出到FPGA 34作為採樣時鐘；The clock buffer 33 is used to buffer the test vector signal generated by one of the test channels and output it to the FPGA 34 as a sampling clock;

FPGA 34用於根據採樣時鐘採集高速窗口比較器32的比較結果，並將結果發送給控制終端2。The FPGA 34 is used to collect the comparison results of the high-speed window comparator 32 according to the sampling clock, and send the results to the control terminal 2 .

控制終端2用於控制激勵信號測試通道產生時鐘信號，判斷兩個激勵信號測試通道產生的時鐘信號是否邊沿對齊，並進行時序校準。The control terminal 2 is used to control the excitation signal test channel to generate a clock signal, determine whether the clock signals generated by the two excitation signal test channels are edge aligned, and perform timing calibration.

在一種可能的實現方式中，所述繼電器網路和所述窗口比較器支援100~800MHz工作頻率。In a possible implementation, the relay network and the window comparator support an operating frequency of 100~800MHz.

在一種可能的實現方式中，所述控制終端控制所述繼電器網路選通測試通道之一與所述時鐘緩衝器輸入端和所述窗口比較器第二輸入端連通用作校準基準通道，依次選通其他多個激勵信號測試通道之一與所述高速窗口比較器第一輸入端連通作為被校準通道進行時序校準。In a possible implementation, the control terminal controls one of the relay network gating test channels to be connected to the clock buffer input end and the second input end of the window comparator to be used as a calibration reference channel, in sequence Select one of the other multiple excitation signal test channels to be connected to the first input end of the high-speed window comparator as the calibrated channel for timing calibration.

如圖2所示，本發明另一個實施例提供一種時序校準方法，用於對數位測試機的若干測試通道中的測試信號進行時序校準，該方法包括：As shown in Figure 2, another embodiment of the present invention provides a timing calibration method for timing calibration of test signals in several test channels of a digital testing machine. The method includes:

選通數位測試機的任意兩個測試通道，以輸出測試信號；Select any two test channels of the digital testing machine to output test signals;

採用窗口比較器對選通的兩個測試通道輸出的測試信號進行比較，並將比較結果輸出到FPGA；Use a window comparator to compare the test signals output by the two gated test channels, and output the comparison results to the FPGA;

被選通的兩個測試通道其中之一輸出的測試信號經時鐘緩衝器傳輸到FPGA作為採樣時鐘；The test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer as the sampling clock;

FPGA根據採樣時鐘採集窗口比較器的輸出結果，並將結果資訊發送給控制終端；The FPGA collects the output results of the window comparator according to the sampling clock and sends the result information to the control terminal;

控制終端根據FPGA的輸出結構調整對應的測試通道中測試信號的時鐘相位，以完成對測試通道的時序校準。在一種可能的實現方式中，所述數位測試機1的多個激勵信號測試通道連接所述高速繼電器網路31的輸入端，高速繼電器網路31的第一輸出端連接所述高速窗口比較器32的第一輸入端，高速繼電器網路31的第二輸出端連接所述高速窗口比較器32的第二輸入端和所述時鐘緩衝器33的輸入端，所述高速窗口比較器32的輸出端連接所述FPGA 34的第一輸入端，所述時鐘緩衝器 33的輸出端連接所述FPGA 34的第二輸入端，所述FPGA 34的輸出端連接所述控制終端 2。The control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA to complete the timing calibration of the test channel. In a possible implementation, the multiple excitation signal test channels of the digital testing machine 1 are connected to the input end of the high-speed relay network 31, and the first output end of the high-speed relay network 31 is connected to the high-speed window comparator. The first input terminal of 32 and the second output terminal of the high-speed relay network 31 are connected to the second input terminal of the high-speed window comparator 32 and the input terminal of the clock buffer 33. The output of the high-speed window comparator 32 The first input terminal of the clock buffer 33 is connected to the first input terminal of the FPGA 34 , the output terminal of the clock buffer 33 is connected to the second input terminal of the FPGA 34 , and the output terminal of the FPGA 34 is connected to the control terminal 2 .

在一種可能的實現方式中，所述控制終端2控制所述高速繼電器網路31中的繼電器斷開或閉合，使被選通的兩個激勵信號測試通道分別輸出到所述高速繼電器網路31的第一輸出端和第二輸出端。In a possible implementation, the control terminal 2 controls the relays in the high-speed relay network 31 to open or close, so that the two gated excitation signal test channels are output to the high-speed relay network 31 respectively. the first output terminal and the second output terminal.

在一個具體示例中，數字測試機1包含的至少512個測試通道均連接到高速繼電器網路31的輸入端，512個測試通道對應傳輸512個測試向量（Pattern），高速繼電器網路31將數位測試機1包含的至少512個測試通道任意選擇兩個測試通道輸出，高速繼電器網路31的兩個輸出端均連接到高速窗口比較器32的輸入端，同時其中一個高速繼電器網路31的輸出端連接到時鐘緩衝器 33的輸入端，高速窗口比較器32的輸出端連接FPGA 34，時鐘緩衝器 33的輸出端連接FPGA 34，FPGA 34利用時鐘緩衝器 33輸出的採樣時鐘，來採樣高速窗口比較器32的比較結果，然後將採樣結果傳給控制終端2，例如控制終端2為電腦，由電腦判斷本次測試的兩個測試通道是否邊沿對齊，並進行時序校準。In a specific example, at least 512 test channels included in the digital testing machine 1 are connected to the input end of the high-speed relay network 31. The 512 test channels correspond to the transmission of 512 test vectors (Pattern). The high-speed relay network 31 transmits digital The test machine 1 includes at least 512 test channels and randomly selects two test channel outputs. Both output terminals of the high-speed relay network 31 are connected to the input terminals of the high-speed window comparator 32, and at the same time, the output of one of the high-speed relay network 31 The terminal is connected to the input terminal of the clock buffer 33, the output terminal of the high-speed window comparator 32 is connected to the FPGA 34, the output terminal of the clock buffer 33 is connected to the FPGA 34, and the FPGA 34 uses the sampling clock output by the clock buffer 33 to sample the high-speed window The comparison result of the comparator 32 is then transmitted to the control terminal 2. For example, the control terminal 2 is a computer. The computer determines whether the two test channels of this test are edge aligned and performs timing calibration.

在一種可能的實現方式中，所述控制終端2控制所述高速繼電器網路31選通測試通道之一與所述時鐘緩衝器 33輸入端和所述高速窗口比較器32第二輸入端連通用作校準基準通道，該基準通道稱為通道2，依次選通其他多個激勵信號測試通道之一與所述高速窗口比較器第一輸入端連通作為被校準通道進行時序校準，該被校準通道稱為通道1。In a possible implementation, the control terminal 2 controls one of the gating test channels of the high-speed relay network 31 to be connected to the input end of the clock buffer 33 and the second input end of the high-speed window comparator 32 As a calibration reference channel, this reference channel is called channel 2. One of the other multiple excitation signal test channels is sequentially selected and connected to the first input end of the high-speed window comparator as the calibrated channel for timing calibration. The calibrated channel is called is channel 1.

在一個具體示例中，所述控制終端2將未經高速窗口比較器32選通的其他激勵信號測試通道依次進行選通，並根據所述基準通道2對被校準通道1進行時序校準。In a specific example, the control terminal 2 sequentially gates other excitation signal test channels that have not been gated by the high-speed window comparator 32 , and performs timing calibration on the calibrated channel 1 according to the reference channel 2 .

在一個具體示例中，電腦控制數字測試機中被選通的兩個激勵信號測試通道產生時鐘信號，例如時鐘信號為100MHz時鐘信號。In a specific example, two gated excitation signal test channels in a computer-controlled digital testing machine generate a clock signal, for example, the clock signal is a 100MHz clock signal.

在一種可能的實現方式中，該方法進一步包括：以所述採樣時鐘所在的測試通道作為校準基準通道，依次選通其他多個測試通道之一與所述窗口比較器連通作為被校準通道進行時序校準。In a possible implementation, the method further includes: using the test channel where the sampling clock is located as a calibration reference channel, and sequentially selecting one of the other multiple test channels to be connected to the window comparator as the calibrated channel to perform timing. Calibration.

在一種可能的實現方式中，如果被校準通道產生的時鐘信號邊沿與基準通道產生的時鐘信號邊沿不對齊，所述控制系統控制所述數位測試機激勵信號測試通道調整被校準通道輸出的時鐘相位，直到被校準通道的時鐘相位與基準通道產生的時鐘信號邊沿對齊。In a possible implementation, if the edge of the clock signal generated by the calibrated channel is not aligned with the edge of the clock signal generated by the reference channel, the control system controls the excitation signal test channel of the digital testing machine to adjust the clock phase output by the calibrated channel. , until the clock phase of the calibrated channel is edge-aligned with the clock signal generated by the reference channel.

在一個具體示例中，所述高速窗口比較器的輸出結果為隨機的0和1時，被校準通道與基準通道產生的時鐘信號邊沿對齊；所述高速窗口比較器的輸出結果為固定的0或1時，被校準通道與基準通道產生的時鐘信號邊沿不對齊，由此可以判斷被校準通道與基準通道產生的時鐘信號是否邊沿對齊，從而實現時序校準。In a specific example, when the output result of the high-speed window comparator is random 0 and 1, the clock signal generated by the calibrated channel and the reference channel is edge-aligned; the output result of the high-speed window comparator is a fixed 0 or 1. 1, the edges of the clock signals generated by the calibrated channel and the reference channel are not aligned. From this, it can be judged whether the edges of the clock signals generated by the calibrated channel and the reference channel are aligned, thereby achieving timing calibration.

當被校準通道與基準通道產生的時鐘信號邊沿不對齊時，所述控制系統2控制所述數位測試機1調整被校準通道輸出的時鐘相位，直到被校準通道與基準通道產生時鐘信號邊沿對齊，其中利用二分查找法調整被校準通道輸出的時鐘相位使得被校準通道與基準通道產生的時鐘信號邊沿對齊。When the edges of the clock signals generated by the calibrated channel and the reference channel are not aligned, the control system 2 controls the digital testing machine 1 to adjust the clock phase output by the calibrated channel until the edges of the clock signals generated by the calibrated channel and the reference channel are aligned, The binary search method is used to adjust the clock phase output by the calibrated channel so that the edges of the clock signals generated by the calibrated channel and the reference channel are aligned.

在一種可能的實現方式中，若測得被校準通道比基準通道相位超前，則令被校準通道輸出延遲N nS，此時若測得被校準通道比基準通道相位滯後，則調整被校準通道輸出延遲為N/2 nS，此時若測得被校準通道比基準通道相位滯後，則被校準通道比基準通道相位超前在0~N/2 nS範圍，若測得被校準通道比基準通道相位超前，則被校準通道比基準通道相位超前在N/2~N nS範圍，其中N＞0。In a possible implementation, if the measured phase of the calibrated channel is ahead of the reference channel, the output of the calibrated channel is delayed by N nS. At this time, if the measured phase of the calibrated channel is lagging behind the reference channel, the output of the calibrated channel is adjusted. The delay is N/2 nS. At this time, if the phase of the calibrated channel is measured to be lagging behind the reference channel, the phase of the calibrated channel is ahead of the reference channel in the range of 0~N/2 nS. If the phase of the calibrated channel is measured to be ahead of the reference channel , then the phase of the calibrated channel is ahead of the reference channel in the range of N/2~N nS, where N>0.

在一個具體示例中，通道1為被校準通道，即其他多個激勵信號測試通道之一與所述高速窗口比較器第一輸入端連通的通道；通道2為基準通道，即高速繼電器網路將被選通的兩個激勵信號測試通道之一與所述時鐘緩衝器輸入端和所述高速窗口比較器第二輸入端連通的通道，通道1和通道2都沒有輸出延遲時，測得通道1比通道2相位超前，增加通道1輸出延遲5nS，然後測得通道1比通道2相位滯後，則修改通道1輸出延遲為2.5nS，然後如果測得通道1比通道2相位滯後，則通道1比通道2相位超前在0~2.5nS範圍, 如果測得通道1比通道2相位超前，則通道1比通道2相位超前在2.5~5nS範圍，根據範圍判斷再依次二分判斷查找，最終找出實際的相位差。In a specific example, channel 1 is the channel to be calibrated, that is, one of the other multiple excitation signal test channels is connected to the first input end of the high-speed window comparator; channel 2 is the reference channel, that is, the high-speed relay network will One of the two gated excitation signal test channels is a channel connected to the input end of the clock buffer and the second input end of the high-speed window comparator. When neither channel 1 nor channel 2 has an output delay, channel 1 is measured. The phase is ahead of channel 2, increase the output delay of channel 1 by 5nS, and then measure the phase lag of channel 1 than channel 2, then modify the output delay of channel 1 to 2.5nS, and then if the measured phase lag of channel 1 is lag than channel 2, then channel 1 will be The phase lead of channel 2 is in the range of 0~2.5nS. If the measured phase lead of channel 1 is in the range of 2.5~5nS, then the phase lead of channel 1 is in the range of 2.5~5nS. Based on the range judgment, the search will be divided into two parts to finally find out the actual phase difference.

本發明提供的測試系統校準不需要連接待測數位晶片，校準完成後數位測試機再連接待測數位晶片。The calibration of the test system provided by the present invention does not require connecting the digital chip to be tested. After the calibration is completed, the digital testing machine is connected to the digital chip to be tested.

在一個具體示例中，本發明的測試系統的基準通道和所有被校準通道的校準精度為50ps，該精度主要是和高速窗口比較器的參數有關。In a specific example, the calibration accuracy of the reference channel and all calibrated channels of the test system of the present invention is 50ps. This accuracy is mainly related to the parameters of the high-speed window comparator.

需要說明的是，本實施例提供的時序校準系統的原理及工作流程與上述時序校準方法相似，相關之處可以參照上述說明，在此不再贅述。It should be noted that the principle and work flow of the timing calibration system provided in this embodiment are similar to the above-mentioned timing calibration method. For relevant points, reference can be made to the above description, which will not be described again here.

本發明實施例提供的時序校準系統和方法，無需外接示波器等儀器，利用了高速窗口比較器，可以快速實現數位測試機pattern測試通道的時序校準，提高了時序校準效率，並且校準精度能夠達到50ps以內，滿足校準精度要求。The timing calibration system and method provided by the embodiments of the present invention do not require external instruments such as oscilloscopes. They use high-speed window comparators to quickly realize timing calibration of the pattern test channel of a digital testing machine, improve timing calibration efficiency, and the calibration accuracy can reach 50 ps. Within, the calibration accuracy requirements are met.

顯然，本發明的上述實施例僅僅是為清楚地說明本發明所作的舉例，而並非是對本發明的實施方式的限定，對於所屬領域的具有通常知識者來說，在上述說明的基礎上還可以做出其它不同形式的變化或變動，這裡無法對所有的實施方式予以窮舉，凡是屬於本發明的技術方案所引伸出的顯而易見的變化或變動仍處於本發明的保護範圍之列。Obviously, the above-mentioned embodiments of the present invention are only examples to clearly illustrate the present invention, and are not intended to limit the implementation of the present invention. For those with ordinary knowledge in the field, based on the above description, they can also Other changes or modifications can be made in different forms, and it is impossible to exhaustively enumerate all the implementations here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

1:數位測試機 2:控制終端 3:時序校準板卡 31:高速繼電器網路 32:高速窗口比較器 33:時鐘緩衝器 34:FPGA 1: Digital testing machine 2:Control terminal 3: Timing calibration board 31:High speed relay network 32: High-speed window comparator 33: Clock buffer 34:FPGA

圖1示出本發明實施例提供的一種時序校準系統的示意圖。 圖2示出本發明實施例提供的一種時序校準方法的流程圖。 Figure 1 shows a schematic diagram of a timing calibration system provided by an embodiment of the present invention. Figure 2 shows a flow chart of a timing calibration method provided by an embodiment of the present invention.

Claims (10)

一種時序校準方法，其特徵在於，用於對一數位測試機的若干測試通道中的一測試信號進行時序校準，該方法包括： 選通所述數位測試機的任意兩個測試通道，以輸出測試信號； 採用一窗口比較器對選通的兩個測試通道輸出的測試信號進行比較，並將比較結果輸出到一FPGA； 被選通的兩個測試通道其中之一輸出的測試信號經一時鐘緩衝器傳輸到所述FPGA作為一採樣時鐘； 所述FPGA根據所述採樣時鐘採集所述窗口比較器的輸出結果，並將結果資訊發送給一控制終端； 所述控制終端根據所述FPGA的輸出結果調整對應的測試通道中測試信號的時鐘相位，以完成對測試通道的時序校準。 A timing calibration method, characterized in that it is used to perform timing calibration on a test signal in several test channels of a digital testing machine. The method includes: Gating any two test channels of the digital test machine to output test signals; A window comparator is used to compare the test signals output by the two gated test channels, and the comparison result is output to an FPGA; The test signal output by one of the two gated test channels is transmitted to the FPGA through a clock buffer as a sampling clock; The FPGA collects the output result of the window comparator according to the sampling clock, and sends the result information to a control terminal; The control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output result of the FPGA to complete the timing calibration of the test channel. 根據請求項1所述的時序校準方法，其中，該方法進一步包括：以所述採樣時鐘所在的測試通道作為一校準基準通道，依次選通其他多個測試通道之一與所述窗口比較器連通作為一被校準通道進行時序校準。The timing calibration method according to claim 1, wherein the method further includes: using the test channel where the sampling clock is located as a calibration reference channel, and sequentially selecting one of the other multiple test channels to connect to the window comparator. Perform timing calibration as a calibrated channel. 根據請求項1所述的時序校準方法，其中，所述數位測試機的多個激勵信號測試通道連接一繼電器網路的輸入端，所述繼電器網路的第一輸出端連接所述窗口比較器的第一輸入端，所述繼電器網路的第二輸出端連接所述窗口比較器的第二輸入端和所述時鐘緩衝器的輸入端，所述窗口比較器的輸出端連接所述FPGA的第一輸入端，所述時鐘緩衝器的輸出端連接所述FPGA的第二輸入端，所述FPGA的輸出端連接所述控制終端。The timing calibration method according to claim 1, wherein the plurality of excitation signal test channels of the digital testing machine are connected to the input end of a relay network, and the first output end of the relay network is connected to the window comparator. The first input end of the relay network is connected to the second input end of the window comparator and the input end of the clock buffer. The output end of the window comparator is connected to the FPGA. The first input terminal, the output terminal of the clock buffer is connected to the second input terminal of the FPGA, and the output terminal of the FPGA is connected to the control terminal. 根據請求項3所述的時序校準方法，其中，所述控制終端控制所述繼電器網路中的繼電器斷開或閉合，使被選通的兩個激勵信號測試通道分別輸出到所述繼電器網路的第一輸出端和第二輸出端。The timing calibration method according to claim 3, wherein the control terminal controls the relays in the relay network to open or close, so that the two gated excitation signal test channels are output to the relay network respectively. the first output terminal and the second output terminal. 根據請求項2所述的時序校準方法，其中，如果所述被校準通道產生的時鐘信號邊沿與一基準通道產生的時鐘信號邊沿不對齊，所述控制系統控制所述數位測試機的多個激勵信號測試通道調整所述被校準通道輸出的時鐘相位，直到所述被校準通道的時鐘相位與所述基準通道產生的時鐘信號邊沿對齊。The timing calibration method according to claim 2, wherein if the edge of the clock signal generated by the calibrated channel is not aligned with the edge of the clock signal generated by a reference channel, the control system controls a plurality of excitations of the digital testing machine The signal test channel adjusts the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the edge of the clock signal generated by the reference channel. 根據請求項5所述的時序校準方法，其中，利用二分查找法調整所述被校準通道輸出的時鐘相位。The timing calibration method according to claim 5, wherein a binary search method is used to adjust the clock phase output by the calibrated channel. 根據請求項6所述的時序校準方法，其中，若測得所述被校準通道比所述基準通道相位超前，則令所述被校準通道輸出延遲N nS，此時若測得所述被校準通道比所述基準通道相位滯後，則調整所述被校準通道輸出延遲為N/2 nS，此時若測得所述被校準通道比所述基準通道相位滯後，則所述被校準通道比所述基準通道相位超前在0~N/2 nS範圍，若測得所述被校準通道比所述基準通道相位超前，則所述被校準通道比所述基準通道相位超前在N/2~N nS範圍，其中N＞0。The timing calibration method according to claim 6, wherein if the phase of the calibrated channel is measured to be ahead of the reference channel, the output of the calibrated channel is delayed by N nS. At this time, if the calibrated channel is measured to be If the phase of the channel is lagging behind that of the reference channel, then the output delay of the calibrated channel is adjusted to N/2 nS. At this time, if it is measured that the phase of the calibrated channel is lagging behind that of the reference channel, then the calibrated channel will be The phase lead of the reference channel is in the range of 0~N/2 nS. If it is measured that the phase of the calibrated channel is ahead of the phase of the reference channel, then the phase of the calibrated channel is ahead of the reference channel by N/2~N nS. range, where N>0. 一種執行上述請求項1-7中任一項時序校準方法的時序校準系統，其特徵在於，該系統包括：一數位測試機、一控制終端和一時序校準板卡； 所述時序校準板卡包括：一繼電器網路、一窗口比較器、一時鐘緩衝器和一FPGA； 其中，所述數位測試機包含多個激勵信號測試通道； 所述繼電器網路用於將所述數位測試機的所述多個激勵信號測試通道選通任意兩個激勵信號測試通道分別輸出到所述窗口比較器； 所述窗口比較器用於對選通後的兩個激勵信號測試通道輸出的時鐘信號進行比較，判斷兩個時鐘信號邊沿是否對齊，並將判斷結果輸出到所述FPGA； 所述時鐘緩衝器用於將所選通的激勵信號測試通道之一輸出的時鐘信號緩衝後輸出到所述FPGA作為一採樣時鐘； 所述FPGA用於根據所述採樣時鐘採集所述窗口比較器的比較結果，並將結果發送給所述控制終端； 所述控制終端用於控制所述多個激勵信號測試通道產生時鐘信號，判斷兩個激勵信號測試通道產生的時鐘信號是否邊沿對齊，並進行時序校準。 A timing calibration system that performs any one of the timing calibration methods in claims 1-7 above, characterized in that the system includes: a digital testing machine, a control terminal and a timing calibration board; The timing calibration board includes: a relay network, a window comparator, a clock buffer and an FPGA; Wherein, the digital testing machine includes multiple excitation signal test channels; The relay network is used to select any two excitation signal test channels of the plurality of excitation signal test channels of the digital testing machine and output them to the window comparator respectively; The window comparator is used to compare the clock signals output by the two excitation signal test channels after gating, judge whether the edges of the two clock signals are aligned, and output the judgment result to the FPGA; The clock buffer is used to buffer the clock signal output by one of the selected excitation signal test channels and then output it to the FPGA as a sampling clock; The FPGA is configured to collect the comparison results of the window comparator according to the sampling clock, and send the results to the control terminal; The control terminal is used to control the plurality of excitation signal test channels to generate clock signals, determine whether the clock signals generated by the two excitation signal test channels are edge aligned, and perform timing calibration. 根據請求項8所述的時序校準系統，其中，所述繼電器網路和所述窗口比較器支援100~800MHz工作頻率。The timing calibration system according to claim 8, wherein the relay network and the window comparator support an operating frequency of 100~800MHz. 根據請求項8所述的時序校準系統，其中，所述控制終端控制所述繼電器網路選通測試通道之一與所述時鐘緩衝器輸入端和所述窗口比較器第二輸入端連通用作一校準基準通道，依次選通其他多個激勵信號測試通道之一與所述窗口比較器第一輸入端連通作為一被校準通道進行時序校準。The timing calibration system according to claim 8, wherein the control terminal controls one of the relay network gating test channels to be connected to the input end of the clock buffer and the second input end of the window comparator for use as A calibration reference channel is sequentially selected to connect one of the other excitation signal test channels to the first input end of the window comparator as a calibrated channel for timing calibration.
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