CN114646870B - Time sequence calibration method and system - Google Patents
Time sequence calibration method and system Download PDFInfo
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- CN114646870B CN114646870B CN202210115782.8A CN202210115782A CN114646870B CN 114646870 B CN114646870 B CN 114646870B CN 202210115782 A CN202210115782 A CN 202210115782A CN 114646870 B CN114646870 B CN 114646870B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012360 testing method Methods 0.000 claims abstract description 147
- 238000005070 sampling Methods 0.000 claims abstract description 19
- 230000003111 delayed effect Effects 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000005284 excitation Effects 0.000 description 16
- 239000013598 vector Substances 0.000 description 10
- 238000004891 communication Methods 0.000 description 3
- 230000000638 stimulation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
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Abstract
The invention discloses a time sequence calibration method and a system, wherein the time sequence calibration method is used for time sequence calibration of test signals in a plurality of test channels of a digital tester, and comprises the following steps: gating any two test channels of the digital tester to output test signals; comparing the test signals output by the two selected test channels by adopting a window comparator, and outputting a comparison result to the FPGA; the test signal output by one of the two selected test channels is transmitted to the FPGA through the clock buffer to serve as a sampling clock; the FPGA acquires the output result of the window comparator according to the sampling clock and sends the result information to the control terminal; the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to complete the time sequence calibration of the test channel.
Description
Technical Field
The present invention relates to the field of chip testing, and more particularly, to a timing calibration method and system.
Background
The digital chip tester generally supports pattern (test vector) test, and is used for judging whether the chip functions normally or not by testing the pattern, so that the rapid test of large-scale mass production of the digital chip is realized.
The digital chip tester generally supports hundreds of test channels, and digital signals output by each test channel are required to be output to pins of a digital chip to be tested at the same time, namely, the digital signals need to be aligned along edges so as to ensure that time sequences among signals output to the pins of the digital chip to be tested are correct. To ensure that the edges of the digital signals output by all the test channels of all the digital chip testers are aligned, the digital signal timing calibration is needed to be realized.
The existing method generally judges whether the test edges of the test channels are aligned one by one through a high-speed oscilloscope, and the method needs an additional high-speed oscilloscope, has high cost and is inconvenient to use; or outputting a signal phase after the clock through two channels, and measuring and calculating whether the edges are aligned in a mode of collecting voltage after charging the phase signals through a capacitor.
Disclosure of Invention
It is an object of the present invention to provide a timing calibration method and system to solve at least one of the problems of the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the first aspect of the present invention provides a timing calibration method for performing timing calibration on test signals in a plurality of test channels of a digital tester, the method comprising:
gating any two test channels of the digital tester to output test signals;
comparing the test signals output by the two selected test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two selected test channels is transmitted to the FPGA through the clock buffer to serve as a sampling clock;
the FPGA acquires the output result of the window comparator according to the sampling clock and sends the result information to the control terminal;
the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to complete the time sequence calibration of the test channel.
Optionally, the method further comprises: and sequentially gating one of the other multiple test channels and communicating with the window comparator to serve as a calibrated channel to perform time sequence calibration by taking the test channel in which the sampling clock is positioned as a calibration reference channel.
Optionally, the multiple excitation signal test channels of the digital testing machine are connected with the input end of the relay network, the first output end of the relay network is connected with the first input end of the window comparator, the second output end of the relay network is connected with the second input end of the window comparator and the input end of the clock buffer, the output end of the window comparator is connected with the first input end of the FPGA, the output end of the clock buffer is connected with the second input end of the FPGA, and the output end of the FPGA is connected with the control terminal.
Optionally, the control terminal controls the relay in the relay network to be opened or closed, so that the two selected excitation signal test channels are respectively output to the first output end and the second output end of the relay network.
Optionally, if the clock signal edge generated by the calibrated channel is not aligned with the clock signal edge generated by the reference channel, the control system controls the digital tester stimulation signal test channel to adjust the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the clock signal edge generated by the reference channel.
Alternatively, a binary search is used to adjust the clock phase of the calibrated channel output.
Optionally, if the calibrated channel is measured to be in advance of the reference channel phase, the calibrated channel is delayed by N nS, and if the calibrated channel is measured to be in behind the reference channel phase, the calibrated channel is adjusted to be delayed by N/2nS, and if the calibrated channel is measured to be in behind the reference channel phase, the calibrated channel is in advance of the reference channel phase by 0-N/2 nS, and if the calibrated channel is measured to be in advance of the reference channel phase, the calibrated channel is in advance of the reference channel phase by N/2-N nS, wherein N > 0.
A second aspect of the present invention provides a timing calibration system for performing the above-described timing calibration method, the system comprising: the device comprises a digital testing machine, a control terminal and a time sequence calibration board card;
the timing calibration board card includes: the device comprises a relay network, a window comparator, a clock buffer and an FPGA;
the digital tester comprises a plurality of excitation signal testing channels;
the relay network is used for gating a plurality of excitation signal test channels of the digital testing machine to any two excitation signal test channels and outputting the excitation signal test channels to the window comparator respectively;
the window comparator is used for comparing clock signals output by the two gated excitation signal test channels, judging whether edges of the two clock signals are aligned or not, and outputting a judging result to the FPGA;
the clock buffer is used for buffering a clock signal output by one of the selected excitation signal test channels and outputting the clock signal to the FPGA as a sampling clock;
the FPGA is used for collecting the comparison result of the window comparator according to the sampling clock and sending the result to the control terminal;
the control terminal is used for controlling the excitation signal test channels to generate clock signals, judging whether the clock signals generated by the two excitation signal test channels are aligned in edge, and performing time sequence calibration.
Optionally, the relay network and the window comparator support 100-800 MHz operating frequencies.
Optionally, the control terminal controls one of the relay network strobe test channels to be connected with the clock buffer input end and the second input end of the high-speed window comparator to serve as a calibration reference channel, and sequentially gates one of the other multiple stimulus signal test channels to be connected with the first input end of the window comparator to serve as a calibrated channel for time sequence calibration.
The beneficial effects of the invention are as follows:
the technical scheme of the invention provides a time sequence calibration method and a time sequence calibration system, which can realize time sequence calibration without external oscilloscopes and other instruments, and are convenient to use. According to the time sequence calibration method, the time sequence calibration of the test channels of the digital tester can be rapidly realized by utilizing the high-speed relay network and the high-speed window comparator in the time sequence calibration board, the time sequence calibration efficiency is improved, the calibration precision of all the test channels can reach within 50ps, and the calibration precision requirement is met.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Fig. 1 shows a schematic diagram of a timing calibration system according to an embodiment of the present invention.
Fig. 2 shows a flowchart of a timing calibration method according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
As shown in fig. 1, one embodiment of the present invention provides a timing calibration system including a digital tester 1, a control terminal 2, and a timing calibration board 3.
The digital tester 1 includes a plurality of test channels, and each test channel is correspondingly transmitted with a test vector (Pattern), and the test vector is used as a test signal to be sent to a pin of a product to be tested by the digital tester. A typical digital tester 1 includes 512, 768, 1024 test channels. I.e. 512 test vectors are transmitted for a corresponding 512 test channels.
The control terminal 2 may be a computer or a cloud server, and is mainly used for controlling the execution of the time sequence calibration process.
The timing alignment board 3 includes: a high speed relay network 31, a high speed window comparator 32, a clock buffer 33 and an FPGA 34.
The high-speed relay network 31 is used for gating any two test channels of the digital tester, so that two test vectors in the two gated test channels are respectively output to the high-speed window comparator 32. In one specific example, the high-speed relay network 31 and the high-speed window comparator 32 support a maximum of 800MHz operating frequency.
The high-speed window comparator 32 is configured to compare the test vector signals output by the two gated test channels, determine whether edges of the two test vector signals are aligned, and output a determination result to the FPGA34;
the clock buffer 33 is configured to buffer a test vector signal generated by one of the test channels and output the buffered test vector signal to the FPGA34 as a sampling clock;
the FPGA34 is configured to collect the comparison result of the high-speed window comparator 32 according to the sampling clock, and send the result to the control terminal 2.
The control terminal 2 is used for controlling the excitation signal test channels to generate clock signals, judging whether the clock signals generated by the two excitation signal test channels are aligned in edge, and performing time sequence calibration.
In one possible implementation, the relay network and the window comparator support 100-800 MHz operating frequencies.
In one possible implementation manner, the control terminal controls one of the relay network strobe test channels to be connected with the clock buffer input end and the window comparator second input end to serve as a calibration reference channel, and sequentially gates one of the other multiple stimulus signal test channels to be connected with the high-speed window comparator first input end to serve as a calibrated channel for time sequence calibration.
As shown in fig. 2, another embodiment of the present invention provides a timing calibration method for performing timing calibration on test signals in a plurality of test channels of a digital tester, the method comprising:
gating any two test channels of the digital tester to output test signals;
comparing the test signals output by the two selected test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two selected test channels is transmitted to the FPGA through the clock buffer to serve as a sampling clock;
the FPGA acquires the output result of the window comparator according to the sampling clock and sends the result information to the control terminal;
the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to complete the time sequence calibration of the test channel. In one possible implementation manner, the multiple excitation signal test channels of the digital test machine 1 are connected to the input end of the high-speed relay network 31, the first output end of the high-speed relay network 31 is connected to the first input end of the high-speed window comparator 32, the second output end of the high-speed relay network 31 is connected to the second input end of the high-speed window comparator 32 and the input end of the clock BUFFE33, the output end of the high-speed window comparator 32 is connected to the first input end of the FPGA34, the output end of the clock buffer 33 is connected to the second input end of the FPGA34, and the output end of the FPGA34 is connected to the control terminal 2.
In one possible implementation, the control terminal 2 controls the relays in the high-speed relay network 31 to be opened or closed, so that the two excitation signal test channels that are selected are output to the first output terminal and the second output terminal of the high-speed relay network 31, respectively.
In a specific example, at least 512 test channels included in the digital testing machine 1 are all connected to the input end of the high-speed relay network 31, 512 test channels correspondingly transmit 512 test vectors (patterns), the high-speed relay network 31 randomly selects two test channels for outputting at least 512 test channels included in the digital testing machine 1, two output ends of the high-speed relay network 31 are all connected to the input end of the high-speed window comparator 32, meanwhile, one output end of the high-speed relay network 31 is connected to the input end of the clock buffer 33, the output end of the high-speed window comparator 32 is connected to the FPGA, the output end of the clock buffer 33 is connected to the FPGA, the FPGA samples the comparison result of the high-speed window comparator 32 by using the sampling clock output by the clock buffer 33, and then the sampling result is transmitted to the control terminal 2, for example, the control terminal 2 is a computer, and the computer determines whether the edges of the two test channels of the current test are aligned and performs time sequence calibration.
In one possible implementation, the control terminal 2 controls the high-speed relay network 31 to gate one of the test channels in communication with the clock buffer 33 input and the high-speed window comparator 32 second input to serve as a calibration reference channel, referred to as channel 2, and sequentially gates one of the other multiple stimulus signal test channels in communication with the high-speed window comparator first input to serve as a calibrated channel, referred to as channel 1, for timing calibration.
In a specific example, the control terminal 2 sequentially gates the other stimulus signal test channels that are not gated by the high-speed window comparator 32, and performs timing calibration on the calibrated channel 1 according to the reference channel 2.
In one specific example, the computer controls two stimulus signal test channels that are gated in the digital tester to generate a clock signal, e.g., the clock signal is a 100MHz clock signal.
In one possible implementation, the method further includes: and sequentially gating one of the other multiple test channels and communicating with the window comparator to serve as a calibrated channel to perform time sequence calibration by taking the test channel in which the sampling clock is positioned as a calibration reference channel.
In one possible implementation, if the clock signal edge generated by the calibrated channel is not aligned with the clock signal edge generated by the reference channel, the control system controls the digital tester stimulation signal test channel to adjust the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the clock signal edge generated by the reference channel.
In a specific example, when the output result of the high-speed window comparator is random 0 and 1, the calibrated channel is aligned with the clock signal edge generated by the reference channel; when the output result of the high-speed window comparator is fixed 0 or 1, the edges of the clock signals generated by the calibrated channel and the reference channel are not aligned, so that whether the edges of the clock signals generated by the calibrated channel and the reference channel are aligned can be judged, and time sequence calibration is realized.
When the clock signal edges generated by the calibrated channel and the reference channel are not aligned, the control system 2 controls the digital testing machine 1 to adjust the clock phase output by the calibrated channel until the clock signal edges generated by the calibrated channel and the reference channel are aligned, wherein the clock phase output by the calibrated channel is adjusted by using a binary search method so that the clock signal edges generated by the calibrated channel and the reference channel are aligned.
In one possible implementation, if the calibrated channel is phase-advanced from the reference channel, the calibrated channel output is delayed by N nS, then if the calibrated channel is phase-retarded from the reference channel, the calibrated channel output delay is adjusted to N/2nS, then if the calibrated channel is phase-retarded from the reference channel, the calibrated channel is phase-advanced from the reference channel by 0 to N/2nS, and if the calibrated channel is phase-advanced from the reference channel, the calibrated channel is phase-advanced from the reference channel by N/2 to N nS, where N > 0.
In a specific example, the channel 1 is a calibrated channel, that is, one of the other multiple excitation signal test channels is in communication with the first input terminal of the high-speed window comparator; and when the channel 2 is a reference channel, namely one of two excitation signal test channels which are to be gated by the high-speed relay network is communicated with the input end of the clock buffer and the second input end of the high-speed window comparator, and the channel 1 and the channel 2 are not delayed in output, the phase of the channel 1 is detected to be advanced compared with that of the channel 2, the output delay of the channel 1 is increased by 5nS, then the phase delay of the channel 1 is detected to be delayed compared with that of the channel 2, the output delay of the channel 1 is modified to be 2.5nS, then if the phase delay of the channel 1 is detected to be delayed compared with that of the channel 2, the phase advance of the channel 1 is in the range of 0-2.5 nS, and if the phase advance of the channel 1 is detected to be advanced compared with that of the channel 2, the phase advance of the channel 1 is in the range of 2.5-5 nS, the phase advance of the channel 1 is judged to be searched by two times in sequence according to the range judgment, and finally the actual phase difference is found.
The test system provided by the invention does not need to be connected with the digital chip to be tested in calibration, and the digital tester is connected with the digital chip to be tested after the calibration is completed.
In one specific example, the calibration accuracy of the reference channel and all calibrated channels of the test system of the present invention is 50ps, which is primarily related to the parameters of the high-speed window comparator.
It should be noted that, the principle and workflow of the timing calibration system provided in this embodiment are similar to those of the timing calibration method described above, and the relevant points can be referred to the above description, which is not repeated here.
The time sequence calibration system and the time sequence calibration method provided by the embodiment of the invention do not need to be externally connected with instruments such as an oscilloscope, and the like, can quickly realize the time sequence calibration of the pattern test channel of the digital tester by utilizing the high-speed window comparator, improve the time sequence calibration efficiency, ensure that the calibration precision can reach within 50ps, and meet the calibration precision requirement.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (7)
1. A method for timing calibration of test signals in a plurality of test channels of a digital tester, the method comprising:
gating any two test channels of the digital tester to output test signals;
comparing the test signals output by the two selected test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two selected test channels is transmitted to the FPGA through the clock buffer to serve as a sampling clock;
the FPGA acquires the output result of the window comparator according to the sampling clock and sends the result information to the control terminal;
the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output result of the FPGA so as to complete the time sequence calibration of the test channel;
the method further comprises the steps of: and sequentially gating one of the other multiple test channels and communicating with the window comparator to serve as a calibrated channel to perform time sequence calibration by taking the test channel in which the sampling clock is positioned as a calibration reference channel.
2. The timing calibration method of claim 1, wherein a plurality of test channels of the digital tester are connected to an input of a relay network, a first output of the relay network is connected to a first input of the window comparator, a second output of the relay network is connected to a second input of the window comparator and an input of the clock buffer, an output of the window comparator is connected to a first input of the FPGA, an output of the clock buffer is connected to a second input of the FPGA, and an output of the FPGA is connected to the control terminal.
3. The timing calibration method of claim 2, wherein the control terminal controls the relays in the relay network to be opened or closed such that the two test channels that are gated are output to the first output terminal and the second output terminal of the relay network, respectively.
4. The timing calibration method of claim 1 wherein if the test signal edge generated by the calibrated channel is not aligned with the test signal edge generated by the reference channel, the control terminal controls the digital tester test channel to adjust the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the test signal edge generated by the reference channel.
5. The method of timing calibration according to claim 4, wherein the clock phase of the calibrated channel output is adjusted using a binary search.
6. The timing calibration method according to claim 5, wherein if the calibrated channel is phase-advanced from the reference channel, the calibrated channel output is delayed by N nS, and if the calibrated channel is phase-retarded from the reference channel, the calibrated channel output is adjusted by N/2nS, and if the calibrated channel is phase-retarded from the reference channel, the calibrated channel is phase-advanced from the reference channel by 0 to N/2nS, and if the calibrated channel is phase-advanced from the reference channel, the calibrated channel is phase-advanced from the reference channel by N/2 to N nS, wherein N > 0.
7. A timing calibration system for performing the timing calibration method of any of claims 1-6, the system comprising: the device comprises a digital testing machine, a control terminal and a time sequence calibration board card;
the timing calibration board card includes: the device comprises a relay network, a window comparator, a clock buffer and an FPGA;
the digital testing machine comprises a plurality of testing channels;
the relay network is used for gating a plurality of test channels of the digital testing machine to any two test channels and outputting the test channels to the window comparator respectively;
the window comparator is used for comparing the test signals output by the two gated test channels, judging whether the edges of the two test signals are aligned or not, and outputting a judging result to the FPGA;
the clock buffer is used for buffering a test signal output by one of the selected test channels and outputting the test signal to the FPGA as a sampling clock;
the FPGA is used for collecting the comparison result of the window comparator according to the sampling clock and sending the result to the control terminal;
the control terminal is used for controlling the test channels to generate test signals, judging whether the test signals generated by the two test channels are aligned in edge, and performing time sequence calibration;
the relay network and the window comparator support 100-800 MHz working frequency;
and the control terminal controls one of the relay network gating test channels to be connected with the input end of the clock buffer and the second input end of the window comparator to serve as a calibration reference channel, and sequentially gates one of the other multiple test channels to be connected with the first input end of the window comparator to serve as a calibrated channel for time sequence calibration.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210115782.8A CN114646870B (en) | 2022-02-07 | 2022-02-07 | Time sequence calibration method and system |
| PCT/CN2022/127520 WO2023147732A1 (en) | 2022-02-07 | 2022-10-26 | Timing calibration method and system |
| TW111141229A TWI826083B (en) | 2022-02-07 | 2022-10-28 | Timing calibration method and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210115782.8A CN114646870B (en) | 2022-02-07 | 2022-02-07 | Time sequence calibration method and system |
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| CN114646870A CN114646870A (en) | 2022-06-21 |
| CN114646870B true CN114646870B (en) | 2024-03-12 |
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| CN202210115782.8A Active CN114646870B (en) | 2022-02-07 | 2022-02-07 | Time sequence calibration method and system |
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| CN (1) | CN114646870B (en) |
| TW (1) | TWI826083B (en) |
| WO (1) | WO2023147732A1 (en) |
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| CN114646870B (en) * | 2022-02-07 | 2024-03-12 | 苏州华兴源创科技股份有限公司 | Time sequence calibration method and system |
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| CN109633508A (en) * | 2018-12-24 | 2019-04-16 | 电子科技大学 | Acquisition channel synchronism detection method in digital integrated electronic circuit test macro |
| CN111123076A (en) * | 2020-01-09 | 2020-05-08 | 苏州华兴源创科技股份有限公司 | Calibration device and automatic test equipment |
| CN111786768A (en) * | 2020-07-10 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Multichannel parallel test calibration method |
| CN112711296A (en) * | 2020-12-25 | 2021-04-27 | 北京航天测控技术有限公司 | Calibration system |
| CN213547494U (en) * | 2020-11-25 | 2021-06-25 | 久元电子股份有限公司 | Time sequence calibration device for multi-channel group |
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| US6704882B2 (en) * | 2001-01-22 | 2004-03-09 | Mayo Foundation For Medical Education And Research | Data bit-to-clock alignment circuit with first bit capture capability |
| EP2871494B1 (en) * | 2013-11-08 | 2018-03-21 | u-blox AG | Phase-alignment between clock signals |
| KR102605646B1 (en) * | 2018-06-07 | 2023-11-24 | 에스케이하이닉스 주식회사 | Assymetric pulse width comparator circuit and clock phase correction circuit including the same |
| DE102019121891A1 (en) * | 2018-08-20 | 2020-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | CLOCK WORK CYCLE SETTING AND CALIBRATION CIRCUIT AND METHOD FOR OPERATING THE SAME |
| US10841072B2 (en) * | 2018-12-05 | 2020-11-17 | Samsung Electronics Co., Ltd. | System and method for providing fast-settling quadrature detection and correction |
| US10797683B1 (en) * | 2020-03-06 | 2020-10-06 | Faraday Technology Corp. | Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases |
| CN114646870B (en) * | 2022-02-07 | 2024-03-12 | 苏州华兴源创科技股份有限公司 | Time sequence calibration method and system |
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2022
- 2022-02-07 CN CN202210115782.8A patent/CN114646870B/en active Active
- 2022-10-26 WO PCT/CN2022/127520 patent/WO2023147732A1/en unknown
- 2022-10-28 TW TW111141229A patent/TWI826083B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633508A (en) * | 2018-12-24 | 2019-04-16 | 电子科技大学 | Acquisition channel synchronism detection method in digital integrated electronic circuit test macro |
| CN111123076A (en) * | 2020-01-09 | 2020-05-08 | 苏州华兴源创科技股份有限公司 | Calibration device and automatic test equipment |
| CN111786768A (en) * | 2020-07-10 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Multichannel parallel test calibration method |
| CN213547494U (en) * | 2020-11-25 | 2021-06-25 | 久元电子股份有限公司 | Time sequence calibration device for multi-channel group |
| CN112711296A (en) * | 2020-12-25 | 2021-04-27 | 北京航天测控技术有限公司 | Calibration system |
Also Published As
| Publication number | Publication date |
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| TWI826083B (en) | 2023-12-11 |
| TW202332927A (en) | 2023-08-16 |
| WO2023147732A1 (en) | 2023-08-10 |
| CN114646870A (en) | 2022-06-21 |
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