TW202245194A - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
- Publication number
- TW202245194A TW202245194A TW110134936A TW110134936A TW202245194A TW 202245194 A TW202245194 A TW 202245194A TW 110134936 A TW110134936 A TW 110134936A TW 110134936 A TW110134936 A TW 110134936A TW 202245194 A TW202245194 A TW 202245194A
- Authority
- TW
- Taiwan
- Prior art keywords
- interconnect structure
- backside
- substrate
- heat dissipation
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 151
- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 206
- 230000017525 heat dissipation Effects 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims description 137
- 239000012530 fluid Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 description 305
- 230000008569 process Effects 0.000 description 115
- 239000002086 nanomaterial Substances 0.000 description 103
- 125000006850 spacer group Chemical group 0.000 description 98
- 238000005530 etching Methods 0.000 description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 25
- 239000010703 silicon Substances 0.000 description 25
- 229910021332 silicide Inorganic materials 0.000 description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 24
- 239000012535 impurity Substances 0.000 description 18
- 239000011810 insulating material Substances 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 239000004020 conductor Substances 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 238000000231 atomic layer deposition Methods 0.000 description 13
- 238000000151 deposition Methods 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 11
- 229910052737 gold Inorganic materials 0.000 description 11
- 239000010931 gold Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 238000002513 implantation Methods 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000000137 annealing Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 239000007943 implant Substances 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 229910005540 GaP Inorganic materials 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- -1 combinations thereof Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000002826 coolant Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011152 fibreglass Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical group [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000002135 nanosheet Substances 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- CGZLUZNJEQKHBX-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti][Ti][W] CGZLUZNJEQKHBX-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Bipolar Transistors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
揭示具有改善散熱的半導體元件及其製造方法。在一個實施例中,一種元件包括第一電晶體結構;在第一電晶體結構的前側上的前側互連結構,前側互連結構包括前側導電線;在第一電晶體結構的背側上的背側互連結構,背側互連結構包括背側導電線,背側導電線具有大於前側導電線線寬的線寬;及耦合至背側互連結構的第一散熱基板。
Description
無
半導體元件用於多種電子應用,諸如個人電腦、手機、數位相機、及其他電子設備。半導體元件通常藉由在半導體基板上方依序沉積材料的絕緣或介電層、導電層、及半導體層,且使用微影術圖案化各種材料層以在其上形成電路組件及元件製造。
半導體行業藉由不斷減小最小特徵尺寸來不斷提高各種電子組件 (例如,電晶體、二極體、電阻器、電容器等) 的積體密度,從而允許更多組件整合至給定面積中。然而,隨著最小特徵尺寸的減小,出現了應解決的其他問題。
無
以下揭示內容提供用於實施所提供標的物的不同特徵的許多不同實施例、或實例。下文描述組件及配置的特定實例以簡化本揭示內容。當然,這些僅為實例且非意欲為限制性的。舉例而言,在以下描述中第一特徵於第二特徵上方或上的形成可包括第一及第二特徵直接接觸地形成的實施例,且亦可包括額外特徵可形成於第一特徵與第二特徵之間使得第一特徵及第二特徵可不直接接觸的實施例。此外,本揭示內容在各種實例中可重複參考數字及/或字母。此重複為出於簡單及清楚的目的,且本身且不指明所論述的各種實施例及/或組態之間的關係。
此外,為了方便用於描述如諸圖中圖示的一個元件或特徵與另一(複數個)元件或(複數個)特徵的關係的描述,在本文中可使用空間相對術語,諸如「在……下面」、「在……之下」、「下部」、「在……之上」、「上部」及類似者。空間相對術語意欲涵蓋除了諸圖中所描繪的定向以外的元件在使用或操作時的不同定向。元件可另外定向 (旋轉90度或處於其他定向) ,且本文中所使用的空間相對描述符可類似地加以相應解釋。
各種實施例提供了具有改善的散熱的半導體元件及其製造方法。半導體元件可包括在電晶體結構的相對側上的前側互連結構 (亦稱為後段製程(back end of line,BEOL)互連結構) 及背側互連結構 (亦稱為埋入式電源網路(buried power network,BPN)) 。提供背側互連結構可減少前側互連結構所需的層數,且背側互連結構可具有比前側互連結構更寬的接線,前述兩者透過前側互連結構及背側互連結構,提供改善的散熱。在一些實施例中,前側互連結構可耦合至散熱器,且背側互連結構可耦合至基板。基板可包括嵌入式流體通道,且熱量可經由散熱器及基板兩者分散。在一些實施例中,前側互連結構可耦合至基板,且背側互連結構可耦合至散熱器。熱量可經由散熱器分散。提供背側互連結構,且經由背側互連結構以及前側互連結構散熱,改善了散熱、改善了元件效能、且減少了元件缺陷。
以下在特定上下文中描述實施例,即,包含奈米FET的晶片。然而,各種實施例可應用於包含替代奈米FET或與奈米FET組合的其他類型的電晶體 (例如,鰭式場效電晶體 (fin field effect transistor,FinFET)、或平面電晶體等) 的晶片。
第1圖在三維視圖中示出了根據一些實施例的奈米FET (例如,奈米線FET、或奈米片FET (奈米FET) 等) 實例。奈米FET包括基板50 (例如半導體基板) 上鰭片66上方的奈米結構55 (例如,奈米片、或奈米線等) 。奈米結構55充當奈米FET的通道區。奈米結構55可包括p型奈米結構、n型奈米結構、或其組合。隔離區68設置在相鄰鰭片66之間,鰭片66可突出於相鄰隔離區68之上及之間。儘管隔離區68被描述及圖示為與基板50分開,如本文所用,術語「基板」可指單獨的半導體基板或半導體基板與隔離區的組合。此外,儘管鰭片66的底部部分被圖示為具有基板50的單一、連續材料,但鰭片66的底部部分及/或基板50可包含單個材料或複數個材料。在此上下文中,鰭片66指在相鄰隔離區68之間延伸的部分。
閘極介電層100在鰭片66的頂表面及側壁上方,且沿著奈米結構55的頂表面、側壁、及底表面。閘電極102在閘極介電層100上方。磊晶源極/汲極區92設置在閘極介電層100及閘電極102的相對側上的鰭片66上。
第1圖進一步示出了後續圖中使用的參考橫截面。橫截面A-A'沿閘電極102的縱軸,且在例如垂直於奈米FET的磊晶源極/汲極區92之間的電流流動方向的方向上。橫截面B-B'平行於橫截面A-A',且延伸穿過複數個奈米FET的磊晶源極/汲極區92。橫截面C-C'垂直於橫截面A-A',並平行於奈米FET的鰭片66的縱軸,且在例如奈米FET的磊晶源極/汲極區92之間的電流流動方向上。為了清楚起見,後續圖參考了這些參考橫截面。
本文討論的一些實施例在使用後閘極製程形成的奈米FET的上下文中討論。在其他實施例中,可使用先閘極製程。此外,一些實施例考慮可用於平面元件 (諸如平面FET) 、或鰭式場效電晶體(fin field-effect transistor,FinFET)中的態樣。
第2圖至第31C圖為根據一些實施例的製造奈米FET的中間階段的橫截面圖。第2圖至第5圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第16A圖、第17A圖、第18A圖、第19A、第20A圖、第21A圖、第22A圖、第23A圖、第24A圖、第25A圖、第26A圖、第27A圖、第28A圖、第29A圖、第30A圖、及第31A圖示出了第1圖中所示的參考橫截面A-A'。第6B圖、第7B圖、第8B圖、第9B圖、第10B圖、第11B圖、第12B圖、第12D圖、第13B圖、第14B圖、第15B圖、第16B圖、第17B圖、第18B圖、第19B圖、第20B圖、第21B圖、第22B圖、第23B圖、第24B圖、第25B圖、第26B圖、第27B圖、第28B圖、第29B圖、第30B圖、及第31B圖示出了第1圖中所示的參考橫截面B-B'。第6C圖、第7C圖、第8C圖、第9C圖、第10C圖、第11C圖、第11D圖、第12C圖、第12E圖、第13C圖、第14C圖、第15C圖、第16C圖、第17C圖、第18C圖、第19C圖、第20C圖、第21C圖、第22C圖、第23C圖、第24C圖、第25C圖、第26C圖、第27C圖、第28C圖、第29C圖、第30C圖、及第31C圖示出了第1圖中所示的參考截面C-C'。
在第2圖中,提供了基板50。基板50可為半導體基板,諸如體半導體、或絕緣體上半導體(semiconductor-on-insulator,SOI)基板等,其可經摻雜 (例如,使用p型或n型摻雜劑) 或無摻雜。基板50可為晶圓,諸如矽晶圓。通常,SOI基板為形成在絕緣體層上的半導體材料層。絕緣體層可為例如埋入式氧化物(buried oxide,BOX)層、或氧化矽層等。絕緣體層設置在基板上,通常為矽或玻璃基板。亦可使用其他基板,諸如多層或梯度基板。在一些實施例中,基板50的半導體材料可包括矽;鍺;包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦的化合物半導體;包括矽鍺、磷砷化鎵、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵、及/或磷砷化銦鎵的合金半導體;或其組合。
基板50具有n型區50N及p型區50P。n型區50N可用於形成n型元件,諸如N型金屬-氧化物-半導體 (N-Metal-Oxide-Semiconductor;NMOS) 電晶體,例如,n型奈米FET。p型區50P可用於形成p型元件,諸如P型金屬-氧化物-半導體 (P-Metal-Oxide-Semiconductor;PMOS) 電晶體,例如,p型奈米FET。n型區50N可與p型區50P實體分開 (如分隔器20所示) ,且可在n型區50N與p型區50P之間設置任意數目的元件特徵 (例如,其他主動元件、摻雜區、或隔離結構等) 。儘管示出了一個n型區50N及一個p型區50P,但可提供任意數目的n型區50N及p型區50P。
此外,在第2圖中,在基板50上方形成多層堆疊64。多層堆疊64包括第一半導體層51A至51C (統稱為第一半導體層51) 及第二半導體層53A至53C (統稱為第二半導體層53) 的交替層。為了說明的目的,且如下文更詳細地討論的,第二半導體層53將經移除且第一半導體層51將經圖案化,以在n型區50N及p型區50P中形成奈米FET的通道區。在這種實施例中,n型區50N及p型區50P兩者中的通道區可具有相同的材料組成 (例如,矽或另一半導體材料) 且可同時形成。
在一些實施例中,第二半導體層53可經移除,且第一半導體層51可經圖案化,以在n型區50N中形成奈米FET的通道區,且第一半導體層51可經移除,且第二半導體層53可經圖案化,以在p型區50P中形成奈米FET的通道區。在一些實施例中,第一半導體層51可經移除,且第二半導體層53可經圖案化以在n型區50N中形成奈米FET的通道區,且第二半導體層53可經移除,且第一半導體層51可經圖案化,以在p型區50P中形成奈米FET的通道區。在一些實施例中,第一半導體層51可經移除,且第二半導體層53可經圖案化,以在n型區50N及p型區50P兩者中形成奈米FET的通道區。
出於說明目的,多層堆疊64被示為包括三層的第一半導體層51及三層的第二半導體層53。在一些實施例中,多層堆疊64可包括任意數目的第一半導體層51及第二半導體層53。多層堆疊64的層中的各者可使用諸如化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)、氣相磊晶(vapor phase epitaxy,VPE)、或分子束磊晶(molecular beam epitaxy,MBE)等的製程進行磊晶生長。在一些實施例中,第一半導體層51可由適合於p型奈米FET的第一半導體材料形成,諸如矽鍺等。第二半導體層53可由適合於n型奈米FET的第二半導體材料形成,諸如矽、或碳化矽等。出於說明目的,多層堆疊64被示為具有由第一半導體材料形成的最底部第一半導體層51。在一些實施例中,多層堆疊64可形成為具有由第二半導體材料形成的最底部第二半導體層53。
第一半導體材料及第二半導體材料可為彼此具有高蝕刻選擇性的材料。因此,可移除第一半導體材料的第一半導體層51而不顯著移除第二半導體材料的第二半導體層53。這允許圖案化第二半導體層53以形成奈米FET的通道區。類似地,在移除第二半導體層53且圖案化第一半導體層51以形成通道區的實施例中,可移除第二半導體材料的第二半導體層53而不顯著移除第一半導體材料的第一半導體層51。這允許圖案化第一半導體層51以形成奈米FET的通道區。
在第3圖中,鰭片66形成在基板50中,且奈米結構55形成在多層堆疊64中。在一些實施例中,奈米結構55及鰭片66可藉由在多層堆疊64及基板50中蝕刻溝槽,而分別形成在多層堆疊64及基板50中。蝕刻可為任何可接受的蝕刻製程,例如反應離子蝕刻(reactive ion etching,RIE)、中性束蝕刻(neutral beam etching,NBE)、及類似者、或其組合。蝕刻可為各向異性的。藉由蝕刻多層堆疊64形成奈米結構55,可進一步自第一半導體層51定義第一奈米結構52A至C (統稱為第一奈米結構52) ,且自第二半導體層53定義第二奈米結構54A至54C (統稱為第二奈米結構54) 。第一奈米結構52及第二奈米結構54可統稱為奈米結構55。
鰭片66及奈米結構55可藉由任何適合的方法進行圖案化。舉例而言,鰭片66及奈米結構55可使用一或複數個微影術製程進行圖案化,包括雙重圖案化或多重圖案化製程。通常,雙重圖案化或多重圖案化製程結合了光學微影術及自對準製程,允許產生具有例如比使用單個、直接微影術製程可獲得的節距更小節距的圖案。舉例而言,在一個實施例中,在基板上方形成犧牲層且使用光學微影術製程圖案化。使用自對準製程沿著經圖案化犧牲層形成間隔物。接著移除犧牲層,且剩餘的間隔物隨後可用於圖案化鰭片66及奈米結構55。
第3圖示出了n型區50N及p型區50P中的鰭片66及奈米結構55,其具有大體相同的寬度,以便於說明。在一些實施例中,n型區50N中的鰭片66及奈米結構55的寬度可大於或小於p型區50P中的鰭片66及奈米結構55的寬度。此外,儘管鰭片66及奈米結構55中的各者被示為具有始終一致的寬度,但在一些實施例中,鰭片66及/或奈米結構55可具有錐形側壁。因此,鰭片66及/或奈米結構55中的各者的寬度可在朝向基板50的方向上持續增加。在這種實施例中,垂直堆疊中的奈米結構55中的各者可具有不同的寬度,且形狀可為梯形。
第4圖中,隔離區 (又稱淺溝槽隔離(shallow trench isolation,STI)區) 68形成鄰近鰭片66。STI區68可藉由在基板50、鰭片66、及奈米結構55上方、以及在鰭片66及奈米結構55的相鄰者之間沉積絕緣材料形成。絕緣材料可為氧化物 (諸如氧化矽) 、氮化物等、或其組合,且可藉由高密度電漿CVD (high-density plasma CVD,HDP-CVD)、可流動CVD (flowable CVD,FCVD)、類似者、或其組合形成。可使用任何可接受製程形成的其他絕緣材料。在所示實施例中,絕緣材料為藉由FCVD製程形成的氧化矽。一旦形成絕緣材料,可執行退火製程。在一些實施例中,絕緣材料的形成使得多餘的絕緣材料覆蓋奈米結構55。儘管絕緣材料圖示為單個層,但一些實施例可利用複數個層。舉例而言,在一些實施例中,可沿基板50、鰭片66、及奈米結構55的表面形成襯墊 (未單獨示出) 。此後,可在襯墊上方形成如上文討論的填充材料。
接著將移除製程應用於絕緣材料,以移除奈米結構55上方的多餘絕緣材料。在一些實施例中,可使用平坦化製程,諸如化學機械研磨(chemical mechanical polish,CMP)、回蝕製程、或其組合等。平坦化製程曝光奈米結構55,使得在平坦化製程完成之後奈米結構55及絕緣材料的頂表面齊平。
接著凹陷絕緣材料以形成STI區68。絕緣材料經凹陷使得n型區50N及p型區50P中的奈米結構55及鰭片66突出於STI區68的相鄰者之間。STI區68的頂表面可具有如圖中所示的平面、凸面、凹面 (諸如碟形) 、或其組合。STI區68的頂表面可藉由適當的蝕刻形成為平的、凸的、及/或凹的。STI區68可使用可接受的蝕刻製程來凹陷,諸如對絕緣材料的材料具有選擇性的蝕刻製程,例如,以比蝕刻奈米結構55的材料更快的速率蝕刻絕緣材料的材料。如第4圖中所示,STI區68的頂表面可在鰭片66的頂表面之上。然而,在一些實施例中,STI區68的頂表面可設置成與鰭片66的頂表面齊平或在鰭片66的頂表面之下。在一些實施例中,使用稀氫氟(dilute hydrofluoric,dHF)酸移除氧化物可用於回蝕絕緣材料。
上文關於第2圖至第4圖所述的製程僅為鰭片66及奈米結構55如何形成的一個實例。在一些實施例中,鰭片66及/或奈米結構55可使用遮罩及磊晶生長製程形成。舉例而言,可在基板50的上表面上方形成介電層,且溝槽可經蝕刻穿過介電層以曝光下伏基板50。磊晶結構可在溝槽中磊晶生長,且介電層可經凹陷使得磊晶結構突出於介電層以形成鰭片66及/或奈米結構55。磊晶結構可包含上面討論的半導體材料 (諸如第一半導體材料及第二半導體材料) 的交替層。在磊晶生長磊晶結構的一些實施例中,磊晶生長材料可在生長期間經原位摻雜,這可避免先前及/或後續植入。在一些實施例中,原位摻雜及植入摻雜可一起使用。
此外,僅出於說明目的,第一半導體層51 (及由此產生的第一奈米結構52) 及第二半導體層53 (及由此產生的第二奈米結構54) 在本文中被圖示及討論為在p型區50P及n型區50N中包含相同材料。因此,在一些實施例中,第一半導體層51及第二半導體層53中的一者或兩者可為不同的材料,或在p型區50P及n型區50N中以不同的次序形成。
此外,在第4圖中,可在鰭片66、奈米結構55、及/或STI區68中形成適當的阱 (未單獨示出) 。在具有不同阱類型的實施例中,n型區50N及p型區50P的不同植入步驟可使用光阻劑或其他遮罩 (未單獨示出) 達成。舉例而言,可在n型區50N及p型區50P中的鰭片66及STI區68上方形成光阻劑。光阻劑經圖案化以曝光p型區50P。光阻劑可藉由使用旋裝技術形成,且可使用可接受的光學微影術技術來圖案化。一旦光阻劑經圖案化,則在p型區50P中執行n型雜質植入,且光阻劑可充當遮罩以防止n型雜質被植入n型區50N。n型雜質可為植入該區的磷、砷、或銻等,其濃度範圍為約10
13原子/立方公分至約10
14原子/立方公分。在植入之後,諸如藉由可接受的灰化製程移除光阻劑。
在植入p型區50P之後或之前,在p型區50P及n型區50N中的鰭片66、奈米結構55、及STI區68上方形成光阻劑或其他遮罩 (未單獨示出) 。光阻劑經圖案化以曝光n型區50N。光阻劑可藉由使用旋裝技術形成,且使用可接受的光學微影術技術進行圖案化。一旦光阻劑經圖案化,可在n型區50N中執行p型雜質植入,且光阻劑可充當遮罩以防止p型雜質被植入p型區50P中。p型雜質可為植入該區的硼、氟化硼、或銦等,濃度範圍為約10
13原子/立方公分至約10
14原子/立方公分。在植入之後,可移除光阻劑,諸如藉由可接受的灰化製程。
在n型區50N及p型區50P的植入之後,可執行退火以修復植入損傷且活化植入的p型及/或n型雜質。在一些實施例中,磊晶鰭片的生長材料可在生長期間經原位摻雜,這可避免植入。在一些實施例中,原位摻雜及植入摻雜可一起使用。
在第5圖中,虛設介電層70形成在鰭片66及/或奈米結構55上。虛設介電層70可為,例如,氧化矽、氮化矽、或其組合等。虛設介電層70可根據可接受的技術沉積或熱生長。
在虛設介電層70上方形成虛設閘極層72,在虛設閘極層72上方形成遮罩層74。虛設閘極層72可沉積在虛設介電層70上方且接著經平坦化,諸如藉由CMP。虛設閘極層72可為導電或非導電材料,且可選自包括非晶矽、多晶矽 (聚矽) 、多晶矽鍺 (聚矽鍺) 、金屬氮化物、金屬矽化物、金屬氧化物、及金屬的組。虛設閘極層72可藉由物理氣相沉積(physical vapor deposition,PVD)、CVD、濺射沉積、或用於沉積所選材料的其他技術來沉積。虛設閘極層72可由對STI區68的蝕刻具有高蝕刻選擇性的其他材料製成。
遮罩層74可沉積在虛設閘極層72上方。遮罩層74可包括例如氮化矽、或氮氧化矽等。在所示實施例中,形成單個虛設閘極層72及單個遮罩層74穿越n型區50N及p型區50P。注意,僅用於說明目的,虛設介電層70被示為僅覆蓋鰭片66及奈米結構55。在一些實施例中,可沉積虛設介電層70,使得虛設介電層70覆蓋STI區68。因此,虛設介電層70可在虛設閘極層72與STI區68之間延伸。
第6A圖至第31C圖示出了製造實施例元件中的各種額外步驟。第6A圖至第31C圖示出了n型區50N或p型區50P中的特徵。在第6A圖至第6C圖中,使用可接受的微影術及蝕刻技術圖案化遮罩層74 (見第5圖) ,以形成遮罩78。遮罩78的圖案可轉移至虛設閘極層72及虛設介電層70,以分別形成虛設閘極76及虛設閘極介電質71。虛設閘極76覆蓋奈米結構55的各自的通道區。遮罩78的圖案可用於將虛設閘極76的各者與相鄰虛設閘極76實體分開。虛設閘極76可具有垂直於各自的鰭片66及奈米結構55的縱向方向的縱向方向。
在第7A圖至第7C圖中,第一間隔物層80及第二間隔物層82分別形成在第6A圖至第6C圖所示的結構上方。第一間隔物層80及第二間隔物層82隨後經圖案化以充當用於形成自對準源極/汲極區的間隔層。在第7A圖至第7C圖中,第一間隔物層80形成在STI區68的頂表面上;奈米結構55及遮罩78的頂表面及側壁上;及虛設閘極76、虛設閘極介電質71、及鰭片66的側壁上。第二間隔物層82沉積在第一間隔物層80上方。第一間隔物層80可由氧化矽、氮化矽、或氮氧化矽等形成,使用諸如熱氧化的技術或藉由CVD、ALD、及類似者來沉積。第二間隔物層82可由具有與第一間隔物層80的材料不同的蝕刻速率的材料形成,諸如氧化矽、氮化矽、或氮氧化矽等,且可藉由CVD、或ALD等來沉積。
在形成第一間隔物層80之後且在形成第二間隔物層82之前,可執行用於淺摻雜源極/汲極(lightly doped source/drain,LDD)區 (未單獨示出) 的植入。在具有不同元件類型的實施例中,類似於上文第4圖中討論的植入,可在曝光p型區50P的同時在n型區50N上方形成諸如光阻劑的遮罩,且可將適當類型 (例如,p型) 的雜質植入p型區50P中經曝光的鰭片66及奈米結構55中。接著可移除遮罩。隨後,可在曝光n型區50N的同時在p型區50P上方形成諸如光阻劑的遮罩,且可將適當類型 (例如,n型) 的雜質植入n型區50N中經曝光的鰭片66及奈米結構55中。接著可移除遮罩。n型雜質可為前面討論的任何n型雜質,且p型雜質可為前面討論的任何p型雜質。淺摻雜源極/汲極區可具有在約1x10
15原子/立方公分至約1x10
19原子/立方公分範圍內的雜質濃度。退火可用於修復植入損傷及活化植入雜質。
在第8A圖至第8C圖中,第一間隔物層80及第二間隔物層82分別經蝕刻以形成第一間隔物81及第二間隔物83。如下文將更詳細討論的,第一間隔物81及第二間隔物83用於自對準隨後形成的源極/汲極區,以及在後續加工期間保護鰭片66及/或奈米結構55的側壁。第一間隔物層80及第二間隔物層82可使用適合的蝕刻製程來蝕刻,諸如各向同性蝕刻製程 (例如,濕式蝕刻製程) 、或各向異性蝕刻製程 (例如,乾式蝕刻製程) 等。在一些實施例中,第二間隔物層82的材料具有與第一間隔物層80的材料不同的蝕刻速率,使得第一間隔物層80可在圖案化第二間隔物層82時充當蝕刻停止層,且第二間隔物層82可在圖案化第一間隔物層80時充當遮罩。舉例而言,可使用各向異性蝕刻製程蝕刻第二間隔物層82,其中第一間隔物層80用作蝕刻停止層。第二間隔物層82的剩餘部分形成如第8B圖中所示的第二間隔物83。此後,如第8B圖及第8C圖中所示,在蝕刻第一間隔物層80的經曝光部分時,第二間隔物83用作遮罩,形成第一間隔物81。
如第8B圖中所示,第一間隔物81及第二間隔物83設置在奈米結構55及鰭片66的側壁上。如第8C圖中所示,在一些實施例中,第二間隔物層82可自鄰接遮罩78、虛設閘極76、及虛設閘極介電質71的第一間隔物層80上方移除,且第一間隔物81設置在遮罩78、虛設閘極76、及虛設閘極介電質71的側壁上。在其他實施例中,第二間隔物層82的一部分可保留在鄰接遮罩78、虛設閘極76、及虛設閘極介電質71的第一間隔物層80上方。
注意,上述揭示內容一般描述了形成間隔物及LDD區的製程。可使用其他製程及順序。舉例而言,可利用更少或額外的間隔物,可利用不同的步驟順序 (例如,可在沉積第二間隔物層82之前圖案化第一間隔物81) ,可形成及移除額外間隔物、及/或類似者。此外,可使用不同的結構及步驟來形成n型及p型元件。
在第9A圖至第9C圖中,第一凹槽86及第二凹槽87形成在奈米結構55、鰭片66、及基板50中。磊晶材料可用作源極/汲極區及/或虛設區,隨後將在第一凹槽86及第二凹槽87中形成。第一凹槽86可延伸穿過第一奈米結構52A至52C及第二奈米結構54A至54C,且進入鰭片66及基板50中。在一些實施例中,STI區68的頂表面可與第一凹槽86的底表面齊平。在一些實施例中,STI區68的頂表面可在第一凹槽86的底表面之上或之下。第二凹槽87可延伸穿過第一奈米結構52A至52C及第二奈米結構54A至54C,且進入鰭片66及基板50中,深度大於第一凹槽86。第二凹槽87的底表面可設置在第一凹槽86的底表面及STI區68的頂表面之下。
第一凹槽86及第二凹槽87可藉由使用各向異性蝕刻製程 (諸如RIE、或NBE等) 蝕刻奈米結構55、鰭片66、及基板50來形成。在用於形成第一凹槽86及第二凹槽87的蝕刻製程期間,第一間隔物81、第二間隔物83、及遮罩78遮蔽奈米結構55、鰭片66、及基板50的部分。可使用單個蝕刻製程或複數個蝕刻製程來蝕刻奈米結構55、鰭片66、及基板50的各個層。定時蝕刻製程可用於在第一凹槽86及第二凹槽87達到所需深度之後停止蝕刻。第二凹槽87可藉由用於蝕刻第一凹槽86的相同製程以及在蝕刻第一凹槽86之前或之後的額外蝕刻製程來蝕刻。在一些實施例中,在執行第二凹槽87的額外蝕刻製程時,可遮蔽對應於第一凹槽86的區。
第10A圖至第10C圖中,由第一半導體材料 (例如,第一奈米結構52) 藉由第一凹槽86及第二凹槽87曝光形成的多層堆疊64的層的側壁的部分,經蝕刻以在n型區50N及p型區50P中形成側壁凹槽88。儘管鄰接側壁凹槽88的第一奈米結構52的側壁在第10C圖中示出為直的,但側壁可為凹的或凸的。可使用各向同性蝕刻製程 (諸如濕式蝕刻等) 蝕刻側壁。在第二奈米結構54包括例如矽或碳化矽、且第一奈米結構52包括例如矽鍺的實施例中,可使用氟化氫、或另一基於氟的蝕刻劑等的濕式或乾式蝕刻製程來蝕刻n型區50N及p型區50P中的第一奈米結構52的側壁。
在第11A圖至第11D圖中,第一內間隔物90形成在側壁凹槽88中。第一內間隔物90可藉由在第10A圖至第10C圖中所示的結構上方沉積內間隔物層 (未單獨示出) 形成。第一內間隔物90充當隨後形成的源極/汲極區與閘極結構之間的隔離特徵。如下文將更詳細地討論的,源極/汲極區將形成在第一凹槽86及第二凹槽87中,而第一奈米結構52將替換為相應的閘極結構。
內間隔物層可藉由共形沉積製程 (諸如CVD、或ALD等) 沉積。內間隔物層可包含諸如氮化矽或氮氧化矽的材料,儘管可利用諸如具有小於約3.5的k值的低介電常數 (低k) 材料的任何適合材料。接著可各向異性地蝕刻內間隔層以形成第一內間隔物90。儘管第一內間隔物90的外側壁被圖示為與第二奈米結構54的側壁齊平,第一內間隔物90的外側壁可延伸超出第二奈米結構54的側壁或自第二奈米結構54的側壁凹陷。
此外,儘管第一內間隔物90的外側壁在第11C圖中被圖示為直的,但第一內間隔物90的外側壁可為凹的或凸的。作為實例,第11D圖示出了一個實施例,其中第一奈米結構52的側壁為凹的,第一內間隔物90的外側壁為凹的,且第一內間隔物90自第二奈米結構54的側壁凹陷。內間隔物層可藉由各向異性蝕刻製程來蝕刻,諸如RIE、或NBE等。第一內間隔物90可用於防止後續蝕刻製程 (諸如用於形成閘極結構的蝕刻製程) 損壞後續形成的源極/汲極區 (諸如磊晶源極/汲極區92,下文將參考第12A圖至第12E圖討論) 。
第12A圖至第12E圖中,第一磊晶材料91形成在第二凹槽87中,且磊晶源極/汲極區92形成在第一凹槽86及第二凹槽87中。在一些實施例中,第二凹槽87中的第一磊晶材料91可為犧牲材料,隨後將其移除以形成背側通孔 (諸如背側通孔130,下面參考第26A圖至第26C圖討論) 。在一些實施例中,磊晶源極/汲極區92可在第二奈米結構54上施加應力,從而提高效能。
如第12C圖中所示,磊晶源極/汲極區92形成在第一凹槽86及第二凹槽87中,使得各個虛設閘極76設置在磊晶源極/汲極區92的各自相鄰對之間。在一些實施例中,第一間隔物81用於將磊晶源極/汲極區92與虛設閘極76分開,且第一內間隔物90用於將磊晶源極/汲極區92與第一奈米結構52分開適當的側向距離,以便磊晶源極/汲極區92不會使所得奈米FET的後續形成的閘極短路。
可生長第一磊晶材料91,使得第一磊晶材料91的頂表面與第一凹槽86的底表面 (見第11A圖至第11D圖) 及STI區68的頂表面齊平。然而,在一些實施例中,第一磊晶材料91的頂表面可設置在STI區68的頂表面之上或之下。第一磊晶材料91可使用諸如CVD、ALD、VPE、或MBE等的製程在第二凹槽87中磊晶生長。第一磊晶材料91可包括任何可接受的材料,諸如矽鍺等。第一磊晶材料91可由對基板50、磊晶源極/汲極區92、及介電層 (諸如STI區68及下面參考第24A圖至第24C圖討論的第二介電層125) 的材料具有高蝕刻選擇性的材料形成。因此,可移除第一磊晶材料91且用背側通孔替換,而無需顯著移除磊晶源極/汲極區92、基板50、或STI區68。
n型區50N (例如,NMOS區) 中的磊晶源極/汲極區92可藉由遮蔽p型區50P (例如,PMOS區) 形成。接著,在n型區50N中的第一凹槽86及第二凹槽87中磊晶生長磊晶源極/汲極區92。磊晶源極/汲極區92可包括適合於n型奈米FET的任何可接受材料。舉例而言,若第二奈米結構54為矽,則磊晶源極/汲極區92可包括在第二奈米結構54上施加拉伸應變的材料,諸如矽、碳化矽、摻磷碳化矽、或磷化矽等。磊晶源極/汲極區92可具有自奈米結構55的各自上表面提升的表面,且可具有小平面。
p型區50P (例如,PMOS區) 中的磊晶源極/汲極區92可藉由遮蔽n型區50N (例如,NMOS區) 形成。接著,在p型區50P中的第一凹槽86及第二凹槽87中磊晶生長磊晶源極/汲極區92。磊晶源極/汲極區92可包括適合於p型奈米FET的任何可接受材料。舉例而言,若第二奈米結構54為矽,則磊晶源極/汲極區92可包含對第二奈米結構54施加壓縮應變的材料,諸如矽鍺、摻硼矽鍺、鍺、或鍺錫等。磊晶源極/汲極區92亦可具有自奈米結構55的各自表面提升的表面,且可具有小平面。
磊晶源極/汲極區92、第一奈米結構52、第二奈米結構54、鰭片66及/或基板50可植入摻雜劑以形成源極/汲極區,類似於先前討論的形成淺摻雜源極/汲極區的製程,接著進行退火。源極/汲極區可具有在約1x10
19原子/立方公分與約1x10
21原子/立方公分之間的雜質濃度。源極/汲極區的n型及/或p型雜質可為先前討論的任何雜質。在一些實施例中,磊晶源極/汲極區92可在生長期間經原位摻雜。
由於用於在n型區50N及p型區50P中形成磊晶源極/汲極區92的磊晶製程,磊晶源極/汲極區92的上表面具有側向向外擴展超出奈米結構55側壁的小平面。在一些實施例中,這些小平面導致同一奈米FET的鄰接磊晶源極/汲極區92合併,如第12D圖中所示。在其他實施例中,如第12B圖中所示,在磊晶製程完成之後,鄰接磊晶源極/汲極區92保持分開。在第12B圖及第12D圖中所示的實施例中,可形成延伸至STI區68的頂表面的第一間隔物81,從而阻擋磊晶生長。在一些實施例中,可調整用於形成第一間隔物81的間隔物蝕刻,以移除間隔物材料且允許磊晶生長區延伸至STI區68的表面。
磊晶源極/汲極區92可包含一或複數個半導體材料層。舉例而言,磊晶源極/汲極區92可包含第一半導體材料層92A、第二半導體材料層92B、及第三半導體材料層92C。任何數目的半導體材料層可用於磊晶源極/汲極區92。第一半導體材料層92A、第二半導體材料層92B、及第三半導體材料層92C中的各者可由不同的半導體材料形成,且可摻雜至不同的摻雜劑濃度。在一些實施例中,第一半導體材料層92A可具有小於第二半導體材料層92B且大於第三半導體材料層92C的摻雜劑濃度。在磊晶源極/汲極區92包括三個半導體材料層的實施例中,可以沉積第一半導體材料層92A,第二半導體材料層92B可沉積在第一半導體材料層92A上方,且第三半導體材料層92C可沉積在第二半導體材料層92B上方。
第12E圖示出了一個實施例,其中第一奈米結構52的側壁為凹的,第一內間隔物90的外側壁為凹的,且第一內間隔物90自第二奈米結構54的側壁凹陷。如第12E圖中所示,磊晶源極/汲極區92可形成為與第一內間隔物90接觸,且可延伸超過第二奈米結構54的側壁。
在第13A圖至第13C圖中,第一層間介電(interlayer dielectric,ILD)層96分別沉積在第12A圖至第12C圖中所示的結構上方。第一ILD 96可由介電材料形成,且可藉由任何適合的方法沉積,諸如CVD、電漿增強CVD (plasma-enhanced CVD,PECVD)、或FCVD。介電材料可包括磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、或無摻雜矽酸鹽玻璃(undoped silicate glass,USG)等。可使用藉由任何可接受製程形成的其他絕緣材料。在一些實施例中,接觸蝕刻停止層(contact etch stop layer,CESL) 94設置在第一ILD 96與磊晶源極/汲極區92、遮罩78、第一間隔物81、第二間隔物83、及STI區68之間。CESL 94可包含介電材料,諸如氮化矽、氧化矽、或氮氧化矽等,具有與上覆第一ILD 96的材料不同的蝕刻速率。
在第14A圖至第14C圖中,可執行諸如CMP的平坦化製程,以使第一ILD 96及CESL 94的頂表面與虛設閘極76或遮罩78的頂表面齊平。平坦化製程亦可移除虛設閘極76上的遮罩78、及第一間隔物81沿遮罩78的側壁的部分。在平坦化製程之後,在製程變化範圍內,虛設閘極76、第一間隔物81、第一ILD 96、及CESL 94的頂表面可彼此齊平。因此,虛設閘極76的頂表面經由第一ILD 96曝光。在一些實施例中,遮罩78可保留,在這種情況下,平坦化製程將第一ILD 96的頂表面與遮罩78、第一間隔物81、及CESL 94的頂表面齊平。
在第15A圖至第15C圖中,在一或複數個蝕刻步驟中移除虛設閘極76、及遮罩78 (若存在) ,形成第三凹槽98。亦移除第三凹槽98中的虛設閘極介電質71的部分。在一些實施例中,藉由各向異性乾式蝕刻製程移除虛設閘極76及虛設閘極介電質71。舉例而言,蝕刻製程可包括使用反應氣體 (多種) 的乾式蝕刻製程,反應氣體以比蝕刻第一ILD 96、CESL 94、或第一間隔物81更快的速率選擇性蝕刻虛設閘極76。第三凹槽98中的各者曝光及/或覆蓋奈米結構55的部分,其在隨後完成的奈米FET中充當通道區。用作通道區的奈米結構55的部分設置在磊晶源極/汲極區92的相鄰對之間。在移除期間,當蝕刻虛設閘極76時,虛設閘極介電質71可用作蝕刻停止層。接著,可在移除虛設閘極76之後移除虛設閘極介電質71。
在第16A圖至第16C圖中,第一奈米結構52經移除,延伸第三凹槽98。第一奈米結構52可藉由使用對第一奈米結構52的材料具有選擇性的蝕刻劑執行各向同性蝕刻製程 (諸如濕式蝕刻等) 來移除,而與第一奈米結構52相比,第二奈米結構54、基板50、STI區68、第一ILD 96、CESL 94、第一間隔物81、及第一內間隔物90保持相對未蝕刻。在第二奈米結構54包括例如Si或SiC、且第一奈米結構52包括例如SiGe的實施例中,四甲基氫氧化銨(Tetramethylammonium Hydroxide;TMAH)、或氫氧化銨(NH
4OH)等可用於移除第一奈米結構52。
在第17A圖至第17C圖中,形成用於替換閘極的閘極介電層100及閘電極102。閘極介電層100共形地沉積在第三凹槽98中。閘極介電層100可形成在第二奈米結構54的頂表面、側壁、及底表面上。閘極介電層100亦可沉積在第一ILD 96、CESL 94、第一間隔物81、及STI區68的頂表面上。
根據一些實施例,閘極介電層100包含一或複數個介電層,諸如氧化物、金屬氧化物、類似者、或其組合。舉例而言,在一些實施例中,閘極介電層100可包含氧化矽層及氧化矽層上方的金屬氧化物層。在一些實施例中,閘極介電層100包括高k介電材料,且在這些實施例中,閘極介電層100可具有大於約7.0的k值,且可包括金屬氧化物或鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛、及其組合的矽酸鹽。閘極介電層100的結構在n型區50N及p型區50P中可相同或不同。閘極介電層100的形成方法可包括分子束沉積(molecular-beam deposition,MBD)、ALD、或PECVD等。
閘電極102沉積在閘極介電層100上方,且填充第三凹槽98的剩餘部分。閘電極102可包括含金屬材料,諸如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、其組合、或其多層。舉例而言,儘管在第17A圖及第17C圖中示出為單層閘電極102,但閘電極102可包含任意數目的襯墊層、任意數目的功函數調諧層、及填充材料。構成閘電極102的層的任何組合可沉積在第二奈米結構54的鄰接層之間。
n型區50N及p型區50P中的閘極介電層100的形成可同時發生,使得各個區中的閘極介電層100由相同的材料形成,且閘電極102的形成可同時發生,使得各個區中的閘電極102由相同的材料形成。在一些實施例中,各個區中的閘極介電層100可藉由不同的製程形成,使得閘極介電層100可為不同的材料及/或具有不同數目的層,及/或各個區中的閘電極102可藉由不同的製程形成,使得閘電極102可為不同的材料及/或具有不同數目的層。當使用不同的製程時,可使用各種遮罩步驟來遮蔽及曝光適當的區。
在填充第三凹槽98之後,可執行諸如CMP的平坦化製程,以移除閘極介電層100的多餘部分及閘電極102的材料,其中多餘部分在第一ILD 96、第一間隔物81、及CESL 94的上表面上方。閘電極102及閘極介電層100的材料的剩餘部分由此形成所得奈米FET的替換閘極結構。閘電極102及閘極介電層100可統稱為「閘極結構」。
在第18A圖至第18C圖中,閘極結構 (包括閘極介電層100及相應的上覆閘電極102) 經凹陷,使得直接在各個閘極結構的上方及在第一間隔物81的相對部分之間形成凹槽。在凹槽中填充包括一或多層的介電材料 (諸如氮化矽、或氮氧化矽等) 的閘極遮罩104,接著進行平坦化製程,以移除在第一ILD 96、CESL 94、及第一間隔物81上方延伸的介電材料的多餘部分。隨後形成的閘極觸點 (諸如閘極觸點114,下面參考第20A圖及第20C圖討論) 穿越閘極遮罩104以接觸經凹陷閘電極102的上表面。
如第18A圖至第18C圖中進一步所示,第二ILD 106沉積在第一ILD 96、CESL 94、及閘極遮罩104上方。在一些實施例中,第二ILD 106為藉由FCVD形成的可流動膜。在一些實施例中,第二ILD 106由諸如PSG、BSG、BPSG、或USG等的介電材料形成,且可藉由諸如CVD、或PECVD等的任何適合的方法沉積。
在第19A圖至第19C圖中,蝕刻第二ILD 106、第一ILD 96、CESL 94、及閘極遮罩104以形成第四凹槽108,曝光磊晶源極/汲極區92及/或閘極結構的表面。第四凹槽108可藉由使用各向異性蝕刻製程 (諸如RIE、或NBE等) 蝕刻而形成。在一些實施例中,第四凹槽108可使用第一蝕刻製程蝕刻穿過第二ILD 106及第一ILD 96;可使用第二蝕刻製程蝕刻穿過閘極遮罩104;且可使用第三蝕刻製程蝕刻穿過CESL 94。可在第二ILD 106上方形成諸如光阻劑的遮罩且進行圖案化,以自第一蝕刻製程及第二蝕刻製程遮蔽第二ILD 106的部分。在一些實施例中,蝕刻製程可過度蝕刻,且因此,第四凹槽108可延伸至磊晶源極/汲極區92及/或閘極結構。第四凹槽108的底表面可與磊晶源極/汲極區92及/或閘極結構的頂表面齊平 (例如,在同一位準上、或與基板50的距離相同) 、或低於這些頂表面 (例如,更靠近基板50) 。儘管第19C圖將第四凹槽108示為在同一橫截面曝光磊晶源極/汲極區92及閘極結構,但在一些實施例中,磊晶源極/汲極區92及閘極結構可在不同橫截面中曝光,從而降低隨後形成的觸點短路的風險。
在形成第四凹槽108之後,在磊晶源極/汲極區92上方形成第一矽化物區110。在一些實施例中,第一矽化物區110藉由首先沉積能夠與下伏磊晶源極/汲極區92的半導體材料 (例如,矽、矽鍺、或鍺等) 反應以形成矽化物或鍺化物區的金屬 (未單獨示出) 來形成。金屬可包括鎳、鈷、鈦、鉭、鉑、鎢、其他貴金屬、其他難熔金屬、稀土金屬或其合金。可在磊晶源極/汲極區92的經曝光部分上方沉積金屬,接著可執行熱退火製程以形成第一矽化物區110。接著藉由例如蝕刻製程移除經沉積金屬的未反應部分。儘管第一矽化物區110被稱為矽化物區,但第一矽化物區110亦可為鍺化物區或矽鍺化物區 (例如,包含矽及鍺的區) 等。在一個實施例中,第一矽化物區110包含矽鈦化物,且厚度範圍為約2 奈米至約10 奈米。
在第20A圖至第20C圖中,源極/汲極觸點112及閘極觸點114 (亦稱為觸點插座) 形成在第四凹槽108中。源極/汲極觸點112及閘極觸點114可各包含一或多層,諸如阻障層、擴散層、及填充材料。舉例而言,在一些實施例中,源極/汲極觸點112及閘極觸點114各包括阻障層及導電材料。源極/汲極觸點112及閘極觸點114各電耦合至下伏導電特徵 (例如,在所示實施例中,在磊晶源極/汲極區92上方的閘電極102或第一矽化物區110) 。閘極觸點114電耦合至閘電極102,且源極/汲極觸點112電耦合至磊晶源極/汲極區92上方的第一矽化物區110。阻障層可包括鈦、氮化鈦、鉭、或氮化鉭等。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、或鎳等。可執行諸如CMP的平坦化製程以移除源極/汲極觸點112及閘極觸點114的多餘部分,這些多餘部分在第二ILD 106的頂表面上方。
磊晶源極/汲極區92、第二奈米結構54、及閘極結構 (包括閘極介電層100及閘電極102) 可統稱為電晶體結構109。第一互連結構 (諸如下文關於第21A圖至第21C圖討論的前側互連結構120) 可形成在電晶體結構109的前側上方,且第二互連結構 (諸如下文關於第27A圖至第27C圖討論的背側互連結構140) 可形成在電晶體結構109的背側上方。儘管電晶體結構109被描述為包括奈米FET,但其他實施例可包括具有不同類型電晶體 (例如,平面FET、FinFET、或薄膜電晶體(thin film transistor,TFT)等) 的電晶體結構109。
儘管第20A圖至第20C圖示出了延伸至磊晶源極/汲極區92中的各者的源極/汲極觸點112,但可自磊晶源極/汲極區92的某些者中省略源極/汲極觸點112。舉例而言,如下文更詳細地解釋的,導電特徵 (例如,背側通孔或電源軌) 可隨後經由一或複數個磊晶源極/汲極區92的背側附接。對於這些特定的磊晶源極/汲極區92,源極/汲極觸點112可省略,或可為未電連接至任何上覆導電線 (諸如下面參考第21A圖至第21C圖討論的第一導電特徵122) 的虛設觸點。
第21A圖至第27C圖示出了在電晶體結構109上形成前側互連結構及背側互連結構的中間步驟。前側互連結構及背側互連結構可各包含電連接至電晶體結構109的導電特徵 (例如,奈米FET) 。在第21A圖至第27C圖中,以「A」結尾的圖示出了沿第1圖的線A-A'的橫截面圖,以「B」結尾的圖示出了沿第1圖的線B-B'的橫截面圖,以「C」結尾的圖示出了沿第1圖的線C-C'的橫截面圖。第21A圖至第27C圖中描述的製程步驟可應用於n型區50N及p型區50P兩者。如上所述,背側導電特徵 (例如,背側通孔或電源軌) 可連接至磊晶源極/汲極區92中的一或多者。因此,源極/汲極觸點112可自磊晶源極/汲極區92中任選地省略。
在第21A圖至第21C圖中,前側互連結構120形成在第二ILD 106上。前側互連結構120可稱為前側互連結構,因為它形成在電晶體結構109上 (例如,電晶體結構的與在其上形成電晶體結構109的基板50相對的一側) 。
前側互連結構120可包含形成在一或複數個堆疊的第一介電層124中的第一導電特徵122的一或多層。堆疊的第一介電層124中的各者可包含介電材料,諸如低k介電材料、超低k (extra low-k,ELK)介電材料等。第一介電層124可使用適當的製程 (諸如,CVD、ALD、PVD、或PECVD等) 沉積。
第一導電特徵122可包含導電線及導電通孔,互連導電線的層。導電通孔可延伸穿過第一介電層124的各自一者,以在導電線的層之間提供垂直連接。第一導電特徵122可藉由任何可接受的製程形成,諸如鑲嵌製程、或雙重鑲嵌製程等。
在一些實施例中,可使用鑲嵌製程形成第一導電特徵122,其中利用光學微影術及蝕刻技術的組合來圖案化各自的第一介電層124,以形成對應於第一導電特徵122的所需圖案的溝槽。可以沉積可選的擴散阻障及/或可選的黏合層,且接著用導電材料填充溝槽。用於阻障層的適合材料包括鈦、氮化鈦、氧化鈦、鉭、氮化鉭、氧化鈦、或其組合等,且用於導電材料的適合材料包括銅、銀、金、鎢、鋁、鈷、鎢、釕、或其組合等。在一個實施例中,可藉由沉積銅或銅合金的種晶層,且藉由電鍍填充溝槽,來形成第一導電特徵122。CMP製程等可用於自各自的第一介電層124的表面移除多餘的導電材料,且將第一介電層124及第一導電特徵122的表面平坦化以用於後續加工。
第21A圖至第21C圖示出了前側互連結構120中的四層第一導電特徵122及第一介電層124。然而,應理解,前側互連結構120可包含設置在任意數目的第一介電層124中的任意數目的第一導電特徵122。前側互連結構120可電連接至閘極觸點114及源極/汲極觸點112以形成功能電路。在一些實施例中,由前側互連結構120形成的功能電路可包含邏輯電路、記憶體電路、或影像感測電路等。
在第22A圖至第22C圖中,載體基板180藉由第一鍵結層182A及第二鍵結層182B (統稱為鍵結層182) 結合至前側互連結構120的頂表面。載體基板180可為玻璃載體基板、陶瓷載體基板、或晶圓 (例如,矽晶圓) 等。載體基板180可在後續加工步驟期間及在完成的元件中提供結構支撐。
在各種實施例中,載體基板180可使用適合的技術 (諸如介電-介電鍵結等) 鍵結至前側互連結構120。介電-介電鍵結可包含在前側互連結構120上沉積第一鍵結層182A。在一些實施例中,第一鍵結層182A包含藉由CVD、ALD、或PVD等沉積的氧化矽 (例如,高密度電漿(high-density plasma,HDP)氧化物等) 。第二鍵結層182B同樣可為使用例如CVD、ALD、PVD、或熱氧化等進行鍵結之前,在載體基板180的表面上形成的氧化物層。其他適合的材料可用於第一鍵結層182A及第二鍵結層182B。
介電-介電鍵結製程可進一步包括對第一鍵結層182A及第二鍵結層182B中的一或多者施加表面處理。表面處理可包括電漿處理。電漿處理可在真空環境中執行。在電漿處理之後,表面處理可進一步包括清洗製程 (例如,使用去離子水等的沖洗) ,其可應用於鍵結層182中的一或多者。接著,將載體基板180與前側互連結構120對準,且將兩者彼此按壓,以啟動載體基板180與前側互連結構120的預鍵結。預鍵結可在室溫下進行 (例如,在約21°C與約25°C之間) 。在預鍵結之後,可藉由例如將前側互連結構120及載體基板180加熱至約170°C的溫度來應用退火製程。
進一步地在第22A圖至第22C圖中,在將載體基板180鍵結至前側互連結構120之後,可翻轉元件,使得電晶體結構109的背側朝上。電晶體結構109的背側可指與電晶體結構109的前側相對的一側。
在第23A圖至第23C圖中,對基板50的背側應用了減薄製程。減薄製程可包含平坦化製程 (例如,機械研磨、或CMP等) 、蝕刻製程、或其組合等。減薄製程可曝光與前側互連結構120相對的第一磊晶材料91的表面。此外,在減薄製程後,基板50的一部分可保留在電晶體結構109上方。如第23A圖至第23C圖中所示,基板50、第一磊晶材料91、STI區68、及鰭片66的背側表面可在減薄製程後彼此齊平。
在第24A圖至第24C圖中,移除鰭片66及基板50的剩餘部分,且用第二介電層125替換。可使用適合的蝕刻製程,諸如各向同性蝕刻製程 (例如,濕式蝕刻製程) 、或各向異性蝕刻製程 (例如,乾式蝕刻製程) 等。蝕刻製程可為對鰭片66及基板50的材料具有選擇性的製程 (例如,以比蝕刻STI區68、閘極介電層100、磊晶源極/汲極區92、第一磊晶材料91、及第一內間隔物90的材料更快的速率蝕刻鰭片66及基板50的材料) 中的一者。在蝕刻鰭片66及基板50之後,可曝光STI區68、閘極介電層100、磊晶源極/汲極區92、第一磊晶材料91、及第一內間隔物90的表面。
接著將第二介電層125沉積在電晶體結構109的背側,經由移除鰭片66及基板50而形成的凹槽中。第二介電層125可沉積在STI區68、閘極介電層100、磊晶源極/汲極區92、第一磊晶材料91、及第一內間隔物90上方。第二介電層125可實體接觸STI區68、閘極介電層100、磊晶源極/汲極區92、第一磊晶材料91、及第一內間隔物90的表面。第二介電層125可大體上類似於如上文關於第18A圖至第18C圖所述的第二ILD 106。舉例而言,第二介電層125可由類似材料形成,且使用與第二ILD 106類似的製程。如第24A圖至第24C圖中所示,CMP製程等可用於移除第二介電層125的材料,使得第二介電層125的頂表面與STI區68及第一磊晶材料91的頂表面齊平。
在第25A圖至第25C圖中,第一磊晶材料91經移除以形成第五凹槽128,且第二矽化物區129形成在第五凹槽128中。第一磊晶材料91可藉由適合的蝕刻製程移除,蝕刻製程可為各向同性蝕刻製程,諸如濕式蝕刻製程。蝕刻製程可對第一磊晶材料91的材料具有高蝕刻選擇性。因此,可移除第一磊晶材料91,而無需顯著移除第二介電層125、STI區68、或磊晶源極/汲極區92。第五凹槽128可曝光STI區68的側壁、磊晶源極/汲極區92的背側表面、及第二介電層125的側壁。
接著第二矽化物區129可形成在磊晶源極/汲極區92背側上的第五凹槽128中。第二矽化物區129可類似於上文關於第19A圖至第19C圖所述的第一矽化物區110。舉例而言,第二矽化物區129可由類似材料形成,且使用與第一矽化物區110類似的製程。
在第26A圖至第26C圖中,背側通孔130形成在第五凹槽128中。背側通孔130可延伸穿過第二介電層125及STI區68,且可經由第二矽化物區129電耦合至磊晶源極/汲極區92。背側通孔130可類似於如上文關於第20A圖至第20C圖所述的源極/汲極觸點112。舉例而言,背側通孔130可由類似材料形成,且使如源極/汲極觸點112的類似製程。背側通孔130可包括銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或釕等。可執行諸如CMP的平坦化製程,以移除背側通孔130的多餘部分,這些多餘部分在STI區68及第二介電層125的頂表面上方。
在第27A圖至第27C圖中,形成第一導電線132及第三介電層134。第一導電線132及第三介電層134可形成在背側通孔130、第二介電層125、及STI區68上方。第三介電層134可由與第二ILD 106相同或類似的材料以及方式形成,如上文關於第18A圖至第18C圖所述。
第一導電線132形成在第三介電層134中。形成第一導電線132可包括例如使用光學微影術及蝕刻製程組合,在第三介電層134中圖案化凹槽。第三介電層134中的凹槽的圖案可對應於第一導電線132的圖案。接著藉由在凹槽中沉積導電材料,來形成第一導電線132。在一些實施例中,第一導電線132包含金屬層,金屬層可為單層或複合層,包括含不同材料形成的複數個子層。在一些實施例中,第一導電線132包含銅、鋁、鈷、鎢、鈦、鉭、或釕等。在用導電材料填充凹槽之前,可沉積可選的擴散阻障層及/或可選的黏合層。用於阻障層/黏合層的適合材料包括鈦、氮化鈦、氧化鈦、鉭、氮化鉭、或氧化鈦等。第一導電線132可使用例如CVD、ALD、PVD、或電鍍等形成。第一導電線132經由背側通孔130及第二矽化物區129電耦合至磊晶源極/汲極區92。可執行平坦化製程 (例如,CMP、研磨、或回蝕等) 以移除形成在第三介電層134上方的第一導電線132的多餘部分。
在一些實施例中,第一導電線132為背側電源軌,其為將磊晶源極/汲極區92電連接至參考電壓、或供應電壓等的導電線。藉由將電源軌置放在所得半導體晶片的背側而非半導體晶片的前側,可實現優點。舉例而言,藉由包括前側互連結構120及背側互連結構140,電晶體結構109中產生的熱量可經由前側互連結構120及背側互連結構140自電晶體結構109的兩側散熱。具體而言,可經由前側互連結構120的第一導電特徵122且經由背側互連結構140的第一導電線132及第二導電特徵136散熱。
藉由將電源軌移動至電晶體結構109的背側,可減小前側互連結構120的厚度T
1。與常規前側互連結構相比,前側互連結構120的厚度T
1可減小至少50%,且前側互連結構120的厚度T
1可在約0.5 微米至約2 微米的範圍內。前側互連結構120中的互連層的數目可減少至約6個,而常規前側互連結構可具有約10個互連層。減小前側互連結構120的厚度改善了經由前側互連結構120的散熱,且可達成經由前側互連結構120的散熱約為經由傳統前側互連結構散熱的150%。
此外,背側互連結構140的導電特徵可具有大於前側互連結構120的導電特徵的寬度 (諸如至少為前側互連結構120的導電特徵的寬度的約兩倍) 。背側互連結構140的厚度T
2可相同於或小於前側互連結構120的厚度。舉例而言,前側互連結構120的導電特徵可具有自約15 奈米至約45 奈米範圍內的最小線寬,而背側互連結構140的導電特徵可具有在約30 奈米至約60 奈米範圍內的最小線寬。背側互連結構140的厚度T
2可在約0.5微米至約1 微米的範圍內。經由背側互連結構140散發的熱量可甚至大於經由前側互連結構120散發的熱量。舉例而言,經由背側互連結構140散發的熱量可為經由常規前側互連結構散發的熱量的約300%。因此,與常規元件相比,經由前側互連結構120及背側互連結構140的整體散熱可改善約450%。
此外,奈米FET的閘極密度及/或前側互連結構120的互連密度可增大。半導體晶片的背側可容納更寬的電源軌、降低電阻且提高奈米FET的功率傳輸效率。舉例而言,第一導電線132的寬度可為前側互連結構120的第一層級導電線 (例如,第一導電特徵122) 的寬度的至少兩倍。
背側互連結構140的剩餘部分形成在第三介電層134及第一導電線132上方。背側互連結構140可稱為背側互連結構,因為它形成在電晶體結構109的背側上 (例如,電晶體結構109上形成主動元件的一側的相對側) 。背側互連結構140可包含第三介電層134及第一導電線132。
背側互連結構140的剩餘部分可包含材料,且使用與前側互連結構120相同或類似的製程形成,如上文關於第21A圖至第21C圖所述。具體而言,背側互連結構140可包含在第四介電層138中形成的第二導電特徵136的堆疊層。第二導電特徵136可包括路由線 (例如,用於路由至隨後形成的接觸墊及外部連接器,及自隨後形成的接觸墊及外部連接器路由) 。第二導電特徵136可進一步經圖案化以包括一或複數個嵌入式被動元件,諸如電阻器、電容器、或電感器等。嵌入式被動元件可與第一導電線132 (例如,電源軌) 整合,以在奈米FET的背側上提供電路 (例如,電源電路) 。
在第28A圖至第28C圖中,執行載體基板去鍵結以自前側互連結構120拆離 (或「去鍵結」) 載體基板180。在一些實施例中,去鍵結包括投射光,諸如鍵結層182上的雷射或紫外(ultraviolet,UV)光,使得鍵結層182在光的熱量下分解,且可移除載體基板180。
在第29A圖至第29C圖中,翻轉第28A圖至第28C圖的結構,將散熱器160附接至前側互連結構120,將第一基板170附接至背側互連結構140,且將第二基板190附接至第一基板170。如第29A圖至第29C圖中所示,散熱器160可附接至第一介電層124及第一導電特徵122。在一些實施例中,散熱器160可包含諸如矽、玻璃、金屬、或聚合物等的材料。散熱器160可藉由熔融鍵結等鍵結至前側互連結構120。在一些實施例中,散熱器160可經由介電-介電鍵結,鍵結至前側互連結構120,而不使用任何黏合劑材料 (例如,晶片附接膜) 。鍵結可包括預鍵結及退火。在預鍵結期間,施加小的壓力以將散熱器160壓在前側互連結構120上。預鍵結在低溫下執行,諸如室溫 (例如,在約15°C至約30°C的溫度範圍內) 。在一些實施例中,諸如原生氧化物的氧化物形成在散熱器160及前側互連結構120彼此面對的表面處,且用於鍵結。接著在隨後的退火步驟中提高鍵結強度,其中前側互連結構120及散熱器160在高溫下退火,諸如在約100°C至約400°C的溫度範圍內。在退火之後,形成鍵結,諸如熔融鍵,將前側互連結構120鍵結至散熱器160。舉例而言,所述鍵結可為前側互連結構120及散熱器160之間的共價鍵。經由熔融鍵將散熱器160直接鍵結至前側互連結構120,可降低散熱器160與前側互連結構120之間的熱阻,這可提高散熱器160的冷卻能力。將散熱器160直接鍵結至前側互連結構120,可進一步減少用於將散熱器160附接至前側互連結構120的熱介面材料,從而降低成本。
在一些實施例中,散熱器160可經由黏合劑附接至前側互連結構120。散熱器160可經由黏合劑結合介電-介電鍵結、或代替介電-介電鍵結附接至前側互連結構120。黏合劑可為熱介面材料(thermal interface material,TIM)或其他黏合劑。TIM可為具有良好導熱性的黏合劑材料。黏合劑可為任何適合的黏合劑、環氧樹脂、或晶片附接膜(die attach film,DAF)等。黏合劑可沉積在散熱器160與任何第一介電層124及/或第一導電特徵122之間。
如第29A圖至第29C圖中所示,散熱器160可包括通道161及導熱鰭片163,形成於散熱器160的與前側互連結構120相對的表面上。通道161可藉由機械製程 (諸如機械模切等) 、激光切割、可接受的光學微影術及蝕刻技術等來形成。通道161及導熱鰭片163可用於改善散熱器160的熱傳遞。
第一基板170可經由第一導電連接器162附接至背側互連結構140。第一基板170可包括諸如矽的半導體基板,經摻雜或無摻雜,或絕緣體上半導體(semiconductor-on-insulator,SOI)基板的主動層。第一基板170可包括其他半導體材料,諸如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP;或其組合。亦可使用其他基板,諸如多層或梯度基板。在一些實施例中,第一基板170可為中介層基板。在第一基板170為中介層基板的實施例中,第一基板170可不含主動元件,且可提供背側互連結構140與第二基板190之間的互連。第一基板170可包括可選被動元件。
第一基板170可包括導電通孔178 (有時稱為穿矽通孔或穿基板通孔(through substrate via,TSV)) 、鍵結墊174、鍵結墊176、及金屬化層 (未單獨示出) 。金屬化層可設計成連接各種元件以形成功能電路。金屬化層可由介電材料 (例如,低k介電材料) 及導電材料 (例如,銅) 的交替層形成,其中通孔將導電材料層互連。金屬化層可經由任何適合的製程 (諸如沉積、鑲嵌、或雙重鑲嵌等) 形成。
在一些實施例中,鍵結墊174及鍵結墊176可藉由在第一基板170的相對側上將凹槽 (未單獨示出) 形成在介電層 (未單獨示出) 或第一基板170中來形成。凹槽可形成為允許鍵結墊174及鍵結墊176嵌入介電層/第一基板170中。在一些實施例中,省略凹槽,且可在介電層/第一基板170上形成鍵結墊174及鍵結墊176。在一些實施例中,鍵結墊174及鍵結墊176包括由銅、鈦、鎳、金、鈀、類似者、或其組合製成的薄種晶層。鍵結墊174及鍵結墊176的導電材料可沉積在薄種晶層上方。導電材料可藉由電化學電鍍製程、無電解電鍍製程、CVD、原子層沉積(atomic layer deposition,ALD)、PVD、類似者、或其組合形成。在一個實施例中,鍵結墊174及鍵結墊176的導電材料包括銅、鎢、鋁、銀、金等,或其組合。在一些實施例中,鍵結墊174及鍵結墊176的導電材料包括銅、鎢、鋁、銀、金、類似者、或其組合。在一些實施例中,鍵結墊174及鍵結墊176為UBM,其包括三層的導電材料,諸如鈦層、銅層、及鎳層。材料及層的其他配置,諸如鉻/鉻銅合金/銅/金的配置,或鈦/鈦鎢/銅的配置,或銅/鎳/金的配置,可用於形成鍵結墊174及鍵結墊176。在一些實施例中,導電通孔178延伸穿過第一基板170,且將鍵結墊174中的至少一者耦合至鍵結墊176中的至少一者。
在一些實施例中,通道172形成在第一基板170中。通道172可為冷卻劑 (諸如油、水、或氣體等) 可在其中流動的空隙。冷卻劑可導入通道172,以將電晶體結構109中產生的熱量傳導出去。通道172的形成可包括蝕刻第一基板 (諸如第29A圖至第29C圖中的基板170B) 以形成微溝槽,用第二及第三基板 (諸如基板170A及170C) 覆蓋微溝槽以密封微溝槽,且在基板170A及170C中形成開口以連接至微溝槽。基板170A及170C中的開口及微溝槽統稱為通道172。第一基板170包括基板170A至170C。使用虛線示出通道172,以指示它們可形成或可不形成。在一些實施例中,散熱器160可含有與通道172相似或相同的通道。
第一基板170可藉由鍵結墊176及第一導電連接器162機械連接及電連接至前側互連結構120。第一導電連接器162可為球閘陣列(ball grid array,BGA)連接器、焊球、金屬柱、可控塌陷晶片連接(C4)凸點、微凸點、或無電解鎳-無電解鈀-浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸點等。第一導電連接器162可包括導電材料,諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者、或其組合。第一基板170可置放在前側互連結構120上方,且可執行回流製程以回流第一導電連接器162,且經由第一導電連接器162將鍵結墊176鍵結至前側互連結構120。
第二基板190可經由第二導電連接器164附接至第一基板170。第二導電連接器164可相同或類似於第一導電連接器162。第二基板190可由半導體材料製成,諸如矽、鍺、或金剛石等。在一些實施例中,亦可使用諸如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化鍺矽、磷化砷鎵、磷化銦鎵、這些的組合、及類似者的化合物材料。另外,第二基板190可為絕緣體上矽(silicon-on-insulator,SOI)基板。通常,SOI基板包括半導體材料層,諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator,SGOI)、或其組合。在一些實施例中,第二基板190可基於諸如玻璃纖維增強樹脂芯的絕緣芯。在一些實施例中,芯材料可為諸如FR4的玻璃纖維樹脂。在一些實施例中,芯材料可包括雙馬來醯亞胺三嗪(BT)樹脂、其他印刷電路板(printed circuit board,PCB)材料、或其他膜。諸如層板的堆積膜可用於第二基板190。第二基板190可藉由鍵結墊174以及第二導電連接器164機械鍵結及電鍵結至第一基板170,其方法類似於或相同於上述關於第一基板170機械鍵結及電鍵結至前側互連結構120的方法。
如上文關於第27A圖至第27C圖所述,除了前側互連結構120之外,還包括背側互連結構140,改善了電晶體結構109的散熱。散熱器160可經由前側互連結構120的第一導電特徵122熱耦合至電晶體結構109。第一基板170可經由第一導電連接器162、第二導電特徵136、第一導電線132、及背側通孔130熱耦合至電晶體結構109。散熱器160及第一基板170可分別用於進一步散發前側互連結構120及背側互連結構140的熱量,進一步改善電晶體結構109的散熱。改善電晶體結構109的散熱提高了元件效能,且減少了元件缺陷。
在第30A圖至第30C中,散熱器160附接至背側互連結構140,第一基板170附接至前側互連結構120,且第二基板190附接至第一基板170。散熱器160、第一基板170、及第二基板190中的各者可分別相同於或相似於上面關於第29A圖至第29C圖討論的散熱器160、第一基板170、及第二基板190,且可藉由與上面關於第29A圖至第29C圖討論的類似或相同的構件及方法經附接。第30A圖至第30C圖中所示的實施例可類似於第29A圖至第29C圖中所示的實施例,除了第28A圖至第28C圖中所示的結構在附接散熱器160、第一基板170、及第二基板190之前沒有翻轉。
如上文關於第27A圖至第27C圖所述,除了前側互連結構120之外,還包括背側互連結構140,改善了電晶體結構109的散熱。第一基板170可經由前側互連結構120的第一導電特徵122熱耦合至電晶體結構109。散熱器160可經由第一導電連接器162、第二導電特徵136、第一導電線132、及背側通孔130熱耦合至電晶體結構109。散熱器160及第一基板170可用於分別進一步散發背側連接結構140及前側互連結構120的熱量,進一步改善電晶體結構109的散熱。改善電晶體結構109的散熱改善了元件效能,且減少了元件缺陷。。
在第31A圖至第31C圖中,第二基板190附接至前側互連結構120,第一基板170附接至背側互連結構140,且散熱器160附接至與背側互連結構140相對的第一基板170。散熱器160,第一基板170、及第二基板190中的各者可分別相同於或相似於上文關於第29A圖至第29C圖討論的散熱器160、第一基板170、及第二基板190,且可藉由與上面關於第29A圖至第29C圖討論的類似或相同的構件及方法附接。第二基板190可附接至前側互連結構120,類似於第29A圖至第29C圖中討論的散熱器160,且散熱器160可附接至第一基板170,類似於第29A圖至第29C圖中討論的第二基板190。第31A圖至第31C圖中所示的實施例可類似於第29A圖至29C中所示的實施例,不同之處在於,第一基板170在背側互連結構140與散熱器160之間,而非在前側互連結構120與第二基板190之間。
如上文關於第27A圖至第27C圖所述,除了前側互連結構120之外,還包括背側互連結構140,改善了電晶體結構109的散熱。第一基板170可經由第一導電連接器162、第二導電特徵136、第一導電線132、及背側通孔130熱耦合至電晶體結構109。散熱器可經由第一基板170熱耦合至電晶體結構109。第二基板190可經由前側互連結構120的第一導電特徵122熱耦合至電晶體結構109。散熱器160及第一基板170可用於進一步散發背側互連結構140的熱量,進一步改善電晶體結構109的散熱。改善電晶體結構109的散熱提高了元件效能,且減少了元件缺陷。
實施例可達成優點。舉例而言,除了前側互連結構120之外,還包括背側互連結構140,有助於減小前側互連結構120的厚度,改善經由前側互連結構120的散熱。與前側互連結構120相比,背側互連結構140可具有增大的線寬及減小的厚度,且可進一步用於散發電晶體結構109中產生的熱量。前側互連結構120及背側互連結構140可附接至散熱器160或第一基板170,可進一步散發前側互連結構120及背側互連結構140的熱量。改善散熱,提高了元件效能且減少了元件缺陷。
根據一個實施例,一種元件包括第一電晶體結構;在第一電晶體結構的前側上的前側互連結構,前側互連結構包括前側導電線;第一電晶體結構背側上的背側互連結構,背側互連結構包括背側導電線,背側導電線具有大於前側導電線的線寬的線寬;及耦合至背側互連結構的第一散熱基板。在實施例中,第一散熱基板包括散熱器,散熱器包括與背側互連結構相對的表面中的通道及鰭片。在實施例中,第一散熱基板包括嵌入式流體通道。在一個實施例中,元件進一步包括耦合至前側互連結構的第二散熱基板。在實施例中,前側互連結構具有0.5 微米至2 微米範圍內的厚度,且背側互連結構具有0.5 微米至1 微米範圍內的厚度。在實施例中,前側互連結構的最小線寬的範圍為15 奈米至45 奈米,且背側互連結構的最小線寬的範圍為30 奈米至60 奈米。在實施例中,元件進一步包含第二基板耦合至與背側互連結構相對的第一散熱基板,第二基板為印刷電路板。
根據另一實施例,一種元件包括半導體通道區上方的閘極結構;鄰接閘極結構及半導體通道區的第一源極/汲極區;耦合至閘極結構的面向第一方向的表面的閘極觸點;耦合至第一源極/汲極區的的一表面的第一源極/汲極觸點,此表面面向與第一方向相對的第二方向;耦合至在第二方向上與第一源極/汲極區相對的第一源極/汲極觸點的第一互連結構;及耦合至在第二方向上與第一源極/汲極觸點相對的第一互連結構的第一散熱基板。在實施例中,第一散熱基板包含在與第一互連結構相對的表面中具有鰭片及通道的散熱器。在實施例中,第一散熱基板包括複數個嵌入式流體通道。在一個實施例中,元件進一步包括第二互連結構,第二互連結構耦合至在第一方向上與閘極結構相對的閘極觸點;及第二散熱基板,第二散熱基板耦合至在第一方向上與閘極觸點相對的第二互連結構。在實施例中,第二散熱基板包括在與第二互連結構相對的表面中具有鰭片及通道的散熱器。在實施例中,第二散熱基板包括複數個嵌入式流體通道。在實施例中,元件進一步包括第二散熱基板,第二散熱基板耦合至在第二方向上與第一互連結構相對的第一散熱基板,第二散熱基板包括在與第一散熱基板相對的表面中具有鰭片及通道的散熱器。
根據又另一實施例,一種方法包括形成第一電晶體在第一基板上;曝光第一磊晶材料,曝光第一磊晶材料包括減薄第一基板的背側;用第一背側通孔替換第一磊晶材料,第一背側通孔電耦合至第一電晶體的第一源極/汲極區;形成背側互連結構在與第一源極/汲極區相對的第一背側上方;及將第一散熱基板耦合至與第一背側通孔相對的背側互連結構。在實施例中,方法進一步包括經由設置在與背側互連結構相對的第一散熱基板的表面中的鰭片,散發第一電晶體中產生的熱量。在實施例中,方法進一步包括經由設置在第一散熱基板中的嵌入式流體通道中的流體,散發第一電晶體中產生的熱量。在實施例中,方法進一步包括形成前側互連結構在與背側互連結構相對的第一電晶體上方;及將第二散熱基板耦合至與背側互連結構相對的前側互連結構。在實施例中,方法進一步包括經由設置在與前側互連結構相對的第二散熱基板的表面中的鰭片,散發第一電晶體中產生的熱量。在實施例中,方法進一步包括經由設置在第二散熱基板中的嵌入式流體通道中的流體,散發第一電晶體中產生的熱量。
前述內容概述若干實施例的特徵,使得熟習此項技術者可更佳地理解本揭示內容的態樣。熟習此項技術者應瞭解,其可易於使用本揭示作為用於設計或修改用於實施本文中引入的實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。熟習此項技術者亦應認識到,此類等效構造並不偏離本揭示內容的精神及範疇,且此類等效構造可在本文中進行各種改變、取代、及替代而不偏離本揭示內容的精神及範疇。
20:分隔器
50:基板
50N:n型區
50P:p型區
51:第一半導體層
51A、51B、51C:第一半導體層
52:第一奈米結構
52A、52B、52C:第一奈米結構
53:第二半導體層
53A、53B、53C:第二半導體層
54:第二奈米結構
54A、54B、54C:第二奈米結構
55:奈米結構
64:多層堆疊
66:鰭片
68:隔離區
70:虛設介電層
71:虛設閘極介電質
72:虛設閘極層
74:遮罩層
76:虛設閘極
78:遮罩
80:第一間隔物層
81:第一間隔物
82:第二間隔物層
83:第二間隔物
86:第一凹槽
87:第二凹槽
88:側壁凹槽
90:第一內間隔物
91:第一磊晶材料
92:磊晶源極/汲極區
92A:第一半導體材料層
92B:第二半導體材料層
92C:第三半導體材料層
94:接觸蝕刻停止層
96:第一層間介電層
98:第三凹槽
100:閘極介電層
102:閘電極
104:閘極遮罩
106:第二層間介電層
108:第四凹槽
109:電晶體結構
110:第一矽化物區
112:源極/汲極觸點
114:閘極觸點
120:前側互連結構
122:第一導電特徵
124:第一介電層
125:第二介電層
128:第五凹槽
129:第二矽化物區
130:背側通孔
132:第一導電線
134:第三介電層
136:第二導電特徵
138:第四介電層
140:背側互連結構
160:散熱器
161:通道
162:第一導電連接器
163:導熱鰭片
164:第二導電連接器
170:第一基板
170A、170B、170C:基板
172:通道
174:鍵結墊
176:鍵結墊
178:導電通孔
180:載體基板
182:鍵結層
182A:第一鍵結層
182B:第二鍵結層
190:第二基板
T
1、T
2:厚度
A-A':橫截面
B-B':橫截面
C-C':橫截面
本揭示內容的態樣在與隨附圖式一起研讀時自以下詳細描述內容來最佳地理解。應注意,根據行業中的標準慣例,各種特徵未按比例繪製。實際上,各種特徵的尺寸可為了論述清楚經任意地增大或減小。
第1圖在三維視圖中示出了根據一些實施例的奈米結構場效電晶體 (場效電晶體(field-effect transistor;FET)) 的實例。
第2圖、第3圖、第4圖、第5圖、第6A圖、第6B圖、第6C圖、第7A圖、第7B圖、第7C圖、第8A圖、第8B圖、第8C圖、第9A圖、第9B圖、第9C圖、第10A圖、第10B圖、第10C圖、第11A圖、第11B圖、第11C圖、第11D圖、第12A圖、第12B圖、第12C圖、第12D圖、第12E圖、第13A圖、第13B圖、第13C圖、第14A圖、第14B圖、第14C圖、第15A圖、第15B圖、第15C圖、第16A圖、第16B圖、第16C圖、第17A圖、第17B圖、第17C圖、第18A圖、第18B圖、第18C圖、第19A圖、第19B圖、第19C圖、第20A圖、第20B圖、第20C圖、第21A圖、第21B圖、第21C圖、第22A圖、第22B圖、第22C圖、第23A圖、第23B圖、第23C圖、第24A圖、第24B圖、第24C圖、第25A圖、第25B圖、第25C圖、第26A圖、第26B圖、第26C圖、第27A圖、第27B圖、第27C圖、第28A圖、第28B圖、第28C圖、第29A圖、第29B圖、第29C圖、第30A圖、第30B圖、第30C圖、第31A圖、第31B圖、及第31C圖為根據一些實施例的製造奈米FET的中間階段的橫截面圖。
54A、54B、54C:第二奈米結構
81:第一間隔物
90:第一內間隔物
92:磊晶源極/汲極區
94:接觸蝕刻停止層
96:第一層間介電層
100:閘極介電層
102:閘電極
104:閘極遮罩
106:第二層間介電層
109:電晶體結構
110:第一矽化物區
112:源極/汲極觸點
114:閘極觸點
120:前側互連結構
122:第一導電特徵
124:第一介電層
125:第二介電層
129:第二矽化物區
130:背側通孔
132:第一導電線
134:第三介電層
136:第二導電特徵
138:第四介電層
140:背側互連結構
160:散熱器
161:通道
162:第一導電連接器
163:導熱鰭片
164:第二導電連接器
170:第一基板
174:鍵結墊
176:鍵結墊
178:導電通孔
190:第二基板
Claims (20)
- 一種元件,包含: 一第一電晶體結構; 一前側互連結構,在該第一電晶體結構的一前側上,該前側互連結構包含複數個前側導電線; 一背側互連結構,在該第一電晶體結構的一背側上,該背側互連結構包含複數個背側導電線,該些背側導電線具有大於該些前側導電線的複數個線寬的複數個線寬;及 一第一散熱基板,耦合至該背側互連結構。
- 如請求項1所述之元件,其中該第一散熱基板包含一散熱器,該散熱器包含與該背側互連結構相對的一表面中的複數個通道及複數個鰭片。
- 如請求項1所述之元件,其中該第一散熱基板包含複數個嵌入式流體通道。
- 如請求項1所述之元件,進一步包含耦合至該前側互連結構的一第二散熱基板。
- 如請求項1所述之元件,其中該前側互連結構具有0.5 微米至2 微米範圍內的一厚度且該背側互連結構具有0.5 微米至1 微米範圍內的一厚度。
- 如請求項1所述之元件,其中該前側互連結構的一最小線寬的範圍為15 奈米至45 奈米,且其中該背側互連結構的一最小線寬的範圍為30 奈米至60 奈米。
- 如請求項1所述之元件,進一步包含一第二基板耦合至與該背側互連結構相對的該第一散熱基板,其中該第二基板為一印刷電路板。
- 一種元件,包含: 一閘極結構,在一半導體通道區上方; 一第一源極/汲極區,鄰接該閘極結構及該半導體通道區; 一閘極觸點,耦合至該閘極結構的面向一第一方向的一表面; 一第一源極/汲極觸點,耦合至該第一源極/汲極區的一表面,該表面面向與該第一方向相反的一第二方向; 一第一互連結構,耦合至在該第二方向上與該第一源極/汲極區相對的該第一源極/汲極觸點;及 一第一散熱基板,耦合至在該第二方向上與該第一源極/汲極觸點相對的該第一互連結構。
- 如請求項8所述之元件,其中該第一散熱基板包含一散熱器,該散熱器在與該第一互連結構相對的一表面中具有複數個鰭片及複數個通道。
- 如請求項8所述之元件,其中該第一散熱基板包含複數個嵌入式流體通道。
- 如請求項8所述之元件,進一步包含: 一第二互連結構,耦合至在該第一方向上與該閘極結構相對的該閘極觸點;及 一第二散熱基板,耦合至在該第一方向上與該閘極觸點相對的該第二互連結構。
- 如請求項11所述之元件,其中該第二散熱基板包含一散熱器,該散熱器在與該第二互連結構相對的一表面中具有複數個鰭片及複數個通道。
- 如請求項11所述之元件,其中該第二散熱基板包含複數個嵌入式流體通道。
- 如請求項8所述之元件,進一步包含一第二散熱基板,該第二散熱基板耦合至在該第二方向上與該第一互連結構相對的該第一散熱基板,其中該第二散熱基板包含一散熱器,該散熱器在與該第一散熱基板相對的一表面中具有複數個鰭片及複數個通道。
- 一種方法,包含: 形成一第一電晶體於一第一基板上; 曝光一第一磊晶材料,其中曝光該第一磊晶材料包含減薄該第一基板的一背側; 用一第一背側通孔替換該第一磊晶材料,該第一背側通孔電耦合至該第一電晶體的一第一源極/汲極區; 形成一背側互連結構在與該第一源極/汲極區相對的該第一背側通孔上方;及 將一第一散熱基板耦合至與該第一背側通孔相對的該背側互連結構。
- 如請求項15所述之方法,進一步包含:經由設置在與該背側互連結構相對的該第一散熱基板的一表面中的複數個鰭片,散發在該第一電晶體中產生的熱量。
- 如請求項15所述之方法,進一步包含經由設置在該第一散熱基板中的複數個嵌入式流體通道中的一流體,散發在該第一電晶體中產生的熱量。
- 如請求項15所述之方法,進一步包含: 形成一前側互連結構在與該背側互連結構相對的該第一電晶體上方;及 將一第二散熱基板耦合至與該背側互連結構相對的該前側互連結構。
- 如請求項18所述之方法,進一步包含經由設置在與該前側互連結構相對的該第二散熱基板的一表面中的複數個鰭片,散發在該第一電晶體中產生的熱量。
- 如請求項19所述之方法,進一步包含經由設置在該第二散熱基板中的複數個嵌入式流體通道中的一流體,散發在該第一電晶體中產生的熱量。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163184506P | 2021-05-05 | 2021-05-05 | |
US63/184,506 | 2021-05-05 | ||
US17/381,583 US11990404B2 (en) | 2021-05-05 | 2021-07-21 | Heat dissipation for semiconductor devices and methods of manufacture |
US17/381,583 | 2021-07-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202245194A true TW202245194A (zh) | 2022-11-16 |
TWI785809B TWI785809B (zh) | 2022-12-01 |
Family
ID=83247257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110134936A TWI785809B (zh) | 2021-05-05 | 2021-09-17 | 半導體元件及其製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11990404B2 (zh) |
KR (1) | KR20220151107A (zh) |
CN (1) | CN115084053A (zh) |
DE (1) | DE102021119223A1 (zh) |
TW (1) | TWI785809B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11990404B2 (en) * | 2021-05-05 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation for semiconductor devices and methods of manufacture |
US11817394B2 (en) * | 2021-10-11 | 2023-11-14 | International Business Machines Corporation | Semiconductor circuit power delivery |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242778B1 (en) | 1998-09-22 | 2001-06-05 | International Business Machines Corporation | Cooling method for silicon on insulator devices |
JP2001196372A (ja) | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置 |
US7943428B2 (en) | 2008-12-24 | 2011-05-17 | International Business Machines Corporation | Bonded semiconductor substrate including a cooling mechanism |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US9006829B2 (en) | 2012-08-24 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aligned gate-all-around structure |
US9209247B2 (en) | 2013-05-10 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned wrapped-around structure |
CN104241279B (zh) | 2013-06-18 | 2017-09-01 | 中芯国际集成电路制造(上海)有限公司 | 一种集成电路及其制造方法 |
US9136332B2 (en) | 2013-12-10 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company Limited | Method for forming a nanowire field effect transistor device having a replacement gate |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9608116B2 (en) | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9412817B2 (en) | 2014-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide regions in vertical gate all around (VGAA) devices and methods of forming same |
US9536738B2 (en) | 2015-02-13 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical gate all around (VGAA) devices and methods of manufacturing the same |
US9502265B1 (en) | 2015-11-04 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical gate all around (VGAA) transistors and methods of forming the same |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
KR102430496B1 (ko) | 2017-09-29 | 2022-08-08 | 삼성전자주식회사 | 이미지 센싱 장치 및 그 제조 방법 |
US11437283B2 (en) | 2019-03-15 | 2022-09-06 | Intel Corporation | Backside contacts for semiconductor devices |
KR20200134362A (ko) | 2019-05-21 | 2020-12-02 | 삼성전자주식회사 | 반도체 소자 |
US11195818B2 (en) * | 2019-09-12 | 2021-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit |
TWI741935B (zh) * | 2020-04-28 | 2021-10-01 | 台灣積體電路製造股份有限公司 | 半導體元件與其製作方法 |
US11355410B2 (en) * | 2020-04-28 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermal dissipation in semiconductor devices |
US11450600B2 (en) * | 2020-05-12 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices including decoupling capacitors |
DE102020131432A1 (de) * | 2020-05-22 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain-kontaktstruktur |
US20220028752A1 (en) * | 2020-07-27 | 2022-01-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and method for forming the same |
US11990404B2 (en) * | 2021-05-05 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat dissipation for semiconductor devices and methods of manufacture |
US20230187307A1 (en) * | 2021-12-15 | 2023-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Heat-Dissipating Structures for Semiconductor Devices and Methods of Manufacture |
US20230335519A1 (en) * | 2022-04-13 | 2023-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Packages Including Mixed Bond Types and Methods of Forming Same |
-
2021
- 2021-07-21 US US17/381,583 patent/US11990404B2/en active Active
- 2021-07-26 DE DE102021119223.4A patent/DE102021119223A1/de active Pending
- 2021-09-17 TW TW110134936A patent/TWI785809B/zh active
-
2022
- 2022-02-23 KR KR1020220023924A patent/KR20220151107A/ko not_active Application Discontinuation
- 2022-03-21 CN CN202210277567.8A patent/CN115084053A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US11990404B2 (en) | 2024-05-21 |
TWI785809B (zh) | 2022-12-01 |
KR20220151107A (ko) | 2022-11-14 |
CN115084053A (zh) | 2022-09-20 |
DE102021119223A1 (de) | 2022-11-10 |
US20220359369A1 (en) | 2022-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI764411B (zh) | 封裝半導體元件及其形成方法 | |
KR102515296B1 (ko) | 디커플링 커패시터를 포함한 반도체 디바이스 | |
US11342326B2 (en) | Self-aligned etch in semiconductor devices | |
US20210375861A1 (en) | Backside Interconnect Structures for Semiconductor Devices and Methods of Forming the Same | |
CN113517280B (zh) | 半导体器件及其形成方法 | |
US20220367454A1 (en) | Backside Interconnect Structures for Semiconductor Devices and Methods of Forming the Same | |
TWI785809B (zh) | 半導體元件及其製造方法 | |
TW202205460A (zh) | 形成半導體裝置的方法 | |
TW202326973A (zh) | 半導體封裝及其製造方法與封裝裝置 | |
US20240194559A1 (en) | Thermal dissipation in semiconductor devices | |
KR102455200B1 (ko) | 반도체 디바이스의 방열 | |
US20240096805A1 (en) | Semiconductor devices with backside routing and method of forming same | |
KR102456276B1 (ko) | 후측 전력 레일들을 포함하는 반도체 디바이스들용 스페이서들 | |
KR102526328B1 (ko) | 후면 측 비아들을 포함한 반도체 디바이스들 및 그 형성 방법들 | |
US20230013764A1 (en) | Semiconductor Devices Including Backside Capacitors and Methods of Manufacture | |
US11862561B2 (en) | Semiconductor devices with backside routing and method of forming same | |
TW202240710A (zh) | 半導體裝置的形成方法 | |
KR102460887B1 (ko) | 후면 전력 레일을 포함하는 패키징된 반도체 디바이스 및 그 형성 방법 | |
KR102432494B1 (ko) | 반도체 소자에서의 자체 정렬 에칭 | |
TW202414552A (zh) | 半導體裝置及其製造方法 | |
CN118116973A (zh) | 半导体器件及其制造方法 | |
CN117393503A (zh) | 半导体器件及其形成方法 |