TW202243178A - 電子裝置及其線路結構 - Google Patents

電子裝置及其線路結構 Download PDF

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TW202243178A
TW202243178A TW111112762A TW111112762A TW202243178A TW 202243178 A TW202243178 A TW 202243178A TW 111112762 A TW111112762 A TW 111112762A TW 111112762 A TW111112762 A TW 111112762A TW 202243178 A TW202243178 A TW 202243178A
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metal layer
insulating layer
electronic device
substrate
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王裕霖
陳蔚宗
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元太科技工業股份有限公司
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Abstract

一種電子裝置包括基板、線路結構、氧化物絕緣層與氮化物絕緣層。線路結構配置在基板上，並包括外層金屬層與內層金屬層。外層金屬層的成分不包括鉬。內層金屬層配置在外層金屬層與基板之間，而內層金屬層的成分包括鉬。氧化物絕緣層配置在線路結構上，並直接接觸外層金屬層。氮化物絕緣層配置在氧化物絕緣層上，其中氧化物絕緣層位在氮化物絕緣層與外層金屬層之間。

Description

電子裝置及其線路結構
本發明是有關於一種電子裝置，且特別是有關於一種能減少或防止絕緣層的剝離的電子裝置。
目前一些電子裝置，例如顯示器，具有線路層來傳輸電訊號，以使電子裝置能運作，例如顯示影像。線路層通常被絕緣層所覆蓋而能受到保護。不過，受到製程或材料特性的影響，絕緣層與線路層之間的結合力有時候會降低，以至於絕緣層容易從線路層剝離。如此，不僅線路層沒有受到保護，而且絕緣層的剝離也容易造成線路層損壞。
本發明至少一實施例提出一種線路結構，其能減少或防止絕緣層的剝離。
本發明至少一實施例提出一種電子裝置，其包括上述線路結構。
本發明至少一實施例所提供的線路結構，其設置於電子裝置內，其中電子裝置包括基板，而線路結構配置在基板上，並包括外層金屬層與內層金屬層。外層金屬層的成分不包括鉬，而內層金屬層配置在外層金屬層與基板之間，其中內層金屬層的成分包括鉬。
在本發明至少一實施例中，上述外層金屬層為鋁金屬層、鈦金屬層或鉭金屬層。
在本發明至少一實施例中，上述外層金屬層的厚度大於或等於30埃。
在本發明至少一實施例中，上述內層金屬層包括鉬金屬層或鉬合金層。
本發明至少一實施例所提供的電子裝置包括基板、上述線路結構、氧化物絕緣層與氮化物絕緣層。氧化物絕緣層配置在線路結構上，並直接接觸外層金屬層。氮化物絕緣層配置在氧化物絕緣層上，其中氧化物絕緣層位在氮化物絕緣層與外層金屬層之間。
在本發明至少一實施例中，上述外層金屬層的厚度介於30埃至300埃之間。
在本發明至少一實施例中，上述氧化物絕緣層為氧化矽層，而氮化物絕緣層為氮化矽層。
在本發明至少一實施例中，上述內層金屬層包括鉬金屬層或鉬合金層。
在本發明至少一實施例中，上述電子裝置還包括內層線路層。內層線路層配置在基板上，並位在基板與線路結構之間。
在本發明至少一實施例中，上述電子裝置還包括至少一絕緣層。絕緣層覆蓋內層線路層，並位在線路結構與內層線路層之間。
在本發明至少一實施例中，上述電子裝置還包括多個半導體層。這些半導體層配置在絕緣層上，其中這些半導體層與內層線路層重疊，而線路結構局部覆蓋各個半導體層，並電性連接這些半導體層。
在本發明至少一實施例中，各個半導體層的材料為氧化銦鎵鋅（Indium Gallium Zinc Oxide，IGZO）。
在本發明至少一實施例中，上述電子裝置還包括多個接合墊。這些接合墊配置在氮化物絕緣層上，並電性連接線路結構。
在本發明至少一實施例中，上述電子裝置還包括顯像部與對向基板。顯像部配置在氮化物絕緣層上。對向基板配置在顯像部上。
上述外層金屬層與氧化物絕緣層之間能產生足夠強度的結合力，以減少或防止氧化物絕緣層與氮化物絕緣層剝離，進而降低或避免線路結構損壞。
在以下的內文中，為了清楚呈現本案的技術特徵，圖式中的元件（例如層、膜、基板以及區域等）的尺寸（例如長度、寬度、厚度與深度）會以不等比例的方式放大，而且有的元件數量會減少。因此，下文實施例的說明與解釋不受限於圖式中的元件數量以及元件所呈現的尺寸與形狀，而應涵蓋如實際製程及/或公差所導致的尺寸、形狀以及兩者的偏差。例如，圖式所示的平坦表面可以具有粗糙及/或非線性的特徵，而圖式所示的銳角可以是圓的。所以，本案圖式所呈示的元件主要是用於示意，並非旨在精準地描繪出元件的實際形狀，也非用於限制本案的申請專利範圍。
其次，本案內容中所出現的「約」、「近似」或「實質上」等這類用字不僅涵蓋明確記載的數值與數值範圍，而且也涵蓋發明所屬技術領域中具有通常知識者所能理解的可允許偏差範圍，其中此偏差範圍可由測量時所產生的誤差來決定，而此誤差例如是起因於測量系統或製程條件兩者的限制。此外，「約」可表示在上述數值的一個或多個標準偏差內，例如±30％、±20％、±10％或±5％內。本案文中所出現的「約」、「近似」或「實質上」等這類用字可依光學性質、蝕刻性質、機械性質或其他性質來選擇可以接受的偏差範圍或標準偏差，並非單以一個標準偏差來套用以上光學性質、蝕刻性質、機械性質以及其他性質等所有性質。
圖1是本發明至少一實施例的電子裝置的剖面示意圖。請參閱圖1，本實施例的電子裝置100可以是一種顯示裝置，而圖1簡略地繪示電子裝置100的結構。具體而言，電子裝置100可以包括控制基板200、顯像部110與對向基板120，其中控制基板200包括基板210、元件陣列層220以及鈍化層230，而元件陣列層220配置在基板210與鈍化層230之間。
顯像部110配置在鈍化層230上，而對向基板120配置在顯像部110上，所以顯像部110會在控制基板200與對向基板120之間。電子裝置100具有顯示區A11以及非顯示區A12，其中非顯示區A12位於顯示區A11的周圍。顯像部110分布於整個顯示區A11以及一部分非顯示區A12，但不會分布於大部分非顯示區A12。
電子裝置100可以是液晶顯示面板（Liquid Crystal Display Panel，LCD Panel）、電濕潤顯示面板（electrowetting display panel）、電泳式顯示面板（Electrophoretic Display Panel，EPD Display Panel）、有機發光二極體（Organic Light-Emitting Diode，OLED）顯示面板或發光二極體（Light-Emitting Diode，LED）顯示面板。因此，顯像部110可以包括液晶層、電濕潤材料層、電泳式電子墨水、多個有機發光二極體或多個發光二極體，其中發光二極體可以是微型發光二極體（micro-LED，μLED）或次毫米發光二極體（mini-LED）。
當電子裝置100為液晶顯示面板時，對向基板120可以是彩色濾光基板，而基板210可以是透光基板，例如玻璃板或透明高分子基板。當電子裝置100為有機發光二極體顯示面板或發光二極體顯示面板時，對向基板120可以是透光基板，例如玻璃板，而基板210可以是不透明的（opaque）線路基板。
圖2A是圖1中的控制基板在顯示區內的俯視示意圖，而圖2B是圖2A中沿線2B-2B剖面繪製的剖面示意圖，其中圖2A是在省略鈍化層230的條件下繪製控制基板200。請參閱圖2A與圖2B，元件陣列層220包括配置在基板210上的線路結構221，其中線路結構221分布於顯示區A11（請參考圖1）。
線路結構221具有多層膜（multilayer）。以圖2B為例，線路結構221可以包括外層金屬層221a與內層金屬層221b，其中內層金屬層221b配置在外層金屬層221a與基板210之間。外層金屬層221a的成分不包括鉬，而內層金屬層221b的成分包括鉬。
例如，外層金屬層221a可為鋁金屬層、鈦金屬層或鉭金屬層，所以外層金屬層221a不含鉬金屬與鉬離子。外層金屬層221a與內層金屬層221b皆可利用物理氣相沉積（Physical Vapor Deposition，PVD）而形成，其中此物理氣相沉積包括濺鍍或蒸鍍。外層金屬層221a的厚度T21a可大於或等於30埃。例如，厚度T21a可介於30埃至300埃之間，像是80埃。
內層金屬層221b可具有多層膜，並可包括彼此堆疊的第一金屬層M21、第二金屬層M22與第三金屬層M23。外層金屬層221a配置在第一金屬層M21上，並可直接接觸第一金屬層M21。第二金屬層M22配置在第三金屬層M23與第一金屬層M21之間，並可接觸第三金屬層M23與第一金屬層M21。第三金屬層M23可位在基板210與第二金屬層M22之間。
內層金屬層221b可包括鉬金屬層或鉬合金層。以圖2B為例，第一金屬層M21為鉬金屬層或鉬鉻合金層，並含有重量百分比在97%以上的鉬。此外，第三金屬層M23的材料可以相同於第一金屬層M21的材料。例如，第三金屬層M23也可以是鉬金屬層或鉬鉻合金層，並含有重量百分比在97%以上的鉬。第二金屬層M22的材料不同於第一金屬層M21的材料，其中第二金屬層M22為不含鉬的金屬層，例如鋁金屬層。
鈍化層230包括氮化物絕緣層231與氧化物絕緣層232，其中氧化物絕緣層232可為氧化矽層，而氮化物絕緣層231可為氮化矽層。氧化物絕緣層232配置在線路結構221上，並直接接觸外層金屬層221a與氮化物絕緣層231。氮化物絕緣層231配置在氧化物絕緣層232上，所以氧化物絕緣層232可以位在氮化物絕緣層231與外層金屬層221a之間。此外，顯像部110（繪示於圖1）配置在氮化物絕緣層231上，所以氮化物絕緣層231位在顯像部110與氧化物絕緣層232之間。
外層金屬層221a與氧化物絕緣層232之間能產生較強的結合力，以使外層金屬層221a能做為連接氧化物絕緣層232與內層金屬層221b的黏合層，進而減少或防止鈍化層230剝離。當外層金屬層221a的厚度T21a大於或等於30埃以上時，鈍化層230更能通過百格刀測試（Cross Cut Adhesion Test）。
詳細而言，當外層金屬層221a的厚度T21a大於或等於80埃以上，例如160埃或240埃時，縱使使用黏力強的3M™ super bond film tape 396號膠帶進行百格刀測試，氧化物絕緣層232與氮化物絕緣層231基本上也不會剝離，從而達到相當於ASTM的5B等級。因此，外層金屬層221a確實能使鈍化層230與線路結構221之間產生較強的結合力，以減少或防止鈍化層230剝離，進而降低或避免線路結構221被剝離的鈍化層230損壞。
電子裝置100的元件陣列層220還包括內層線路層222與絕緣層223、224。內層線路層222配置在基板210上，並位在基板210與線路結構221之間。絕緣層223與224全面性覆蓋基板210與內層線路層222，並位在線路結構221與內層線路層222之間。絕緣層223可以接觸線路結構221，而絕緣層224可以接觸內層線路層222，其中絕緣層224位在絕緣層223與基板210之間。此外，絕緣層223的材料可以是氧化矽，而絕緣層224的材料可以是氮化矽。
內層線路層222也可以具有多層結構。例如，內層線路層222可以包括三層金屬層222a、222b與222c，其中金屬層222b位於金屬層222a與222c之間，並可接觸金屬層222a與222c，而金屬層222c可接觸基板210。內層線路層222的材料與結構可相同於線路結構221的材料與結構，其中金屬層222a與222c可為鉬金屬層或鉬鉻合金層，並含有重量百分比在97%以上的鉬。
須說明的是，在本實施例中，元件陣列層220包括兩層絕緣層223與224，但在其他實施例中，元件陣列層220可以只包括單一層絕緣層。例如，圖2B中的絕緣層224可被省略，而絕緣層223的厚度增加，以使絕緣層223能全面性覆蓋基板210與內層線路層222，並接觸線路結構221與內層線路層222。
元件陣列層220還包括多個半導體層TC2，其中這些半導體層TC2配置在絕緣層223上，而各個半導體層TC2的材料可為氧化銦鎵鋅、多晶矽或單晶矽。這些半導體層TC2與內層線路層222重疊，而線路結構221局部覆蓋各個半導體層TC2，並電性連接這些半導體層TC2。元件陣列層220可以具有多個電晶體元件T21，其中這些電晶體元件T21是由線路結構221、內層線路層222、絕緣層223、224與這些半導體層TC2所形成的薄膜電晶體（Thin Film Transistor，TFT）。
具體而言，線路結構221可包括多個源極TS2與多個汲極TD2，而內層線路層222可包括多個閘極TG2。這些閘極TG2分別與這些半導體層TC2重疊，其中絕緣層223與224位在閘極TG2與半導體層TC2之間，以使閘極TG2與半導體層TC2之間能形成電容。
這些源極TS2與這些汲極TD2位在這些半導體層TC2上，並分別電性連接這些半導體層TC2，其中相鄰的源極TS2與汲極TD2分別鄰接其中一個半導體層TC2的相對兩側。如此，這些電晶體元件T21得以形成，而各個電晶體元件T21具有一個源極TS2、一個汲極TD2、一個閘極TG2與一個半導體層TC2。
特別一提的是，在圖2B所示的實施例中，電晶體元件T21為底閘極型（bottom gate）薄膜電晶體。在其他實施例中，電晶體元件T21也可以是頂閘極型（top gate）薄膜電晶體。因此，電晶體元件T21不限制是底閘極型薄膜電晶體。
其次，從圖2B來看，半導體層TC2夾置在氧化物絕緣層232與絕緣層223，其中氧化物絕緣層232與絕緣層223兩者材料皆可為氧化矽。當半導體層TC2的材料為氧化銦鎵鋅時，由於氧化銦鎵鋅易被氮化物所影響而喪失半導體特性，因此夾置半導體層TC2的氧化物絕緣層232與絕緣層223能保護半導體層TC2，以使半導體層TC2不與氮化物（例如絕緣層223與氮化物絕緣層231）接觸，從而讓半導體層TC2保有原本的半導體特性。
控制基板200還可以包括多個接觸窗241（圖2B僅繪示一個）與多個電極242，其中這些電極242分別電性連接這些接觸窗241，並且位在氮化物絕緣層231上，而顯像部110（請參考圖1）覆蓋這些電極242。這些接觸窗241實質上可以是導電柱，並且形成在鈍化層230中，其中各個接觸窗241能貫穿鈍化層230，並且連接汲極TD2，以使這些汲極TD2能透過這些接觸窗241而電性連接這些電極242。
線路結構221還可包括多條資料線L21，而內層線路層222還可以包括多條掃描線S22，其中這些資料線L21連接這些源極TS2，而這些掃描線S22連接這些閘極TG2。因此，這些掃描線S22所傳輸的訊號能傳遞至這些閘極TG2，以控制這些電晶體元件T21的開啟與關閉，進而控制這些資料線L21所傳輸的畫素訊號能經由電晶體元件T21而輸入至這些電極242，以使上述畫素訊號能輸入至顯像部110，例如輸入至液晶層、電濕潤材料層、電泳式電子墨水、有機發光二極體層或發光二極體，從而讓電子裝置100能顯示影像。
圖3A是圖1中的控制基板在非顯示區內的俯視示意圖，而圖3B是圖3A中沿線3B-3B剖面繪製的剖面示意圖，其中圖3A是在省略鈍化層230的條件下繪製控制基板200。請參閱圖3A與圖3B，元件陣列層220還包括多個接觸窗291與多個接合墊292，其中這些接合墊292分別電性連接這些接觸窗291。
這些接合墊292配置在氮化物絕緣層231上，並分布在非顯示區A12內（請參考圖1），其中顯像部110未覆蓋任何接合墊292，以使這些接合墊292能電性連接外部電子元件（未繪示）。例如，這些接合墊292能透過焊料或異方向性導電膜（Anisotropic Conductive Film，ACF）而電性連接線路基板。如此，裝設在此線路基板上的晶片能電性連接接合墊292，其中線路基板可以是軟性印刷電路板（Flexible Printed Circuit，FPC），而晶片可以是源極驅動器。
線路結構221更分布於非顯示區A12（請參考圖1），其中這些資料線L21從顯示區A11延伸至非顯示區A12。這些接觸窗291實質上也可以是導電柱，並形成在鈍化層230中，其中各個接觸窗291也能貫穿鈍化層230，並連接資料線L21，以使這些接合墊292電性連接線路結構221的這些資料線L21。如此，上述晶片（例如源極驅動器）能從這些接合墊292輸入畫素訊號至這些資料線L21，以使這些資料線L21能傳輸畫素訊號至這些電晶體元件T21，進而輸入至這些電極242。
由於外層金屬層221a能使鈍化層230與線路結構221之間產生較強的結合力，因此在非顯示區A12內的鈍化層230也很難或不會剝離。如此，在電性連接外部電子元件（例如裝設有晶片的線路基板）的過程中，鈍化層230實質上能被完整地保留，以保護線路結構221，並降低或避免非顯示區A12內的線路結構221被剝離的鈍化層230損壞。
須說明的是，上述實施例所揭示的電子裝置100是以顯示裝置作為舉例說明。然而，在其他實施例中，電子裝置100也可以是其他裝置，例如觸控感測面板或影像感測器。因此，電子裝置100不限制是顯示裝置，而以上線路結構221以及鈍化層230（包括氮化物絕緣層231與氧化物絕緣層232）也可應用於顯示裝置以外的其他裝置，例如觸控感測面板或影像感測器。
值得一提的是，在以上實施例中，氧化物絕緣層232局部覆蓋絕緣層223。請參閱圖2B與圖3B，氧化物絕緣層232覆蓋元件陣列層220，但不覆蓋部分絕緣層223，以使氮化物絕緣層231能覆蓋及接觸絕緣層223。所以，氧化物絕緣層232不會全面性覆蓋元件陣列層220。不過，在其他實施例中，氧化物絕緣層232也可全面性覆蓋元件陣列層220，即氧化物絕緣層232可以全面性覆蓋絕緣層223。
圖4A與圖4B是本發明另一實施例的電子裝置的控制基板之剖面示意圖，其中圖4A是控制基板400在顯示區內的剖面示意圖，而圖4B是控制基板400在非顯示區內的剖面示意圖。請參閱圖4A與圖4B，控制基板400與200相似，其中控制基板400與200之間的差異僅在於控制基板400所包括的鈍化層430。
具體而言，在圖4A與圖4B所示的實施例中，鈍化層430包括氮化物絕緣層231與氧化物絕緣層432，其中氧化物絕緣層432的材料可相同於氧化物絕緣層232的材料。有別於氧化物絕緣層232，氧化物絕緣層432全面性覆蓋元件陣列層220，即全面性覆蓋絕緣層223。如此，接觸絕緣層223的部分氧化物絕緣層432可夾置在氮化物絕緣層231與絕緣層223之間，如圖4A與圖4B所示。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明精神和範圍內，當可作些許更動與潤飾，因此本發明保護範圍當視後附的申請專利範圍所界定者為準。
100:電子裝置 110:顯像部 120:對向基板 200、400:控制基板 210:基板 220:元件陣列層 221:線路結構 221a:外層金屬層 221b:內層金屬層 222:內層線路層 222a、222b、222c:金屬層 223、224:絕緣層 230、430:鈍化層 231:氮化物絕緣層 232、432:氧化物絕緣層 241、291:接觸窗 242:電極 292:接合墊 A11:顯示區 A12:非顯示區 L21:資料線 M21:第一金屬層 M22:第二金屬層 M23:第三金屬層 S22:掃描線 T21:電晶體元件 T21a:厚度 TC2:半導體層 TD2:汲極 TG2:閘極 TS2:源極
圖1是本發明至少一實施例的電子裝置的剖面示意圖。 圖2A是圖1中的控制基板在顯示區內的俯視示意圖。 圖2B是圖2A中沿線2B-2B剖面繪製的剖面示意圖。 圖3A是圖1中的控制基板在非顯示區內的俯視示意圖。 圖3B是圖3A中沿線3B-3B剖面繪製的剖面示意圖。 圖4A與圖4B是本發明另一實施例的電子裝置的控制基板之剖面示意圖。
200:控制基板
210:基板
220:元件陣列層
221:線路結構
221a:外層金屬層
221b:內層金屬層
222:內層線路層
222a、222b、222c:金屬層
223、224:絕緣層
230:鈍化層
231:氮化物絕緣層
232:氧化物絕緣層
241:接觸窗
242:電極
L21:資料線
M21:第一金屬層
M22:第二金屬層
M23:第三金屬層
T21:電晶體元件
T21a:厚度
TC2:半導體層
TD2:汲極
TG2:閘極
TS2:源極

Claims (16)

  1. 一種電子裝置，包括： 一基板； 一線路結構，配置在該基板上，並包括： 一外層金屬層，其中該外層金屬層的成分不包括鉬； 一內層金屬層，配置在該外層金屬層與基板之間，其中該內層金屬層的成分包括鉬； 一氧化物絕緣層，配置在該線路結構上，並直接接觸該外層金屬層；以及 一氮化物絕緣層，配置在該氧化物絕緣層上，其中該氧化物絕緣層位在該氮化物絕緣層與該外層金屬層之間。
  2. 如請求項1所述的電子裝置，其中該外層金屬層為鋁金屬層、鈦金屬層或鉭金屬層。
  3. 如請求項1或2所述的電子裝置，其中該外層金屬層的厚度大於或等於30埃。
  4. 如請求項1或2所述的電子裝置，其中該外層金屬層的厚度介於30埃至300埃之間。
  5. 如請求項1所述的電子裝置，其中該氧化物絕緣層為氧化矽層，而該氮化物絕緣層為氮化矽層。
  6. 如請求項1所述的電子裝置，其中該內層金屬層包括鉬金屬層或鉬合金層。
  7. 如請求項1所述的電子裝置，還包括： 一內層線路層，配置在該基板上，並位在該基板與該線路結構之間。
  8. 如請求項7所述的電子裝置，還包括： 至少一絕緣層，覆蓋該內層線路層，並位在該線路結構與該內層線路層之間。
  9. 如請求項8所述的電子裝置，還包括： 多個半導體層，配置在該至少一絕緣層上，其中該些半導體層與該內層線路層重疊，而該線路結構局部覆蓋各該半導體層，並電性連接該些半導體層。
  10. 如請求項9所述的電子裝置，其中各該半導體層的材料為氧化銦鎵鋅。
  11. 如請求項1所述的電子裝置，還包括： 多個接合墊，配置在該氮化物絕緣層上，並電性連接該線路結構。
  12. 如請求項1所述的電子裝置，還包括： 一顯像部，配置在該氮化物絕緣層上；以及 一對向基板，配置在該顯像部上。
  13. 一種線路結構，設置於一電子裝置內，其中該電子裝置包括一基板，而該線路結構配置在該基板上，並包括： 一外層金屬層，其中該外層金屬層的成分不包括鉬；以及 一內層金屬層，配置在該外層金屬層與基板之間，其中該內層金屬層的成分包括鉬。
  14. 如請求項13所述的線路結構，其中該外層金屬層為鋁金屬層、鈦金屬層或鉭金屬層。
  15. 如請求項13或14所述的線路結構，其中該外層金屬層的厚度大於或等於30埃。
  16. 如請求項13所述的線路結構，其中該內層金屬層包括鉬金屬層或鉬合金層。
TW111112762A 2021-04-23 2022-04-01 電子裝置及其線路結構 TW202243178A (zh)

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