TW202222036A - Processor capable of being directly activated and output by external signal composed of an input unit, an output unit and a timing counting control module - Google Patents
Processor capable of being directly activated and output by external signal composed of an input unit, an output unit and a timing counting control module Download PDFInfo
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Abstract
Description
本發明係關於一種處理器,尤指一種可由外部訊號直接啟動輸出的處理器。The present invention relates to a processor, especially a processor whose output can be directly activated by an external signal.
一般來說,微處理器(Micro Processing Unit, MPU)、微控制器(Micro Control Unit, MCU)等等的處理器通常係以內部核心邏輯區塊、周邊功能區塊以及輸入輸出介面所組成,如圖5所示,係一種已知的處理器600,其包括一內部核心邏輯區塊610(運算邏輯單元611)、一周邊功能區塊620(計時計數器621、程式記憶體622、暫存器623)以及一輸入輸出介面630(輸入埠631、輸岀埠632),該處理器600並藉由該內部核心邏輯區塊610來控制該周邊功能區塊620的運作以及該輸入輸出介面630所傳送或接收的訊號。而為了優化該處理器600的效能,通常該處理器600更包括一中斷產生器640,該中斷產生器640用以使該處理器600中斷執行現有的程式,轉而執行另一個程式,並在完成執行另一個程式後繼續執行現有的程式,藉由中斷操作而不等待現有的程式執行完畢。Generally speaking, processors such as Micro Processing Unit (MPU) and Micro Control Unit (MCU) are usually composed of internal core logic blocks, peripheral function blocks and input and output interfaces. As shown in FIG. 5, a known
然而,雖然已知的處理器已引進了中斷操作的操作方式,但已知的處理器仍需要等待數十個時脈週期之後,才能輸出所需訊號,即現有的中斷操作仍造成訊號輸出的延遲,因此,確實有待提出更佳解決方案的必要性。However, although the known processor has introduced the operation mode of the interrupt operation, the known processor still needs to wait for dozens of clock cycles before outputting the required signal, that is, the existing interrupt operation still causes the signal output to fail. delay, therefore, the need for a better solution is really pending.
有鑑於上述現有技術之不足,本發明的主要目的在於提供一可由外部訊號直接啟動輸出的處理器,其不須透過處理器的內部核心邏輯區塊,即可根據外部的觸發訊號來產生可程式脈衝訊號,藉此,達到提升控制精準度的目的。In view of the above-mentioned deficiencies of the prior art, the main purpose of the present invention is to provide a processor that can be directly activated and output by an external signal, which can generate a programmable signal according to an external trigger signal without going through the internal core logic block of the processor. Pulse signal, thereby achieving the purpose of improving the control accuracy.
為達成上述目的所採取的主要技術手段係令前述可由外部訊號直接啟動輸出的處理器包括: 一輸入單元; 一輸出單元; 一計時計數控制模組,與該輸入單元以及該輸出單元電性連接, 一暫存器,與該計時計數控制模組電性連接;以及 一內部核心邏輯區塊,與該暫存器電性連接; 其中,由該輸入單元取得一觸發訊號,該計時計數控制模組根據該觸發訊號控制該輸出單元輸出一可程式脈衝訊號, 該處理器不以該內部核心邏輯區塊來控制該輸出單元輸出該可程式脈衝訊號。 The main technical means adopted to achieve the above purpose are to enable the aforementioned processors that can be directly activated and output by external signals include: an input unit; an output unit; A timing counting control module is electrically connected with the input unit and the output unit, a register, electrically connected to the timing counting control module; and an internal core logic block electrically connected to the register; Wherein, a trigger signal is obtained from the input unit, and the timing counting control module controls the output unit to output a programmable pulse signal according to the trigger signal, The processor does not use the internal core logic block to control the output unit to output the programmable pulse signal.
由上述構造,該計時計數控制模組可根據該觸發訊號產生該可程式脈衝訊號,使該處理器其不須等待該內部核心邏輯區塊的運算,即可根據外部的該觸發訊號來產生該可程式脈衝訊號,藉此達到提升控制精準度的目的。With the above structure, the timing count control module can generate the programmable pulse signal according to the trigger signal, so that the processor can generate the programmable pulse signal according to the external trigger signal without waiting for the operation of the internal core logic block. Programmable pulse signal to achieve the purpose of improving control accuracy.
關於本發明可由外部訊號直接啟動輸出的處理器之一實施例,請參閱圖1所示,該處理器100至少包括一輸入單元10、一計時計數控制模組20,一輸出單元30、一暫存器40以及一內部核心邏輯區塊50。該輸入單元10用以接收一觸發訊號ONtrigger。該計時計數控制模組20與該輸入單元10電性連接,用以透過該輸入單元10接收該觸發訊號ONtrigger,該輸出單元30與該計時計數控制模組20電性連接,該輸出單元30用以輸出該計時計數控制模組20產生的一可程式脈衝訊號Pprogram,該暫存器40與該計時計數控制模組20電性連接,該內部核心邏輯區塊50與該暫存器40電性連接。換言之,該計時計數控制模組20係用以根據該觸發訊號ONtrigger控制該輸出單元30輸出該可程式脈衝訊號Pprogram。藉此,該處理器100無須等待該內部核心邏輯區塊50的運算,即可根據外部的該觸發訊號ONtrigger以及該計時計數控制模組20,即時地產生該可程式脈衝訊號Pprogram,避免該內部核心邏輯區塊50造成的延遲,達到提升精準控制的目的。For an embodiment of the present invention, the processor that can be directly activated and output by an external signal, please refer to FIG. 1 , the
於一實施例中,該觸發訊號為該處理器100之內部觸發訊號或由該處理器100之外部電路所接收之一外部觸發訊號。In one embodiment, the trigger signal is an internal trigger signal of the
於一實施例中,該處理器100可實現為應用於切換式電力轉換器、馬達驅動控制器或自動反應控制器之控制器,且本發明不以此為限制。In one embodiment, the
於一實施例中,該輸入單元10以及該輸出單元30為該處理器100之輸入輸出埠。In one embodiment, the
於一實施例中,該可程式脈衝訊號Pprogram為一脈寬調變訊號、一時脈訊號或一單擊(single shot)訊號,且本發明不以此為限制。In one embodiment, the programmable pulse signal Pprogram is a pulse width modulation signal, a clock signal or a single shot signal, and the invention is not limited thereto.
於一實施例中,為了配合電路設計,該處理器100更可配置多個計時計數控制模組。如圖2所示,在本實施例中,一處理器100’可配置兩個計時計數控制模組(即該計時計數控制模組20a以及一計時計數控制模組20b),該計時計數控制模組20a與一暫存器40a電性連接、該計時計數控制模組20b與一暫存器40b電性連接,該暫存器40a、該暫存器40b與該內部核心邏輯區塊50電性連接,且在此實施例中,該計時計數控制模組20b可用以實現訊號延遲或計數的功能,且本發明不以此為限制。In one embodiment, in order to match the circuit design, the
在另一實施例中,亦可先以該計時計數控制模組20a實現訊號延遲的功能來延遲該觸發訊號ONtrigger,再以該計時計數控制模組20b產生該可程式脈衝訊號Pprogram,且本發明不以此為限制。In another embodiment, the timing and
為了進一步說明本發明之該計時計數控制模組20,請參閱圖3所示,其至少包括一正反器21、一第一邏輯閘22、一第二邏輯閘23以及一計時計數單元24,其中該正反器21與該第一邏輯閘22電性連接,該第一邏輯閘22與該第二邏輯閘23電性連接,該計時計數單元24與該第一邏輯閘22以及該第二邏輯閘23電性連接,其中,圖3所揭示之實施例僅用以示例,而非用以限制本發明。To further illustrate the timing
進一步地,該正反器21具有一輸入端D、一輸出端Q、一時脈輸入端CLK、一設定端S以及一重置端R。該輸入端D與該設定端S用以接收一邏輯高電位Vh,該時脈輸入端CLK用以接收該觸發訊號ONtrigger,該輸出端Q用以輸出一閂鎖訊號ONlatch,該重置端R用以接收一重置訊號D-FF Reset,因此,該正反器21用以被該觸發訊號ONtrigger觸發並使該閂鎖訊號ONlatch改變狀態(例如:由低電壓準位轉換為高電壓準位),並用以根據該重置訊號D-FF Reset使該閂鎖訊號ONlatch改變狀態(例如:由高電壓準位轉換為低電壓準位)。Further, the flip-
於一實施例中,該正反器為D型正反器,且本發明不以此為限制。In one embodiment, the flip-flop is a D-type flip-flop, and the present invention is not limited thereto.
該第一邏輯閘22具有一第一輸入端221、一第二輸入端222以及一輸出端223,該第一輸入端221與該計時計數單元24電性連接,用以接收一溢位訊號event,該第二輸入端222與該正反器21的該輸出端Q電性連接並接收該閂鎖訊號ONlatch,該輸出端223用以輸出該可程式脈衝訊號Pprogram,該第一邏輯閘22用以根據該溢位訊號event以及該閂鎖訊號ONlatch產生該可程式脈衝訊號Pprogram。The
該第二邏輯閘23具有一第一輸入端231、一第二輸入端232以及一輸出端233,該第一輸入端231用以接收一內部時脈訊號Clock,該第二輸入端232與該第一邏輯閘22的該輸出端223電性連接並接收該可程式脈衝訊號Pprogram,該輸出端233與該計時計數單元24電性連接用以輸出一閘控時脈訊號gated clock至該計時計數單元24的時脈輸入端,該第二邏輯閘23用以根據該內部時脈訊號Clock以及該可程式脈衝訊號Pprogram產生該閘控時脈訊號gated clock。The
於一實施例中,該第一邏輯閘22以及該第二邏輯閘23可由及閘來實現,且本發明不以此為限制。In an embodiment, the
進一步的,該溢位訊號event為該計時計數單元24向上計數或向下計數發生溢位時所產生之控制訊號。舉例來說,於16進位時,當該計時計數單元24為向上計數,且由FFFF向上計數而溢位時,產生該溢位訊號event。Further, the overflow signal event is a control signal generated when the
於一實施例中,該溢位訊號event為低準位觸發的訊號,即當該溢位訊號event由高電壓準位轉換為低電壓準位時,使對應之電路執行對應之作動。In one embodiment, the overflow signal event is a signal triggered by a low level, that is, when the overflow signal event is converted from a high voltage level to a low voltage level, the corresponding circuit is made to perform a corresponding action.
以下將配合圖4,並以前述之該計時計數控制模組20為例來說明該計時計數控制模組20之運作方法,需注意的是,下述之高電壓準位以及低電壓準位僅為用以說明本發明,並非用以限定本發明,本發明所屬技術領域之通常知識者可根據其需求替換使用高電壓準位或低電壓準位來完成本發明。請同時參考圖3以及圖4,首先,於時點Ta,該觸發訊號ONtrigger由低電壓準位轉換為高電壓準位,因此該正反器21被驅動,使該閂鎖訊號ONlatch由低電壓準位轉換為高電壓準位,同時,因為該溢位訊號event為高電壓準位,因此該可程式脈衝訊號Pprogram因為該閂鎖訊號ONlatch以及該溢位訊號event而由低電壓準位轉換為高電壓準位,同時,藉由該內部時脈訊號Clock與該可程式脈衝訊號Pprogram,產生對應之該閘控時脈訊號gated clock。時點Ta1,該觸發訊號ONtrigger由高電壓準位轉換為低電壓準位,而該閂鎖訊號ONlatch、該溢位訊號event、該可程式脈衝訊號Pprogram以及該重置訊號D-FF Reset維持不變。於時點Tb,該閂鎖訊號ONlatch仍保持高電壓準位,該溢位訊號event由高電壓準位轉換為低電壓準位,因此該可程式脈衝訊號Pprogram由高電壓準位轉換低高電壓準位。於時點Tc,該重置訊號D-FF Reset由高電壓準位轉換為低電壓準位,該正反器21被重置,因此該閂鎖訊號ONlatch由高電壓準位轉換低高電壓準位。於時點Tc1,該重置訊號Reset由低電壓準位轉換為高電壓準位。於此,完成一個操作週期,該計時計數控制模組20回到初始狀態以等待下一個該觸發訊號ONtrigger。The operation method of the timing
於此實施例中,該計時計數控制模組20除了根據該觸發訊號ONtrigger對應產生該可程式脈衝訊號Pprogram,更產生作為該計時計數單元24之時脈訊號之該閘控時脈訊號gated clock,換言之,該計時計數控制模組20根據該觸發訊號ONtrigger產生一個或多個脈衝訊號。In this embodiment, the timing
在另一實施例中,可藉由節制 (enable/halt) 該計時計數單元24的計數與否來同步該計時計數單元24的動作。In another embodiment, the actions of the
在另一實施例中,該計時計數控制模組20可包括二個該計時計數單元(24A、24B),該等計時計數單元(24A、24B)彼此具有一計數起始差異值(例如:計時計數單元24B的計數值大於該計時計數單元24A),使該等計時計數單元(24A、24B)以相同時脈同時計數,並該觸發訊號ONtrigger直接鎖存該計時計數單元24B當時的值,並與該計時計數單元24A的值做比較,當該計時計數單元24A追上該計時計數單元24B時,產生該溢位訊號event。In another embodiment, the timing
綜上所述,由於本發明之該計時計數控制模組20可根據該觸發訊號ONtrigger即時產生該可程式脈衝訊號Pprogram,使該處理器100無須經由該內部核心邏輯區塊50進行運算,不受該內部核心邏輯區塊50能力或延遲的影響,即可快速且精準的產生周邊電路所需之該可程式脈衝訊號Pprogram,實現以低階處理器控制高階系統之功能,不僅減少系統控制成本,並達到提升控制精準度的目的。To sum up, because the
10:輸入單元
20、20a、20b:計時計數控制模組
21:正反器
22:第一邏輯閘
221:第一輸入端
222:第二輸入端
223:輸出端
23:第二邏輯閘
231:第一輸入端
232:第二輸入端
233:輸出端
24:計時計數單元
30:輸出單元
40、40a、40b:暫存器
50:內部核心邏輯區塊
100、100’:處理器
600:處理器
610:內部核心邏輯區塊
611:運算邏輯單元
620:周邊功能區塊
621:計時計數器
622:程式記憶體
623:暫存器
630:輸入輸出介面
631:輸入埠
632:輸岀埠
640:中斷產生器
CLK:時脈輸入端
Clock:內部時脈訊號
D:輸入端
event:溢位訊號
gated clock:閘控時脈訊號
ONtrigger:觸發訊號
ONlatch:閂鎖訊號
Pprogram:可程式脈衝訊號
Q:輸出端
R:重置端
D-FF Reset:重置訊號
S:設定端
Ta、Ta1、Tb、Tc、Tc1:時點
Vh:邏輯高電位
10:
圖1係本發明之實施例的系統架構方塊圖。 圖2係本發明之實施例的又一系統架構方塊圖。 圖3係本發明之計時計數控制模組的一實施例的架構方塊圖。 圖4係本發明之一實施例的時序示意圖。 圖5係一種已知的處理器之系統架構示意圖。 FIG. 1 is a block diagram of a system architecture according to an embodiment of the present invention. FIG. 2 is a block diagram of yet another system architecture according to an embodiment of the present invention. FIG. 3 is a structural block diagram of an embodiment of the timing counting control module of the present invention. FIG. 4 is a timing diagram of an embodiment of the present invention. FIG. 5 is a schematic diagram of a system architecture of a known processor.
10:輸入單元 10: Input unit
20:計時計數控制模組 20: Timing count control module
30:輸出單元 30: Output unit
40:暫存器 40: Scratchpad
50:內部核心邏輯區塊 50: Internal core logic block
100:處理器 100: Processor
ONtrigger:觸發訊號 ONtrigger: trigger signal
Pprogram:可程式脈衝訊號 Pprogram: Programmable pulse signal
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