CN114545801B

CN114545801B - Processor capable of directly starting output by external signal

Info

Publication number: CN114545801B
Application number: CN202011292707.6A
Authority: CN
Inventors: 梁伟成; 张平
Original assignee: Xinqiao Technology Co ltd
Current assignee: Xinqiao Technology Co ltd
Priority date: 2020-11-18
Filing date: 2020-11-18
Publication date: 2024-07-02
Anticipated expiration: 2040-11-18
Also published as: CN114545801A

Abstract

The invention relates to a processor capable of directly starting output by an external signal, which mainly comprises an input unit, an output unit and a timing counting control module, wherein the timing counting control module is electrically connected with the input unit and the output unit.

Description

Processor capable of directly starting output by external signal

Technical Field

The present invention relates to a processor, and more particularly, to a processor capable of directly starting output by an external signal.

Background

Generally, the processor of the microprocessor (Micro Processing Unit, MPU), microcontroller (Micro Control Unit, MCU) and the like is generally composed of an internal core logic block, a peripheral function block and an input/output interface, as shown in fig. 5, a known processor 600 includes an internal core logic block 610 (arithmetic logic unit 611), a peripheral function block 620 (timer counter 621, program memory 622, register 623) and an input/output interface 630 (input interface 631, output interface 632), wherein the processor 600 controls the operation of the peripheral function block 620 and signals transmitted or received by the input/output interface 630 through the internal core logic block 610. In order to optimize the performance of the processor 600, the processor 600 generally further includes an interrupt generator 640, where the interrupt generator 640 is configured to interrupt the processor 600 from executing an existing program, execute another program, and continue to execute the existing program after completing execution of the other program, without waiting for the execution of the existing program to complete by interrupting operation.

However, although the known processor has introduced the operation mode of the interrupt operation, the known processor still needs to wait for several tens of clock cycles before outputting the required signal, i.e. the existing interrupt operation still causes a delay in signal output, so the need for a better solution is still felt.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is a primary object of the present invention to provide a processor capable of directly starting output by external signals, which can generate programmable pulse signals according to external trigger signals without passing through an internal core logic block of the processor, thereby achieving the purpose of improving control accuracy.

The main technical means adopted to achieve the above purpose is that the processor capable of directly starting output by external signals comprises:

An input unit;

an output unit;

The timing counting control module is electrically connected with the input unit and the output unit, and the buffer is electrically connected with the timing counting control module; and

The internal core logic block is electrically connected with the register;

Wherein, the input unit obtains a trigger signal, the timing and counting control module controls the output unit to output a programmable pulse signal according to the trigger signal,

The processor does not control the output unit to output the programmable pulse signal by the internal core logic block.

By the above structure, the timing counting control module can generate the programmable pulse signal according to the trigger signal, so that the processor can generate the programmable pulse signal according to the external trigger signal without waiting for operation of the internal core logic block, thereby achieving the purpose of improving control accuracy.

For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and to the accompanying drawings, which are intended to illustrate the invention only and are not intended to limit the scope of the claims.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the description below are only some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a system architecture according to an embodiment of the present invention;

FIG. 2 is a block diagram of yet another system architecture according to an embodiment of the present invention;

FIG. 3 is a block diagram illustrating an embodiment of a timing count control module according to the present invention;

FIG. 4 is a timing diagram of one embodiment of the present invention; and

FIG. 5 is a system architecture diagram of a conventional processor.

Reference numerals

10. Timing and counting control module of input units 20, 20a and 20b

21. Flip-flop 22 first logic gate

221. First input end 222 second input end

223. Output 23 second logic gate

231. A first input end 232 and a second input end

233. Output end 24 timing and counting unit

30. Output units 40, 40a, 40b buffer

50. Internal core logic block 100, 100' processor

600. Processor 610 internal core logic block

611. Peripheral functional block of arithmetic logic unit 620

621. Timer counter 622 program memory

623. Input/output interface of buffer 630

631. Input interface 632 and output interface

640. Interrupt Generator CLK clock input

Clock internal Clock signal D input terminal

Event overflow signal gated clock signal

ONtrigger trigger signal ONlatch latch signal

Pprogram programmable pulse signal Q output terminal

R Reset terminal D-FF Reset signal

S sets the points of time of the ends Ta, ta1, tb, tc1

Vh logic high potential

Detailed Description

Referring to fig. 1, the processor 100 includes at least an input unit 10, a timing count control module 20, an output unit 30, a register 40 and an internal core logic block 50. The input unit 10 is configured to receive a trigger signal ONtrigger. The timing and counting control module 20 is electrically connected to the input unit 10, and is configured to receive the trigger signal ONtrigger through the input unit 10, the output unit 30 is electrically connected to the timing and counting control module 20, the output unit 30 is configured to output a programmable pulse signal Pprogram generated by the timing and counting control module 20, the buffer 40 is electrically connected to the timing and counting control module 20, and the internal core logic block 50 is electrically connected to the buffer 40. In other words, the timing count control module 20 is configured to control the output unit 30 to output the programmable pulse signal Pprogram according to the trigger signal ONtrigger. Therefore, the processor 100 can generate the programmable pulse signal Pprogram in real time according to the external trigger signal ONtrigger and the timing and counting control module 20 without waiting for the operation of the internal core logic block 50, so as to avoid the delay caused by the internal core logic block 50 and achieve the purpose of improving the accurate control.

In one embodiment, the trigger signal is an internal trigger signal of the processor 100 or an external trigger signal received by an external circuit of the processor 100.

In one embodiment, the processor 100 may be implemented as a controller applied to a switching power converter, a motor driving controller, or an auto-reaction controller, and the present invention is not limited thereto.

In one embodiment, the input unit 10 and the output unit 30 are input/output interfaces of the processor 100.

In an embodiment, the programmable pulse signal Pprogram is a pulse width modulated signal, a clock signal, or a single shot signal, and the invention is not limited thereto.

In one embodiment, the processor 100 may further be configured with a plurality of timing count control modules in order to accommodate circuit design. As shown in fig. 2, in the present embodiment, the processor 100' may be configured with two timing and counting control modules (i.e. the timing and counting control module 20a and the timing and counting control module 20 b), the timing and counting control module 20a is electrically connected to the buffer 40a, the timing and counting control module 20b is electrically connected to the buffer 40b, the buffer 40a and the buffer 40b are electrically connected to the internal core logic block 50, and in this embodiment, the timing and counting control module 20b may be used to implement a signal delay or counting function, and the invention is not limited thereto.

In another embodiment, the timing and counting control module 20a may be used to delay the trigger signal ONtrigger and the timing and counting control module 20b may be used to generate the programmable pulse signal Pprogram, which is not limited in the present invention.

For further explanation of the timing and counting control module 20 of the present invention, please refer to fig. 3, which at least includes a flip-flop 21, a first logic gate 22, a second logic gate 23 and a timing and counting unit 24, wherein the flip-flop 21 is electrically connected to the first logic gate 22, the first logic gate 22 is electrically connected to the second logic gate 23, and the timing and counting unit 24 is electrically connected to the first logic gate 22 and the second logic gate 23, wherein the embodiment disclosed in fig. 3 is for illustration only and not for limiting the present invention.

Further, the flip-flop 21 has an input terminal D, an output terminal Q, a clock input terminal CLK, a set terminal S, and a reset terminal R. The input terminal D and the set terminal S are used for receiving a logic high voltage Vh, the clock input terminal CLK is used for receiving the trigger signal ONtrigger, the output terminal Q is used for outputting a latch signal ONlatch, and the Reset terminal R is used for receiving a Reset signal D-FF Reset, so that the flip-flop 21 is used for being triggered by the trigger signal ONtrigger and changing the latch signal ONlatch (for example, changing the state of the latch signal ONlatch (for example, changing the state of the latch signal from a low voltage level to a high voltage level) according to the Reset signal D-FF Reset.

In one embodiment, the flip-flop is a D-type flip-flop, and the invention is not limited thereto.

The first logic gate 22 has a first input end 221, a second input end 222, and an output end 223, the first input end 221 is electrically connected to the timing counting unit 24 for receiving an overflow signal event, the second input end 222 is electrically connected to the output end Q of the flip-flop 21 and receives the latch signal ONlatch, the output end 223 is used for outputting the programmable pulse signal Pprogram, and the first logic gate 22 is used for generating the programmable pulse signal Pprogram according to the overflow signal event and the latch signal ONlatch.

The second logic gate 23 has a first input end 231, a second input end 232 and an output end 233, the first input end 231 is used for receiving an internal Clock signal Clock, the second input end 232 is electrically connected with the output end 223 of the first logic gate 22 and receives the programmable pulse signal Pprogram, the output end 233 is electrically connected with the timing counting unit 24 and is used for outputting a gate Clock signal gate Clock to the Clock input end of the timing counting unit 24, and the second logic gate 23 is used for generating the gate Clock signal gate Clock according to the internal Clock signal Clock and the programmable pulse signal Pprogram.

In an embodiment, the first logic gate 22 and the second logic gate 23 may be implemented by and gates, and the present invention is not limited thereto.

Further, the overflow signal event is a control signal generated when the timer counting unit 24 counts up or counts down an overflow. For example, at 16 carry, the overflow signal event is generated when the timing count unit 24 is counting up and overflows by FFFF counting up.

In one embodiment, the overflow signal event is a low level triggered signal, i.e. when the overflow signal event is converted from a high voltage level to a low voltage level, the corresponding circuit is caused to perform the corresponding operation.

The following description of the operation method of the timing and counting control module 20 will be given by taking the timing and counting control module 20 as an example in conjunction with fig. 4, and it should be noted that the following high voltage levels and low voltage levels are merely for illustrating the present invention, and are not limiting, and those skilled in the art can use the high voltage levels or the low voltage levels instead according to the requirements of the present invention. Referring to fig. 3 and fig. 4, first, at time Ta, the trigger signal ONtrigger is converted from a low voltage level to a high voltage level, so that the flip-flop 21 is driven to convert the latch signal ONlatch from the low voltage level to the high voltage level, and meanwhile, because the overflow signal event is a high voltage level, the programmable pulse signal Pprogram is converted from the low voltage level to the high voltage level because of the latch signal ONlatch and the overflow signal event, and meanwhile, the internal Clock signal Clock and the programmable pulse signal Pprogram generate the corresponding gate Clock signal. At time Ta1, the trigger signal ONtrigger is switched from a high voltage level to a low voltage level, and the latch signal ONlatch, the overflow signal event, the programmable pulse signal Pprogram, and the Reset signal D-FF Reset remain unchanged. At time Tb, the latch signal ONlatch still maintains the high voltage level, and the overflow signal event is converted from the high voltage level to the low voltage level, so that the programmable pulse signal Pprogram is converted from the high voltage level to the low high voltage level. At time Tc, the Reset signal D-FF Reset is changed from the high voltage level to the low voltage level, and the flip-flop 21 is Reset, so that the latch signal ONlatch is changed from the high voltage level to the low voltage level. At time Tc1, the Reset signal Reset is converted from a low voltage level to a high voltage level. Here, an operation cycle is completed, and the timer count control module 20 returns to the initial state to wait for the next trigger signal ONtrigger.

In this embodiment, the timing and counting control module 20 generates the gate clock signal gated as the clock signal of the timing and counting unit 24 in addition to correspondingly generating the programmable pulse signal Pprogram according to the trigger signal ONtrigger, in other words, the timing and counting control module 20 generates one or more pulse signals according to the trigger signal ONtrigger.

In another embodiment, the action of the timing counter unit 24 may be synchronized by throttling (enable/halt) the counting of the timing counter unit 24.

In another embodiment, the timing and counting control module 20 may include two timing and counting units, where the two timing and counting units have a counting start difference value (for example, the count value of the first timing and counting unit is greater than the count value of the second timing and counting unit), so that the two timing and counting units count simultaneously with the same clock, and the trigger signal ONtrigger directly latches the current value of the first timing and counting unit and compares the current value with the value of the second timing and counting unit, and when the second timing and counting unit catches up with the first timing and counting unit, the overflow signal event is generated.

In summary, since the timing and counting control module 20 of the present invention can generate the programmable pulse signal Pprogram in real time according to the trigger signal ONtrigger, the processor 100 can quickly and accurately generate the programmable pulse signal Pprogram required by the peripheral circuit without being affected by the capability or delay of the internal core logic block 50 without performing the operation through the internal core logic block 50, thereby realizing the function of controlling the higher-level system by the lower-level processor, not only reducing the system control cost, but also achieving the purpose of improving the control accuracy.

The foregoing is merely exemplary of the present invention and is not intended to limit the scope of the present invention.

Claims

1. A processor capable of directly enabling output by an external signal, comprising:

An input unit;

an output unit;

the first timing counting control module is electrically connected with the input unit and the output unit,

The buffer is electrically connected with the first timing and counting control module; and

The internal core logic block is electrically connected with the register;

Wherein the input unit obtains a trigger signal, the first timing and counting control module controls the output unit to output a programmable pulse signal according to the trigger signal,

Wherein the processor does not use an internal core logic block to control the output unit to output the programmable pulse signal; wherein the first timing count control module further comprises:

the flip-flop is provided with a clock input end, an output end and a reset end, wherein the clock input end receives the trigger signal, the output end outputs a latch signal, and the reset end receives a reset signal;

The first logic gate is provided with a first input end, a second input end and an output end, wherein the first input end receives an overflow signal, the second input end is electrically connected with the output end of the flip-flop and receives the latch signal, and the output end of the first logic gate outputs the programmable pulse signal;

A second logic gate having a first input, a second input, and an output, the first input of the second logic gate receiving an internal clock signal, the second input of the second logic gate being electrically connected to the input of the first logic gate and receiving the programmable pulse signal, the output of the second logic gate outputting a gating clock signal; and

The timing counting unit is electrically connected with the first input end of the first logic gate and the output end of the second logic gate.

2. The processor of claim 1, wherein the processor further comprises:

The second timing and counting control module is electrically connected with the first timing and counting control module and the output unit and is arranged between the first timing and counting control module and the output unit; and

The second register is electrically connected with the second timing and counting control module and the internal core logic block and is configured between the second timing and counting control module and the internal core logic block.

3. The processor of claim 1, wherein at a first time point, the trigger signal, the latch signal, the overflow signal, the reset signal, and the programmable pulse signal are at a first voltage level; at a second time point, the overflow signal is converted from the first voltage level to a second voltage level, the latch signal and the reset signal are the first voltage level, the programmable pulse signal is converted from the first voltage level to the second voltage level, and the trigger signal is the second voltage level; at a third time point, the reset signal and the latch signal are converted from the first voltage level to the second voltage level, and the trigger signal, the programmable pulse signal and the overflow signal are the second voltage level, wherein the first time point is earlier than the second time point, and the second time point is earlier than the third time point.

4. The processor of claim 3, wherein the trigger signal is converted from the first voltage level to the second voltage level at a fourth time point, the fourth time point being later than the first time point and earlier than the second time point.

5. The processor of claim 4, wherein the reset signal is converted from the second voltage level to the first voltage level at a fifth time point, the fifth time point being later than the third time point.

6. The processor of one of claims 3,4 or 5, wherein the first voltage level is a high voltage level and the second voltage level is a low voltage level.

7. The processor of claim 1, wherein the flip-flop is a D-type flip-flop.

8. The processor of claim 1, wherein the first logic gate and the second logic gate are and gates.

9. The processor of claim 1, wherein the operation of the timing counter is synchronized with throttling the count of the timing counter.

10. The processor of claim 1, wherein the first timing count control module comprises two timing count units, the timing count units having count start difference values from each other, and wherein the trigger signal latches the value of one of the timing count units, and wherein the overflow signal is generated when the other one of the timing count units catches up with the value of one of the timing count units.

11. The processor of claim 1, wherein the trigger signal is an external trigger signal from outside the processor.

12. The processor of claim 1, wherein the programmable pulse signal is a pulse width modulated signal, a clock signal, or a single click signal.

13. The processor of claim 1, wherein the first timing count control module generates a plurality of pulse signals including the programmable pulse signal based on the trigger signal.