CN111985174B - RT latch and latching method - Google Patents
RT latch and latching method Download PDFInfo
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- CN111985174B CN111985174B CN202010914490.1A CN202010914490A CN111985174B CN 111985174 B CN111985174 B CN 111985174B CN 202010914490 A CN202010914490 A CN 202010914490A CN 111985174 B CN111985174 B CN 111985174B
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Abstract
The invention relates to an RT latch and a latching method, wherein the RT latch comprises: a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch. The output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the latches, so that the RT latches send response signals to the upper stage RT latch and request signals to the lower stage RT latch simultaneously, and the high-speed parallel operation of the RT latches is ensured. Meanwhile, the invention only uses two SR latches, one NOT gate, one three-input NAND gate and one AND gate, and only uses 7 gate units, and the signal latch can be realized by 30 transistors, so that the circuit is simple and the production cost is low.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an RT latch and a latching method.
Background
With the proposal of many-core architecture, researchers have proposed a Global Asynchronous Local Synchronous (GALS) system in order to solve the problem of multiple clock domains and the problem of reusability of IP core module updates in the system. The asynchronous mode can well solve the problem of clock synchronization between single modules. Meanwhile, the sampling period can be adjusted among the modules according to the clock frequency of the modules, and the power consumption of the system is greatly reduced. The asynchronous controller mainly realizes the functions of the communication and coordination circuit through a handshake protocol. Is generally applied to a micro pipeline structure which is a common data path structure in an SoC network.
In the prior art, in consideration of the need of adopting a handshake protocol for communication, latch circuits based on C unit design are mainly available, the transistors are more, the circuit scale is generally larger, the cost is high, the circuit design is complex, and the energy efficiency is low. Another is a circuit based on delay matching design, such as a click controller used in Loihi (first-line neuro-mimicry chip issued by Intel) of Intel, but the method needs to consider delay matching between a control path and a data path, and uses a trigger to ensure normal operation of the circuit, so that the circuit design is complex, and the circuit cost and the power consumption need to be further optimized.
Disclosure of Invention
The invention aims to provide a latch and a latching method, which are used for reducing the production cost and improving the operation speed.
In order to achieve the above object, the present invention provides the following solutions:
an RT latch comprising: a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch;
the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch;
the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of a first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and a data path of the RT latch;
one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate;
one output end of the second SR latch is connected with the input end of the NOT gate in the previous stage of the RT latch, and the other output end of the second SR latch is connected with the other input end of the AND gate.
Optionally, the first SR latch includes a first nand gate and a second nand gate, and the second SR latch includes a third nand gate and a fourth nand gate;
the input end of the NOT gate is connected with the output end of a third NOT gate in the RT latch of the next stage; the output end of the NOT gate is connected with one input end of the second NOT gate;
the third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the upper stage of the RT latch; the output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate;
the other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate; the output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the RT latch of the next stage;
the other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate; the output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the RT latch of the upper stage.
Optionally, the first nand gate, the second nand gate, the third nand gate and the fourth nand gate are two-input nand gates.
Optionally, the RT latch communicates using a 4-phase bundled data protocol.
A latching method is applied to the latch and comprises the following steps:
acquiring a request signal sent by a previous stage RT latch;
according to the request signal sent by the previous stage RT latch, a latch signal is sent out, and data are latched;
after the data latch, a response signal is sent to the upper stage RT latch, and a request signal is sent to the lower stage RT latch.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses an RT latch and a latching method, wherein the RT latch comprises an NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch; the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch; the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of a first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and a data path of the latch; one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate; one output end of the second SR latch is connected with the input end of the NOT gate in the previous stage of the RT latch, and the other output end of the second SR latch is connected with the other input end of the AND gate.
In the invention, the output ends of the three-input NAND gate are connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the latch, so that the RT latch sends out a response signal to the upper stage RT latch and sends out a request signal to the lower stage RT latch at the same time, thereby ensuring the high-speed parallel operation of the RT latches.
The invention only uses two SR latches, one NOT gate, one three-input NAND gate and one AND gate, only uses 7 gate units, and can realize signal latching by 30 transistors, and has simple circuit and low production cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of an RT latch according to an embodiment of the present invention;
FIG. 2 is a simplified diagram of an RT latch according to an embodiment of the present invention;
FIG. 3 is a diagram of an example application of an RT latch provided by an embodiment of the invention;
FIG. 4 is a STG diagram of handshake protocol signals in a conventional C-unit control latch according to an embodiment of the present invention;
FIG. 5 is a STG diagram of a conventional RT control latch handshake protocol signal provided by an embodiment of the present invention;
fig. 6 is a STG diagram of an RT controlled latch according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a latch and a latching method, which are used for reducing the production cost and improving the operation speed.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
The internal circuit of the latch is designed based on the Relative Timing (RT). Fig. 1 is a circuit diagram of an RT latch according to an embodiment of the present invention, as shown in fig. 1, the circuit includes: a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch. The input end of the NOT gate is connected with one output end of a second SR latch in the next stage of RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch. The second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of the first SR latch in the previous stage RT latch. The output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and the data path of the RT latch. One output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate. One output end of the second SR latch is connected with the input end of the NOT gate in the previous stage RT latch, and the other output end of the second SR latch is connected with the other input end of the AND gate.
In this embodiment, the first SR latch includes a first and second nand gate, and the second SR latch includes a third and fourth nand gate. The first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate are two-input NAND gates. The input end of the NOT gate is connected with the output end of a third NOT gate in the next stage of RT latch, and the output end of the NOT gate is connected with one input end of the second NOT gate. The third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the previous stage RT latch. The output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate. The other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate. The output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the next stage RT latch. The other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate. The output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the previous stage RT latch. Two SR latches in the latch are used for the transfer of handshake signals, while and gate, not gate and three-input nand gate are used to realize correct circuit logic, which is equivalent to adding constraint to the triggering of handshake signals.
Fig. 2 is a simplified diagram of an RT latch according to an embodiment of the present invention, as shown in fig. 2, in the diagram, rin is an RT latch request signal input by an RT latch circuit of a previous stage, ain is a response signal of the RT latch circuit of the previous stage, rout is an output request signal of the RT latch circuit of a next stage to the RT latch circuit of the next stage, and Aout is a response signal of the RT latch circuit of the next stage to the RT latch circuit of the next stage. Lt denotes a control signal generated by the RT latch for controlling the transmission of signals in the data path.
The specific working process of the RT latch provided in this embodiment is as follows:
assuming that the initial states of all signals (Rin, ain, rout, aout) are (0000), the initial states of the internal signals (a, b, X1, X2, and X3) are all 1. Lt=x1, the initial state is 1, the control signal is valid when Lt is 0, and the initial control signal is invalid. When the data of the previous stage RT latch is ready, the Rin of the RT control latch is pulled high to a high level, and after passing through a 3-input NAND gate, the X1 signal is pulled low, so that the Ain signal is pulled high, namely a response signal is generated for the previous stage RT latch, and the left handshake is completed. At the same time the Rout signal is pulled high, since the Rout signal is the request signal output to the next stage RT latch, indicating that the data is ready at this stage, then a handshake cycle is completed as long as the Aout signal waiting for the next stage RT latch to return is set to 1, the lt signal is set to inactive.
Since the time that the input Rin signal passes from X1 to the outputs of two identical 2-input nand gates is the same, the RT latch will simultaneously issue a response signal Ain to the previous stage RT latch and a request signal to the next stage RT latch. That is, instead of waiting for the stage circuit to latch the data (Ain pulled high to 1) before issuing the Rout request signal, the RT latch latches the data (Lt is asserted) and simultaneously notifies the next stage RT latch to prepare to accept the data (Rout pulled high to 1). This design enables the RT latches to operate in parallel at high speed.
The RT latch provided in this embodiment communicates using a 4-phase bundled data protocol. Fig. 3 is an exemplary diagram of an application of an RT latch according to an embodiment of the invention, as shown in fig. 3. The working principle (data latching method) of the RT latch in application is as follows:
based on the intermediate stage RT latch, when the data of the previous stage RT latch is ready, the previous stage RT latch sends out a request req to the current RT latch. The RT latch then issues a latch signal Lt to latch the data to the current RT latch. After the data is latched, the current RT latch issues a response signal ack again, and at the same time, the current RT latch issues a request req to the next stage to inform that the data of the current stage is ready, and the next stage RT latch can collect. After the next stage RT latch collects data, a reply signal ack will be sent to inform the current stage.
The basic principle of the RT latch circuit, the conventional RT latch, is described as follows:
the operation of the RT latch circuit obeys a certain Relative Timing (Relative Timing) relationship, i.e. the occurrence of signals is prioritized from signal to signal. Assuming event a has priority before event B, event B must occur after event a occurs. This event triggering mechanism, like the clock in the synchronous circuit, triggers the register when the clock arrives, except that the clock trigger is replaced by an event trigger here, so called relative timing. This timing constraint is guaranteed by the RT circuit itself, a constraint relationship that exists itself.
STG diagram (Singal Transition Graph, signal transition diagram) is used to describe concurrency and sequency of asynchronous signals, i.e., the relative timing relationship between signals. Fig. 4 is a STG diagram of handshake protocol signals in a conventional C-unit control latch according to an embodiment of the present invention, where signal rin+ in the STG diagram represents a transition from 0 to 1 of Rin, and Rin-represents a transition from 1 to 0 of Rin. The arrow points from rin+ to ain+, meaning that rin+ must occur before ain+ occurs. As can be seen from the STG graph, to ensure that the next stage receives data (aout+), the next stage new data can only come (rin+), the conventional C-cell latch uses aout+ to Ain-relationship chain constraints. After this constraint is canceled, the STG diagram in fig. 5 is obtained, and the two pairs of handshake signals (Rin, ain) and (Rout, aout) are completely independent of each other, so that the parallelism and the operation speed of the system operation can be greatly improved. However, there is a problem in that the next group (RIn, ain) may occur again before the handshake is completed by (Rout, aout), i.e. new data arrives again in case the current data has not yet been received, which may lead to data transmission errors.
The RT latch provided in this embodiment can avoid this problem, because the circuit logic of the RT latch circuit itself can guarantee this timing assumption: aout+ precedes Ain-.
The present invention classifies timing hypotheses (signaling logic) into two types, one for ensuring that data moves correctly between stages, as in conventional asynchronous designs in bundled data protocols. The other is used inside the latch. For example, for the timing in FIG. 1, rout+ must precede X1+, b-and Rin-, while ain+ must precede X1+, a-and Aout-. Aout+ to Ain-relation chain constraints are guaranteed. From the circuit point of view, 8 gates are sequentially passed from rin+ to aout+, 13 gates are passed from rin+ to ain+, and aout+ occurs before ain+ from the signal propagation gate number point of view. Fig. 6 is a STG diagram of an RT controlled latch according to an embodiment of the invention.
Because the delay of each gate has a difference, a time sequence test is performed on the delay, and the delay time of each gate circuit is measured. The result shows that the signal transmission time T (rin+to aout+) is always greater than T1 (rin+to Ain-), which proves that the RT latch circuit provided by the embodiment can normally operate without adding a delay unit or other circuit logic.
Meanwhile, the Montecello method was adopted, and research was conducted at process corners (tt, ff, ss, sf, fs) to gradually decrease Vdd from 1.2V and test the performance of each circuit. The minimum operating voltage at which each latch controller circuit can maintain the correct logic function is obtained through experimentation, and table 1 is the minimum operating voltage that satisfies the conditions of each process corner. As can be seen from table 1, other circuits, such as long hold control latch circuits, can only have a supply voltage as low as 0.7V at the minimum, and half-decoupled control latch circuits can only have a supply voltage above 0.75V. The RT latch controller circuit in the present application can work normally at all process corners as low as vdd=0.275V, with good supply voltage robustness.
TABLE 1
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
(1) The RT latch provided by the invention introduces timing assumptions to enable the control signals to work in parallel. The method of timing assumption generated by the gate level delay attribute (gate number, different delays on different gates) of the circuit is utilized to ensure the sequence of signal generation instead of adding extra circuit logic design, so that the hardware cost can be reduced better.
(2) The RT latch in the invention does not need to be designed based on a traditional C unit, can be realized in a standard library, and is better suitable for the traditional EDA design flow.
(3) Compared with the traditional control latch circuit (27-36 transistors) and click circuit (84 transistors) based on the C unit design, the RT latch provided by the invention only uses 7 gates (30 transistors), the number of transistors is reduced by about 2 times on average, the circuit is simpler, and the production cost is lower.
(4) The RT latch circuit in the invention can normally work at all process corners (tt, ss, ff, sf, fs) based on the working voltage of 0.275V, normally processes data, and has good power supply voltage robustness.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the core concept of the invention; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (5)
1. An RT latch, comprising: a NOT gate, a three-input NAND gate, an AND gate, a first SR latch and a second SR latch;
the input end of the NOT gate is connected with one output end of a second SR latch in the next stage of the RT latch, and the output end of the NOT gate is connected with the first input end of the three-input NAND gate and one input end of the first SR latch;
the second input end of the three-input NAND gate is connected with the output end of the AND gate, and the third input end of the three-input NAND gate is connected with one input end of the second SR latch and one output end of a first SR latch in the previous stage of the RT latch; the output end of the three-input NAND gate is connected with the other input end of the first SR latch, the other input end of the second SR latch and a data path of the RT latch;
one output end of the first SR latch is connected with a third input end of a three-input NAND gate in the next stage of the RT latch, and the other output end of the first SR latch is connected with one input end of the AND gate;
one output end of the second SR latch is connected with the input end of the NOT gate in the previous stage of the RT latch, and the other output end of the second SR latch is connected with the other input end of the AND gate.
2. The RT latch of claim 1, wherein the first SR latch comprises a first nand gate and a second nand gate, the second SR latch comprises a third nand gate and a fourth nand gate;
the input end of the NOT gate is connected with the output end of a third NOT gate in the RT latch of the next stage; the output end of the NOT gate is connected with one input end of the second NOT gate;
the third input end of the three-input NAND gate is connected with one input end of the fourth NAND gate and the output end of the first NAND gate in the upper stage of the RT latch; the output end of the three-input NAND gate is connected with one input end of the first NAND gate and one input end of the third NAND gate;
the other input end of the first NAND gate is connected with the output end of the second NAND gate and one input end of the AND gate; the output end of the first NAND gate is connected with the other input end of the second NAND gate and the third input end of the three-input NAND gate in the RT latch of the next stage;
the other input end of the third NAND gate is connected with the output end of the fourth NAND gate and the other input end of the AND gate; the output end of the third NAND gate is connected with the other input end of the fourth NAND gate and the input end of the NOT gate in the RT latch of the upper stage.
3. The RT latch of claim 2, wherein the first nand gate, the second nand gate, the third nand gate, and the fourth nand gate are two-input nand gates.
4. The RT latch of claim 1, wherein the RT latch communicates using a 4-phase bundled data protocol.
5. A latching method as claimed in any one of claims 1 to 4, applied to a latch comprising:
acquiring a request signal sent by a previous stage RT latch;
according to the request signal sent by the previous stage RT latch, a latch signal is sent out, and data are latched;
after the data latch, a response signal is sent to the upper stage RT latch, and a request signal is sent to the lower stage RT latch.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USH1796H (en) * | 1996-05-02 | 1999-07-06 | Sun Microsystems, Inc. | Method and circuit for eliminating hold time violations in synchronous circuits |
| CN106291322A (en) * | 2016-08-08 | 2017-01-04 | 宁波大学 | A kind of cmos circuit aging sensor using delay structure for amplifying |
| CN108170616A (en) * | 2016-12-07 | 2018-06-15 | 上海复旦微电子集团股份有限公司 | The system that cross clock domain signal transmission is realized using latch |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100593139B1 (en) * | 2004-12-30 | 2006-06-26 | 주식회사 하이닉스반도체 | Counter circuit for controlling off chip driver and method for changing output current value of off chip driver using the same |
| US8508276B2 (en) * | 2010-08-25 | 2013-08-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including latch circuit |
-
2020
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USH1796H (en) * | 1996-05-02 | 1999-07-06 | Sun Microsystems, Inc. | Method and circuit for eliminating hold time violations in synchronous circuits |
| CN106291322A (en) * | 2016-08-08 | 2017-01-04 | 宁波大学 | A kind of cmos circuit aging sensor using delay structure for amplifying |
| CN108170616A (en) * | 2016-12-07 | 2018-06-15 | 上海复旦微电子集团股份有限公司 | The system that cross clock domain signal transmission is realized using latch |
Non-Patent Citations (2)
| Title |
|---|
| 1.6 GHz电荷泵锁相环的设计;陈勇 等;《微电子学》;第40卷(第4期);第531-534页 * |
| 一种新颖的抗辐射加固SR锁存器设计;苏霖 等;《微电子学与计算机》;第34卷(第9期);第136-140页 * |
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