TW202203564A - Flyback converter and switching controller circuit and control method thereof - Google Patents

Flyback converter and switching controller circuit and control method thereof Download PDF

Info

Publication number
TW202203564A
TW202203564A TW110103901A TW110103901A TW202203564A TW 202203564 A TW202203564 A TW 202203564A TW 110103901 A TW110103901 A TW 110103901A TW 110103901 A TW110103901 A TW 110103901A TW 202203564 A TW202203564 A TW 202203564A
Authority
TW
Taiwan
Prior art keywords
signal
switching
period
primary side
waveform
Prior art date
Application number
TW110103901A
Other languages
Chinese (zh)
Other versions
TWI783365B (en
Inventor
陳裕昌
張煒旭
林昆餘
楊大勇
Original Assignee
立錡科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 立錡科技股份有限公司 filed Critical 立錡科技股份有限公司
Priority to US17/356,767 priority Critical patent/US11496063B2/en
Publication of TW202203564A publication Critical patent/TW202203564A/en
Application granted granted Critical
Publication of TWI783365B publication Critical patent/TWI783365B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Details Of Television Scanning (AREA)

Abstract

A flyback converter includes a transformer, a primary side switch, a secondary side switch and a switching controller circuit. A secondary side switching signal includes a synchronous rectifying pulse and a ZVS (zero voltage switching) pulse for synchronous rectification and ZVS of the primary side switch. The ZVS pulse is enabled according to a first characteristic of a resonant waveform and a primary side switching signal is enabled according to a second characteristic of the resonant waveform. When an output current rises, the primary side switching signal is disabled during an inhibition period such that the primary side switching signal does not overlap the ZVS pulse to avoid both the primary side switch and the secondary side switch conductive at the same time. The inhibition period relates to a rising edge of the primary side switching signal and a resonant period of the resonant waveform.

Description

返馳式轉換器及其切換控制電路與控制方法Flyback converter and switching control circuit and control method thereof

本發明係有關一種返馳式轉換器，特別是指一種具有零電壓切換功能且可避免一次側與二次側短路電流的返馳式轉換器。本發明也有關於用於返馳電源供應器的控制電路與控制方法。The present invention relates to a flyback converter, in particular to a flyback converter which has a zero-voltage switching function and can avoid short-circuit currents on the primary side and the secondary side. The present invention also relates to a control circuit and a control method for a flyback power supply.

圖1A與圖1B顯示先前技術之返馳式轉換器(返馳式轉換器1001A與1001B)。其中一次側控制電路80用以產生一次側切換訊號S1C，藉此控制一次側開關S1以切換功率變壓器10而產生輸出電壓Vo，二次側控制電路200用以產生二次側切換訊號S2C，以控制二次側開關S2而進行二次側的同步整流以及零電壓切換(ZVS, zero voltage switching)。返馳式轉換器1001A與1001B中的二次側開關S2分別位於二次側繞組的下側與上側。1A and 1B show a prior art flyback converter (flyback converters 1001A and 1001B). The primary side control circuit 80 is used to generate the primary side switching signal S1C, thereby controlling the primary side switch S1 to switch the power transformer 10 to generate the output voltage Vo, and the secondary side control circuit 200 is used to generate the secondary side switching signal S2C to The secondary side switch S2 is controlled to perform synchronous rectification and zero voltage switching (ZVS, zero voltage switching) on the secondary side. The secondary side switches S2 in the flyback converters 1001A and 1001B are located on the lower side and the upper side of the secondary side windings, respectively.

圖2顯示對應於圖1A與圖1B先前技術之返馳式轉換器的操作波形示意圖。本實施例中，本發明之返馳式轉換器操作於不連續導通模式(DCM – Discontinuous Conduction Mode)。返馳式轉換器1001A或1001B的二次側切換訊號S2C具有同步整流脈波PSR以及零電壓切換（zero voltage switching，ZVS）脈波PZV，在一次側開關S1導通後又再度關斷時，同步整流脈波PSR用以控制同步整流開關S2於功率變壓器10的去磁階段導通以達成二次側的同步整流，另一方面，零電壓切換脈波PZV則用以達成前述之一次側開關S1的零電壓切換。FIG. 2 is a schematic diagram showing the operation waveforms of the flyback converter of the prior art corresponding to FIGS. 1A and 1B . In this embodiment, the flyback converter of the present invention operates in a discontinuous conduction mode (DCM - Discontinuous Conduction Mode). The secondary side switching signal S2C of the flyback converter 1001A or 1001B has a synchronous rectification pulse PSR and a zero voltage switching (ZVS) pulse PZV. When the primary side switch S1 is turned on and then turned off again, the synchronization The rectification pulse PSR is used to control the synchronous rectification switch S2 to be turned on during the demagnetization stage of the power transformer 10 to achieve the synchronous rectification of the secondary side. On the other hand, the zero voltage switching pulse PZV is used to achieve the aforementioned primary side switch S1 . Zero voltage switching.

此先前技術中，採用了「波峰/波谷鎖定」的技術，根據輸出電流的位準，適應性地選擇諧振波形（例如一次側開關電壓VDS1於DCM時的諧振波形）諧振時一波形特徵，一次側開關電壓VDS1於DCM時的諧振波形之某序位的波峰（例如VDS1的第三個波峰P3），開始前述的零電壓切換脈波PZV。此外，一次側控制電路80與二次側控制電路90還根據上述的諧振波形的另一特徵，例如鄰接序位的波谷（例如VDS1的第四個波谷V4）而同步一次側開關S1的導通時點。藉此，此先前技術可使一次側開關S1與二次側開關S2皆達到零電壓切換，以提高電源轉換效率，且得以在無需額外的隔離通信路徑（例如脈波變壓器）的條件下， 使一次側開關S1與二次側開關S2的開關時間彼此同步且不重疊，避免同時導通而造成短路電流。In this prior art, the technique of "peak/valley locking" is adopted to adaptively select the resonant waveform (such as the resonant waveform of the primary side switching voltage VDS1 in DCM) according to the level of the output current. The peak of a certain sequence of the resonant waveform of the side switching voltage VDS1 in DCM (eg, the third peak P3 of VDS1 ) starts the aforementioned zero-voltage switching pulse PZV. In addition, the primary-side control circuit 80 and the secondary-side control circuit 90 also synchronize the turn-on timing of the primary-side switch S1 according to another characteristic of the above-mentioned resonant waveform, such as a valley adjacent to the sequence (eg, the fourth valley V4 of VDS1 ) . In this way, the prior art enables both the primary side switch S1 and the secondary side switch S2 to achieve zero-voltage switching, so as to improve the power conversion efficiency, and to enable the The switching times of the primary side switch S1 and the secondary side switch S2 are synchronized with each other and do not overlap, so as to avoid short-circuit current caused by simultaneous conduction.

然而，在某些負載變化的情況下，仍會造成一次側開關S1與二次側開關S2同時導通而造成短路電流，如圖3所示，此為該先前技術的缺點。圖3顯示對應於圖1A與圖1B先前技術之返馳式轉換器的操作波形示意圖。在切換週期[n]時的負載電流Io，在切換週期[n+1]時加大，因負載電流加大，造成一次側S1開關訊號S1C提前導通，此時如果二次側S2C的PVZ訊號如果還維持上一切換週期的導通時間，將造成一次側開關及二次側開關同時導通，造成短路，燒毁轉換器。However, under certain load changes, the primary-side switch S1 and the secondary-side switch S2 are still turned on at the same time, resulting in a short-circuit current, as shown in FIG. 3 , which is a disadvantage of the prior art. FIG. 3 is a schematic diagram showing the operation waveforms of the flyback converter of the prior art corresponding to FIGS. 1A and 1B . The load current Io during the switching period [n] increases during the switching period [n+1]. Due to the increased load current, the switching signal S1C of the primary side S1 is turned on in advance. At this time, if the PVZ signal of the secondary side S2C is turned on in advance If the on-time of the previous switching cycle is also maintained, the primary side switch and the secondary side switch will be turned on at the same time, resulting in a short circuit and burning the converter.

相較於前述的先前技術，本發明除了可使一次側開關S1與二次側開關S2皆達到零電壓切換，且得以使一次側開關S1與二次側開關S2的開關時間同步之外，還可在各種負載變化下，有效地避免一次側開關S1與二次側開關S2同時導通而造成的短路電流。Compared with the aforementioned prior art, the present invention not only enables the primary side switch S1 and the secondary side switch S2 to achieve zero-voltage switching, and enables the switching times of the primary side switch S1 and the secondary side switch S2 to be synchronized, but also Under various load changes, the short-circuit current caused by the simultaneous conduction of the primary side switch S1 and the secondary side switch S2 can be effectively avoided.

就其中一個觀點言，本發明提供了一種切換控制電路，用以控制一返馳式轉換器，以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包括一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間；一一次側開關，用以切換該功率變壓器的一一次側繞組；以及一二次側開關，用以切換該功率變壓器的一二次側繞組；該切換控制電路包含：一一次側控制電路，用以產生一一次側切換訊號，以一切換週期控制該一次側開關；以及一二次側控制電路，用以產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換；其中，該二次側控制電路根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波，其中，該一次側控制電路根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵；其中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。In one aspect, the present invention provides a switching control circuit for controlling a flyback converter to convert an input power source to generate an output power source. The flyback converter includes a power transformer to electrically Insulatedly coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a power transformer a secondary side winding; the switching control circuit includes: a primary side control circuit for generating a primary side switching signal to control the primary side switch with a switching cycle; and a secondary side control circuit for generating a The secondary side switching signal is used to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectifying (Synchronous Rectifying, SR) pulse wave and a zero voltage switching (zero voltage switching, ZVS) pulse wave, the synchronous The rectification pulse is used to control the secondary side switch to conduct a synchronous rectification period to achieve secondary side synchronous rectification, and the zero voltage switching pulse is used to control the secondary side switch to conduct a zero voltage switching period, thereby enabling the primary The side switch achieves zero-voltage switching; wherein, the secondary-side control circuit enables the zero-voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary-side control circuit is based on the The primary side switching signal is enabled by the second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; wherein, when the output power of the output power supply Or when the output current is rising compared to the steady state, in the current switching cycle, the primary-side control circuit enables the primary-side switching signal according to the third waveform characteristic of the DCM resonant waveform to avoid the primary-side switching Turning on at the same time as the secondary side switch, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching cycle.

在一較佳實施例中，該DCM諧振波形對應於該一次側開關的汲源極電壓之諧振波形，其中該第二波形特徵對應於該DCM諧振波形的第V個波谷，該第三波形特徵對應於該DCM諧振波形的第W個波谷，其中W大於V。In a preferred embodiment, the DCM resonant waveform corresponds to the resonant waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the Vth trough of the DCM resonant waveform, and the third waveform characteristic Corresponds to the Wth trough of the DCM resonant waveform, where W is greater than V.

在一較佳實施例中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路控制該一次側切換訊號，於一禁止時段內禁能該一次側切換訊號，使得該一次側切換訊號與該零電壓切換脈波於該禁止時段不重疊，以避免該一次側開關與該二次側開關同時導通；其中該禁止時段相關於前一個該切換週期內的該一次側切換訊號之上升緣以及該DCM諧振波形的一諧振週期。In a preferred embodiment, when the output power or output current of the output power supply increases compared to the steady state, in the current switching cycle, the primary side control circuit controls the primary side switching signal, and when a disable The primary side switching signal is disabled during the period, so that the primary side switching signal and the zero-voltage switching pulse do not overlap during the forbidden period, so as to prevent the primary side switch and the secondary side switch from being turned on at the same time; wherein the forbidden period is related to The rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform.

在一較佳實施例中，該DCM諧振波形的該諧振週期相關於該一次側繞組的電感值與該一次側開關的雜散電容值。In a preferred embodiment, the resonant period of the DCM resonant waveform is related to the inductance value of the primary side winding and the stray capacitance value of the primary side switch.

在一較佳實施例中，該一次側控制電路根據該輸出電源而產生一導通控制訊號，用以觸發該一次側切換訊號且決定該一次側開關於每一切換週期中的導通時點與導通時段，其中該一次側控制電路於每一切換週期中，產生示意一預禁止時段的一預禁止訊號；其中當該導通控制訊號在該預禁止時段內轉為致能時，該一次側控制電路產生示意該禁止時段的一禁止訊號，以於該禁止時段內遮罩該導通控制訊號而禁能該一次側切換訊號之觸發；其中該預禁止訊號根據前一個該切換週期的該一次側切換訊號的上升緣以及該諧振週期而產生，其中該預禁止時段涵蓋至少前一個該切換週期的該零電壓切換脈波。In a preferred embodiment, the primary side control circuit generates a conduction control signal according to the output power to trigger the primary side switching signal and determine the conduction time point and conduction period of the primary side switch in each switching cycle , wherein the primary side control circuit generates a pre-inhibition signal indicating a pre-inhibition period in each switching cycle; wherein when the conduction control signal turns to be enabled within the pre-inhibition period, the primary side control circuit generates A prohibition signal indicating the prohibition period is used to mask the conduction control signal during the prohibition period to disable the triggering of the primary side switching signal; wherein the pre-inhibition signal is based on the previous switching cycle of the primary side switching signal. The rising edge and the resonant period are generated, wherein the pre-inhibition period covers the zero-voltage switching pulse of at least one preceding switching period.

在一較佳實施例中，當該導通控制訊號在該預禁止時段之外轉為致能時，允許該導通控制訊號觸發該一次側切換訊號。In a preferred embodiment, when the conduction control signal is turned to be enabled outside the pre-inhibition period, the conduction control signal is allowed to trigger the primary side switching signal.

在一較佳實施例中，當該禁止訊號被致能後，根據相關於該諧振波形的一諧振同步訊號計時對應的該禁止時段，使得該禁止時段至少維持一個該諧振週期。In a preferred embodiment, after the prohibition signal is enabled, the corresponding prohibition period is timed according to a resonance synchronization signal related to the resonant waveform, so that the prohibition period is maintained for at least one resonance period.

在一較佳實施例中，當該禁止訊號被致能後，以該諧振波形相關訊號計時對應的該禁止時段，使得於該禁止時段結束後，該一次側切換訊號於該DCM諧振波形的第三波形特徵而被致能，而達成零電壓切換，其中該第三波形特徵晚於對應於前一個切換週期內的該第二波形特徵。In a preferred embodiment, after the disable signal is enabled, the corresponding disable period is timed by the resonant waveform related signal, so that after the disable period ends, the primary side switching signal is at the first position of the DCM resonant waveform. Three waveform features are enabled to achieve zero voltage switching, wherein the third waveform feature is later than the second waveform feature corresponding to the previous switching period.

在一較佳實施例中，當該禁止訊號被致能時，於當前之該切換週期內，該一次側切換訊號的致能時點與該零電壓切換脈波相距1.5個該諧振週期。In a preferred embodiment, when the disable signal is enabled, in the current switching period, the enabling time point of the primary side switching signal is 1.5 resonant periods away from the zero-voltage switching pulse.

在一較佳實施例中，該一次側控制電路包括：一斜坡產生電路，用以於每一該切換週期中，該一次側切換訊號的膝點開始產生一基礎斜坡訊號；一波谷選擇電路，用以於該一次側切換訊號的上升緣取樣與保持該基礎斜坡訊號而產生一波谷記憶訊號，且，用以產生一第一斜坡訊號與一第二斜坡訊號，其中該第一斜坡訊號與該第二斜坡訊號分別與該基礎斜坡訊號具有對應的一第一偏移位準與一第二偏移位準；以及一禁止訊號產生電路，用以比較該第一斜坡訊號與該基礎斜坡訊號，以及比較該第二斜坡訊號與該基礎斜坡訊號而產生該預禁止訊號，其中該預禁止時段對應於該基礎斜坡訊號介於該第一斜坡訊號與該第二斜坡訊號的期間，且，用以判斷該導通控制訊號的上升緣是否發生於該預禁止時段內而產生該禁止訊號。In a preferred embodiment, the primary-side control circuit includes: a ramp generating circuit for generating a basic ramp signal at the knee point of the primary-side switching signal in each switching cycle; a valley selection circuit, It is used for sampling and maintaining the basic ramp signal at the rising edge of the primary side switching signal to generate a valley memory signal, and for generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the The second ramp signal has a first offset level and a second offset level corresponding to the base ramp signal respectively; and a disable signal generating circuit for comparing the first ramp signal and the base ramp signal, and comparing the second ramp signal and the basic ramp signal to generate the pre-inhibition signal, wherein the pre-inhibition period corresponds to the period during which the basic ramp signal is between the first ramp signal and the second ramp signal, and is used for It is judged whether the rising edge of the conduction control signal occurs within the pre-inhibition period to generate the inhibit signal.

在一較佳實施例中，該第一偏移位準與該第二偏移位準相關於該諧振週期。In a preferred embodiment, the first offset level and the second offset level are related to the resonance period.

在一較佳實施例中，該一次側控制電路更包括：一諧振偵測電路，用以根據該功率變壓器的一輔助繞組所產生的一輔助訊號，而產生相關於該諧振波形的一諧振同步訊號；其中該禁止訊號產生電路更根據該諧振同步訊號，以計時該禁止時段，使得該禁止時段至少維持一個該諧振週期。In a preferred embodiment, the primary side control circuit further includes: a resonance detection circuit for generating a resonance synchronization related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer The signal; wherein the prohibition signal generating circuit is further used to time the prohibition period according to the resonance synchronization signal, so that the prohibition period maintains at least one resonance period.

就另一個觀點言，本發明也提供了一種返馳式轉換器，用以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包含：一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間；一一次側開關，用以切換該功率變壓器的一一次側繞組；一二次側開關，用以切換該功率變壓器的一二次側繞組； 一一次側控制電路，用以產生一一次側切換訊號，以一切換週期控制該一次側開關；以及一二次側控制電路，用以產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換；其中，該二次側控制電路根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波，其中，該一次側控制電路根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵；其中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。In another aspect, the present invention also provides a flyback converter for converting an input power source to generate an output power source, the flyback converter comprises: a power transformer coupled in an electrically insulating manner between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; a secondary side switch for switching a secondary side winding of the power transformer; a a primary side control circuit for generating a primary side switching signal to control the primary side switch with a switching cycle; and a secondary side control circuit for generating a secondary side switching signal to control the secondary side A switch, wherein the secondary side switching signal has a synchronous rectifying (Synchronous Rectifying, SR) pulse and a zero voltage switching (ZVS) pulse, and the synchronous rectifying pulse is used to control the conduction of the secondary side switch A synchronous rectification period is used to achieve secondary side synchronous rectification, and the zero-voltage switching pulse is used to control the secondary-side switch to conduct a zero-voltage switching period, thereby enabling the primary-side switch to achieve zero-voltage switching; The side control circuit enables the zero voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary side control circuit enables the zero voltage switching pulse according to a second waveform characteristic of the DCM resonant waveform The primary side switching signal, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; wherein, when the output power or output current of the output power supply increases compared to the steady state, In the current switching cycle, the primary side control circuit enables the primary side switching signal according to the third waveform characteristic of the DCM resonant waveform, so as to prevent the primary side switch and the secondary side switch from being turned on at the same time, wherein the first side switch is turned on at the same time. The time point of the three waveform features is later than the time point corresponding to the second waveform feature in the current switching cycle.

就另一個觀點言，本發明也提供了一種用以控制一返馳式轉換器之控制方法，以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包括一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間；一一次側開關，用以切換該功率變壓器的一一次側繞組；以及一二次側開關，用以切換該功率變壓器的一二次側繞組；該方法包含：產生一一次側切換訊號，以一切換週期控制該一次側開關；以及產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換；其中，於穩態下，產生零電壓切換脈波的步驟包括：根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波，其中，於穩態下，產生該一次側切換訊號的步驟包括：根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵；以及當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。From another point of view, the present invention also provides a control method for controlling a flyback converter to convert an input power source to generate an output power source. The flyback converter includes a power transformer to electrically Insulatedly coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a power transformer A secondary side winding; the method includes: generating a primary side switching signal to control the primary side switch with a switching period; and generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching The signal has a synchronous rectifying (SR) pulse and a zero voltage switching (ZVS) pulse, and the synchronous rectifying pulse is used to control the secondary side switch to conduct a synchronous rectification period to achieve secondary side synchronous rectification, the zero-voltage switching pulse is used to control the secondary-side switch to conduct a zero-voltage switching period, thereby enabling the primary-side switch to achieve zero-voltage switching; wherein, in a steady state, a zero-voltage switching pulse is generated The step includes: enabling the zero-voltage switching pulse wave according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein, in a steady state, the step of generating the primary-side switching signal includes: according to the DCM A second waveform feature of the resonant waveform enables the primary side switching signal, wherein the second waveform feature of the DCM resonant waveform is later than the first waveform feature of the DCM resonant waveform; and when the output power or output of the output power supply When the current is rising compared to the steady state, in the current switching period, the primary side switching signal is enabled according to the third waveform characteristic of the DCM resonant waveform, so as to prevent the primary side switch and the secondary side switch at the same time turn on, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching cycle.

在一較佳實施例中，該DCM諧振波形對應於該一次側開關的汲源極電壓之諧振波形，其中該第二波形特徵對應於該DCM諧振波形的第V個波谷，該第三波形特徵對應於該DCM諧振波形的第W個波谷，其中W大於V。In a preferred embodiment, the DCM resonant waveform corresponds to the resonant waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the Vth trough of the DCM resonant waveform, and the third waveform characteristic Corresponds to the Wth trough of the DCM resonant waveform, where W is greater than V.

在一較佳實施例中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，於一禁止時段內禁能該一次側切換訊號，使得該一次側切換訊號與該零電壓切換脈波於該禁止時段不重疊，以避免該一次側開關與該二次側開關同時導通；其中該禁止時段相關於前一個該切換週期內的該一次側切換訊號之上升緣以及該DCM諧振波形的一諧振週期。In a preferred embodiment, when the output power or output current of the output power supply increases compared to the steady state, in the current switching cycle, the primary side switching signal is disabled during a prohibition period, so that the The primary side switching signal and the zero-voltage switching pulse do not overlap in the prohibition period, so as to prevent the primary side switch and the secondary side switch from being turned on at the same time; wherein the prohibition period is related to the primary side switching in the previous switching period The rising edge of the signal and a resonant period of the DCM resonant waveform.

在一較佳實施例中，產生該一次側切換訊號的步驟更包括：根據該輸出電源而產生一導通控制訊號，用以觸發該一次側切換訊號且決定該一次側開關於每一切換週期中的導通時點與導通時段；於每一切換週期中，產生示意一預禁止時段的一預禁止訊號；以及當該導通控制訊號在該預禁止時段內轉為致能時，產生示意該禁止時段的一禁止訊號，以於該禁止時段內遮罩該導通控制訊號而禁能該一次側切換訊號之觸發；其中該預禁止訊號根據前一個該切換週期的該一次側切換訊號的上升緣以及該諧振週期而產生，其中該預禁止時段涵蓋至少前一個該切換週期的該零電壓切換脈波。In a preferred embodiment, the step of generating the primary-side switching signal further comprises: generating a conduction control signal according to the output power, for triggering the primary-side switching signal and determining the primary-side switch in each switching cycle In each switching cycle, a pre-inhibition signal indicating a pre-inhibition period is generated; and when the conduction control signal turns to be enabled within the pre-inhibition period, a pre-inhibition signal indicating the inhibition period is generated a prohibition signal to mask the conduction control signal during the prohibition period to disable the triggering of the primary side switching signal; wherein the pre-inhibition signal is based on the rising edge of the primary side switching signal in the previous switching cycle and the resonance period, wherein the pre-inhibition period covers the zero-voltage switching pulse of at least one preceding switching period.

在一較佳實施例中，產生該一次側切換訊號的步驟更包括：當該導通控制訊號在該預禁止時段之外轉為致能時，允許該導通控制訊號觸發該一次側切換訊號。In a preferred embodiment, the step of generating the primary-side switching signal further includes: when the conducting-control signal is enabled outside the pre-inhibition period, allowing the conducting-control signal to trigger the primary-side switching signal.

在一較佳實施例中，產生該一次側切換訊號的步驟更包括：當該禁止訊號被致能後，根據相關於該諧振波形的一諧振同步訊號計時對應的該禁止時段，使得該禁止時段至少維持一個該諧振週期。In a preferred embodiment, the step of generating the primary side switching signal further includes: after the prohibition signal is enabled, timing the corresponding prohibition period according to a resonant synchronization signal related to the resonant waveform, so that the prohibition period is At least one such resonant period is maintained.

在一較佳實施例中，產生該一次側切換訊號的步驟更包括：當該禁止訊號被致能後，以該諧振波形相關訊號計時對應的該禁止時段，使得於該禁止時段結束後，該一次側切換訊號於該DCM諧振波形的第三波形特徵而被致能，而達成零電壓切換，其中該第三波形特徵晚於對應於前一個切換週期內的該第二波形特徵。In a preferred embodiment, the step of generating the primary-side switching signal further includes: when the prohibition signal is enabled, timing the corresponding prohibition period with the resonant waveform related signal, so that after the prohibition period ends, the The primary-side switching signal is enabled at a third waveform characteristic of the DCM resonant waveform to achieve zero-voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period.

在一較佳實施例中，產生該禁止訊號的步驟包括：於每一該切換週期中，該一次側切換訊號的膝點開始產生一基礎斜坡訊號；於該一次側切換訊號的上升緣取樣與保持該基礎斜坡訊號而產生一波谷記憶訊號；產生一第一斜坡訊號與一第二斜坡訊號，其中該第一斜坡訊號與該第二斜坡訊號分別與該基礎斜坡訊號具有對應的一第一偏移位準與一第二偏移位準；比較該第一斜坡訊號與該基礎斜坡訊號，且，比較該第二斜坡訊號與該基礎斜坡訊號而產生該預禁止訊號，其中該預禁止時段對應於該基礎斜坡訊號介於該第一斜坡訊號與該第二斜坡訊號的期間；以及判斷該導通控制訊號的上升緣是否發生於該預禁止時段內而產生該禁止訊號。In a preferred embodiment, the step of generating the disable signal includes: in each switching cycle, the knee point of the primary side switching signal starts to generate a basic ramp signal; sampling and summing at the rising edge of the primary side switching signal; maintaining the base ramp signal to generate a valley memory signal; generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset corresponding to the base ramp signal shift level and a second offset level; compare the first ramp signal with the base ramp signal, and compare the second ramp signal with the base ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to During the period when the basic ramp signal is between the first ramp signal and the second ramp signal; and judging whether the rising edge of the conduction control signal occurs within the pre-prohibition period to generate the prohibition signal.

在一較佳實施例中，該第一偏移位準與該第二偏移位準相關於該諧振週期。In a preferred embodiment, the first offset level and the second offset level are related to the resonance period.

底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

本發明中的圖式均屬示意，主要意在表示各電路間之耦接關係，以及各訊號波形之間之關係，至於電路、訊號波形與頻率則並未依照比例繪製。The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

圖4顯示根據本發明之返馳式轉換器的較佳實施例示意圖（返馳式轉換器1004）。返馳式轉換器1004用以轉換輸入電壓Vin而產生輸出電壓Vo與輸出電流Io，而提供電源予負載電路(未示出，為本領域具有通常知識者所熟知，在此不予贅述)。返馳式轉換器1004包含功率變壓器10、一次側控制電路100以及二次側控制電路200。FIG. 4 shows a schematic diagram of a preferred embodiment of a flyback converter according to the present invention (flyback converter 1004 ). The flyback converter 1004 is used to convert the input voltage Vin to generate the output voltage Vo and the output current Io to provide power to the load circuit (not shown, which is well known to those skilled in the art, and will not be repeated here). The flyback converter 1004 includes a power transformer 10 , a primary side control circuit 100 and a secondary side control circuit 200 .

功率變壓器10以電性絕緣的方式耦接於輸入電壓Vin與輸出電壓Vo之間，一次側開關S1耦接於功率變壓器10的一次側繞組W1，其中一次側繞組W1耦接於輸入電壓Vin。二次側開關S2與功率變壓器10的二次側繞組W2串接於輸出電壓Vo與二次側接地節點之間。在本實施例中，二次側開關S2耦接於功率變壓器10的二次側繞組W2與二次側接地節點之間。二次側開關S2亦可耦接於功率變壓器10的二次側繞組W2與輸出電壓Vo之間，如圖1B之二次側電路所示意。為簡化說明，接下來以如圖4所示之二次側開關S2耦接於功率變壓器10的二次側繞組W2與二次側接地節點之間的實施例進行說明，然而相同的精神也可適用於如圖1B之二次側所示的另一種形式。The power transformer 10 is electrically isolated between the input voltage Vin and the output voltage Vo. The primary side switch S1 is coupled to the primary side winding W1 of the power transformer 10 , wherein the primary side winding W1 is coupled to the input voltage Vin. The secondary side switch S2 and the secondary side winding W2 of the power transformer 10 are connected in series between the output voltage Vo and the secondary side grounding node. In this embodiment, the secondary side switch S2 is coupled between the secondary side winding W2 of the power transformer 10 and the secondary side grounding node. The secondary side switch S2 can also be coupled between the secondary side winding W2 of the power transformer 10 and the output voltage Vo, as shown in the secondary side circuit of FIG. 1B . In order to simplify the description, the following description will be given with the embodiment in which the secondary side switch S2 is coupled between the secondary side winding W2 of the power transformer 10 and the secondary side ground node as shown in FIG. 4 , but the same spirit can also be used. An alternative form as shown on the secondary side of Figure 1B is applicable.

一次側控制電路100用以產生一次側切換訊號S1C，一次側切換訊號S1C用以控制一次側開關S1以切換功率變壓器10的一次側繞組W1，其中一次側繞組W1耦接於輸入電壓Vin。二次側控制電路200用以產生二次側切換訊號S2C，以控制二次側開關S2之導通與關斷，而切換功率變壓器10的二次側繞組W2產生輸出電壓Vo。其中VDS1為一次側開關S1的汲極的電壓，而VDS2為二次側開關S2的第一端的電壓。本實施例中，所述的二次側開關S2的第一端為汲極（電流流出端），而二次側開關S2的第二端為源極（電流流入端）。還需說明的是，在二次側開關S2耦接於功率變壓器10的二次側繞組W2與輸出電壓Vo之間的實施例中，如圖1B之二次側電路所示，所述的二次側開關S2的第一端為源極（電流流入端），而二次側開關S2的第二端為汲極（電流流出端）。The primary side control circuit 100 is used for generating the primary side switching signal S1C, and the primary side switching signal S1C is used for controlling the primary side switch S1 to switch the primary side winding W1 of the power transformer 10, wherein the primary side winding W1 is coupled to the input voltage Vin. The secondary side control circuit 200 is used for generating the secondary side switching signal S2C to control the on and off of the secondary side switch S2 and switch the secondary side winding W2 of the power transformer 10 to generate the output voltage Vo. Wherein VDS1 is the voltage of the drain of the primary side switch S1, and VDS2 is the voltage of the first terminal of the secondary side switch S2. In this embodiment, the first terminal of the secondary side switch S2 is the drain (current outflow terminal), and the second terminal of the secondary side switch S2 is the source (current inflow terminal). It should also be noted that, in the embodiment in which the secondary side switch S2 is coupled between the secondary side winding W2 of the power transformer 10 and the output voltage Vo, as shown in the secondary side circuit of FIG. 1B , the two The first terminal of the secondary side switch S2 is the source (current inflow terminal), and the second terminal of the secondary side switch S2 is the drain (current outflow terminal).

請同時參閱圖5，圖5顯示對應於本發明之返馳式轉換器的實施例之波形示意圖。本實施例中，本發明之返馳式轉換器操作於不連續導通模式(DCM – Discontinuous Conduction Mode)。根據本發明，二次側切換訊號S2C具有同步整流脈波PSR以及零電壓切換（zero voltage switching，ZVS）脈波PZV，在一次側開關S1導通後又再度關斷時(如圖5之t3)，同步整流脈波PSR用以控制二次側開關S2導通一同步整流時段TSR以達成二次側的同步整流，其中，同步整流時段TSR大致上同步於二次側繞組W2的感應電流的導通時段，換言之，同步整流時段TSR開始於二次側繞組W2自一次側繞組W1轉移能量而產生二次側電流Isr的時點(t3)，且同步整流時段TSR結束於二次側繞組W2的二次側電流Isr降為0的時點(t4)，如此可提升電源轉換效率。Please refer to FIG. 5 at the same time. FIG. 5 shows a schematic diagram of waveforms corresponding to an embodiment of the flyback converter of the present invention. In this embodiment, the flyback converter of the present invention operates in a discontinuous conduction mode (DCM - Discontinuous Conduction Mode). According to the present invention, the secondary side switching signal S2C has a synchronous rectification pulse wave PSR and a zero voltage switching (ZVS) pulse wave PZV. When the primary side switch S1 is turned on and then turned off again (t3 in FIG. 5 ) , the synchronous rectification pulse PSR is used to control the secondary side switch S2 to conduct a synchronous rectification period TSR to achieve the synchronous rectification of the secondary side, wherein the synchronous rectification period TSR is substantially synchronized with the conduction period of the induced current of the secondary side winding W2 , in other words, the synchronous rectification period TSR starts at the time point (t3) when the secondary side winding W2 transfers energy from the primary side winding W1 to generate the secondary side current Isr, and the synchronous rectification period TSR ends at the secondary side of the secondary side winding W2 The time point when the current Isr drops to 0 ( t4 ) can improve the power conversion efficiency.

請繼續參閱圖5，另一方面，零電壓切換脈波PZV則用以達成前述之一次側開關S1的零電壓切換。詳言之，本實施例中，當返馳式轉換器1004操作於不連續導通模式時，功率變壓器10於一次側開關S1導通時感磁(magnetizing，t2-t3，圖5)，且於該一次側開關S1轉為不導通時將感磁時所獲得的能量傳送到該輸出電壓Vo；當同步整流脈波PSR控制二次側開關S2導通，而使得功率變壓器10去磁完成後(demagnetized，t4，圖5)，二次側開關S2會先控制為不導通(t4-t5，圖5)，此時功率變壓器10會開始產生DCM諧振波形，所述的DCM諧振波形可對應於例如一次側電壓VDS1、二次側電壓VDS2或輔助繞組W3所產生的輔助電壓Vaux或DEMAG，此外，所述之DCM諧振波形的諧振週期Trng相關於功率變壓器10的電感值與雜散電容值，特別是一次側繞組W1的電感值與相關的雜散電容值。Please continue to refer to FIG. 5 . On the other hand, the zero-voltage switching pulse PZV is used to achieve the aforementioned zero-voltage switching of the primary-side switch S1 . To be more specific, in this embodiment, when the flyback converter 1004 operates in the discontinuous conduction mode, the power transformer 10 is magnetizing (magnetizing, t2-t3, FIG. 5 ) when the primary side switch S1 is turned on, and in this When the primary side switch S1 is turned non-conductive, the energy obtained during magnetic induction is transferred to the output voltage Vo; when the synchronous rectification pulse PSR controls the secondary side switch S2 to be turned on, so that the power transformer 10 is demagnetized (demagnetized, t4, Fig. 5), the secondary side switch S2 is first controlled to be non-conductive (t4-t5, Fig. 5), at this time, the power transformer 10 starts to generate a DCM resonance waveform, and the DCM resonance waveform can correspond to, for example, the primary side The voltage VDS1, the secondary side voltage VDS2 or the auxiliary voltage Vaux or DEMAG generated by the auxiliary winding W3, in addition, the resonant period Trng of the DCM resonant waveform is related to the inductance value and stray capacitance value of the power transformer 10, especially the primary The inductance value of the side winding W1 and the associated stray capacitance value.

而當二次側開關S2再度根據零電壓切換脈波PZV而導通時(如圖5之t5)，功率變壓器10會在二次側繞組W2感應負向的二次側電流Isr，當二次側開關S2於零電壓切換脈波PZV結束再度關斷時(如t6)，功率變壓器10會在一次側繞組W1感應負向的一次側電流Ip，在此期間(如t6-t7)，負向的一次側電流Ip可將一次側開關S1之寄生電容Cp放電，使得一次側開關S1的汲極電壓VDS1下降至較低的電壓，並將電荷通過一次側繞組W1回充至輸入電源，當一次側開關S1接著導通，可使一次側開關S1達成柔性切換。在一較佳實施例中，負向的一次側電流Ip可將一次側開關S1之寄生電容Cp放電至大致上為0V，可使一次側開關S1達成零電壓切換(ZVS – Zero Voltage Switching)。When the secondary side switch S2 is turned on again according to the zero-voltage switching pulse PZV ( t5 in FIG. 5 ), the power transformer 10 will induce a negative secondary side current Isr in the secondary side winding W2 . When the switch S2 is turned off again at the end of the zero-voltage switching pulse PZV (eg t6), the power transformer 10 will induce a negative primary side current Ip in the primary side winding W1, during this period (eg t6-t7), the negative side current Ip The primary side current Ip can discharge the parasitic capacitance Cp of the primary side switch S1, so that the drain voltage VDS1 of the primary side switch S1 drops to a lower voltage, and the charge is recharged to the input power through the primary side winding W1, when the primary side The switch S1 is then turned on, so that the primary-side switch S1 can achieve flexible switching. In a preferred embodiment, the negative primary side current Ip can discharge the parasitic capacitance Cp of the primary side switch S1 to approximately 0V, so that the primary side switch S1 can achieve zero voltage switching (ZVS - Zero Voltage Switching).

需說明的是，前述之「零電壓切換」係指，在電晶體(如對應於一次側開關S1)將導通之前，藉由放電電流將電晶體之寄生電容的殘存電壓，通過無能損放電路徑(例如對應於一次側繞組W1)，放電至較低的電壓，並將電荷回充至無能損之元件(如輸入電源)中，使得電晶體導通時，其汲源極電壓已先降低為較低的電壓，由於其寄生電容(如對應於Cp)所儲存的電荷在此過程中不以電晶體之導通電阻放電，可提高電源轉換效率。It should be noted that the aforementioned "zero voltage switching" means that before the transistor (for example, corresponding to the primary side switch S1 ) will be turned on, the residual voltage of the parasitic capacitance of the transistor is passed through the lossless discharge path by the discharge current. (for example, corresponding to the primary side winding W1), discharge to a lower voltage, and recharge the charge to a non-destructive component (such as an input power supply), so that when the transistor is turned on, its drain-source voltage has been reduced to a lower voltage. The low voltage can improve the power conversion efficiency because the charge stored in its parasitic capacitance (eg, corresponding to Cp) is not discharged through the on-resistance of the transistor during the process.

此外需說明的是：因電路零件的本身之寄生效應或是零件間相互的匹配不一定為理想，因此，雖然欲使寄生電容Cp放電至0V，但實際可能並無法準確地放電至0V，而僅是接近0V，亦即，根據本發明，可接受由於電路的不理想性而使寄生電容Cp放電後之電壓與0V間具有一定程度的誤差，此即前述之放電至「大致上」為0V之意，本文中其他提到「大致上」之處亦同。In addition, it should be noted that due to the parasitic effect of the circuit components or the mutual matching between components is not necessarily ideal, therefore, although the parasitic capacitance Cp is intended to be discharged to 0V, it may not be able to discharge to 0V accurately, and It is only close to 0V, that is, according to the present invention, it is acceptable to have a certain degree of error between the voltage after the parasitic capacitance Cp is discharged and 0V due to the imperfection of the circuit, that is, the aforementioned discharge to "substantially" 0V The same is true for other references to "substantially" in this article.

在一實施例中，前述的零電壓切換脈波PZV的起始時點同步於功率變壓器10去磁後的諧振波形的第一波形特徵，以圖5的實施例舉例而言，二次側控制電路200根據輸出電流Io的位準，適應性地選擇二次側開關電壓VDS2於功率變壓器10去磁後，諧振波形的某序位的波谷，開始前述的零電壓切換脈波PZV，藉此使二次側開關S2亦達到零電壓切換。例如圖5中，於時點t5開始前述的零電壓切換脈波PZV，其對應於VDS2的第三個波谷，同時也是VDS1的第三個波峰P3，為求一致，皆依一次側開關電壓VDS1之特徵而標示為P3。此外，一次側控制電路100還根據根據輸出電流Io的位準，適應性選擇上述的諧振波形的另一特徵，例如以鄰接次序位的波谷（例如圖5的時點t7，VDS1的第四個波谷V4）做為一次側開關S1的導通起始時點。藉此，可使一次側開關S1與二次側開關S2皆達到零電壓切換，以提高電源轉換效率，且得以在無需額外的隔離通信路徑（例如脈波變壓器）的條件下， 使一次側開關S1與二次側開關S2的開關時間同步且不重疊。在一較佳實施例中，於穩態下（例如圖5中的切換週期[n]），一次側開關S1與二次側開關S2的開關之間的不重疊時間為0.5個諧振週期Trng。In one embodiment, the start time point of the aforementioned zero-voltage switching pulse PZV is synchronized with the first waveform characteristic of the resonant waveform after the power transformer 10 is demagnetized. Taking the embodiment of FIG. 5 as an example, the secondary side control circuit 200 According to the level of the output current Io, the secondary-side switching voltage VDS2 is adaptively selected after the power transformer 10 is demagnetized, and the trough of a certain sequence of the resonant waveform starts the aforementioned zero-voltage switching pulse PZV, thereby making the two The secondary side switch S2 also achieves zero-voltage switching. For example, in FIG. 5, the aforementioned zero-voltage switching pulse PZV starts at time t5, which corresponds to the third trough of VDS2 and is also the third peak P3 of VDS1. The feature is marked as P3. In addition, the primary side control circuit 100 also adaptively selects another feature of the above-mentioned resonant waveform according to the level of the output current Io, for example, the valleys located in adjacent order (for example, at time t7 in FIG. 5 , the fourth valley of VDS1 V4) is used as the starting point of the turn-on of the primary side switch S1. In this way, both the primary-side switch S1 and the secondary-side switch S2 can achieve zero-voltage switching, so as to improve the power conversion efficiency, and the primary-side switch can be switched without an additional isolated communication path (such as a pulse transformer). S1 and the switching time of the secondary side switch S2 are synchronized and do not overlap. In a preferred embodiment, in a steady state (eg switching period [n] in FIG. 5 ), the non-overlapping time between the switching of the primary side switch S1 and the secondary side switch S2 is 0.5 resonant period Trng.

請繼續參閱圖5，為了避免前述的短路電流，在一實施例中，例如當輸出電流Io或輸出功率因負載變化而提高時，一次側開關S1的導通時點將被延後至少一個上述諧振波形的一個諧振週期Trng，具體以圖5舉例而言，當輸出電流Io於時點t8提高後，於切換週期[n+1]中，當返馳式轉換器1004根據回授，而欲較前一個切換週期提前導通一次側開關S1時，受到如圖所示的禁止時段Tinh(t9~t11)的遮罩與延遲，因而於切換週期[n+1]中，至一次側開關電壓VDS1的第五個波谷V5(t11)才開始導通一次側開關S1。換言之，於禁止時段Tinh中可確保一次側切換訊號S1C與該零電壓切換脈波PZV不會重疊，可有效避免一次側開關S1與二次側開關S2同時導通。Please continue to refer to FIG. 5 , in order to avoid the aforementioned short-circuit current, in one embodiment, for example, when the output current Io or the output power increases due to load changes, the turn-on time of the primary side switch S1 will be delayed by at least one of the above-mentioned resonant waveforms One resonance period Trng of , specifically taking FIG. 5 as an example, when the output current Io increases at the time point t8, in the switching period [n+1], when the flyback converter 1004 wants to compare the previous one according to the feedback When the primary side switch S1 is turned on in advance of the switching period, it is masked and delayed by the prohibition period Tinh (t9~t11) as shown in the figure. Therefore, in the switching period [n+1], to the fifth voltage of the primary side switch voltage VDS1 The primary side switch S1 is turned on only after the first wave valley V5 (t11). In other words, it can ensure that the primary side switching signal S1C and the zero-voltage switching pulse PZV do not overlap during the prohibition period Tinh, which can effectively prevent the primary side switch S1 and the secondary side switch S2 from being turned on at the same time.

請繼續參閱圖5，在一實施例中，當返馳式轉換器1004根據回授，而欲較前一個切換週期提前導通，且提前導通的時點早於前述的零電壓切換脈波PZV的起始時點時，則一次側開關S1的導通時點將依回授而決定，亦即，不需如前述地延後。具體以圖5舉例而言，於切換週期[n+2]中，當返馳式轉換器1004根據回授，而使得導通時點被提前至一次側開關電壓VDS1的第三個波谷V3(t12)時，由於一次側開關電壓VDS1的第三個波谷V3早於零電壓切換脈波PZV原應於切換週期[n+2]中的起始時點（如t13之P3），因此，一次側開關S1直接於一次側開關電壓VDS1的第三個波谷V3(t12)導通。此外，當一次側開關S1的導通時點先於零電壓切換脈波PZV時，則此切換週期[n+2]將不產生零電壓切換脈波PZV。Please continue to refer to FIG. 5 , in one embodiment, when the flyback converter 1004 is turned on earlier than the previous switching cycle according to the feedback, and the time point of turning on in advance is earlier than the start of the aforementioned zero-voltage switching pulse PZV At the start time, the turn-on time of the primary side switch S1 will be determined according to the feedback, that is, there is no need to delay as described above. Taking FIG. 5 as an example, in the switching period [n+2], when the flyback converter 1004 is turned on according to the feedback, the turn-on time point is advanced to the third trough V3 of the primary-side switching voltage VDS1 (t12) , since the third trough V3 of the primary-side switching voltage VDS1 is earlier than the zero-voltage switching pulse PZV, which should be at the beginning of the switching period [n+2] (such as P3 in t13), the primary-side switch S1 It is directly turned on at the third valley V3 (t12) of the primary-side switching voltage VDS1. In addition, when the turn-on time of the primary side switch S1 is earlier than the zero-voltage switching pulse PZV, the switching period [n+2] will not generate the zero-voltage switching pulse PZV.

根據本發明，在一實施例中，任一當前的切換週期(如切換週期[n+1])的禁止時段Tinh，相關於前一個切換週期(如切換週期[n])的零電壓切換脈波PZV所在的位置，具體而言，係根據前一個切換週期內的一次側切換訊號S1C之上升緣以及DCM諧振波形的諧振週期Trng而產生，其實施細節容後詳述。According to the present invention, in one embodiment, the prohibition period Tinh of any current switching period (eg switching period [n+1]) is related to the zero-voltage switching pulse of the previous switching period (eg switching period [n]). Specifically, the position of the wave PZV is generated according to the rising edge of the primary side switching signal S1C in the previous switching period and the resonance period Trng of the DCM resonance waveform. The details of its implementation will be described in detail later.

請繼續參閱圖5，根據提高的輸出電流Io而達成新的穩態後，如切換週期[n+3]所示，一次側開關S1將於一次側開關電壓VDS1的第三個波谷V3(t15)導通，而零電壓切換脈波PZV亦將適應性地提前至一次側開關電壓VDS1的第二個波峰V2(t14，對應於VDS2的第二個波谷)起始。Please continue to refer to FIG. 5 , after reaching a new steady state according to the increased output current Io, as indicated by the switching period [n+3], the primary side switch S1 will switch to the third trough V3 of the primary side switch voltage VDS1 (t15 ) is turned on, and the zero-voltage switching pulse PZV will adaptively advance to the start of the second peak V2 (t14, corresponding to the second valley of VDS2) of the primary-side switching voltage VDS1.

請繼續參閱圖4，圖4還顯示了本發明之返馳式轉換器中，一次側控制電路的一具體實施例示意圖（一次側控制電路100）。本實施例中，一次側控制電路100包括PWM(脈寬調變, pulse width modulation)產生電路110，負緣偵測電路120、諧振偵測電路130、波谷修正電路140、膝點偵測電路150、斜坡產生電路160、波谷選擇電路170以及禁止訊號產生電路180。Please continue to refer to FIG. 4 . FIG. 4 also shows a schematic diagram of a specific embodiment of the primary side control circuit (the primary side control circuit 100 ) in the flyback converter of the present invention. In this embodiment, the primary side control circuit 100 includes a PWM (pulse width modulation) generating circuit 110 , a negative edge detection circuit 120 , a resonance detection circuit 130 , a valley correction circuit 140 , and a knee point detection circuit 150 , a ramp generation circuit 160 , a valley selection circuit 170 and a disable signal generation circuit 180 .

請同時參閱圖6，圖6顯示對應於本發明之返馳式轉換器的實施例之波形示意圖。Please refer to FIG. 6 at the same time. FIG. 6 shows a schematic diagram of waveforms corresponding to an embodiment of the flyback converter of the present invention.

在一實施例中，PWM產生電路110根據回授(例如但不限於輸出電壓Vo及/或輸出電流Io)而產生導通控制訊號TD，藉此觸發與決定一次側開關S1的導通時點與導通時段，PWM產生電路110同時還根據波谷指示訊號P_PWM與禁止訊號INH而產生一次側切換訊號S1C，用以控制一次側開關S1。In one embodiment, the PWM generation circuit 110 generates the conduction control signal TD according to the feedback (such as but not limited to the output voltage Vo and/or the output current Io), thereby triggering and determining the conduction time point and conduction period of the primary side switch S1. , the PWM generating circuit 110 also generates the primary side switching signal S1C according to the valley indicating signal P_PWM and the inhibiting signal INH, so as to control the primary side switch S1.

負緣偵測電路120用以偵測一次側切換訊號S1C的負緣（亦即，下降緣）而產生負緣訊號CyL，用以示意一次側切換訊號S1C的負緣的發生時點。The negative edge detection circuit 120 is used for detecting the negative edge (ie, the falling edge) of the primary side switching signal S1C to generate the negative edge signal CyL, which is used to indicate the occurrence time of the negative edge of the primary side switching signal S1C.

斜坡產生電路160用以根據膝點訊號Knee與負緣訊號CyL產生斜坡訊號Rmp，具體而言，斜坡產生電路160於一次側開關電壓VDS1的膝點開始產生斜坡訊號Rmp，直到一次側切換訊號S1C的負緣而重置。The ramp generation circuit 160 is used for generating the ramp signal Rmp according to the knee signal Knee and the negative edge signal CyL. Specifically, the ramp generation circuit 160 starts to generate the ramp signal Rmp at the knee point of the primary side switching voltage VDS1 until the primary side switching signal S1C reset by the negative edge.

波谷選擇電路170用以取樣保持前一切換週期的斜坡訊號Rmp而產生波谷記憶訊號VN，且用以根據斜坡訊號Rmp而產生具有偏移的斜坡訊號Rmp1與Rmp2。The valley selection circuit 170 is used for sampling and holding the ramp signal Rmp of the previous switching period to generate the valley memory signal VN, and for generating the offset ramp signals Rmp1 and Rmp2 according to the ramp signal Rmp.

禁止訊號產生電路180則用以根據斜坡訊號Rmp1、Rmp2以及波谷記憶訊號VN而產生禁止訊號INH。其中一次側開關S1於禁止訊號INH的禁止時段Tinh內被禁能而延遲其導通的時點，具體而言，禁止訊號產生電路180根據前一切換週期的波谷記憶訊號VN與斜坡訊號Rmp1、Rmp2，而估算前一切換週期的零電壓切換脈波PZV，藉此估算對應於當前的切換週期的零電壓切換脈波PZV的時點，而產生對應於當前的切換週期的禁止訊號INH。The inhibit signal generating circuit 180 is used for generating the inhibit signal INH according to the ramp signals Rmp1, Rmp2 and the valley memory signal VN. Among them, the primary side switch S1 is disabled during the disable period Tinh of the disable signal INH to delay its turn-on time point. The zero-voltage switching pulse PZV of the previous switching period is estimated, thereby estimating the time point of the zero-voltage switching pulse PZV corresponding to the current switching period, and the disable signal INH corresponding to the current switching period is generated.

膝點偵測電路150用以根據輔助訊號DEMAG而產生用以示意一次側開關電壓VDS1之膝點的膝點訊號Knee。The knee point detection circuit 150 is used for generating a knee point signal Knee for indicating the knee point of the primary side switch voltage VDS1 according to the auxiliary signal DEMAG.

諧振偵測電路130用以根據輔助訊號DEMAG而產生用以示意一次側開關電壓VDS1為下降緣時的諧振同步訊號SYNC。The resonance detection circuit 130 is used for generating the resonance synchronization signal SYNC according to the auxiliary signal DEMAG to indicate that the primary-side switching voltage VDS1 is at the falling edge.

波谷修正電路140則用以根據諧振同步訊號SYNC產生波谷指示訊號P_PWM。The valley correction circuit 140 is used for generating the valley indication signal P_PWM according to the resonance synchronization signal SYNC.

本實施例中，如圖6所示，本發明之返馳式轉換器的具體操作為：於穩態時（如切換週期[n]），二次側控制電路200於一次側開關電壓VDS1的第三個波峰（如切換週期[n]中的P3）而致能零電壓切換脈波PZV，一次側控制電路根據一次側開關電壓VDS1的第四個波谷（如切換週期[n]中的V4）而致能一次側切換訊號S1C，其中一次側開關電壓VDS1的第四個波谷V4晚於一次側開關電壓VDS1的第三個波峰P3。In this embodiment, as shown in FIG. 6 , the specific operation of the flyback converter of the present invention is as follows: in a steady state (eg switching period [n]), the secondary side control circuit 200 switches the voltage VDS1 on the primary side The third peak (such as P3 in the switching period [n]) enables the zero-voltage switching pulse PZV, and the primary side control circuit is based on the fourth trough of the primary side switching voltage VDS1 (such as V4 in the switching period [n]) ) to enable the primary side switching signal S1C, wherein the fourth trough V4 of the primary side switching voltage VDS1 is later than the third peak P3 of the primary side switching voltage VDS1.

而當輸出電源的輸出功率或輸出電流Io相較於穩態為上升時，於當前的切換週期中（如切換週期[n+1]），該一次側控制電路則延後例如一個波谷而致能一次側切換訊號S1C，亦即，如本實施例中，根據一次側開關電壓VDS1的第五個波谷（切換週期[n+1]中的V5）而致能一次側切換訊號S1C，以避免一次側開關S1與二次側開關S2同時導通，其中一次側開關電壓VDS1的第五個波谷之時點（切換週期[n+1]中的V5），晚於一次側開關電壓VDS1的第四個波谷於當前的該切換週期中所對應的時點（切換週期[n+1]中的V4）。When the output power or output current Io of the output power supply increases compared to the steady state, in the current switching cycle (such as the switching cycle [n+1]), the primary side control circuit is delayed by, for example, a trough. The primary-side switching signal S1C is enabled, that is, as in this embodiment, the primary-side switching signal S1C is enabled according to the fifth trough of the primary-side switching voltage VDS1 (V5 in the switching period [n+1]) to avoid The primary side switch S1 and the secondary side switch S2 are turned on at the same time, and the time point of the fifth trough of the primary side switch voltage VDS1 (V5 in the switching period [n+1]) is later than the fourth time point of the primary side switch voltage VDS1. The trough is at the time point corresponding to the current switching cycle (V4 in the switching cycle [n+1]).

以下分別更具體地描述上述的子電路的操作，以達成上述的功能。The operations of the above-mentioned sub-circuits are described in more detail below to achieve the above-mentioned functions.

圖7顯示本發明之返馳式轉換器中，諧振偵測電路的一具體實施例示意圖（諧振偵測電路130）。諧振偵測電路130包括放大電路131、電晶體132以及電流電壓轉換電路133，諧振偵測電路130用以偵測輔助訊號DEMAG是否低於參考訊號VR而產生諧振同步訊號SYNC，在一實施例中，參考訊號VR為0或接近於0的參考電壓，使得諧振同步訊號SYNC示意輔助訊號DEMAG為負壓，諧振同步訊號SYNC同時也示意了一次側開關電壓VDS1低於輸入電壓Vin。就一觀點而言，諧振同步訊號SYNC的上升緣可用以示意一次側開關電壓VDS1自波峰下降至波谷的中點，而諧振同步訊號SYNC的下降緣可用以示意一次側開關電壓VDS1自波谷上升至波峰的中點。FIG. 7 shows a schematic diagram of a specific embodiment of the resonance detection circuit in the flyback converter of the present invention (the resonance detection circuit 130 ). The resonance detection circuit 130 includes an amplifier circuit 131, a transistor 132 and a current-to-voltage conversion circuit 133. The resonance detection circuit 130 is used to detect whether the auxiliary signal DEMAG is lower than the reference signal VR to generate a resonance synchronization signal SYNC. In one embodiment , the reference signal VR is a reference voltage of 0 or close to 0, so that the resonant synchronization signal SYNC indicates that the auxiliary signal DEMAG is a negative voltage, and the resonant synchronization signal SYNC also indicates that the primary side switch voltage VDS1 is lower than the input voltage Vin. From one point of view, the rising edge of the resonant synchronization signal SYNC can be used to indicate that the primary-side switching voltage VDS1 drops from the peak to the midpoint of the trough, and the falling edge of the resonant synchronization signal SYNC can be used to indicate that the primary-side switching voltage VDS1 rises from the trough to the midpoint of the trough. The midpoint of the crest.

圖8顯示本發明之返馳式轉換器中，波谷修正電路的一具體實施例示意圖（波谷修正電路140）。波谷修正電路140包括延遲電路141以及邏輯電路，用以產生波谷指示訊號P_PWM，波谷指示訊號P_PWM之下降緣對齊於諧振同步訊號SYNC之下降緣，而延遲電路141將諧振同步訊號SYNC之上升緣延遲，而致能波谷指示訊號P_PWM，使得波谷指示訊號P_PWM之上升緣較諧振同步訊號SYNC之上升緣延後，其中延後的時間長度可藉由電容與電流源而調整。就一觀點而言，在適當選擇延後的時間長度時，波谷指示訊號P_PWM之上升緣例如可用以指示一次側開關電壓VDS1的波谷的發生時點。FIG. 8 shows a schematic diagram of a specific embodiment of the valley correction circuit in the flyback converter of the present invention (the valley correction circuit 140 ). The valley correction circuit 140 includes a delay circuit 141 and a logic circuit for generating a valley indication signal P_PWM, the falling edge of the valley indication signal P_PWM is aligned with the falling edge of the resonance synchronization signal SYNC, and the delay circuit 141 delays the rising edge of the resonance synchronization signal SYNC , and enable the valley indication signal P_PWM, so that the rising edge of the valley indication signal P_PWM is delayed from the rising edge of the resonance synchronization signal SYNC, and the delay time length can be adjusted by the capacitor and the current source. From one point of view, when the delay time length is appropriately selected, the rising edge of the valley indicating signal P_PWM can be used to indicate the occurrence time of the valley of the primary-side switching voltage VDS1 , for example.

圖9顯示本發明之返馳式轉換器中，膝點偵測電路的一具體實施例示意圖（膝點偵測電路150）。膝點偵測電路150包括比較器151、脈波電路152、狀態電路153，以及邏輯電路。其中狀態電路153例如可為正反器。比較器151比較輔助訊號DEMAG與參考訊號VK而產生比較結果KneeCMP，脈波電路152根據比較結果KneeCMP，以及與比較結果KneeCMP具有單邊延遲反相關係的延遲反相訊號KCdb，而產生一膝點脈波KP以觸發正反器153而致能膝點訊號Knee，負緣訊號CyL用以重置膝點訊號Knee，換言之，如圖6所示，膝點訊號Knee的上升緣示意一次側開關電壓VDS1的膝點。FIG. 9 shows a schematic diagram of a specific embodiment of the knee detection circuit (knee detection circuit 150 ) in the flyback converter of the present invention. The knee detection circuit 150 includes a comparator 151, a pulse circuit 152, a state circuit 153, and a logic circuit. The state circuit 153 can be, for example, a flip-flop. The comparator 151 compares the auxiliary signal DEMAG and the reference signal VK to generate a comparison result KneeCMP. The pulse circuit 152 generates a knee point according to the comparison result KneeCMP and the delayed inversion signal KCdb having a unilateral delayed inversion relationship with the comparison result KneeCMP. The pulse wave KP triggers the flip-flop 153 to enable the knee signal Knee, and the negative edge signal CyL is used to reset the knee signal Knee. In other words, as shown in FIG. 6 , the rising edge of the knee signal Knee indicates the primary side switching voltage Knee point of VDS1.

圖10顯示本發明之返馳式轉換器中，斜坡產生電路的一具體實施例示意圖（斜坡產生電路160）。斜坡產生電路160包括正反器161以及積分電路162，正反器161根據膝點訊號Knee的上升緣而產生斜坡致能訊號RmpEN，以致能積分電路162開始以電流源對電容器充電而產生斜坡訊號Rmp。其中正反器161受系統重置訊號RST或負緣訊號CyL控制重置的時機，換言之，斜坡訊號Rmp自膝點訊號Knee的上升緣開始充電上升，且結束於下一切換週期的負緣訊號CyL。FIG. 10 shows a schematic diagram of a specific embodiment of the ramp generating circuit (the ramp generating circuit 160 ) in the flyback converter of the present invention. The ramp generating circuit 160 includes a flip-flop 161 and an integrating circuit 162. The flip-flop 161 generates the ramp enabling signal RmpEN according to the rising edge of the knee signal Knee, so that the integrating circuit 162 starts to charge the capacitor with the current source to generate the ramp signal Rmp. The flip-flop 161 is controlled by the system reset signal RST or the negative edge signal CyL to control the reset timing. In other words, the ramp signal Rmp starts to charge and rise from the rising edge of the knee signal Knee, and ends at the negative edge signal of the next switching cycle CyL.

圖11顯示本發明之返馳式轉換器中，波谷選擇電路的一具體實施例示意圖（波谷選擇電路170）。波谷選擇電路170包括放大器171、偏移電路172、取樣保持電路173與175。放大器171根據斜坡訊號Rmp而產生緩衝後的斜坡訊號Rmp， 取樣保持電路173用以自斜坡致能訊號RmpEN之上升緣起取樣斜坡訊號Rmp，且於一次側切換訊號S1C的上升緣取樣保持斜坡訊號Rmp而產生斜坡位準訊號RH1。取樣保持電路175用以根據負緣訊號CyL而於一次側切換訊號S1C的下降緣取樣保持斜坡位準訊號RH1而產生波谷記憶訊號VN，換言之，波谷記憶訊號VN的位準係取樣保持一次側切換訊號S1C於上升緣時點的位準，而於一次側切換訊號S1C的下降緣更新。FIG. 11 shows a schematic diagram of a specific embodiment of the valley selection circuit in the flyback converter of the present invention (the valley selection circuit 170 ). The valley selection circuit 170 includes an amplifier 171 , an offset circuit 172 , and sample-and-hold circuits 173 and 175 . The amplifier 171 generates a buffered ramp signal Rmp according to the ramp signal Rmp, and the sample-and-hold circuit 173 is used for sampling the ramp signal Rmp from the rising edge of the ramp-enable signal RmpEN, and sampling and holding the ramp signal Rmp at the rising edge of the primary-side switching signal S1C The ramp level signal RH1 is generated. The sample and hold circuit 175 is used for sampling and holding the ramp level signal RH1 at the falling edge of the primary side switching signal S1C according to the negative edge signal CyL to generate the valley memory signal VN. In other words, the level of the valley memory signal VN is switched by the sample and hold primary side. The level of the signal S1C at the time of the rising edge is updated by the falling edge of the switching signal S1C on the primary side.

此外，偏移電路172對斜坡訊號Rmp進行偏移，而產生具有偏移的斜坡訊號Rmp1與Rmp2，其中斜坡訊號Rmp1與Rmp2相較於斜坡訊號Rmp的偏移量由對應的電流源與電阻決定。In addition, the offset circuit 172 offsets the ramp signal Rmp to generate the ramp signals Rmp1 and Rmp2 with offsets, wherein the offsets of the ramp signals Rmp1 and Rmp2 compared with the ramp signal Rmp are determined by the corresponding current sources and resistors .

圖12顯示本發明之返馳式轉換器中，禁止訊號產生電路的一具體實施例示意圖（禁止訊號產生電路180）。禁止訊號產生電路180包括比較器181、比較器182、正反器183、184、185與若干邏輯電路。FIG. 12 shows a schematic diagram of a specific embodiment of the prohibition signal generating circuit (the prohibition signal generating circuit 180 ) in the flyback converter of the present invention. The disable signal generating circuit 180 includes a comparator 181 , a comparator 182 , flip-flops 183 , 184 , 185 and several logic circuits.

前述的斜坡訊號Rmp的電壓位準與一次側開關電壓VDS1的膝點後的時長具有正比關係，因此，就一觀點而言，波谷記憶訊號VN的位準即示意了前一切換週期中，一次側開關S1不導通的時段的長度。接著，藉由比較器181比較斜坡訊號Rmp1與波谷記憶訊號VN，以及比較器182比較斜坡訊號Rmp2與波谷記憶訊號VN，而產生對應於一預禁止時段Tpinh的預禁止訊號P_INH，其中預禁止時段Tpinh對應於波谷記憶訊號VN介於斜坡訊號Rmp1與斜坡訊號Rmp2之間之時段，接著由正反器183於諧振同步訊號SYNC的上升緣或導通控制訊號TD的上升緣，根據預禁止訊號P_INH是否被致能，而確定是否致能禁止訊號INH。換言之，在一實施例中，當負載改變而使得由回授所決定的導通控制訊號TD在預禁止訊號P_INH內觸發時，禁止訊號產生電路180致能禁止訊號INH，用以禁能一次側開關S1的導通，其細節將詳述於後。The voltage level of the aforementioned ramp signal Rmp is proportional to the time period after the knee point of the primary-side switching voltage VDS1. Therefore, from a point of view, the level of the valley memory signal VN indicates that in the previous switching cycle, The length of the period during which the primary side switch S1 is not conducting. Next, the comparator 181 compares the ramp signal Rmp1 with the valley memory signal VN, and the comparator 182 compares the ramp signal Rmp2 with the valley memory signal VN to generate a pre-inhibit signal P_INH corresponding to a pre-inhibit period Tpinh, wherein the pre-inhibit period Tpinh corresponds to the period when the valley memory signal VN is between the ramp signal Rmp1 and the ramp signal Rmp2, and then the flip-flop 183 uses the rising edge of the resonant synchronization signal SYNC or the rising edge of the conduction control signal TD according to whether the pre-inhibit signal P_INH is is enabled to determine whether the disable signal INH is enabled. In other words, in one embodiment, when the load changes and the conduction control signal TD determined by the feedback is triggered within the pre-inhibit signal P_INH, the inhibit signal generating circuit 180 enables the inhibit signal INH to disable the primary side switch The turn-on of S1, the details of which will be described later.

此外，負緣訊號CyL用以於一次側切換訊號S1C的負緣重置禁止訊號INH，以等待該切換週期中對禁止訊號INH的致能。另一方面，當禁止訊號INH致能之後，正反器184與185形成延遲電路，用以決定禁止訊號INH的時長，亦即，禁止時段Tinh，一實施例中，禁止時段Tinh由波谷指示訊號P_PWM的相鄰上升緣的週期以及正反器的數量而決定，因此，禁止時段Tinh相關於前述諧振波形的諧振週期Trng，藉此，在一較佳實施例中，於禁止時段Tinh結束後，一次側切換訊號S1C可例如於DCM諧振波形受禁止時段Tinh延遲後的另一個波谷而被致能，而仍能達成零電壓切換。具體而言，本實施例中，禁止時段Tinh大於等於前述諧振波形的諧振週期Trng的1.5倍。In addition, the negative edge signal CyL is used to reset the inhibit signal INH at the negative edge of the primary side switching signal S1C, so as to wait for the enabling of the inhibit signal INH in the switching cycle. On the other hand, after the disable signal INH is enabled, the flip-flops 184 and 185 form a delay circuit for determining the duration of the disable signal INH, that is, the disable period Tinh, in one embodiment, the disable period Tinh is indicated by a valley The period of the adjacent rising edges of the signal P_PWM and the number of flip-flops are determined. Therefore, the prohibition period Tinh is related to the resonant period Trng of the aforementioned resonant waveform. Therefore, in a preferred embodiment, after the prohibition period Tinh ends , the primary-side switching signal S1C can be enabled, for example, in another valley after the DCM resonant waveform is delayed by the disabled period Tinh, and the zero-voltage switching can still be achieved. Specifically, in this embodiment, the prohibition period Tinh is greater than or equal to 1.5 times the resonance period Trng of the aforementioned resonance waveform.

還需說明的是，由於斜坡訊號Rmp1與Rmp2相較於斜坡訊號Rmp的偏移量決定了預禁止時段Tpinh的起點與終點，另一方面，於穩態時，一次側開關S1導通的時點與零電壓切換脈波PZV的結束時點相關於諧振週期Trng，因此，在一實施例中，斜坡訊號Rmp1與Rmp2相較於斜坡訊號Rmp的偏移量相關於諧振週期Trng以及零電壓切換脈波PZV的脈寬TZV。在一較佳實施例中，預禁止時段Tpinh涵蓋至少前一個切換週期的該零電壓切換脈波PZV。It should also be noted that, since the offset of the ramp signals Rmp1 and Rmp2 compared to the ramp signal Rmp determines the start and end points of the pre-inhibition period Tpinh, on the other hand, in the steady state, the time when the primary side switch S1 is turned on is different from the The end point of the zero-voltage switching pulse PZV is related to the resonance period Trng. Therefore, in one embodiment, the offsets of the ramp signals Rmp1 and Rmp2 compared with the ramp signal Rmp are related to the resonance period Trng and the zero-voltage switching pulse PZV. The pulse width of TZV. In a preferred embodiment, the pre-inhibition period Tpinh covers at least the zero-voltage switching pulse wave PZV of the previous switching cycle.

圖13顯示本發明之返馳式轉換器中，PWM產生電路的一具體實施例示意圖（PWM產生電路110）。PWM產生電路110包括計時器111以及正反器112，計時器111根據例如相關於輸出電源的回授訊號而產生導通控制訊號TD，用以根據輸出電源（例如輸出電流Io及或輸出電壓Vo）而決定一次側開關S1的導通時點與導通時段，具體而言，正反器112根據回授相關訊號FBR而重置，以決定一次側切換訊號S1C的導通的時間, 以調節輸出電壓Vout及或輸出電流Iout，且藉由波谷指示訊號P_PWM而使一次側切換訊號S1C的起始時間同步於例如一次側開關電壓VDS1的波谷，而實現前述的零電壓切換，其中，回授相關訊號FBR相關於例如輸出電流Io及或輸出電壓Vo。此外，當負載增加而使得導通控制訊號TD於禁止時段Tinh致能時，邏輯電路113（例如圖示的及閘與反閘）根據禁止訊號INH而於禁止時段Tinh遮罩導通控制訊號TD以禁能一次側切換訊號S1C的觸發，藉此實現前述延遲一次側開關S1的導通時點，而有效避免前述的短路電流。FIG. 13 shows a schematic diagram of a specific embodiment of the PWM generating circuit in the flyback converter of the present invention (the PWM generating circuit 110 ). The PWM generating circuit 110 includes a timer 111 and a flip-flop 112. The timer 111 generates a conduction control signal TD according to, for example, a feedback signal related to the output power, for example, according to the output power (such as the output current Io and or the output voltage Vo) The turn-on time and turn-on period of the primary-side switch S1 are determined. Specifically, the flip-flop 112 is reset according to the feedback related signal FBR to determine the turn-on time of the primary-side switching signal S1C to adjust the output voltage Vout and/or The output current Iout, and the start time of the primary side switching signal S1C is synchronized with, for example, the valley of the primary side switching voltage VDS1 by the valley indicating signal P_PWM, so as to realize the aforementioned zero-voltage switching, wherein the feedback related signal FBR is related to For example, output current Io and or output voltage Vo. In addition, when the load increases so that the conduction control signal TD is enabled during the prohibition period Tinh, the logic circuit 113 (eg, the gate and the anti-gate shown in the figure) masks the conduction control signal TD during the prohibition period Tinh to inhibit according to the prohibition signal INH. The triggering of the primary-side switching signal S1C can be achieved, thereby realizing the delay of the turn-on time point of the primary-side switch S1, thereby effectively avoiding the aforementioned short-circuit current.

具體而言，如圖6中的切換週期[n+1]中，導通控制訊號TD於預禁止時段Tpinh致能，因而觸發了禁止訊號INH，而於禁止時段Tinh遮罩導通控制訊號TD以禁能一次側切換訊號S1C的觸發，使得切換週期[n+2]的一次側切換訊號S1C延遲至禁止時段Tinh結束後才觸發。Specifically, in the switching period [n+1] in FIG. 6 , the conduction control signal TD is enabled during the pre-inhibition period Tpinh, thus triggering the inhibition signal INH, and during the inhibition period Tinh masks the conduction control signal TD to inhibit The primary side switching signal S1C can be triggered, so that the primary side switching signal S1C of the switching period [n+2] is delayed to trigger after the end of the prohibition period Tinh.

圖14顯示本發明之返馳式轉換器中，負緣偵測電路的一具體實施例示意圖（負緣偵測電路120）。負緣偵測電路120包括延遲電路121與若干邏輯電路，用以偵測一次側切換訊號S1C之負緣而產生負緣訊號CyL。FIG. 14 shows a schematic diagram of a specific embodiment of the negative edge detection circuit (negative edge detection circuit 120 ) in the flyback converter of the present invention. The negative edge detection circuit 120 includes a delay circuit 121 and a plurality of logic circuits for detecting the negative edge of the primary side switching signal S1C to generate the negative edge signal CyL.

就一觀點而言，本發明之返馳式轉換器藉由類比式的波谷記憶方式，記憶前一切換週期的波谷發生時點，而於當前的切換週期的對應序位的波谷附近產生預禁止訊號P_INH，且於可能發生一次側開關S1與二次側開關S2可能同時導通時產生禁止訊號INH，以遮罩且禁能一次側切換訊號S1C的觸發，這在當負載增加而使得導通控制訊號TD於預禁止訊號P_INH致能時，可延遲一次側開關S1的導通時點，而有效避免前述的短路電流。此外還值得注意的是，前述一次側開關S1的導通時點的延遲時間Tnov相關於諧振波形的週期，在一較佳實施例中，相關於諧振波形的0.5個諧振週期Trng的倍數，在一較佳實施例中，其等於諧振波形的1.5個諧振週期Trng。From one point of view, the flyback converter of the present invention uses an analog valley memory method to memorize the occurrence time of the valley of the previous switching cycle, and generate a pre-inhibit signal near the valley of the corresponding sequence in the current switching cycle. P_INH, and when it is possible that the primary side switch S1 and the secondary side switch S2 may be turned on at the same time, the inhibition signal INH is generated to mask and disable the triggering of the primary side switching signal S1C. When the load increases, the control signal TD is turned on. When the pre-inhibit signal P_INH is enabled, the turn-on time of the primary-side switch S1 can be delayed, thereby effectively avoiding the aforementioned short-circuit current. In addition, it is worth noting that the delay time Tnov at the turn-on time of the primary side switch S1 is related to the period of the resonant waveform. In a preferred embodiment, it is equal to 1.5 resonant periods Trng of the resonant waveform.

以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。所說明之各個實施例，並不限於單獨應用，亦可以組合應用，舉例而言，兩個或以上之實施例可以組合運用，而一實施例中之部分組成亦可用以取代另一實施例中對應之組成部件。此外，在本發明之相同精神下，熟悉本技術者可以思及各種等效變化以及各種組合，舉例而言，本發明所稱「根據某訊號進行處理或運算或產生某輸出結果」，不限於根據該訊號的本身，亦包含於必要時，將該訊號進行電壓電流轉換、電流電壓轉換、及／或比例轉換等，之後根據轉換後的訊號進行處理或運算產生某輸出結果。由此可知，在本發明之相同精神下，熟悉本技術者可以思及各種等效變化以及各種組合，其組合方式甚多，在此不一一列舉說明。因此，本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described above with respect to the preferred embodiments, but the above-mentioned descriptions are only intended to make it easy for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.

10:功率變壓器 1001A, 1001B, 1004:返馳式轉換器 110:PWM產生電路 111:計時器 112:正反器 120:負緣偵測電路 121:延遲電路 130:諧振偵測電路 131:放大電路 132:電晶體 133:電流電壓轉換電路 140:波谷修正電路 141:延遲電路 150:膝點偵測電路 151:比較器 152:脈波電路 153:狀態電路 160:斜坡產生電路 161:正反器 162:積分電路 170:波谷選擇電路 171:放大器 172:偏移電路 173,  175:取樣保持電路 180:禁止訊號產生電路 181, 182:比較器 183, 184, 185:正反器 80, 100:一次側控制電路 90, 200:二次側控制電路 Cp:寄生電容 CyL:負緣訊號 FBR:回授相關訊號 INH:禁止訊號 Io:輸出電流 Ip:一次側電流 Isr:二次側電流 KCdb:延遲反相訊號 Knee:膝點訊號 KneeCMP:比較結果 KP:膝點脈波 P1~P4:波峰 P_INH:預禁止訊號 P_PWM:波谷指示訊號 PSR:同步整流脈波 PZV:零電壓切換脈波 RH1:斜坡位準訊號 Rmp, Rmp0, Rmp1, Rmp2:斜坡訊號 RmpEN:斜坡致能訊號 RST:系統重置訊號 S1:一次側開關 S1C:一次側切換訊號 S2C:二次側切換訊號 S2:二次側開關 SYNC:諧振同步訊號 t2~t15:時點 TD:導通控制訊號 Tinh:禁止時段 Tpinh:預禁止時段 Trng:諧振週期 TSR:同步整流時段 TZV:脈寬 V1~V4:波谷 Vaux, DEMAG:輔助電壓 VDS1:一次側開關電壓 VDS2:二次側開關電壓 Vin:輸入電壓 VK, VR:參考訊號 VN:波谷記憶訊號 Vo:輸出電壓 W1:一次側繞組 W2:二次側繞組 W3:輔助繞組10: Power Transformer 1001A, 1001B, 1004: Flyback Converters 110: PWM generation circuit 111: Timer 112: Flip-flop 120: Negative edge detection circuit 121: Delay circuit 130: Resonance detection circuit 131: Amplifier circuit 132: Transistor 133: Current-voltage conversion circuit 140: Valley correction circuit 141: Delay circuit 150: Knee detection circuit 151: Comparator 152: Pulse circuit 153: Status Circuit 160: Ramp generation circuit 161: Flip-flop 162: Integrator circuit 170: Valley selection circuit 171: Amplifier 172: Offset circuit 173, 175: Sample and hold circuit 180: Signal generation circuit is prohibited 181, 182: Comparator 183, 184, 185: Flip-flops 80, 100: Primary side control circuit 90, 200: Secondary side control circuit Cp: parasitic capacitance CyL: negative edge signal FBR: Feedback related signal INH: Inhibit Signal Io: output current Ip: primary side current Isr: Secondary side current KCdb: Delayed inverted signal Knee: Knee signal KneeCMP: Compare Results KP: Knee Point Pulse P1~P4: wave crest P_INH: Pre-inhibit signal P_PWM: Valley indication signal PSR: Synchronous Rectification Pulse PZV: zero voltage switching pulse RH1: Ramp level signal Rmp, Rmp0, Rmp1, Rmp2: Ramp signal RmpEN: Ramp enable signal RST: System reset signal S1: Primary side switch S1C: Primary side switching signal S2C: Secondary side switching signal S2: Secondary side switch SYNC: Resonance synchronization signal t2~t15: time point TD: conduction control signal Tinh: Prohibited period Tpinh: Pre-prohibition period Trng: Resonance period TSR: Synchronous Rectification Period TZV: pulse width V1~V4: Valley Vaux, DEMAG: auxiliary voltage VDS1: Primary side switching voltage VDS2: Secondary side switching voltage Vin: input voltage VK, VR: Reference signal VN: Valley memory signal Vo: output voltage W1: Primary winding W2: Secondary winding W3: auxiliary winding

圖1A與圖1B顯示先前技術之返馳式轉換器實施例示意圖。FIG. 1A and FIG. 1B are schematic diagrams showing an embodiment of a flyback converter of the prior art.

圖2顯示對應於圖1A與圖1B先前技術之返馳式轉換器的操作波形示意圖。FIG. 2 is a schematic diagram showing the operation waveforms of the flyback converter of the prior art corresponding to FIGS. 1A and 1B .

圖3顯示對應於圖1A與圖1B先前技術之返馳式轉換器的操作波形示意圖。FIG. 3 is a schematic diagram showing the operation waveforms of the flyback converter of the prior art corresponding to FIGS. 1A and 1B .

圖4顯示根據本發明之返馳式轉換器的較佳實施例示意圖。FIG. 4 shows a schematic diagram of a preferred embodiment of the flyback converter according to the present invention.

圖5顯示對應於本發明之返馳式轉換器的實施例之波形示意圖。FIG. 5 shows a schematic diagram of waveforms corresponding to an embodiment of the flyback converter of the present invention.

圖6顯示對應於本發明之返馳式轉換器的實施例之波形示意圖。FIG. 6 shows a schematic diagram of waveforms corresponding to an embodiment of the flyback converter of the present invention.

圖7顯示本發明之返馳式轉換器中，諧振偵測電路的一具體實施例示意圖。FIG. 7 shows a schematic diagram of a specific embodiment of the resonance detection circuit in the flyback converter of the present invention.

圖8顯示本發明之返馳式轉換器中，波谷修正電路的一具體實施例示意圖。FIG. 8 shows a schematic diagram of a specific embodiment of the valley correction circuit in the flyback converter of the present invention.

圖9顯示本發明之返馳式轉換器中，膝點偵測電路的一具體實施例示意圖。FIG. 9 shows a schematic diagram of a specific embodiment of the knee detection circuit in the flyback converter of the present invention.

圖10顯示本發明之返馳式轉換器中，斜坡產生電路的一具體實施例示意圖。FIG. 10 shows a schematic diagram of a specific embodiment of the ramp generating circuit in the flyback converter of the present invention.

圖11顯示本發明之返馳式轉換器中，波谷選擇電路的一具體實施例示意圖。FIG. 11 shows a schematic diagram of a specific embodiment of the valley selection circuit in the flyback converter of the present invention.

圖12顯示本發明之返馳式轉換器中，禁止訊號產生電路的一具體實施例示意圖。FIG. 12 shows a schematic diagram of a specific embodiment of the inhibit signal generating circuit in the flyback converter of the present invention.

圖13顯示本發明之返馳式轉換器中，PWM產生電路的一具體實施例示意圖。FIG. 13 shows a schematic diagram of a specific embodiment of the PWM generating circuit in the flyback converter of the present invention.

圖14顯示本發明之返馳式轉換器中，負緣偵測電路的一具體實施例示意圖。FIG. 14 shows a schematic diagram of a specific embodiment of the negative edge detection circuit in the flyback converter of the present invention.

無without

CyL:負緣訊號CyL: negative edge signal

INH:禁止訊號INH: Inhibit Signal

Io:輸出電流Io: output current

KCdb:延遲反相訊號KCdb: Delayed inverted signal

Knee:膝點訊號Knee: Knee signal

KneeCMP:比較結果KneeCMP: Compare Results

KP:膝點脈波KP: Knee Point Pulse

P1~P4:波峰P1~P4: wave crest

P_INH:預禁止訊號P_INH: Pre-inhibit signal

P_PWM:波谷指示訊號P_PWM: Valley indication signal

PSR:同步整流脈波PSR: Synchronous Rectification Pulse

PZV:零電壓切換脈波PZV: zero voltage switching pulse

Rmp0,Rmp1,Rmp2:斜坡訊號Rmp0, Rmp1, Rmp2: Ramp signal

RmpEN:斜坡致能訊號RmpEN: Ramp enable signal

S1:一次側開關S1: Primary side switch

S2C:二次側切換訊號S2C: Secondary side switching signal

SYNC:諧振同步訊號SYNC: Resonance synchronization signal

TD:導通控制訊號TD: conduction control signal

Tinh:禁止時段Tinh: Prohibited period

Tpinh:預禁止時段Tpinh: Pre-prohibition period

V1~V5:波谷V1~V5: Valley

DEMAG:輔助電壓DEMAG: auxiliary voltage

VDS1:一次側開關電壓VDS1: Primary side switching voltage

VDS2:二次側開關電壓VDS2: Secondary side switching voltage

Vin:輸入電壓Vin: input voltage

VN:波谷記憶訊號VN: Valley memory signal

Claims (30)

一種切換控制電路，用以控制一返馳式轉換器，以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包括一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間；一一次側開關，用以切換該功率變壓器的一一次側繞組；以及一二次側開關，用以切換該功率變壓器的一二次側繞組；該切換控制電路包含： 一一次側控制電路，用以產生一一次側切換訊號，以一切換週期控制該一次側開關；以及 一二次側控制電路，用以產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換； 其中，於穩態下，該二次側控制電路根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波，該一次側控制電路根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵； 其中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。A switching control circuit is used to control a flyback converter to convert an input power to generate an output power. The flyback converter includes a power transformer, which is coupled to the input voltage and the input voltage in an electrically insulating manner. between the output voltages; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the switching control circuit includes : a primary-side control circuit for generating a primary-side switching signal to control the primary-side switch with a switching period; and a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectifying (SR) pulse wave and a zero voltage switching ( zero voltage switching (ZVS) pulse, the synchronous rectification pulse is used to control the secondary side switch to turn on for a synchronous rectification period to achieve secondary side synchronous rectification, the zero voltage switching pulse is used to control the secondary side switch to turn on a zero-voltage switching period, thereby enabling the primary side switch to achieve zero-voltage switching; Wherein, in a steady state, the secondary side control circuit enables the zero-voltage switching pulse wave according to the first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, and the primary side control circuit according to the DCM resonant waveform The second waveform feature enables the primary-side switching signal, wherein the second waveform feature of the DCM resonance waveform is later than the first waveform feature of the DCM resonance waveform; Wherein, when the output power or output current of the output power supply increases compared to the steady state, in the current switching cycle, the primary side control circuit enables the primary side according to the third waveform characteristic of the DCM resonant waveform The switching signal prevents the primary side switch and the secondary side switch from being turned on at the same time, wherein the time point of the third waveform feature is later than the time point corresponding to the second waveform feature in the current switching cycle. 如請求項1所述之切換控制電路，其中該DCM諧振波形對應於該一次側開關的汲源極電壓之諧振波形，其中該第二波形特徵對應於該DCM諧振波形的第V個波谷，該第三波形特徵對應於該DCM諧振波形的第W個波谷，其中W大於V。The switching control circuit of claim 1, wherein the DCM resonant waveform corresponds to the resonant waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the Vth trough of the DCM resonant waveform, the The third waveform characteristic corresponds to the Wth trough of the DCM resonant waveform, where W is greater than V. 如請求項1所述之切換控制電路， 其中當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路控制該一次側切換訊號，於一禁止時段內禁能該一次側切換訊號，使得該一次側切換訊號與該零電壓切換脈波於該禁止時段不重疊，以避免該一次側開關與該二次側開關同時導通； 其中該禁止時段相關於前一個該切換週期內的該一次側切換訊號之上升緣以及該DCM諧振波形的一諧振週期。The switching control circuit according to claim 1, wherein when the output power or output current of the output power supply increases compared to a steady state, in the current switching cycle, the primary side control circuit controls the primary side switching signal , disabling the primary side switching signal during a forbidden period, so that the primary side switching signal and the zero-voltage switching pulse do not overlap during the forbidden period, so as to prevent the primary side switch and the secondary side switch from being turned on at the same time; The prohibition period is related to the rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform. 如請求項1所述之切換控制電路，其中該DCM諧振波形的該諧振週期相關於該一次側繞組的電感值與該一次側開關的雜散電容值。The switching control circuit of claim 1, wherein the resonant period of the DCM resonant waveform is related to an inductance value of the primary side winding and a stray capacitance value of the primary side switch. 如請求項3所述之切換控制電路，其中該一次側控制電路根據該輸出電源而產生一導通控制訊號，用以觸發該一次側切換訊號且決定該一次側開關於每一切換週期中的導通時點與導通時段，其中該一次側控制電路於每一切換週期中，產生示意一預禁止時段的一預禁止訊號； 其中當該導通控制訊號在該預禁止時段內轉為致能時，該一次側控制電路產生示意該禁止時段的一禁止訊號，以於該禁止時段內遮罩該導通控制訊號而禁能該一次側切換訊號之觸發； 其中該預禁止訊號根據前一個該切換週期的該一次側切換訊號的上升緣以及該諧振週期而產生，其中該預禁止時段涵蓋至少前一個該切換週期的該零電壓切換脈波。The switching control circuit as claimed in claim 3, wherein the primary side control circuit generates a conduction control signal according to the output power to trigger the primary side switching signal and determine the conduction of the primary side switch in each switching cycle a time point and a conduction period, wherein the primary side control circuit generates a pre-inhibition signal indicating a pre-inhibition period in each switching cycle; When the conduction control signal is turned to be enabled within the pre-inhibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period, so as to mask the conduction control signal and disable the primary during the prohibition period Trigger of side switching signal; The pre-inhibition signal is generated according to the rising edge of the primary side switching signal and the resonance period of the previous switching period, wherein the pre-inhibition period covers at least the zero-voltage switching pulse wave of the previous switching period. 如請求項3所述之切換控制電路，其中當該導通控制訊號在該預禁止時段之外轉為致能時，允許該導通控制訊號觸發該一次側切換訊號。The switching control circuit of claim 3, wherein when the conducting control signal is turned to be enabled outside the pre-inhibition period, the conducting control signal is allowed to trigger the primary side switching signal. 如請求項3所述之切換控制電路，其中當該禁止訊號被致能後，根據相關於該諧振波形的一諧振同步訊號計時對應的該禁止時段，使得該禁止時段至少維持一個該諧振週期。The switching control circuit as claimed in claim 3, wherein when the prohibition signal is enabled, the corresponding prohibition period is timed according to a resonance synchronization signal related to the resonant waveform, so that the prohibition period maintains at least one resonance period. 如請求項7所述之切換控制電路，其中當該禁止訊號被致能後，以該諧振波形相關訊號計時對應的該禁止時段，使得於該禁止時段結束後，該一次側切換訊號於該DCM諧振波形的第三波形特徵而被致能，而達成零電壓切換，其中該第三波形特徵晚於對應於前一個切換週期內的該第二波形特徵。The switching control circuit according to claim 7, wherein when the inhibiting signal is enabled, the corresponding inhibiting period is timed by the resonant waveform related signal, so that after the inhibiting period ends, the primary side switching signal is in the DCM A third waveform characteristic of the resonant waveform is enabled to achieve zero voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period. 如請求項7所述之切換控制電路，其中當該禁止訊號被致能時，於當前之該切換週期內，該一次側切換訊號的致能時點與該零電壓切換脈波相距1.5個該諧振週期。The switching control circuit as claimed in claim 7, wherein when the disable signal is enabled, in the current switching cycle, the enable time point of the primary side switching signal is 1.5 times the resonance time away from the zero-voltage switching pulse cycle. 如請求項5所述之切換控制電路，其中該一次側控制電路包括： 一斜坡產生電路，用以於每一該切換週期中，該一次側切換訊號的膝點開始產生一基礎斜坡訊號； 一波谷選擇電路，用以於該一次側切換訊號的上升緣取樣與保持該基礎斜坡訊號而產生一波谷記憶訊號，且，用以產生一第一斜坡訊號與一第二斜坡訊號，其中該第一斜坡訊號與該第二斜坡訊號分別與該基礎斜坡訊號具有對應的一第一偏移位準與一第二偏移位準；以及 一禁止訊號產生電路，用以比較該第一斜坡訊號與該基礎斜坡訊號，以及比較該第二斜坡訊號與該基礎斜坡訊號而產生該預禁止訊號，其中該預禁止時段對應於該基礎斜坡訊號介於該第一斜坡訊號與該第二斜坡訊號的期間，且，用以判斷該導通控制訊號的上升緣是否發生於該預禁止時段內而產生該禁止訊號。The switching control circuit as claimed in claim 5, wherein the primary side control circuit comprises: a ramp generating circuit for generating a basic ramp signal from the knee point of the primary side switching signal in each switching period; a valley selection circuit for sampling and maintaining the basic slope signal at the rising edge of the primary side switching signal to generate a valley memory signal, and for generating a first slope signal and a second slope signal, wherein the first slope signal a ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the base ramp signal; and A prohibition signal generating circuit for comparing the first ramp signal with the basic ramp signal, and comparing the second ramp signal with the basic ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to the basic ramp signal During the period between the first ramp signal and the second ramp signal, and used to determine whether the rising edge of the conduction control signal occurs within the pre-inhibition period to generate the inhibit signal. 如請求項10所述之切換控制電路，其中該第一偏移位準與該第二偏移位準相關於該諧振週期。The switching control circuit of claim 10, wherein the first offset level and the second offset level are related to the resonance period. 如請求項10所述之切換控制電路，該一次側控制電路更包括： 一諧振偵測電路，用以根據該功率變壓器的一輔助繞組所產生的一輔助訊號，而產生相關於該諧振波形的一諧振同步訊號； 其中該禁止訊號產生電路更根據該諧振同步訊號，以計時該禁止時段，使得該禁止時段至少維持一個該諧振週期。The switching control circuit as claimed in claim 10, the primary side control circuit further comprises: a resonance detection circuit for generating a resonance synchronization signal related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer; The prohibition signal generating circuit further time the prohibition period according to the resonance synchronization signal, so that the prohibition period maintains at least one resonance period. 一種返馳式轉換器，用以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包含： 一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間； 一一次側開關，用以切換該功率變壓器的一一次側繞組； 一二次側開關，用以切換該功率變壓器的一二次側繞組； 一一次側控制電路，用以產生一一次側切換訊號，以一切換週期控制該一次側開關；以及 一二次側控制電路，用以產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換； 其中，於穩態下，該二次側控制電路根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波，該一次側控制電路根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵； 其中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。A flyback converter for converting an input power to generate an output power, the flyback converter comprising: a power transformer coupled between the input voltage and the output voltage in an electrically insulating manner; a primary side switch for switching a primary side winding of the power transformer; A secondary side switch for switching a secondary side winding of the power transformer; a primary-side control circuit for generating a primary-side switching signal to control the primary-side switch with a switching period; and a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectifying (SR) pulse wave and a zero voltage switching ( zero voltage switching (ZVS) pulse, the synchronous rectification pulse is used to control the secondary side switch to turn on for a synchronous rectification period to achieve secondary side synchronous rectification, the zero voltage switching pulse is used to control the secondary side switch to turn on a zero-voltage switching period, thereby enabling the primary side switch to achieve zero-voltage switching; Wherein, in a steady state, the secondary side control circuit enables the zero-voltage switching pulse wave according to the first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, and the primary side control circuit according to the DCM resonant waveform The second waveform feature enables the primary-side switching signal, wherein the second waveform feature of the DCM resonance waveform is later than the first waveform feature of the DCM resonance waveform; Wherein, when the output power or output current of the output power supply increases compared to the steady state, in the current switching cycle, the primary side control circuit enables the primary side according to the third waveform characteristic of the DCM resonant waveform The switching signal prevents the primary side switch and the secondary side switch from being turned on at the same time, wherein the time point of the third waveform feature is later than the time point corresponding to the second waveform feature in the current switching cycle. 如請求項13所述之返馳式轉換器，其中該DCM諧振波形對應於該一次側開關的汲源極電壓之諧振波形，其中該第二波形特徵對應於該DCM諧振波形的第V個波谷，該第三波形特徵對應於該DCM諧振波形的第W個波谷，其中W大於V。The flyback converter of claim 13, wherein the DCM resonant waveform corresponds to a resonant waveform of a drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the Vth valley of the DCM resonant waveform , the third waveform characteristic corresponds to the Wth trough of the DCM resonance waveform, where W is greater than V. 如請求項13所述之返馳式轉換器，其中，當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，該一次側控制電路控制該一次側切換訊號，於一禁止時段內禁能該一次側切換訊號，使得該一次側切換訊號與該零電壓切換脈波於該禁止時段不重疊，以避免該一次側開關與該二次側開關同時導通； 其中該禁止時段相關於前一個該切換週期內的該一次側切換訊號之上升緣以及該DCM諧振波形的一諧振週期。The flyback converter of claim 13, wherein when the output power or output current of the output power supply increases compared to a steady state, in the current switching cycle, the primary side control circuit controls the primary side control circuit The side switching signal disables the primary side switching signal during a prohibition period, so that the primary side switching signal and the zero-voltage switching pulse do not overlap during the prohibition period, so as to prevent the primary side switch and the secondary side switch at the same time turn on; Wherein the prohibition period is related to the rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform. 如請求項13所述之返馳式轉換器，其中該DCM諧振波形的該諧振週期相關於該一次側繞組的電感值與該一次側開關的雜散電容值。The flyback converter of claim 13, wherein the resonant period of the DCM resonant waveform is related to an inductance value of the primary side winding and a stray capacitance value of the primary side switch. 如請求項15所述之返馳式轉換器，其中該一次側控制電路根據該輸出電源而產生一導通控制訊號，用以觸發該一次側切換訊號且決定該一次側開關於每一切換週期中的導通時點與導通時段，其中該一次側控制電路於每一切換週期中，產生示意一預禁止時段的一預禁止訊號； 其中當該導通控制訊號在該預禁止時段內轉為致能時，該一次側控制電路產生示意該禁止時段的一禁止訊號，以於該禁止時段內遮罩該導通控制訊號而禁能該一次側切換訊號之觸發； 其中該預禁止訊號根據前一個該切換週期的該一次側切換訊號的上升緣以及該諧振週期而產生，其中該預禁止時段涵蓋至少前一個該切換週期的該零電壓切換脈波。The flyback converter of claim 15, wherein the primary side control circuit generates a turn-on control signal according to the output power to trigger the primary side switching signal and determine the primary side switch in each switching cycle The turn-on time point and turn-on period, wherein the primary side control circuit generates a pre-inhibition signal indicating a pre-inhibition period in each switching cycle; When the conduction control signal is turned to be enabled within the pre-inhibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period, so as to mask the conduction control signal and disable the primary during the prohibition period Trigger of side switching signal; The pre-inhibition signal is generated according to the rising edge of the primary side switching signal and the resonance period of the previous switching period, wherein the pre-inhibition period covers at least the zero-voltage switching pulse wave of the previous switching period. 如請求項15所述之返馳式轉換器，其中當該導通控制訊號在該預禁止時段之外轉為致能時，允許該導通控制訊號觸發該一次側切換訊號。The flyback converter of claim 15, wherein when the conduction control signal is enabled outside the pre-inhibition period, the conduction control signal is allowed to trigger the primary side switching signal. 如請求項15所述之返馳式轉換器，其中當該禁止訊號被致能後，根據相關於該諧振波形的一諧振同步訊號計時對應的該禁止時段，使得該禁止時段至少維持一個該諧振週期。The flyback converter of claim 15, wherein when the disable signal is enabled, the corresponding disable period is timed according to a resonant synchronization signal related to the resonant waveform, so that the disable period maintains at least one of the resonances cycle. 如請求項19所述之返馳式轉換器，其中當該禁止訊號被致能後，以該諧振波形相關訊號計時對應的該禁止時段，使得於該禁止時段結束後，該一次側切換訊號於該DCM諧振波形的第三波形特徵而被致能，而達成零電壓切換，其中該第三波形特徵晚於對應於前一個切換週期內的該第二波形特徵。The flyback converter according to claim 19, wherein when the disable signal is enabled, the corresponding disable period is timed by the resonant waveform related signal, so that after the disable period ends, the primary side switching signal is A third waveform characteristic of the DCM resonant waveform is enabled to achieve zero voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period. 一種用以控制一返馳式轉換器之控制方法，以轉換一輸入電源而產生一輸出電源，該返馳式轉換器包括一功率變壓器，以電性絕緣的方式耦接於該輸入電壓與該輸出電壓之間；一一次側開關，用以切換該功率變壓器的一一次側繞組；以及一二次側開關，用以切換該功率變壓器的一二次側繞組；該控制方法包含： 產生一一次側切換訊號，以一切換週期控制該一次側開關；以及 產生一二次側切換訊號，以控制該二次側開關，其中該二次側切換訊號具有一同步整流（Synchronous Rectifying，SR）脈波以及一零電壓切換（zero voltage switching，ZVS）脈波，該同步整流脈波用以控制該二次側開關導通一同步整流時段以達成二次側同步整流，該零電壓切換脈波用以控制該二次側開關導通一零電壓切換時段，藉此使該一次側開關達成零電壓切換； 其中，於穩態下，產生零電壓切換脈波的步驟包括： 根據一DCM（不連續導通模式）諧振波形的第一波形特徵而致能該零電壓切換脈波， 其中，於穩態下，產生該一次側切換訊號的步驟包括： 根據該DCM諧振波形的第二波形特徵而致能該一次側切換訊號，其中該DCM諧振波形的該第二波形特徵晚於該DCM諧振波形的該第一波形特徵；以及 當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，根據該DCM諧振波形的第三波形特徵而致能該一次側切換訊號，以避免該一次側開關與該二次側開關同時導通，其中該第三波形特徵之時點晚於該第二波形特徵於當前的該切換週期中所對應的時點。A control method for controlling a flyback converter to convert an input power source to generate an output power source, the flyback converter includes a power transformer coupled to the input voltage and the input voltage in an electrically insulating manner between output voltages; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the control method includes: generating a primary side switching signal to control the primary side switch with a switching period; and A secondary side switching signal is generated to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectifying (Synchronous Rectifying, SR) pulse wave and a zero voltage switching (zero voltage switching, ZVS) pulse wave, The synchronous rectification pulse is used to control the secondary-side switch to conduct a synchronous rectification period to achieve secondary-side synchronous rectification, and the zero-voltage switching pulse is used to control the secondary-side switch to conduct a zero-voltage switching period, thereby enabling The primary side switch achieves zero-voltage switching; Wherein, in a steady state, the step of generating a zero-voltage switching pulse wave includes: The zero-voltage switching pulse is enabled according to the first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, Wherein, in a steady state, the step of generating the primary side switching signal includes: enabling the primary-side switching signal according to a second waveform feature of the DCM resonant waveform, wherein the second waveform feature of the DCM resonant waveform is later than the first waveform feature of the DCM resonant waveform; and When the output power or output current of the output power supply increases compared to the steady state, in the current switching cycle, the primary side switching signal is enabled according to the third waveform characteristic of the DCM resonant waveform, so as to avoid the primary side switching signal. The side switch and the secondary side switch are turned on at the same time, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching cycle. 如請求項21所述之控制方法，其中該DCM諧振波形對應於該一次側開關的汲源極電壓之諧振波形，其中該第二波形特徵對應於該DCM諧振波形的第V個波谷，該第三波形特徵對應於該DCM諧振波形的第W個波谷，其中W大於V。The control method of claim 21, wherein the DCM resonant waveform corresponds to the resonant waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the Vth trough of the DCM resonant waveform, the th The three waveform features correspond to the Wth trough of the DCM resonant waveform, where W is greater than V. 如請求項13所述之控制方法，其中當該輸出電源的輸出功率或輸出電流相較於穩態為上升時，於當前的該切換週期中，於一禁止時段內禁能該一次側切換訊號，使得該一次側切換訊號與該零電壓切換脈波於該禁止時段不重疊，以避免該一次側開關與該二次側開關同時導通； 其中該禁止時段相關於前一個該切換週期內的該一次側切換訊號之上升緣以及該DCM諧振波形的一諧振週期。The control method of claim 13, wherein when the output power or output current of the output power supply increases compared to a steady state, in the current switching cycle, the primary-side switching signal is disabled within a prohibition period , so that the primary-side switching signal and the zero-voltage switching pulse do not overlap during the prohibition period, so as to prevent the primary-side switch and the secondary-side switch from being turned on at the same time; Wherein the prohibition period is related to the rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform. 如請求項21所述之控制方法，其中該DCM諧振波形的該諧振週期相關於該一次側繞組的電感值與該一次側開關的雜散電容值。The control method of claim 21, wherein the resonant period of the DCM resonant waveform is related to an inductance value of the primary side winding and a stray capacitance value of the primary side switch. 如請求項23所述之控制方法，其中產生該一次側切換訊號的步驟更包括： 根據該輸出電源而產生一導通控制訊號，用以觸發該一次側切換訊號且決定該一次側開關於每一切換週期中的導通時點與導通時段； 於每一切換週期中，產生示意一預禁止時段的一預禁止訊號；以及 當該導通控制訊號在該預禁止時段內轉為致能時，產生示意該禁止時段的一禁止訊號，以於該禁止時段內遮罩該導通控制訊號而禁能該一次側切換訊號之觸發； 其中該預禁止訊號根據前一個該切換週期的該一次側切換訊號的上升緣以及該諧振週期而產生，其中該預禁止時段涵蓋至少前一個該切換週期的該零電壓切換脈波。The control method according to claim 23, wherein the step of generating the primary side switching signal further comprises: generating a turn-on control signal according to the output power, for triggering the primary side switching signal and determining the turn-on time point and turn-on period of the primary side switch in each switching cycle; In each switching cycle, a pre-inhibit signal indicating a pre-inhibit period is generated; and When the conduction control signal is turned to be enabled within the pre-inhibition period, an inhibition signal indicating the inhibition period is generated, so as to mask the conduction control signal and disable the triggering of the primary side switching signal during the inhibition period; The pre-inhibition signal is generated according to the rising edge of the primary side switching signal and the resonance period of the previous switching period, wherein the pre-inhibition period covers at least the zero-voltage switching pulse of the previous switching period. 如請求項23所述之控制方法，其中產生該一次側切換訊號的步驟更包括：當該導通控制訊號在該預禁止時段之外轉為致能時，允許該導通控制訊號觸發該一次側切換訊號。The control method as claimed in claim 23, wherein the step of generating the primary-side switching signal further comprises: when the conducting-control signal turns to be enabled outside the pre-inhibition period, allowing the conducting-control signal to trigger the primary-side switching signal. 如請求項23所述之控制方法，其中產生該一次側切換訊號的步驟更包括：當該禁止訊號被致能後，根據相關於該諧振波形的一諧振同步訊號計時對應的該禁止時段，使得該禁止時段至少維持一個該諧振週期。The control method of claim 23, wherein the step of generating the primary-side switching signal further comprises: when the prohibition signal is enabled, timing the corresponding prohibition period according to a resonant synchronization signal related to the resonant waveform, so that The prohibition period is maintained for at least one of the resonance periods. 如請求項27所述之控制方法，其中產生該一次側切換訊號的步驟更包括：當該禁止訊號被致能後，以該諧振波形相關訊號計時對應的該禁止時段，使得於該禁止時段結束後，該一次側切換訊號於該DCM諧振波形的第三波形特徵而被致能，而達成零電壓切換，其中該第三波形特徵晚於對應於前一個切換週期內的該第二波形特徵。The control method of claim 27, wherein the step of generating the primary-side switching signal further comprises: when the prohibition signal is enabled, timing the corresponding prohibition period with the resonant waveform related signal, so that the prohibition period ends Then, the primary-side switching signal is enabled at a third waveform characteristic of the DCM resonant waveform to achieve zero-voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period. 如請求項25所述之控制方法，其中產生該禁止訊號的步驟包括： 於每一該切換週期中，該一次側切換訊號的膝點開始產生一基礎斜坡訊號； 於該一次側切換訊號的上升緣取樣與保持該基礎斜坡訊號而產生一波谷記憶訊號； 產生一第一斜坡訊號與一第二斜坡訊號，其中該第一斜坡訊號與該第二斜坡訊號分別與該基礎斜坡訊號具有對應的一第一偏移位準與一第二偏移位準； 比較該第一斜坡訊號與該基礎斜坡訊號，且，比較該第二斜坡訊號與該基礎斜坡訊號而產生該預禁止訊號，其中該預禁止時段對應於該基礎斜坡訊號介於該第一斜坡訊號與該第二斜坡訊號的期間；以及 判斷該導通控制訊號的上升緣是否發生於該預禁止時段內而產生該禁止訊號。The control method as claimed in claim 25, wherein the step of generating the prohibition signal comprises: In each switching period, the knee point of the primary side switching signal starts to generate a basic ramp signal; sampling and maintaining the basic ramp signal at the rising edge of the primary side switching signal to generate a valley memory signal; generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the base ramp signal; comparing the first ramp signal with the base ramp signal, and comparing the second ramp signal with the base ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to the base ramp signal between the first ramp signal and the period of the second ramp signal; and It is judged whether the rising edge of the conduction control signal occurs within the pre-inhibition period to generate the inhibit signal. 如請求項29所述之控制方法，其中該第一偏移位準與該第二偏移位準相關於該諧振週期。The control method of claim 29, wherein the first offset level and the second offset level are related to the resonance period.
TW110103901A 2020-07-03 2021-02-02 Flyback converter and switching controller circuit and control method thereof TWI783365B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/356,767 US11496063B2 (en) 2020-07-03 2021-06-24 Flyback converter and switching controller circuit and control method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063048074P 2020-07-03 2020-07-03
US63/048074 2020-07-03

Publications (2)

Publication Number Publication Date
TW202203564A true TW202203564A (en) 2022-01-16
TWI783365B TWI783365B (en) 2022-11-11

Family

ID=79013063

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110103901A TWI783365B (en) 2020-07-03 2021-02-02 Flyback converter and switching controller circuit and control method thereof

Country Status (2)

Country Link
CN (1) CN113890365B (en)
TW (1) TWI783365B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296544A (en) * 2022-07-22 2022-11-04 昂宝电子（上海）有限公司 Flyback power converter based on primary side feedback

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070109822A1 (en) * 2005-11-14 2007-05-17 Kan-Sheng Kuan Zero voltage switch method for synchronous rectifier and inverter
US7869231B2 (en) * 2008-07-31 2011-01-11 Texas Instruments Incorporated System and method for synchronous rectifier drive that enables converters to operate in transition and discontinuous mode
US10622902B2 (en) * 2012-04-12 2020-04-14 On-Bright Electronics (Shanghai) Co., Ltd. Systems and methods for regulating power conversion systems with output detection and synchronized rectifying mechanisms
TWI458245B (en) * 2013-01-07 2014-10-21 Richtek Technology Corp Switching power conversion device and its switching controller and driving method
TWI599160B (en) * 2015-05-06 2017-09-11 立錡科技股份有限公司 Flyback power converter and controller and driver thereof
US9899931B1 (en) * 2016-10-25 2018-02-20 Alpha And Omega Semiconductor Incorporated Zero voltage switching flyback converter for primary switch turn-off transitions
US10566893B2 (en) * 2017-11-10 2020-02-18 Richtek Technology Corporation ZVS control circuit for use in a flyback power converter
US10574147B2 (en) * 2018-01-16 2020-02-25 Texas Instruments Incorporated Methods and apparatus for zero voltage switching using flyback converters
US10560012B1 (en) * 2018-07-27 2020-02-11 Richtek Technology Corporation ZVS control circuit for use in a flyback power converter
US10425080B1 (en) * 2018-11-06 2019-09-24 Crane Electronics, Inc. Magnetic peak current mode control for radiation tolerant active driven synchronous power converters
CN113489328B (en) * 2018-11-08 2024-02-27 立锜科技股份有限公司 Zero-voltage switching control circuit, flyback power supply circuit and control method thereof

Also Published As

Publication number Publication date
TWI783365B (en) 2022-11-11
CN113890365B (en) 2023-09-29
CN113890365A (en) 2022-01-04

Similar Documents

Publication Publication Date Title
US10566893B2 (en) ZVS control circuit for use in a flyback power converter
US9407155B2 (en) Isolated switching converter with secondary side modulation and control method
US8218339B2 (en) Power converter having synchronous rectifier and control method of synchronous rectifier
US11201554B2 (en) Flyback power converter and ZVS control circuit and control method thereof
KR101658207B1 (en) Synchronous rectification circuit and synchronous rectification m1ethod
TWI707527B (en) Flyback powr converter and secondary side controller circuit and control method thereof
CN113489328B (en) Zero-voltage switching control circuit, flyback power supply circuit and control method thereof
TWI811910B (en) Isolated switching converter with secondary side modulation and control method
TW201018062A (en) Control circuit having off-time modulation to operate power converter at quasi-resonance and in continuous current mode
KR101727290B1 (en) Converter and the driving method thereof
KR101542645B1 (en) On time sampling prevention
TWI777412B (en) Resonant half-bridge flyback power converter and primary controller circuit and control method thereof
CN111628632B (en) Flyback power supply circuit and zero voltage switching control circuit and control method thereof
US11496063B2 (en) Flyback converter and switching controller circuit and control method thereof
US20220052613A1 (en) Synchronous rectification control system and method for quasi-resonant flyback converter
CN113726165A (en) Flyback converter and control method thereof
TWI783365B (en) Flyback converter and switching controller circuit and control method thereof
CN111162676B (en) Flyback power supply circuit and zero voltage switching control circuit and control method thereof
CN109450256B (en) Quasi-resonance power supply controller
CN112713778B (en) Switching control circuit and method for controlling flyback power supply circuit
Koo et al. A new valley-detection method for the quasi-resonance switching
CN114079381B (en) Flyback power conversion circuit and active clamping buffer thereof
TWI842520B (en) Asymmetric half-bridge flyback converter power supply and its control circuit
KR20160147689A (en) Converter and the driving method thereof
KR20140072857A (en) Converter and the driving method thereof