CN113890365B

CN113890365B - Flyback converter and switching control circuit and control method thereof

Info

Publication number: CN113890365B
Application number: CN202110176038.4A
Authority: CN
Inventors: 陈裕昌; 张炜旭; 林昆馀; 杨大勇
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2020-07-03
Filing date: 2021-02-09
Publication date: 2023-09-29
Anticipated expiration: 2041-02-09
Also published as: TWI783365B; TW202203564A; CN113890365A

Abstract

A flyback converter and a switching control circuit and a control method thereof. The flyback converter includes: the power transformer, primary side switch, secondary side switch, and switching control circuit. The secondary side switching signal has synchronous rectification pulse and zero voltage switching pulse to realize the synchronous rectification of the secondary side and the zero voltage switching of the primary side switch. The zero voltage switching pulse is enabled according to a first waveform characteristic of the resonant waveform and the primary side switching signal is enabled according to a second waveform characteristic of the resonant waveform. When the output current rises, the primary side switching signal is forbidden in the forbidden period, so that the primary side switching signal and the zero voltage switching pulse are not overlapped in the forbidden period, and the primary side switch and the secondary side switch are prevented from being conducted simultaneously. The prohibition period is related to the rising edge of the primary-side switching signal in the previous switching period and the resonance period of the resonance waveform.

Description

Flyback converter and switching control circuit and control method thereof

Technical Field

The present invention relates to flyback converters, and more particularly to a flyback converter with zero voltage switching and capable of avoiding short-circuit current between a primary side and a secondary side. The invention also relates to a control circuit and a control method for the flyback power supply.

Background

Fig. 1A and 1B show prior art flyback converters (flyback converters 1001A and 1001B). The primary side control circuit 80 is configured to generate a primary side switching signal S1C, thereby controlling the primary side switch S1 to switch the power transformer 10 to generate the output voltage Vo, and the secondary side control circuit 90 is configured to generate a secondary side switching signal S2C, thereby controlling the secondary side switch S2 to perform synchronous rectification and zero voltage switching (ZVS, zero voltage switching). The secondary side switches S2 in flyback converters 1001A and 1001B are respectively located at the lower side and the upper side of the secondary side winding.

FIG. 2 is a schematic diagram showing the waveforms of the flyback converter according to the prior art of FIGS. 1A and 1B. The prior art flyback converter operates in discontinuous conduction mode (DCM-Discontinuous Conduction Mode). The secondary side switching signal S2C of the flyback converter 1001A or 1001B has a synchronous rectification pulse PSR and a zero voltage switching (zero voltage switching, ZVS) pulse PZV, and the synchronous rectification pulse PSR is used to control the synchronous rectification switch S2 to be turned on in the demagnetization stage of the power transformer 10 to realize synchronous rectification of the secondary side when the primary side switch S1 is turned on and turned off again, and the zero voltage switching pulse PZV is used to realize zero voltage switching of the primary side switch S1.

In this prior art, a "peak/valley lock" technique is adopted, a waveform characteristic of the resonant waveform (e.g., the resonant waveform of the primary side switch voltage VDS1 at DCM) is adaptively selected according to the level of the output current, and the peak of a certain order of the resonant waveform of the primary side switch voltage VDS1 at DCM (e.g., the third peak P3 of VDS 1) starts the zero voltage switching pulse PZV. In addition, the primary control circuit 80 and the secondary control circuit 90 synchronize the turn-on timing of the primary switch S1 according to another characteristic of the resonant waveform (e.g., the trough V4 of the adjacent bit (e.g., the fourth trough V1 of the VDS 1)). Therefore, the prior art can enable the primary side switch S1 and the secondary side switch S2 to achieve zero voltage switching, so as to improve the power conversion efficiency, and enable the switching time of the primary side switch S1 and the switching time of the secondary side switch S2 to be synchronous and not overlapped under the condition that an additional isolated communication path (such as a pulse transformer) is not needed, thereby avoiding short-circuit current caused by simultaneous conduction.

However, under some load variations, the primary switch S1 and the secondary switch S2 are turned on simultaneously to cause a short-circuit current, as shown in fig. 3, which is a disadvantage of the prior art. FIG. 3 is a schematic diagram showing the waveforms of the flyback converter according to the prior art of FIGS. 1A and 1B. The load current Io during the switching period [ n ] increases during the switching period [ n+1], and the primary side S1 switch signal S1C is turned on in advance due to the increase of the load current, and at this time, if the PZV signal of the secondary side switching signal S2C maintains the on time of the previous switching period, the primary side switch and the secondary side switch are turned on simultaneously, resulting in a short circuit, and burning the converter.

Compared with the prior art, the invention can ensure that the primary side switch S1 and the secondary side switch S2 can achieve zero voltage switching, and can ensure that the switching time of the primary side switch S1 and the secondary side switch S2 is synchronous, and can effectively avoid short-circuit current caused by the simultaneous conduction of the primary side switch S1 and the secondary side switch S2 under various load changes.

Disclosure of Invention

In one aspect, the present invention provides a switching control circuit for controlling a flyback converter to convert an input power to generate an output power, the flyback converter including a power transformer electrically coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the switching control circuit includes: a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and a secondary side control circuit for generating a secondary side switching signal for controlling the secondary side switch, wherein the secondary side switching signal has a synchronous rectification (Synchronous Rectifying, SR) pulse for controlling the secondary side switch to conduct a synchronous rectification period for secondary side synchronous rectification and a zero voltage switching (zero voltage switching, ZVS) pulse for controlling the secondary side switch to conduct a zero voltage switching period for thereby enabling the primary side switch to achieve zero voltage switching; wherein the secondary side control circuit enables the zero voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary side control circuit enables the primary side switching signal according to a second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; when the output power or the output current of the output power supply is increased compared with the steady state, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the DCM resonance waveform in the current switching period so as to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

In a preferred embodiment, the DCM resonance waveform corresponds to the resonance waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to the V-th trough of the DCM resonance waveform and the third waveform characteristic corresponds to the W-th trough of the DCM resonance waveform, wherein W is greater than V.

In a preferred embodiment, when the output power or the output current of the output power supply is increased compared with a steady state, the primary side control circuit controls the primary side switching signal in the current switching period to inhibit the primary side switching signal in an inhibit period, so that the primary side switching signal and the zero voltage switching pulse are not overlapped in the inhibit period, and the primary side switch and the secondary side switch are prevented from being simultaneously turned on; the inhibit period is related to a rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform.

In a preferred embodiment, the resonant period of the DCM resonant waveform is related to the inductance of the primary winding and the stray capacitance of the primary switch.

In a preferred embodiment, the primary side control circuit generates a turn-on control signal according to the output power source, for triggering the primary side switching signal and determining a turn-on time and a turn-on period of the primary side switch in each switching cycle, wherein the primary side control circuit generates a pre-inhibit signal indicating a pre-inhibit period in each switching cycle; when the conduction control signal turns into enable in the pre-prohibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period so as to shield the conduction control signal in the prohibition period and prohibit triggering of the primary side switching signal; the pre-inhibit signal is generated according to a rising edge of the primary side switching signal of a previous switching period and the resonance period, wherein the pre-inhibit period covers at least the zero voltage switching pulse of the previous switching period.

In a preferred embodiment, the turn-on control signal is enabled to trigger the primary side switching signal when the turn-on control signal transitions to enable outside the pre-inhibit period.

In a preferred embodiment, after the disable signal is enabled, the corresponding disable period is clocked according to a resonant synchronizing signal associated with the resonant waveform, such that the disable period maintains at least one of the resonant periods.

In a preferred embodiment, after the disable signal is enabled, the corresponding disable period is clocked with the resonant waveform-related signal such that after the disable period is completed, the primary side switching signal is enabled at a third waveform characteristic of the DCM resonant waveform, which is later than the second waveform characteristic corresponding to the previous switching period, to effect zero voltage switching.

In a preferred embodiment, when the disable signal is enabled, the enable timing of the primary side switch signal is 1.5 resonant periods from the zero voltage switch pulse during the current switch period.

In a preferred embodiment, the primary side control circuit includes: a ramp generating circuit for generating a basic ramp signal at the knee point of the primary side switching signal in each switching period; the trough selection circuit is used for sampling and maintaining the basic slope signal at the rising edge of the primary side switching signal to generate a trough memory signal, and is used for generating a first slope signal and a second slope signal, wherein the first slope signal and the second slope signal respectively have a first offset level and a second offset level corresponding to the basic slope signal; and a disable signal generating circuit for comparing the first ramp signal with the base ramp signal and comparing the second ramp signal with the base ramp signal to generate the pre-disable signal, wherein the pre-disable period corresponds to a period of time that the base ramp signal is between the first ramp signal and the second ramp signal, and for determining whether a rising edge of the on control signal occurs within the pre-disable period to generate the disable signal.

In a preferred embodiment, the first and second bias levels are related to the resonant period.

In a preferred embodiment, the primary side control circuit further comprises: a resonance detection circuit for generating a resonance synchronizing signal related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer; the prohibiting signal generating circuit also clocks the prohibiting period according to the resonance synchronizing signal so that the prohibiting period maintains at least one resonance period.

In another aspect, the present invention also provides a flyback converter for converting an input power to generate an output power, the flyback converter comprising: a power transformer electrically coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; a secondary side switch for switching a secondary side winding of the power transformer; a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and a secondary side control circuit for generating a secondary side switching signal for controlling the secondary side switch, wherein the secondary side switching signal has a synchronous rectification (Synchronous Rectifying, SR) pulse for controlling the secondary side switch to conduct a synchronous rectification period for secondary side synchronous rectification and a zero voltage switching (zero voltage switching, ZVS) pulse for controlling the secondary side switch to conduct a zero voltage switching period for thereby enabling the primary side switch to achieve zero voltage switching; wherein the secondary side control circuit enables the zero voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary side control circuit enables the primary side switching signal according to a second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; when the output power or the output current of the output power supply is increased compared with the steady state, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the DCM resonance waveform in the current switching period so as to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

In another aspect, the present invention also provides a control method for controlling a flyback converter to convert an input power to generate an output power, the flyback converter including a power transformer electrically coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the method comprises the following steps: generating a primary side switching signal to control the primary side switch in a switching period; and generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectification (Synchronous Rectifying, SR) pulse and a zero voltage switching (zero voltage switching, ZVS) pulse, the synchronous rectification pulse is used for controlling the secondary side switch to conduct a synchronous rectification period to realize secondary side synchronous rectification, and the zero voltage switching pulse is used for controlling the secondary side switch to conduct a zero voltage switching period, thereby enabling the primary side switch to realize zero voltage switching; wherein, in a steady state, the step of generating a zero voltage switching pulse comprises: enabling the zero voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the step of generating the primary side switching signal in steady state comprises: enabling the primary-side switching signal according to a second waveform characteristic of the DCM resonance waveform, wherein the second waveform characteristic of the DCM resonance waveform is later than the first waveform characteristic of the DCM resonance waveform; and when the output power or the output current of the output power supply is increased compared with the steady state, enabling the primary side switching signal according to a third waveform characteristic of the DCM resonance waveform in the current switching period so as to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

In a preferred embodiment, when the output power or the output current of the output power supply is increased compared with a steady state, the primary side switching signal is inhibited for an inhibition period in the current switching period, so that the primary side switching signal and the zero voltage switching pulse are not overlapped in the inhibition period, and the primary side switch and the secondary side switch are prevented from being simultaneously conducted; the inhibit period is related to a rising edge of the primary side switching signal in the previous switching period and a resonance period of the DCM resonance waveform.

In a preferred embodiment, the step of generating the primary-side switching signal further comprises: generating a conduction control signal according to the output power supply, wherein the conduction control signal is used for triggering the primary side switching signal and determining the conduction time point and the conduction period of the primary side switch in each switching period; generating a pre-inhibit signal indicating a pre-inhibit period in each switching cycle; and when the conduction control signal turns to enable in the pre-prohibition period, generating a prohibition signal indicating the prohibition period, so as to shield the conduction control signal in the prohibition period and prohibit triggering of the primary side switching signal; the pre-inhibit signal is generated according to a rising edge of the primary side switching signal of a previous switching period and the resonance period, wherein the pre-inhibit period covers at least the zero voltage switching pulse of the previous switching period.

In a preferred embodiment, the step of generating the primary-side switching signal further comprises: when the conduction control signal is turned to be enabled outside the pre-prohibition period, the conduction control signal is allowed to trigger the primary side switching signal.

In a preferred embodiment, the step of generating the primary-side switching signal further comprises: when the inhibit signal is enabled, the corresponding inhibit period is timed according to a resonance synchronizing signal related to the resonance waveform, so that the inhibit period maintains at least one resonance period.

In a preferred embodiment, the step of generating the primary-side switching signal further comprises: when the inhibit signal is enabled, the corresponding inhibit period is clocked with the resonant waveform-related signal such that after the inhibit period is over, the primary-side switching signal is enabled at a third waveform characteristic of the DCM resonant waveform, where the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period, to effect zero-voltage switching.

In a preferred embodiment, the step of generating the disable signal includes: in each switching period, the knee point of the primary side switching signal starts to generate a basic slope signal; sampling and holding the basic ramp signal at the rising edge of the primary side switching signal to generate a trough memory signal; generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the base ramp signal; comparing the first ramp signal with the basic ramp signal, and comparing the second ramp signal with the basic ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to a period of time that the basic ramp signal is between the first ramp signal and the second ramp signal; and judging whether the rising edge of the conduction control signal occurs in the pre-prohibition period to generate the prohibition signal.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.

Drawings

Fig. 1A and 1B are schematic diagrams illustrating a flyback converter according to the prior art.

FIG. 2 is a schematic diagram showing the waveforms of the flyback converter according to the prior art of FIGS. 1A and 1B.

FIG. 3 is a schematic diagram showing the waveforms of the flyback converter according to the prior art of FIGS. 1A and 1B.

FIG. 4 shows a schematic diagram of a flyback converter according to a preferred embodiment of the present invention.

Fig. 5 shows a waveform diagram corresponding to an embodiment of the flyback converter of the present invention.

Fig. 6 shows a waveform diagram corresponding to an embodiment of the flyback converter of the present invention.

Fig. 7 shows a schematic diagram of an embodiment of a resonant detection circuit in the flyback converter according to the present invention.

FIG. 8 shows a schematic diagram of a valley correcting circuit in a flyback converter according to an embodiment of the present invention.

FIG. 9 shows a schematic diagram of an embodiment of a knee point detection circuit in a flyback converter according to the present invention.

Fig. 10 shows a schematic diagram of a ramp generation circuit in the flyback converter according to an embodiment of the present invention.

FIG. 11 shows a schematic diagram of a valley selection circuit in a flyback converter according to an embodiment of the present invention.

Fig. 12 shows a schematic diagram of an embodiment of a disable signal generation circuit in the flyback converter according to the present invention.

Fig. 13 shows a schematic diagram of an embodiment of a PWM generation circuit in the flyback converter according to the present invention.

FIG. 14 shows a schematic diagram of a flyback converter according to an embodiment of the present invention.

Description of the symbols in the drawings

10: power transformer

661 a,1001b,1004: flyback converter

110: PWM generating circuit

111: timer device

112: flip-flop

120: negative edge detection circuit

121: delay circuit

130: resonance detection circuit

131: amplifying circuit

132: transistor with a high-voltage power supply

133: current-voltage conversion circuit

140: trough correction circuit

141: delay circuit

150: knee point detection circuit

151: comparator with a comparator circuit

152: pulse circuit

153: status circuit

160: ramp generation circuit

161: flip-flop

162: integrating circuit

170: trough selection circuit

171: amplifier

172: offset circuit

173, 175: sample-and-hold circuit

180: inhibit signal generating circuit

181, 182: comparator with a comparator circuit

183, 184, 185: flip-flop

80, 100: primary side control circuit

90, 200: secondary side control circuit

Cp: parasitic capacitance

CyL: negative edge signal

FBR: feedback related signals

INH: inhibit signal

Io: output current

Ip: primary side current

Isr: secondary side current

KCdb: delaying an inverted signal

Knee: knee point signal

KneeCMP: comparison result

KP: pulse at knee point

P1 to P4: wave crest

P_inh: pre-inhibit signal

P_PWM: trough indication signal

PSR: synchronous rectification pulse

PZV: zero voltage switching pulse

RH1: ramp level signal

Rmp, rmp0, rmp1, rmp2: ramp signal

RmpEN: ramp enable signal

RST: system reset signal

S1: primary side switch

S1C: primary side switching signal

S2C: secondary side switching signal

S2: secondary side switch

SYNC: resonant synchronizing signal

t2 to t15: time point

TD: conduction control signal

Tinh: forbidden period of time

Tpinh: pre-inhibit period

Trng: resonance period

TSR: synchronous rectification period

TZV: pulse width

V1 to V4: trough of wave

Vaux, DEMAG: auxiliary voltage

VDS1: primary side switching voltage

VDS2: secondary side switching voltage

Vin: input voltage

VK, VR: reference signal

VN: trough memory signal

Vo: output voltage

W1: primary side winding

W2: secondary side winding

W3: auxiliary winding

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

Fig. 4 shows a schematic diagram of a flyback converter according to a preferred embodiment of the present invention (flyback converter 1004). The flyback converter 1004 is configured to convert an input voltage Vin to generate an output voltage Vo and an output current Io, and provide power to a load circuit (not shown, well known to those skilled in the art, and not described herein). Flyback converter 1004 includes power transformer 10, primary side control circuit 100, and secondary side control circuit 200.

The power transformer 10 is electrically coupled between the input voltage Vin and the output voltage Vo, and the primary switch S1 is coupled to a primary winding W1 of the power transformer 10, wherein the primary winding W1 is coupled to the input voltage Vin. The secondary side switch S2 and the secondary side winding W2 of the power transformer 10 are connected in series between the output voltage Vo and the secondary side ground node. In the present embodiment, the secondary switch S2 is coupled between the secondary winding W2 of the power transformer 10 and the secondary ground node. The secondary switch S2 may also be coupled between the secondary winding W2 of the power transformer 10 and the output voltage Vo, as illustrated in the secondary circuit of fig. 1B. For simplicity of explanation, an embodiment in which the secondary side switch S2 is coupled between the secondary side winding W2 and the secondary side ground node of the power transformer 10 as shown in fig. 4 is described below, but the same spirit is also applicable to another form as shown in the secondary side of fig. 1B.

The primary side control circuit 100 is configured to generate a primary side switching signal S1C, and the primary side switching signal S1C is configured to control the primary side switch S1 to switch the primary winding W1 of the power transformer 10, wherein the primary winding W1 is coupled to the input voltage Vin. The secondary side control circuit 200 is configured to generate a secondary side switching signal S2C to control on and off of the secondary side switch S2, and to switch the secondary side winding W2 of the power transformer 10 to generate the output voltage Vo. Where VDS1 is the voltage at the drain of primary side switch S1 and VDS2 is the voltage at the first terminal of secondary side switch S2. In this embodiment, the first end of the secondary side switch S2 is a drain (current flowing end), and the second end of the secondary side switch S2 is a source (current flowing end). It should be noted that, in the embodiment in which the secondary side switch S2 is coupled between the secondary side winding W2 of the power transformer 10 and the output voltage Vo, as shown in the secondary side circuit of fig. 1B, the first end of the secondary side switch S2 is a source (current inflow end), and the second end of the secondary side switch S2 is a drain (current outflow end).

Referring to fig. 5, fig. 5 shows waveforms of the flyback converter according to the embodiment of the present invention. In this embodiment, the flyback converter of the present invention operates in discontinuous conduction mode (DCM-Discontinuous Conduction Mode). According to the present invention, the secondary side switching signal S2C has a synchronous rectification pulse PSR and a zero voltage switching (zero voltage switching, ZVS) pulse PZV, when the primary side switch S1 is turned on and turned off again (as t3 in fig. 5), the synchronous rectification pulse PSR is used to control the secondary side switch S2 to turn on a synchronous rectification period TSR for implementing synchronous rectification of the secondary side, wherein the synchronous rectification period TSR is substantially synchronous with a conduction period of an induced current of the secondary side winding W2, in other words, the synchronous rectification period TSR starts at a time point (t 3) when the secondary side winding W2 transfers energy from the primary side winding W1 to generate the secondary side current Isr, and the synchronous rectification period TSR ends at a time point (t 4) when the secondary side current Isr of the secondary side winding W2 falls to 0, so as to enhance the power conversion efficiency.

With continued reference to fig. 5, on the other hand, the zero voltage switching pulse PZV is utilized to achieve the zero voltage switching of the primary switch S1. In detail, in the present embodiment, when the flyback converter 1004 is operated in the discontinuous conduction mode, the power transformer 10 is magnetically induced when the primary switch S1 is turned on (t 2-t3, fig. 5), and the energy obtained when the primary switch S1 is turned off is transferred to the output voltage Vo; when the synchronous rectification pulse PSR controls the secondary side switch S2 to be turned on, so that the power transformer 10 is demagnetized (t 4, fig. 5), the secondary side switch S2 is controlled to be turned off (t 4-t5, fig. 5), and the power transformer 10 starts to generate a DCM resonance waveform, which may correspond to, for example, the primary side voltage VDS1, the secondary side voltage VDS2 or the auxiliary voltage Vaux or DEMAG generated by the auxiliary winding W3, and the resonance period Trng of the DCM resonance waveform is related to the inductance value and the stray capacitance value of the power transformer 10, particularly the inductance value and the associated stray capacitance value of the primary side winding W1.

When the secondary side switch S2 is turned on again according to the zero voltage switching pulse PZV (e.g. t5 of fig. 5), the power transformer 10 induces a negative secondary side current Isr in the secondary side winding W2, and when the secondary side switch S2 is turned off again at the end of the zero voltage switching pulse PZV (e.g. t 6), the power transformer 10 induces a negative primary side current Ip in the primary side winding W1, during which (e.g. t6-t 7), the negative primary side current Ip can discharge the parasitic capacitance Cp of the primary side switch S1, so that the drain voltage VDS1 of the primary side switch S1 drops to a lower voltage, and charges are charged back to the input power source through the primary side winding W1, and when the primary side switch S1 is turned on, the primary side switch S1 can realize flexible switching. In a preferred embodiment, the negative primary side current Ip discharges the parasitic capacitance Cp of the primary side switch S1 to substantially 0V, which enables the primary side switch S1 to achieve zero voltage switching (ZVS-Zero Voltage Switching).

It should be noted that, the aforementioned "zero-voltage switching" means that, before the transistor (corresponding to the primary side switch S1) is turned on, the residual voltage of the parasitic capacitance of the transistor is discharged to a lower voltage through the energy-free discharging path (corresponding to the primary side winding W1, for example) and charges are charged back into the energy-free element (such as the input power supply), so that when the transistor is turned on, the drain-source voltage of the transistor is reduced to the lower voltage, and the charge stored in the parasitic capacitance (corresponding to Cp, for example) is not discharged by the on-resistance of the transistor in the process, thereby improving the power conversion efficiency.

In addition, it should be noted that: since the parasitic effects of the circuit components themselves or the mutual matching between the components are not necessarily ideal, although the parasitic capacitance Cp is intended to be discharged to 0V, it may not be possible to accurately discharge to 0V, but only to approximately 0V, that is, according to the present invention, it is acceptable that the voltage after the parasitic capacitance Cp is discharged and 0V have a certain degree of error due to the circuit non-ideality, which means that the foregoing discharge is to be "approximately" 0V, and other references are also made herein to "approximately".

In an embodiment, the starting point of the zero voltage switching pulse PZV is synchronized with the first waveform characteristic of the resonant waveform after the power transformer 10 is demagnetized, for example, in the embodiment of fig. 5, the secondary side control circuit 200 adaptively selects the secondary side switching voltage VDS2 according to the level of the output current Io, and starts the zero voltage switching pulse PZV after the power transformer 10 is demagnetized, so that the secondary side switch S2 also reaches the zero voltage switching. For example, in fig. 5, the zero voltage switching pulse PZV, which corresponds to the third valley of VDS2 and is also the third peak P3 of VDS1, is labeled P3 for uniformity according to the characteristics of the primary switch voltage VDS1 at time t 5. In addition, the primary-side control circuit 100 adaptively selects another characteristic of the resonant waveform according to the level of the output current Io, for example, a trough (e.g., a fourth trough V4 of the VDS1 at time t7 of fig. 5) of the adjacent sequence bits is used as the conduction start time of the primary-side switch S1. Therefore, the primary side switch S1 and the secondary side switch S2 can achieve zero-voltage switching, so that the power conversion efficiency is improved, and the switching time of the primary side switch S1 and the switching time of the secondary side switch S2 are synchronous and do not overlap under the condition that an additional isolated communication path (such as a pulse transformer) is not needed. In a preferred embodiment, in a steady state (e.g., switching period [ n ] in FIG. 5), the non-overlapping time between the switches of the primary side switch S1 and the secondary side switch S2 is 0.5 resonant periods Trng.

With reference to fig. 5, in order to avoid the aforementioned short-circuit current, in an embodiment, for example, when the output current Io or the output power increases due to a load change, the on-time of the primary switch S1 is delayed by at least one resonance period Trng of the resonance waveform, for example, in fig. 5, when the output current Io increases at a time t8, in the switching period [ n+1], when the flyback converter 1004 intends to conduct the primary switch S1 earlier than the previous switching period according to feedback, the primary switch S1 is shielded and delayed by a forbidden period Tinh (t 9-t 11) as shown in the figure, so that the primary switch S1 starts to conduct in the switching period [ n+1] to the fifth trough V5 (t 11) of the primary switch voltage VDS 1. In other words, the primary side switching signal S1C and the zero voltage switching pulse PZV are ensured not to overlap in the inhibit period Tinh, so that the primary side switch S1 and the secondary side switch S2 are effectively prevented from being turned on simultaneously.

With continued reference to fig. 5, in one embodiment, when the flyback converter 1004 is about to conduct earlier than the previous switching cycle according to the feedback, and the timing of the early conduction is earlier than the start timing of the zero voltage switching pulse PZV, the conduction timing of the primary switch S1 is determined according to the feedback, i.e. without delay as described above. For example, in fig. 5, in the switching period [ n+2], when the flyback converter 1004 is advanced to the third valley V3 (t 12) of the primary-side switching voltage VDS1 according to the feedback, the primary-side switch S1 is turned on directly at the third valley V3 (t 12) of the primary-side switching voltage VDS1 because the third valley V3 of the primary-side switching voltage VDS1 is earlier than the starting point (e.g., P3 of t 13) of the zero-voltage switching pulse PZV in the switching period [ n+2 ]. In addition, when the on time of the primary switch S1 is earlier than the zero voltage switching pulse PZV, the switching period [ n+2] will not generate the zero voltage switching pulse PZV.

According to the present invention, in one embodiment, the prohibition period Tinh of any current switching period (e.g. the switching period [ n+1 ]) is related to the position of the zero voltage switching pulse PZV of the previous switching period (e.g. the switching period [ n ]), specifically, the prohibition period Tinh is generated according to the rising edge of the primary side switching signal S1C in the previous switching period and the resonance period Trng of the DCM resonant waveform, and the implementation details will be described later.

With continued reference to fig. 5, after a new steady state is achieved according to the increased output current Io, as shown in the switching period [ n+3], the primary switch S1 is turned on in the third valley V3 (t 15) of the primary switch voltage VDS1, and the zero voltage switching pulse PZV is also adaptively advanced to start with the second peak P2 (t 14, corresponding to the second valley of the primary switch voltage VDS 2) of the primary switch voltage VDS 1.

Referring to fig. 4, fig. 4 further shows an embodiment of the primary side control circuit (primary side control circuit 100) in the flyback converter of the present invention. In this embodiment, the primary side control circuit 100 includes a PWM (pulse width modulation ) generating circuit 110, a negative edge detecting circuit 120, a resonance detecting circuit 130, a valley correcting circuit 140, a knee point detecting circuit 150, a ramp generating circuit 160, a valley selecting circuit 170, and a disable signal generating circuit 180.

Referring to fig. 6, fig. 6 shows waveforms of the flyback converter according to the embodiment of the present invention.

In an embodiment, the PWM generation circuit 110 generates the on control signal TD according to feedback (such as, but not limited to, the output voltage Vo and/or the output current Io), thereby triggering and determining the on time and the on period of the primary side switch S1, and the PWM generation circuit 110 also generates the primary side switching signal S1C according to the valley indication signal p_pwm and the inhibit signal INH for controlling the primary side switch S1.

The negative edge detection circuit 120 is configured to detect a negative edge (i.e., a falling edge) of the primary side switching signal S1C to generate a negative edge signal CyL, which is used to indicate an occurrence point of the negative edge of the primary side switching signal S1C.

The ramp generating circuit 160 is configured to generate the ramp signal Rmp according to the Knee point signal Knee and the negative edge signal CyL, and specifically, the ramp generating circuit 160 starts generating the ramp signal Rmp at the Knee point of the primary side switching voltage VDS1 until the negative edge of the primary side switching signal S1C is reset.

The valley selecting circuit 170 is used for sampling and holding the ramp signal Rmp of the previous switching period to generate the valley memory signal VN, and is used for generating the ramp signals Rmp1 and Rmp2 with offset according to the ramp signal Rmp.

The inhibit signal generating circuit 180 is used for generating an inhibit signal INH according to the ramp signals Rmp1, rmp2 and the valley memory signal VN. The primary side switch S1 is disabled and delays the turn-on time of the disable signal INH during the disable period Tinh, specifically, the disable signal generating circuit 180 estimates the zero voltage switching pulse PZV of the previous switching period according to the valley memory signal VN and the ramp signals Rmp1 and Rmp2 of the previous switching period, thereby estimating the time of the zero voltage switching pulse PZV corresponding to the current switching period and generating the disable signal INH corresponding to the current switching period.

The Knee point detection circuit 150 is configured to generate a Knee point signal Knee indicating a Knee point of the primary side switching voltage VDS1 according to the auxiliary signal DEMAG.

The resonance detection circuit 130 is configured to generate a resonance synchronization signal SYNC for indicating that the primary side switch voltage VDS1 is at a falling edge according to the auxiliary signal DEMAG.

The valley correcting circuit 140 is configured to generate a valley indication signal p_pwm according to the resonance synchronizing signal SYNC.

In this embodiment, as shown in fig. 6, the flyback converter of the present invention specifically operates as follows: at steady state (e.g., switching period [ n ]), the secondary side control circuit 200 enables the zero voltage switching pulse PZV at the third peak of the primary side switching voltage VDS1 (e.g., P3 in switching period [ n ]), and the primary side control circuit enables the primary side switching signal S1C according to the fourth valley of the primary side switching voltage VDS1 (e.g., V4 in switching period [ n ]), wherein the fourth valley V4 of the primary side switching voltage VDS1 is later than the third peak P3 of the primary side switching voltage VDS 1.

When the output power or the output current Io of the output power source is rising compared to the steady state, the primary side control circuit delays, for example, one trough to enable the primary side switching signal S1C in the current switching period (e.g., switching period [ n+1 ]), that is, enables the primary side switching signal S1C according to the fifth trough (V5 in switching period [ n+1 ]) of the primary side switching voltage VDS1 in the present embodiment, so as to avoid the primary side switch S1 and the secondary side switch S2 from being turned on simultaneously, wherein the time point (V5 in switching period [ n+1 ]) of the fifth trough of the primary side switching voltage VDS1 is later than the time point (V4 in switching period [ n+1 ]) corresponding to the fourth trough of the primary side switching voltage VDS1 in the current switching period.

The operation of the above-described sub-circuits is described in more detail below, respectively, to achieve the above-described functions.

Fig. 7 shows a schematic diagram of an embodiment of a resonance detection circuit (resonance detection circuit 130) in the flyback converter according to the present invention. The resonance detection circuit 130 includes an amplifying circuit 131, a transistor 132 and a current-to-voltage conversion circuit 133, wherein the resonance detection circuit 130 is configured to detect whether the auxiliary signal DEMAG is lower than the reference signal VR to generate a resonance synchronization signal SYNC, and in an embodiment, the reference signal VR is 0 or a reference voltage close to 0, such that the resonance synchronization signal SYNC indicates that the auxiliary signal DEMAG is negative, and the resonance synchronization signal SYNC also indicates that the primary side switch voltage VDS1 is lower than the input voltage Vin. In one aspect, the rising edge of the resonant synchronization signal SYNC may be used to indicate that the primary switch voltage VDS1 falls from the peak to the midpoint of the trough, and the falling edge of the resonant synchronization signal SYNC may be used to indicate that the primary switch voltage VDS1 rises from the trough to the midpoint of the peak.

Fig. 8 shows a schematic diagram of a valley-correction circuit (valley-correction circuit 140) in the flyback converter according to an embodiment of the present invention. The valley correcting circuit 140 includes a delay circuit 141 and a logic circuit for generating a valley indication signal p_pwm, wherein a falling edge of the valley indication signal p_pwm is aligned with a falling edge of the resonance synchronizing signal SYNC, and the delay circuit 141 delays a rising edge of the resonance synchronizing signal SYNC to enable the valley indication signal p_pwm, such that the rising edge of the valley indication signal p_pwm is delayed from the rising edge of the resonance synchronizing signal SYNC, wherein a delay time length is adjustable by a capacitor and a current source. In one aspect, the rising edge of the valley indication signal p_pwm can be used to indicate the occurrence of the valley of the primary-side switching voltage VDS1 when the delay time is properly selected.

Fig. 9 shows a schematic diagram of an embodiment of a knee point detection circuit (knee point detection circuit 150) in the flyback converter according to the present invention. The knee point detection circuit 150 includes a comparator 151, a pulse circuit 152, a status circuit 153, and a logic circuit. The status circuit 153 may be a flip-flop, for example. The comparator 151 compares the auxiliary signal DEMAG with the reference signal VK to generate a comparison result KneeCMP, the pulse circuit 152 generates a Knee pulse KP according to the comparison result KneeCMP and the delayed inverted signal KCdb having a single-side delayed inverted relationship with the comparison result KneeCMP to trigger the flip-flop 153 to enable the Knee signal Knee, and the negative edge signal CyL is used to reset the Knee signal Knee, in other words, as shown in fig. 6, the rising edge of the Knee signal Knee indicates the Knee point of the primary side switch voltage VDS 1.

Fig. 10 shows a schematic diagram of a ramp generation circuit (ramp generation circuit 160) in the flyback converter according to the present invention. The ramp generating circuit 160 includes a flip-flop 161 and an integrating circuit 162, wherein the flip-flop 161 generates a ramp enable signal RmpEN according to a rising edge of the Knee point signal Knee, so that the integrating circuit 162 starts to charge a capacitor with a current source to generate a ramp signal Rmp. The flip-flop 161 is controlled by the system reset signal RST or the negative edge signal CyL to reset, in other words, the ramp signal Rmp starts to rise from the rising edge of the Knee signal Knee, and ends at the negative edge signal CyL of the next switching cycle.

Fig. 11 shows a schematic diagram of a valley selecting circuit (valley selecting circuit 170) in a flyback converter according to an embodiment of the present invention. The valley selection circuit 170 includes an amplifier 171, an offset circuit 172, and sample-and-hold circuits 173 and 175. The amplifier 171 generates a buffered ramp signal Rmp0 according to the ramp signal Rmp, and the sample-hold circuit 173 samples the ramp signal Rmp from the rising edge of the ramp enable signal RmpEN, and samples and holds the ramp signal Rmp at the rising edge of the primary-side switching signal S1C to generate the ramp level signal RH1. The sample-hold circuit 175 is configured to sample-hold the ramp level signal RH1 at the falling edge of the primary side switching signal S1C according to the negative edge signal CyL to generate the valley memory signal VN, in other words, the level of the valley memory signal VN is the level of the rising edge point of the primary side switching signal S1C, and is updated at the falling edge of the primary side switching signal S1C.

In addition, the offset circuit 172 offsets the ramp signal Rmp to generate the ramp signals Rmp1 and Rmp2 with offset, wherein the offset of the ramp signals Rmp1 and Rmp2 compared to the ramp signal Rmp is determined by the corresponding current source and resistor.

Fig. 12 shows a schematic diagram of an embodiment of the disable signal generation circuit (disable signal generation circuit 180) in the flyback converter according to the present invention. The disable signal generating circuit 180 includes a comparator 181, a comparator 182, flip-flops 183, 184, 185 and a plurality of logic circuits.

The voltage level of the ramp signal Rmp has a proportional relationship with the time period after the knee point of the primary switch voltage VDS1, so that, from one point of view, the level of the valley memory signal VN indicates the length of the non-conducting period of the primary switch S1 in the previous switching period. Next, the comparator 181 compares the ramp signal Rmp1 with the valley memory signal VN, and the comparator 182 compares the ramp signal Rmp2 with the valley memory signal VN to generate a pre-inhibit signal p_inh corresponding to a pre-inhibit period Tpinh, wherein the pre-inhibit period Tpinh corresponds to a period of the valley memory signal VN between the ramp signal Rmp1 and the ramp signal Rmp2, and then the flip-flop 183 determines whether to enable the inhibit signal INH according to whether the pre-inhibit signal p_inh is enabled or not at a rising edge of the resonance synchronization signal SYNC or at a rising edge of the on control signal TD. In other words, in one embodiment, when the load changes such that the on control signal TD determined by feedback triggers within the pre-inhibit signal p_inh, the inhibit signal generating circuit 180 enables the inhibit signal INH to inhibit the on of the primary switch S1, the details of which will be described later.

In addition, the negative edge signal CyL is used to reset the inhibit signal INH at the negative edge of the primary side switching signal S1C to wait for the enable of the inhibit signal INH in the switching period. On the other hand, after the disable signal INH is enabled, the flip-flops 184 and 185 form a delay circuit for determining the duration of the disable signal INH, i.e., the disable period Tinh, which is determined by the period of the adjacent rising edge of the valley indication signal p_pwm and the number of flip-flops in one embodiment, so that the disable period Tinh is related to the resonant period Trng of the resonant waveform, and thus, in a preferred embodiment, after the disable period Tinh is completed, the primary side switching signal S1C is enabled, for example, at another valley of the DCM resonant waveform delayed by the disable period Tinh, and zero voltage switching is still enabled. Specifically, in the present embodiment, the prohibition period Tinh is 1.5 times or more the resonance period Trng of the aforementioned resonance waveform.

It should be noted that, since the offset of the ramp signals Rmp1 and Rmp2 compared to the ramp signal Rmp determines the start point and the end point of the pre-inhibit period Tpinh, on the other hand, the time point when the primary switch S1 is turned on and the end point of the zero voltage switching pulse PZV are related to the resonant period Trng in the steady state, in an embodiment, the offset of the ramp signals Rmp1 and Rmp2 compared to the ramp signal Rmp is related to the resonant period Trng and the pulse width TZV of the zero voltage switching pulse PZV. In a preferred embodiment, the pre-inhibit period Tpinh encompasses the zero voltage switching pulse PZV of at least the previous switching period.

Fig. 13 shows a schematic diagram of an embodiment of a PWM generation circuit (PWM generation circuit 110) in the flyback converter according to the present invention. The PWM generation circuit 110 includes a timer 111 and a flip-flop 112, wherein the timer 111 generates a turn-on control signal TD according to a feedback signal related to an output power source (e.g., an output current Io and/or an output voltage Vo) to determine a turn-on time and a turn-on period of the primary switch S1 according to the output power source, and specifically, the flip-flop 112 resets according to a feedback related signal FBR to determine a turn-on time of the primary switch S1C to adjust the output voltage Vout and the output current Iout, and synchronizes a start time of the primary switch S1C with a trough of the primary switch voltage VDS1 through a trough indication signal p_pwm to implement the zero-voltage switching. In addition, when the load increases to enable the on control signal TD during the inhibit period Tinh, the logic circuit (e.g., an and gate and a nand gate as shown) masks the on control signal TD during the inhibit period Tinh according to the inhibit signal INH to inhibit the triggering of the primary side switching signal S1C, thereby realizing the aforementioned delay of the on time of the primary side switch S1 and effectively avoiding the aforementioned short-circuit current.

Specifically, as in the switching period [ n+1] in fig. 6, the on control signal TD is enabled for the pre-prohibition period Tpinh, and thus the prohibition signal INH is triggered, and the on control signal TD is masked for the prohibition period Tinh to prohibit the triggering of the primary side switching signal S1C, so that the primary side switching signal S1C of the switching period [ n+2] is delayed until the prohibition period Tinh is ended.

Fig. 14 shows a schematic diagram of a negative edge detection circuit (negative edge detection circuit 120) in the flyback converter according to an embodiment of the present invention. The negative edge detection circuit 120 includes a delay circuit 121 and a plurality of logic circuits for detecting a negative edge of the primary side switching signal S1C to generate a negative edge signal CyL.

In one aspect, the flyback converter of the present invention memorizes the occurrence time of the trough of the previous switching cycle by using the analog trough memorizing manner, and generates the pre-inhibit signal p_inh near the trough of the corresponding sequence of the current switching cycle, and generates the inhibit signal INH when the primary side switch S1 and the secondary side switch S2 may be simultaneously turned on, so as to shield and inhibit the triggering of the primary side switching signal S1C, which can delay the conduction time of the primary side switch S1 when the load increases to enable the conduction control signal TD in the pre-inhibit signal p_inh, thereby effectively avoiding the aforementioned short-circuit current. It should be noted that the delay time Tnov of the on-time of the primary switch S1 is related to the period of the resonant waveform, and in a preferred embodiment, is related to a multiple of 0.5 resonant periods Trng of the resonant waveform, and in a preferred embodiment, is equal to 1.5 resonant periods Trng of the resonant waveform.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims

1. A switching control circuit is used for controlling a flyback converter to convert an input power supply to generate an output power supply, and the flyback converter comprises a power transformer which is coupled between the input voltage and the output voltage in an electric insulation mode; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the switching control circuit includes:

a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and

a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectification pulse and a zero voltage switching pulse, the synchronous rectification pulse is used for controlling the secondary side switch to conduct a synchronous rectification period to realize secondary side synchronous rectification, and the zero voltage switching pulse is used for controlling the secondary side switch to conduct a zero voltage switching period, so that the primary side switch realizes zero voltage switching;

wherein, in steady state, the secondary side control circuit enables the zero voltage switching pulse according to a first waveform characteristic of a discontinuous conduction mode resonance waveform, and the primary side control circuit enables the primary side switching signal according to a second waveform characteristic of the discontinuous conduction mode resonance waveform, wherein the second waveform characteristic of the discontinuous conduction mode resonance waveform is later than the first waveform characteristic of the discontinuous conduction mode resonance waveform;

When the output power or the output current of the output power supply is increased compared with the steady state, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the discontinuous conduction mode resonance waveform in the current switching period so as to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

2. The switching control circuit of claim 1, wherein the discontinuous conduction mode resonance waveform corresponds to a resonance waveform of a drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to a V-th trough of the discontinuous conduction mode resonance waveform, and the third waveform characteristic corresponds to a W-th trough of the discontinuous conduction mode resonance waveform, wherein W is greater than V;

wherein V, W is a positive integer greater than zero.

3. The switching control circuit of claim 1, wherein when the output power or the output current of the output power supply is increased compared to a steady state, the primary side control circuit controls the primary side switching signal in the current switching period to inhibit the primary side switching signal in an inhibit period, so that the primary side switching signal and the zero voltage switching pulse do not overlap in the inhibit period, and the primary side switch and the secondary side switch are prevented from being simultaneously turned on;

The prohibition period is related to the rising edge of the primary side switching signal in the previous switching period and a resonance period of the discontinuous conduction mode resonance waveform.

4. The switching control circuit of claim 1, wherein the resonant period of the discontinuous conduction mode resonant waveform is related to an inductance value of the primary winding and a stray capacitance value of the primary switch.

5. The switching control circuit of claim 3, wherein the primary side control circuit generates a turn-on control signal according to the output power source for triggering the primary side switching signal and determining a turn-on time and a turn-on period of the primary side switch in each switching cycle, wherein the primary side control circuit generates a pre-disable signal indicating a pre-disable period in each switching cycle;

when the conduction control signal turns into enable in the pre-prohibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period so as to shield the conduction control signal in the prohibition period and prohibit triggering of the primary side switching signal;

the pre-inhibit signal is generated according to a rising edge of the primary side switching signal of a previous switching period and the resonance period, wherein the pre-inhibit period covers at least the zero voltage switching pulse of the previous switching period.

6. The switching control circuit of claim 5, wherein the on control signal is enabled to trigger the primary side switching signal when the on control signal transitions to enable outside of the pre-disable period.

7. The switching control circuit of claim 3, wherein the corresponding inhibit period is timed according to a resonance synchronizing signal associated with the resonance waveform after the inhibit signal is enabled, such that the inhibit period maintains at least one of the resonance periods.

8. The switching control circuit of claim 7 wherein the disable signal is enabled to clock the corresponding disable period with the resonant waveform related signal such that after the disable period is completed, the primary side switching signal is enabled to effect zero voltage switching at the third waveform characteristic of the discontinuous conduction mode resonant waveform, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to a previous switching period.

9. The switching control circuit of claim 7, wherein the enable timing of the primary side switching signal is 1.5 resonant periods from the zero voltage switching pulse during the current switching period when the disable signal is enabled.

10. The switching control circuit of claim 5, wherein the primary side control circuit comprises:

a ramp generating circuit for generating a basic ramp signal at the knee point of the primary side switching signal in each switching period;

the trough selection circuit is used for sampling and maintaining the basic slope signal at the rising edge of the primary side switching signal to generate a trough memory signal, and is used for generating a first slope signal and a second slope signal, wherein the first slope signal and the second slope signal respectively have a first offset level and a second offset level corresponding to the basic slope signal; and

and a disable signal generating circuit for comparing the first ramp signal with the base ramp signal and comparing the second ramp signal with the base ramp signal to generate the pre-disable signal, wherein the pre-disable period corresponds to a period of time during which the base ramp signal is between the first ramp signal and the second ramp signal, and for determining whether a rising edge of the on control signal occurs within the pre-disable period to generate the disable signal.

11. The switching control circuit of claim 10, wherein the first and second bias levels are related to the resonant period.

12. The switching control circuit of claim 10, wherein the primary side control circuit further comprises:

a resonance detection circuit for generating a resonance synchronizing signal related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer;

the prohibiting signal generating circuit also clocks the prohibiting period according to the resonance synchronizing signal so that the prohibiting period maintains at least one resonance period.

13. A flyback converter for converting an input power to produce an output power, the flyback converter comprising:

a power transformer electrically coupled between the input voltage and the output voltage;

a primary side switch for switching a primary side winding of the power transformer;

a secondary side switch for switching a secondary side winding of the power transformer;

14. The flyback converter of claim 13 wherein the discontinuous conduction mode resonant waveform corresponds to a resonant waveform of the drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to a V-th trough of the discontinuous conduction mode resonant waveform, the third waveform characteristic corresponds to a W-th trough of the discontinuous conduction mode resonant waveform, wherein W is greater than V;

Wherein V, W is a positive integer greater than zero.

15. The flyback converter of claim 13 wherein when the output power or output current of the output power supply is rising compared to steady state, the primary side control circuit controls the primary side switching signal during the current switching cycle to disable the primary side switching signal for a disable period such that the primary side switching signal and the zero voltage switching pulse do not overlap during the disable period to avoid the primary side switch and the secondary side switch being turned on simultaneously;

16. The flyback converter of claim 13 wherein the resonant period of the discontinuous conduction mode resonant waveform is related to the inductance of the primary winding and the stray capacitance of the primary switch.

17. The flyback converter of claim 15 wherein the primary side control circuit generates a turn-on control signal according to the output power to trigger the primary side switching signal and determine a turn-on time and a turn-on period of the primary side switch during each switching cycle, wherein the primary side control circuit generates a pre-disable signal indicating a pre-disable period during each switching cycle;

18. The flyback converter of claim 17 wherein the on control signal is allowed to trigger the primary-side switching signal when the on control signal transitions to enable outside of the pre-disable period.

19. The flyback converter of claim 15 wherein when the disable signal is enabled, the corresponding disable period is timed according to a resonant synchronization signal associated with the resonant waveform such that the disable period maintains at least one of the resonant periods.

20. The flyback converter of claim 19 wherein when the disable signal is enabled, clocking the corresponding disable period with the resonant waveform-related signal causes the primary-side switching signal to be enabled at the third waveform characteristic of the discontinuous conduction mode resonant waveform after the disable period has ended, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching cycle to effect zero voltage switching.

21. A control method for controlling a flyback converter to convert an input power to generate an output power includes a power transformer electrically coupled between the input voltage and the output voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the control method comprises the following steps:

generating a primary side switching signal to control the primary side switch in a switching period; and

generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectification pulse and a zero voltage switching pulse, the synchronous rectification pulse is used for controlling the secondary side switch to conduct a synchronous rectification period to realize secondary side synchronous rectification, and the zero voltage switching pulse is used for controlling the secondary side switch to conduct a zero voltage switching period, so that the primary side switch realizes zero voltage switching;

wherein, in a steady state, the step of generating a zero voltage switching pulse comprises:

the zero voltage switching pulse is enabled according to a first waveform characteristic of a discontinuous conduction mode resonance waveform,

Wherein, in a steady state, the step of generating the primary side switching signal comprises:

enabling the primary-side switching signal according to a second waveform characteristic of the discontinuous conduction mode resonance waveform, wherein the second waveform characteristic of the discontinuous conduction mode resonance waveform is later than the first waveform characteristic of the discontinuous conduction mode resonance waveform; and

when the output power or the output current of the output power supply is increased compared with the steady state, the primary side switching signal is enabled according to a third waveform characteristic of the discontinuous conduction mode resonance waveform in the current switching period so as to avoid the simultaneous conduction of the primary side switch and the secondary side switch, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

22. The control method of claim 21, wherein the discontinuous conduction mode resonance waveform corresponds to a resonance waveform of a drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to a V-th trough of the discontinuous conduction mode resonance waveform, and the third waveform characteristic corresponds to a W-th trough of the discontinuous conduction mode resonance waveform, wherein W is greater than V;

Wherein V, W is a positive integer greater than zero.

23. The control method of claim 21, wherein when the output power or the output current of the output power is increased compared to a steady state, the primary side switching signal is disabled for a disable period in the current switching cycle, such that the primary side switching signal and the zero voltage switching pulse do not overlap in the disable period, so as to avoid the primary side switch and the secondary side switch being turned on simultaneously;

24. The control method of claim 21, wherein the resonance period of the discontinuous conduction mode resonance waveform is related to an inductance value of the primary winding and a stray capacitance value of the primary switch.

25. The control method of claim 23, wherein generating the primary-side switching signal further comprises:

generating a conduction control signal according to the output power supply, wherein the conduction control signal is used for triggering the primary side switching signal and determining the conduction time point and the conduction period of the primary side switch in each switching period;

Generating a pre-inhibit signal indicating a pre-inhibit period in each switching cycle; and

when the conduction control signal turns into enable in the pre-prohibition period, a prohibition signal indicating the prohibition period is generated so as to shield the conduction control signal in the prohibition period and prohibit triggering of the primary side switching signal;

26. The control method of claim 25, wherein generating the primary-side switching signal further comprises: when the conduction control signal is turned to be enabled outside the pre-prohibition period, the conduction control signal is allowed to trigger the primary side switching signal.

27. The control method of claim 23, wherein generating the primary-side switching signal further comprises: when the inhibit signal is enabled, the corresponding inhibit period is timed according to a resonance synchronizing signal related to the resonance waveform, so that the inhibit period maintains at least one resonance period.

28. The control method of claim 27, wherein generating the primary-side switching signal further comprises: when the disable signal is enabled, the corresponding disable period is clocked with the resonant waveform-related signal such that after the disable period is over, the primary side switching signal is enabled at the third waveform characteristic of the discontinuous conduction mode resonant waveform, where the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period, to achieve zero voltage switching.

29. The control method of claim 25, wherein the step of generating the disable signal comprises:

in each switching period, the knee point of the primary side switching signal starts to generate a basic slope signal;

sampling and holding the basic ramp signal at the rising edge of the primary side switching signal to generate a trough memory signal;

generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the base ramp signal;

comparing the first ramp signal with the basic ramp signal, and comparing the second ramp signal with the basic ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to a period of time that the basic ramp signal is between the first ramp signal and the second ramp signal; and

Determining whether the rising edge of the on control signal occurs in the pre-inhibit period to generate the inhibit signal.

30. The control method of claim 29, wherein the first and second bias levels are related to the resonant period.