CN113890365A

CN113890365A - Flyback converter and switching control circuit and control method thereof

Info

Publication number: CN113890365A
Application number: CN202110176038.4A
Authority: CN
Inventors: 陈裕昌; 张炜旭; 林昆馀; 杨大勇
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2020-07-03
Filing date: 2021-02-09
Publication date: 2022-01-04
Anticipated expiration: 2041-02-09
Also published as: TWI783365B; CN113890365B; TW202203564A

Abstract

A flyback converter and a switching control circuit and a control method thereof. The flyback converter includes: the power transformer, the primary side switch, the secondary side switch and the switching control circuit. The secondary side switching signal has a synchronous rectification pulse and a zero voltage switching pulse to realize the secondary side synchronous rectification and the primary side switch zero voltage switching. The zero-voltage switching pulse is enabled according to a first waveform characteristic of the resonant waveform, and the primary-side switching signal is enabled according to a second waveform characteristic of the resonant waveform. When the output current rises, the primary side switching signal is forbidden in a forbidden time interval, so that the primary side switching signal and the zero voltage switching pulse are not overlapped in the forbidden time interval, and the primary side switch and the secondary side switch are prevented from being simultaneously conducted. The inhibit period is related to a rising edge of the primary-side switching signal and a resonant period of the resonant waveform in a previous switching cycle.

Description

Flyback converter and switching control circuit and control method thereof

Technical Field

The present invention relates to a flyback converter, and more particularly, to a flyback converter having zero-voltage switching function and capable of avoiding short-circuit current between a primary side and a secondary side. The invention also relates to a control circuit and a control method for the flyback power supply.

Background

Fig. 1A and 1B show prior art flyback converters (

flyback converters

1001A and 1001B). The primary control circuit 80 is configured to generate a primary switching signal S1C to control the primary switch S1 to switch the power transformer 10 to generate an output voltage Vo, and the secondary control circuit 200 is configured to generate a secondary switching signal S2C to control the secondary switch S2 to perform synchronous rectification and Zero Voltage Switching (ZVS) on the secondary side. Secondary side switch S2 in

flyback converters

1001A and 1001B is located below and above the secondary side winding, respectively.

Fig. 2 is a waveform diagram illustrating the operation of the flyback converter corresponding to the prior art in fig. 1A and 1B. In this embodiment, the flyback converter of the present invention operates in a Discontinuous Conduction Mode (DCM-Discontinuous Conduction Mode). The secondary-side switching signal S2C of the

flyback converter

1001A or 1001B has a synchronous rectification pulse PSR and a Zero Voltage Switching (ZVS) pulse PZV, and when the primary-side switch S1 is turned on and then turned off again, the synchronous rectification pulse PSR is used to control the synchronous rectification switch S2 to be turned on in the demagnetization stage of the power transformer 10 to implement the secondary-side synchronous rectification, while the zero voltage switching pulse PZV is used to implement the zero voltage switching of the primary-side switch S1.

In this conventional technique, a "peak/valley locking" technique is adopted, and a waveform characteristic at the time of resonance of a resonance waveform (for example, a resonance waveform of the primary-side switching voltage VDS1 in DCM) is adaptively selected according to a level of an output current, and a peak of a certain order of the resonance waveform of the primary-side switching voltage VDS1 in DCM (for example, a third peak P3 of VDS 1) starts the zero-voltage switching pulse PZV. In addition, the primary-side control circuit 80 and the secondary-side control circuit 90 synchronize the turn-on timing of the primary-side switch S1 according to another characteristic of the resonant waveform, such as the valley of the adjacent sequence (e.g., the fourth valley V4 of VDS 1). Therefore, the prior art can make both the primary switch S1 and the secondary switch S2 achieve zero-voltage switching to improve the power conversion efficiency, and make the switching times of the primary switch S1 and the secondary switch S2 synchronous and non-overlapping without additional isolated communication paths (such as pulse transformers), thereby avoiding short-circuit current caused by simultaneous conduction.

However, under some load variations, the primary switch S1 and the secondary switch S2 are still turned on simultaneously to cause short-circuit current, as shown in fig. 3, which is a disadvantage of the prior art. Fig. 3 is a waveform diagram illustrating the operation of the flyback converter corresponding to the prior art in fig. 1A and 1B. The load current Io in the switching period [ n ] is increased in the switching period [ n +1], and the load current increases, so that the primary side S1 switch signal S1C is turned on earlier, and at this time, if the signal PVZ of the secondary side S2C maintains the on-time of the previous switching period, the primary side switch and the secondary side switch are turned on simultaneously, which causes a short circuit and burns out the converter.

Compared with the prior art, the present invention can achieve zero voltage switching for both the primary switch S1 and the secondary switch S2, synchronize the switching time of the primary switch S1 and the secondary switch S2, and effectively avoid short-circuit current caused by simultaneous conduction of the primary switch S1 and the secondary switch S2 under various load variations.

Disclosure of Invention

In one aspect, the present invention provides a switching control circuit for controlling a flyback converter to convert an input power to generate an output power, the flyback converter including a power transformer electrically isolated from the input voltage; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the switching control circuit includes: a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a Synchronous Rectification (SR) pulse for controlling the secondary side switch to conduct a Synchronous rectification period to implement secondary side Synchronous rectification and a Zero Voltage Switching (ZVS) pulse for controlling the secondary side switch to conduct a zero voltage switching period, thereby enabling the primary side switch to implement zero voltage switching; wherein the secondary-side control circuit enables the zero-voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary-side control circuit enables the primary-side switching signal according to a second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; when the output power or the output current of the output power supply rises compared with a steady state, in the current switching period, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the DCM resonant waveform to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

In a preferred embodiment, the DCM resonance waveform corresponds to a resonance waveform of a drain-source voltage of the primary side switch, wherein the second waveform characteristic corresponds to a vth valley of the DCM resonance waveform, and the third waveform characteristic corresponds to a vth valley of the DCM resonance waveform, wherein W is greater than V.

In a preferred embodiment, when the output power or the output current of the output power supply is increased compared to a steady state, in the current switching period, the primary side control circuit controls the primary side switching signal to disable the primary side switching signal within a disable period, so that the primary side switching signal and the zero voltage switching pulse are not overlapped in the disable period to prevent the primary side switch and the secondary side switch from being turned on simultaneously; wherein the forbidden period is related to a rising edge of the primary-side switching signal in a previous switching cycle and a resonant cycle of the DCM resonant waveform.

In a preferred embodiment, the resonant period of the DCM resonant waveform is related to the inductance of the primary winding and the stray capacitance of the primary switch.

In a preferred embodiment, the primary side control circuit generates a conduction control signal according to the output power for triggering the primary side switching signal and determining a conduction time and a conduction time period of the primary side in each switching period, wherein the primary side control circuit generates a pre-inhibit signal indicating a pre-inhibit time period in each switching period; when the conduction control signal is turned into enable in the pre-prohibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period so as to shield the conduction control signal in the prohibition period and prohibit the triggering of the primary side switching signal; wherein the pre-inhibit signal is generated according to a rising edge of the primary-side switching signal of a previous one of the switching cycles and the resonant cycle, wherein the pre-inhibit period covers at least the zero-voltage switching pulse of the previous one of the switching cycles.

In a preferred embodiment, when the conduction control signal is enabled outside the pre-disable period, the conduction control signal is allowed to trigger the primary-side switching signal.

In a preferred embodiment, after the disable signal is enabled, the corresponding disable period is clocked according to a resonant synchronization signal associated with the resonant waveform such that the disable period is maintained for at least one of the resonant cycles.

In a preferred embodiment, after the disable signal is enabled, the corresponding disable period is clocked by the resonant waveform-related signal such that after the disable period ends, the primary-side switching signal is enabled at a third waveform characteristic of the DCM resonant waveform, thereby implementing zero-voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to a previous switching cycle.

In a preferred embodiment, when the disable signal is enabled, the enabling time of the primary-side switching signal is 1.5 resonant periods away from the zero-voltage switching pulse in the current switching period.

In a preferred embodiment, the primary-side control circuit includes: a ramp generating circuit for generating a basic ramp signal at a knee point of the primary-side switching signal in each switching cycle; a valley selection circuit for sampling and holding the basic ramp signal at a rising edge of the primary side switching signal to generate a valley memory signal, and for generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal have a first offset level and a second offset level corresponding to the basic ramp signal, respectively; and an inhibit signal generating circuit for comparing the first ramp signal with the base ramp signal and comparing the second ramp signal with the base ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to a period in which the base ramp signal is between the first ramp signal and the second ramp signal, and for determining whether a rising edge of the conduction control signal occurs within the pre-inhibit period to generate the inhibit signal.

In a preferred embodiment, the first offset level and the second offset level are related to the resonant period.

In a preferred embodiment, the primary-side control circuit further includes: a resonance detection circuit for generating a resonance synchronization signal related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer; wherein the inhibit signal generating circuit is further configured to clock the inhibit period based on the resonant synchronization signal such that the inhibit period is maintained for at least one of the resonant cycles.

From another perspective, the present invention also provides a flyback converter for converting an input power to generate an output power, the flyback converter comprising: a power transformer coupled between the input voltage and the output voltage in an electrically insulated manner; a primary side switch for switching a primary side winding of the power transformer; a secondary side switch for switching a secondary side winding of the power transformer; a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a Synchronous Rectification (SR) pulse for controlling the secondary side switch to conduct a Synchronous rectification period to implement secondary side Synchronous rectification and a Zero Voltage Switching (ZVS) pulse for controlling the secondary side switch to conduct a zero voltage switching period, thereby enabling the primary side switch to implement zero voltage switching; wherein the secondary-side control circuit enables the zero-voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein the primary-side control circuit enables the primary-side switching signal according to a second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; when the output power or the output current of the output power supply rises compared with a steady state, in the current switching period, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the DCM resonant waveform to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

From another aspect, the present invention also provides a control method for controlling a flyback converter to convert an input power to generate an output power, the flyback converter including a power transformer coupled between the input voltage and the output voltage in an electrically insulated manner; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the method comprises the following steps: generating a primary side switching signal to control the primary side switch in a switching period; generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a Synchronous Rectification (SR) pulse and a Zero Voltage Switching (ZVS) pulse, the Synchronous rectification pulse is used to control the secondary side switch to conduct a Synchronous rectification period to implement secondary side Synchronous rectification, and the zero voltage switching pulse is used to control the secondary side switch to conduct a zero voltage switching period, so as to enable the primary side switch to implement zero voltage switching; wherein, in a steady state, the step of generating the zero-voltage switching pulse comprises: enabling the zero-voltage switching pulse according to a first waveform characteristic of a DCM (discontinuous conduction mode) resonant waveform, wherein in a steady state, the step of generating the primary-side switching signal comprises: enabling the primary-side switching signal according to a second waveform characteristic of the DCM resonant waveform, wherein the second waveform characteristic of the DCM resonant waveform is later than the first waveform characteristic of the DCM resonant waveform; and enabling the primary side switching signal according to a third waveform characteristic of the DCM resonant waveform in the current switching period when the output power or the output current of the output power supply is increased compared to a steady state, so as to prevent the primary side switch and the secondary side switch from being turned on simultaneously, wherein a time point of the third waveform characteristic is later than a time point corresponding to the second waveform characteristic in the current switching period.

In a preferred embodiment, when the output power or the output current of the output power supply rises compared to a steady state, the primary-side switching signal is disabled in a disable period in the current switching cycle, so that the primary-side switching signal and the zero-voltage switching pulse are not overlapped in the disable period, thereby preventing the primary-side switch and the secondary-side switch from being turned on simultaneously; wherein the forbidden period is related to a rising edge of the primary-side switching signal in a previous switching cycle and a resonant cycle of the DCM resonant waveform.

In a preferred embodiment, the step of generating the primary-side switching signal further includes: generating a conduction control signal according to the output power supply, for triggering the primary side switching signal and determining the conduction time and the conduction time period of the primary side in each switching period; generating a pre-inhibit signal indicating a pre-inhibit period in each switching cycle; and generating a disable signal indicative of the disable period when the conduction control signal is asserted during the pre-disable period, to mask the conduction control signal during the disable period and disable triggering of the primary-side switching signal; wherein the pre-inhibit signal is generated according to a rising edge of the primary-side switching signal of a previous one of the switching cycles and the resonant cycle, wherein the pre-inhibit period covers at least the zero-voltage switching pulse of the previous one of the switching cycles.

In a preferred embodiment, the step of generating the primary-side switching signal further includes: when the conduction control signal is turned to be enabled outside the pre-forbidding period, the conduction control signal is allowed to trigger the primary side switching signal.

In a preferred embodiment, the step of generating the primary-side switching signal further includes: when the inhibit signal is enabled, the corresponding inhibit period is timed according to a resonance synchronous signal related to the resonance waveform, so that the inhibit period at least maintains one resonance period.

In a preferred embodiment, the step of generating the primary-side switching signal further includes: and when the inhibit signal is enabled, timing the corresponding inhibit period by the resonance waveform related signal, so that after the inhibit period is ended, the primary side switching signal is enabled at a third waveform characteristic of the DCM resonance waveform to realize zero-voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic corresponding to the previous switching period.

In a preferred embodiment, the step of generating the disable signal comprises: in each switching period, a knee point of the primary side switching signal starts to generate a basic ramp signal; sampling and holding the basic ramp signal at the rising edge of the primary side switching signal to generate a valley memory signal; generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the basic ramp signal; comparing the first ramp signal with the base ramp signal, and comparing the second ramp signal with the base ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to a period in which the base ramp signal is between the first ramp signal and the second ramp signal; and judging whether the rising edge of the conduction control signal occurs in the pre-inhibition time period to generate the inhibition signal.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1A and 1B show schematic diagrams of a flyback converter in the prior art.

Fig. 2 is a waveform diagram illustrating the operation of the flyback converter corresponding to the prior art in fig. 1A and 1B.

Fig. 3 is a waveform diagram illustrating the operation of the flyback converter corresponding to the prior art in fig. 1A and 1B.

Fig. 4 shows a schematic diagram of a preferred embodiment of a flyback converter according to the present invention.

Fig. 5 shows a waveform diagram of an embodiment of a flyback converter according to the present invention.

Fig. 6 shows a waveform diagram of an embodiment of a flyback converter according to the present invention.

Fig. 7 is a schematic diagram of an embodiment of a resonant detection circuit in the flyback converter of the present invention.

Fig. 8 is a schematic diagram of an embodiment of a valley correction circuit in the flyback converter of the present invention.

FIG. 9 is a schematic diagram of a knee point detection circuit in a flyback converter according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of an embodiment of a ramp generation circuit in the flyback converter of the present invention.

Fig. 11 is a schematic diagram of an embodiment of a valley selection circuit in the flyback converter of the present invention.

Fig. 12 is a schematic diagram of an exemplary embodiment of an inhibit signal generation circuit in a flyback converter according to the present invention.

Fig. 13 is a schematic diagram of an embodiment of a PWM generating circuit in the flyback converter of the present invention.

Fig. 14 is a schematic diagram of an embodiment of a negative edge detection circuit in the flyback converter of the present invention.

Description of the symbols in the drawings

10: power transformer

1001A, 1001B, 1004: flyback converter

110: PWM generating circuit

111: timer

112: flip-flop

120: negative edge detection circuit

121: delay circuit

130: resonance detection circuit

131: amplifying circuit

132: transistor with a metal gate electrode

133: current-voltage conversion circuit

140: wave trough correction circuit

141: delay circuit

150: knee point detection circuit

151: comparator with a comparator circuit

152: pulse circuit

153: status circuit

160: ramp generating circuit

161: flip-flop

162: integrating circuit

170: trough selection circuit

171: amplifier with a high-frequency amplifier

172: offset circuit

173, 175: sample-and-hold circuit

180: inhibit signal generating circuit

181, 182: comparator with a comparator circuit

183, 184, 185: flip-flop

80, 100: primary side control circuit

90, 200: secondary side control circuit

Cp: parasitic capacitance

CyL: negative edge signal

FBR: feedback correlation signal

INH: inhibit signal

Io: output current

Ip: primary side current

Isr: secondary side current

KCdb: delaying an inverted signal

Knee: knee point signal

kneeCMP: comparison results

KP: pulse at knee point

P1-P4: wave crest

P _ INH: pre-inhibit signal

P _ PWM: trough indicating signal

PSR: synchronous rectified pulse

PZV: zero voltage switching pulse

RH 1: ramp level signal

Rmp, Rmp0, Rmp1, Rmp 2: ramp signal

RmpEn: ramp enable signal

RST: system reset signal

S1: primary side switch

S1C: primary side switching signal

S2C: secondary side switching signal

S2: secondary side switch

SYNC: resonant synchronization signal

t2-t 15: time point

TD: conduction control signal

Tinh: forbidden period of time

Tpinh: pre-inhibit period

And (5) Trng: period of resonance

TSR: synchronous commutation period

TZV: pulse width

V1-V4: trough of wave

Vaux, DEMAG: auxiliary voltage

VDS 1: primary side switching voltage

VDS 2: secondary side switching voltage

Vin: input voltage

VK, VR: reference signal

VN: valley memory signal

Vo: output voltage

W1: primary side winding

W2: secondary side winding

W3: auxiliary winding

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Fig. 4 shows a schematic diagram of a preferred embodiment of a flyback converter according to the present invention (flyback converter 1004). The flyback converter 1004 is used for converting the input voltage Vin to generate an output voltage Vo and an output current Io, so as to provide power to a load circuit (not shown, well known to those skilled in the art and not described herein). The flyback converter 1004 includes a power transformer 10, a primary-side control circuit 100, and a secondary-side control circuit 200.

The power transformer 10 is electrically insulated and coupled between the input voltage Vin and the output voltage Vo, and the primary-side switch S1 is coupled to the primary-side winding W1 of the power transformer 10, wherein the primary-side winding W1 is coupled to the input voltage Vin. The secondary side switch S2 and the secondary side winding W2 of the power transformer 10 are connected in series between the output voltage Vo and the secondary side ground node. In the present embodiment, the secondary side switch S2 is coupled between the secondary side winding W2 of the power transformer 10 and the secondary side ground node. The secondary-side switch S2 may also be coupled between the secondary winding W2 of the power transformer 10 and the output voltage Vo, as illustrated in the secondary-side circuit of fig. 1B. For simplicity of illustration, the following description will be made with respect to an embodiment in which the secondary-side switch S2 is coupled between the secondary-side winding W2 of the power transformer 10 and the secondary-side ground node as shown in fig. 4, but the same spirit is also applicable to another form as shown in the secondary-side of fig. 1B.

The primary-side control circuit 100 is configured to generate a primary-side switching signal S1C, and the primary-side switching signal S1C is configured to control the primary-side switch S1 to switch a primary-side winding W1 of the power transformer 10, wherein the primary-side winding W1 is coupled to the input voltage Vin. The secondary-side control circuit 200 is configured to generate a secondary-side switching signal S2C to control the on and off of the secondary-side switch S2, so as to switch the secondary winding W2 of the power transformer 10 to generate the output voltage Vo. Wherein VDS1 is the voltage of the drain of the primary-side switch S1, and VDS2 is the voltage of the first terminal of the secondary-side switch S2. In this embodiment, the first terminal of the secondary-side switch S2 is a drain (current flowing terminal), and the second terminal of the secondary-side switch S2 is a source (current flowing terminal). It should be noted that in the embodiment where the secondary-side switch S2 is coupled between the secondary-side winding W2 of the power transformer 10 and the output voltage Vo, as shown in the secondary-side circuit of fig. 1B, the first terminal of the secondary-side switch S2 is a source (current inflow terminal), and the second terminal of the secondary-side switch S2 is a drain (current outflow terminal).

Referring to fig. 5, fig. 5 is a waveform diagram of a flyback converter according to an embodiment of the invention. In this embodiment, the flyback converter of the present invention operates in a Discontinuous Conduction Mode (DCM-Discontinuous Conduction Mode). According to the present invention, the secondary-side switching signal S2C has a synchronous rectification pulse PSR and a Zero Voltage Switching (ZVS) pulse PZV, and when the primary switch S1 is turned on and then turned off again (as shown in t3 of fig. 5), the synchronous rectification pulse PSR is used to control the secondary switch S2 to turn on a synchronous rectification period TSR to achieve secondary-side synchronous rectification, wherein the synchronous rectification period TSR is substantially synchronous with the conduction period of the induced current of the secondary winding W2, in other words, the synchronous rectification period TSR starts at a time point (t3) when the secondary winding W2 transfers energy from the primary winding W1 to generate the secondary current Isr, and the synchronous rectification period TSR ends at a time point (t4) when the secondary current Isr of the secondary winding W2 drops to 0, so as to improve the power conversion efficiency.

Referring to fig. 5, on the other hand, the zero-voltage switching pulse PZV is used to realize the zero-voltage switching of the primary-side switch S1. In detail, in the present embodiment, when the flyback converter 1004 operates in the discontinuous conduction mode, the power transformer 10 senses magnetism (fig. 5) when the primary switch S1 is turned on, and transfers energy obtained during the sensing magnetism to the output voltage Vo when the primary switch S1 is turned off; when the synchronous rectification pulse PSR controls the secondary switch S2 to be turned on to demagnetize the power transformer 10 (demagnetized, t4, fig. 5), the secondary switch S2 is first controlled to be turned off (t4-t5, fig. 5), and the power transformer 10 starts generating a DCM resonance waveform, which may correspond to, for example, the primary voltage VDS1, the secondary voltage VDS2, or the auxiliary voltage Vaux or DEMAG generated by the auxiliary winding W3, and the resonance period Trng of the DCM resonance waveform is related to the inductance and the stray capacitance of the power transformer 10, especially the inductance and the stray capacitance of the primary winding W1.

When the secondary switch S2 is turned on again according to the zero-voltage switching pulse PZV (e.g., t5 in fig. 5), the power transformer 10 induces a negative secondary-side current Isr in the secondary winding W2, and when the secondary switch S2 is turned off again after the zero-voltage switching pulse PZV (e.g., t6), the power transformer 10 induces a negative primary-side current Ip in the primary winding W1, during which period (e.g., t6-t7), the negative primary-side current Ip may discharge the parasitic capacitance Cp of the primary switch S1, so that the drain voltage VDS1 of the primary switch S1 drops to a lower voltage and charges the charge back to the input power source through the primary winding W1, and when the primary switch S1 is then turned on, the primary switch S1 may realize flexible switching. In a preferred embodiment, the negative primary-side current Ip discharges the parasitic capacitance Cp of the primary-side switch S1 to substantially 0V, which enables Zero-Voltage Switching (ZVS-Zero Voltage Switching) of the primary-side switch S1.

It should be noted that the aforementioned "zero voltage switching" means that, before the transistor (e.g., corresponding to the primary-side switch S1) is turned on, the residual voltage of the parasitic capacitance of the transistor is discharged to a lower voltage through the discharge path (e.g., corresponding to the primary-side winding W1) by the discharge current, and charges the charge back to the device (e.g., the input power supply) without energy loss, so that the drain-source voltage of the transistor is reduced to a lower voltage when the transistor is turned on.

Further, it should be noted that: since the parasitic effect of the circuit components or the matching between the components is not necessarily perfect, although the parasitic capacitance Cp is discharged to 0V, it may not be discharged to 0V exactly, but only close to 0V, that is, according to the present invention, it is acceptable that there is a certain degree of error between the voltage of the discharged parasitic capacitance Cp and 0V due to the non-ideal circuit, that is, the aforementioned discharge to "substantially" is 0V, and the other points mentioned in the present document are also "substantially".

In one embodiment, the start time of the zero-voltage switching pulse PZV is synchronized with the first waveform characteristic of the resonant waveform after the power transformer 10 is demagnetized, and for example, in the embodiment shown in fig. 5, the secondary-side control circuit 200 adaptively selects the secondary-side switching voltage VDS2 according to the level of the output current Io, starts the zero-voltage switching pulse PZV at the trough of a certain sequence of the resonant waveform after the power transformer 10 is demagnetized, so that the secondary-side switch S2 also achieves zero-voltage switching. For example, in fig. 5, the zero-voltage switching pulse PZV corresponding to the third valley of the VDS2 and the third peak P3 of the VDS1 is started at time t5, and is marked as P3 according to the characteristics of the primary-side switching voltage VDS1 for matching. In addition, the primary-side control circuit 100 adaptively selects another characteristic of the resonant waveform according to the level of the output current Io, such as a trough of an adjacent sequential bit (e.g., the fourth trough V4 of VDS1 at time t7 of fig. 5) as the turn-on start time of the primary-side switch S1. Therefore, the primary switch S1 and the secondary switch S2 can both achieve zero voltage switching to improve power conversion efficiency, and the switching times of the primary switch S1 and the secondary switch S2 are synchronized and do not overlap without requiring an additional isolated communication path (e.g., a pulse transformer). In a preferred embodiment, in a steady state (e.g., switching period [ n ] in fig. 5), the non-overlap time between the switches of the primary-side switch S1 and the secondary-side switch S2 is 0.5 resonant periods Trng.

Referring to fig. 5, in order to avoid the aforementioned short-circuit current, in an embodiment, for example, when the output current Io or the output power is increased due to a load change, the turn-on time of the primary-side switch S1 is delayed by at least one resonant period Trng of the resonant waveform, specifically, as shown in fig. 5, when the output current Io is increased at a time t8, in a switching period [ n +1], when the flyback converter 1004 attempts to turn on the primary-side switch S1 earlier than the previous switching period according to feedback, the flyback converter is shielded and delayed by the shown prohibition period Tinh (t 9-t 11), so that the primary-side switch S1 is turned on to the valley of the fifth V5(t11) of the primary-side switch voltage VDS1 in the switching period [ n +1 ]. In other words, the prohibition period Tinh ensures that the primary-side switching signal S1C and the zero-voltage switching pulse PZV do not overlap, and the primary-side switch S1 and the secondary-side switch S2 are effectively prevented from being turned on simultaneously.

Referring to fig. 5, in an embodiment, when the flyback converter 1004 is to be turned on earlier than the previous switching cycle according to the feedback and the time point of the early turn-on is earlier than the start time point of the zero-voltage switching pulse PZV, the turn-on time point of the primary-side switch S1 is determined according to the feedback, i.e., does not need to be delayed as described above. Specifically, as shown in fig. 5, in the switching period [ n +2], when the flyback converter 1004 is fed back to advance the turn-on time to the third valley V3(t12) of the primary-side switching voltage VDS1, since the third valley V3 of the primary-side switching voltage VDS1 is earlier than the start time of the zero-voltage switching pulse PZV (e.g., P3 of t 13) in the switching period [ n +2], the primary-side switch S1 is turned on directly at the third valley V3(t12) of the primary-side switching voltage VDS 1. In addition, when the turn-on time of the primary-side switch S1 is earlier than the zero-voltage switching pulse PZV, the zero-voltage switching pulse PZV is not generated in the switching period [ n +2 ].

According to the present invention, in one embodiment, the forbidden period Tinh of any current switching cycle (e.g., switching cycle [ n +1]) is generated with respect to the position of the zero-voltage switching pulse PZV of the previous switching cycle (e.g., switching cycle [ n ]), specifically, according to the rising edge of the primary-side switching signal S1C and the resonant period Trng of the DCM resonant waveform in the previous switching cycle, which will be described in detail later.

With continued reference to fig. 5, after a new steady state is achieved according to the increased output current Io, as shown by the switching period [ n +3], the primary-side switch S1 is turned on at the third valley V3(t15) of the primary-side switching voltage VDS1, and the zero-voltage switching pulse PZV is also adaptively advanced to the beginning of the second peak V2(t14, corresponding to the second valley of the VDS 2) of the primary-side switching voltage VDS 1.

Referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of a primary-side control circuit of the flyback converter of the present invention (the primary-side control circuit 100). In this embodiment, the primary-side control circuit 100 includes a PWM (pulse width modulation) generating circuit 110, a negative edge detecting circuit 120, a resonance detecting circuit 130, a trough correcting circuit 140, a knee point detecting circuit 150, a ramp generating circuit 160, a trough selecting circuit 170, and an inhibit signal generating circuit 180.

Referring to fig. 6, fig. 6 is a waveform diagram of a flyback converter according to an embodiment of the invention.

In one embodiment, the PWM generating circuit 110 generates the on control signal TD according to feedback (such as, but not limited to, the output voltage Vo and/or the output current Io) to trigger and determine the on time and the on period of the primary-side switch S1, and the PWM generating circuit 110 also generates the primary-side switching signal S1C according to the valley indication signal P _ PWM and the disable signal INH to control the primary-side switch S1.

The negative edge detection circuit 120 is configured to detect a negative edge (i.e., a falling edge) of the primary-side switching signal S1C to generate a negative edge signal CyL indicating a timing of occurrence of the negative edge of the primary-side switching signal S1C.

The ramp generating circuit 160 generates the ramp signal Rmp according to the Knee point signal Knee and the negative edge signal CyL, and specifically, the ramp generating circuit 160 starts generating the ramp signal Rmp at the Knee point of the primary-side switching voltage VDS1 until the negative edge of the primary-side switching signal S1C is reset.

The valley selection circuit 170 is used for sampling and holding the ramp signal Rmp of the previous switching period to generate the valley memory signal VN, and is used for generating the ramp signals Rmp1 and Rmp2 with offsets according to the ramp signal Rmp.

The disable signal generating circuit 180 is used for generating the disable signal INH according to the ramp signals Rmp1, Rmp2 and the valley memory signal VN. Specifically, the disable signal generating circuit 180 estimates the zero-voltage switching pulse PZV of the previous switching cycle according to the valley memory signal VN and the ramp signals Rmp1 and Rmp2 of the previous switching cycle, thereby estimating the time of the zero-voltage switching pulse PZV corresponding to the current switching cycle and generating the disable signal INH corresponding to the current switching cycle.

The Knee point detection circuit 150 is configured to generate a Knee point signal Knee indicating a Knee point of the primary-side switching voltage VDS1 according to the assist signal DEMAG.

The resonance detection circuit 130 is configured to generate the resonance synchronization signal SYNC indicating that the primary-side switching voltage VDS1 is at the falling edge according to the auxiliary signal DEMAG.

The valley correction circuit 140 is used for generating a valley indication signal P _ PWM according to the resonant synchronization signal SYNC.

In this embodiment, as shown in fig. 6, the flyback converter of the present invention specifically operates as follows: in a steady state (e.g., the switching period [ n ]), the secondary-side control circuit 200 enables the zero-voltage switching pulse PZV at a third peak (e.g., P3 in the switching period [ n ]) of the primary-side switching voltage VDS1, and the primary-side control circuit enables the primary-side switching signal S1C according to a fourth valley (e.g., V4 in the switching period [ n ]) of the primary-side switching voltage VDS1, wherein the fourth valley V4 of the primary-side switching voltage VDS1 is later than the third peak P3 of the primary-side switching voltage VDS 1.

When the output power or the output current Io of the output power source is increased compared to the steady state, in the current switching period (e.g., the switching period [ n +1]), the primary-side control circuit delays, for example, a valley to enable the primary-side switching signal S1C, i.e., in the present embodiment, the primary-side switching signal S1C is enabled according to a fifth valley of the primary-side switching voltage VDS1 (V5 in the switching period [ n +1]) to prevent the primary-side switch S1 and the secondary-side switch S2 from being turned on at the same time, wherein a time point of the fifth valley of the primary-side switching voltage VDS1 (V5 in the switching period [ n +1]) is later than a time point of the fourth valley of the primary-side switching voltage VDS1 (V4 in the switching period [ n +1]) in the current switching period.

The operation of the above-described subcircuits is described in more detail below to achieve the above-described functionality, respectively.

Fig. 7 shows a schematic diagram of an embodiment of a resonance detection circuit (resonance detection circuit 130) in the flyback converter of the present invention. The resonance detection circuit 130 includes an amplifying circuit 131, a transistor 132, and a current-voltage conversion circuit 133, and the resonance detection circuit 130 is configured to detect whether the auxiliary signal DEMAG is lower than the reference signal VR to generate the resonance synchronization signal SYNC, in an embodiment, the reference signal VR is 0 or a reference voltage close to 0, so that the resonance synchronization signal SYNC indicates that the auxiliary signal DEMAG is a negative voltage, and the resonance synchronization signal SYNC also indicates that the primary-side switching voltage VDS1 is lower than the input voltage Vin. In one aspect, the rising edge of the resonant synchronization signal SYNC may be used to indicate that the primary-side switching voltage VDS1 falls from the peak to the midpoint of the valley, and the falling edge of the resonant synchronization signal SYNC may be used to indicate that the primary-side switching voltage VDS1 rises from the valley to the midpoint of the peak.

Fig. 8 shows a schematic diagram of a valley correction circuit (valley correction circuit 140) in the flyback converter according to an embodiment of the present invention. The valley correction circuit 140 includes a delay circuit 141 and a logic circuit for generating a valley indicating signal P _ PWM, a falling edge of the valley indicating signal P _ PWM is aligned with a falling edge of the resonant synchronization signal SYNC, and the delay circuit 141 delays a rising edge of the resonant synchronization signal SYNC to enable the valley indicating signal P _ PWM, such that the rising edge of the valley indicating signal P _ PWM is delayed from the rising edge of the resonant synchronization signal SYNC, wherein the time length of the delay can be adjusted by a capacitor and a current source. In one aspect, when the delayed time length is properly selected, the rising edge of the valley indication signal P _ PWM can be used to indicate the occurrence time of the valley of the primary-side switching voltage VDS1, for example.

Fig. 9 shows a schematic diagram of a knee point detection circuit (knee point detection circuit 150) in a flyback converter according to an embodiment of the present invention. The knee point detection circuit 150 includes a comparator 151, a pulse circuit 152, a status circuit 153, and a logic circuit. Wherein the status circuit 153 may be a flip-flop, for example. The comparator 151 compares the auxiliary signal DEMAG with the reference signal VK to generate a comparison result KneeCMP, and the pulse circuit 152 generates a Knee point pulse KP to trigger the flip-flop 153 to enable the Knee point signal Knee according to the comparison result KneeCMP and the delayed inverted signal KCdb having a single-sided delayed inverse correlation with the comparison result KneeCMP, and the negative edge signal CyL is used to reset the Knee point signal Knee, in other words, as shown in fig. 6, the rising edge of the Knee point signal Knee indicates the Knee point of the primary-side switching voltage VDS 1.

Fig. 10 shows a schematic diagram of a ramp generation circuit (ramp generation circuit 160) in the flyback converter according to an embodiment of the present invention. The ramp generating circuit 160 includes a flip-flop 161 and an integrating circuit 162, the flip-flop 161 generates a ramp enable signal RmpEN according to a rising edge of the Knee point signal Knee, so that the enabling integrating circuit 162 starts to charge the capacitor with a current source to generate a ramp signal Rmp. The flip-flop 161 is controlled by the system reset signal RST or the negative edge signal CyL, i.e., the ramp signal Rmp starts to charge up from the rising edge of the Knee point signal Knee and ends at the negative edge signal CyL of the next switching cycle.

Fig. 11 shows a schematic diagram of a valley selection circuit (valley selection circuit 170) in the flyback converter of the present invention. The valley selection circuit 170 includes an amplifier 171, an offset circuit 172, and sample-and-

hold circuits

173 and 175. The amplifier 171 generates a buffered ramp signal Rmp according to the ramp signal Rmp, and the sample-and-hold circuit 173 samples the ramp signal Rmp from the rising edge of the ramp enable signal RmpEN and samples and holds the ramp signal Rmp at the rising edge of the primary-side switching signal S1C to generate a ramp level signal RH 1. The sample-and-hold circuit 175 is configured to sample-and-hold the ramp level signal RH1 at the falling edge of the primary side switching signal S1C according to the negative edge signal CyL to generate the valley memory signal VN, i.e., the level of the valley memory signal VN is the level of the sample-and-hold primary side switching signal S1C at the rising edge time, and is updated at the falling edge of the primary side switching signal S1C.

In addition, the offset circuit 172 offsets the ramp signal Rmp to generate the ramp signals Rmp1 and Rmp2 with offsets, wherein the offsets of the ramp signals Rmp1 and Rmp2 compared to the ramp signal Rmp are determined by corresponding current sources and resistors.

Fig. 12 is a schematic diagram of an exemplary disable signal generating circuit of the flyback converter of the present invention (disable signal generating circuit 180). The disable signal generating circuit 180 includes a comparator 181, a comparator 182, flip-

flops

183, 184, 185, and a plurality of logic circuits.

The voltage level of the ramp signal Rmp is proportional to the duration of the primary-side switch voltage VDS1 after the knee point, so that, in one aspect, the level of the valley memory signal VN indicates the length of the period of the previous switching cycle in which the primary-side switch S1 is turned off. Then, the comparator 181 compares the ramp signal Rmp1 with the valley memory signal VN, and the comparator 182 compares the ramp signal Rmp2 with the valley memory signal VN to generate the pre-inhibit signal P _ INH corresponding to a pre-inhibit period tpin which the pre-inhibit period tpin corresponds to a period in which the valley memory signal VN is between the ramp signal Rmp1 and the ramp signal Rmp2, and then the flip-flop 183 determines whether to enable the inhibit signal INH according to whether the pre-inhibit signal P _ INH is enabled or not at a rising edge of the resonant synchronization signal SYNC or a rising edge of the on control signal TD. In other words, in one embodiment, when the load changes such that the conduction control signal TD determined by the feedback is triggered within the pre-inhibit signal P _ INH, the inhibit signal generation circuit 180 enables the inhibit signal INH to inhibit the conduction of the primary-side switch S1, which will be described in detail later.

In addition, the negative edge signal CyL is used to reset the inhibit signal INH at the negative edge of the primary-side switching signal S1C to wait for the inhibit signal INH to be enabled in the switching period. On the other hand, after the inhibit signal INH is enabled, the flip-

flops

184 and 185 form a delay circuit for determining the duration of the inhibit signal INH, i.e., the inhibit period Tinh, which is determined by the period of the adjacent rising edge of the valley indication signal P _ PWM and the number of flip-flops in one embodiment, so that the inhibit period Tinh is related to the resonant period Trng of the resonant waveform, and thus, in one preferred embodiment, after the inhibit period Tinh is over, the primary-side switching signal S1C can be enabled, for example, at another valley of the DCM resonant waveform after the inhibit period Tinh is delayed, and the zero-voltage switching can still be realized. Specifically, in the present embodiment, the inhibition period Tinh is 1.5 times or more the resonance period Trng of the aforementioned resonance waveform.

It should be noted that, since the offset of the ramp signals Rmp1 and Rmp2 with respect to the ramp signal Rmp determines the start point and the end point of the pre-inhibit period tpin, on the other hand, the time point when the primary-side switch S1 is turned on and the end point of the zero-voltage switching pulse PZV are related to the resonant period Trng in the steady state, in one embodiment, the offset of the ramp signals Rmp1 and Rmp2 with respect to the ramp signal Rmp is related to the resonant period Trng and the pulse width TZV of the zero-voltage switching pulse PZV. In a preferred embodiment, the pre-inhibit period tpin covers at least the zero voltage switching pulse PZV of the previous switching cycle.

Fig. 13 is a schematic diagram of an embodiment of a PWM generating circuit in the flyback converter of the present invention (PWM generating circuit 110). The PWM generating circuit 110 includes a timer 111 and a flip-flop 112, wherein the timer 111 generates a turn-on control signal TD according to a feedback signal related to the output power source, for example, to determine a turn-on time and a turn-on period of the primary-side switch S1 according to the output power source (e.g., the output current Io and the output voltage Vo), and specifically, the flip-flop 112 resets according to the feedback related signal FBR to determine a turn-on time of the primary-side switching signal S1C to adjust the output voltage Vout and/or the output current Iout, and synchronizes a start time of the primary-side switching signal S1C with, for example, a valley of the primary-side switching voltage VDS1 through a valley indication signal P _ PWM to realize the zero voltage switching. In addition, when the load increases to enable the on control signal TD in the disable period Tinh, the logic circuit 113 (e.g., an illustrated and nand gate) masks the on control signal TD in the disable period Tinh according to the disable signal INH to disable the triggering of the primary-side switching signal S1C, thereby implementing the on timing of the delayed primary-side switch S1 to effectively avoid the short-circuit current.

Specifically, as shown in the switching period [ n +1] in fig. 6, the on control signal TD is enabled during the pre-inhibit period tpin, thereby triggering the inhibit signal INH, and the on control signal TD is masked during the inhibit period Tinh to inhibit the triggering of the primary-side switching signal S1C, so that the primary-side switching signal S1C of the switching period [ n +2] is delayed until the inhibit period Tinh is over before triggering.

Fig. 14 shows a schematic diagram of an embodiment of a negative edge detection circuit (negative edge detection circuit 120) in the flyback converter of the present invention. The negative edge detection circuit 120 includes a delay circuit 121 and a plurality of logic circuits for detecting a negative edge of the primary side switching signal S1C to generate a negative edge signal CyL.

In one aspect, the flyback converter of the present invention memorizes the valley occurrence time of the previous switching cycle by analog valley memorization, generates the pre-inhibit signal P _ INH near the valley of the corresponding bit of the current switching cycle, and generates the inhibit signal INH when the primary switch S1 and the secondary switch S2 may be turned on simultaneously, so as to mask and inhibit the triggering of the primary switch S1C, which can delay the turn-on time of the primary switch S1 when the load increases to enable the turn-on control signal TD to be enabled by the pre-inhibit signal P _ INH, thereby effectively avoiding the aforementioned short-circuit current. It should be noted that the delay time Tnov at the time of turning on the primary switch S1 is related to the period of the resonant waveform, in a preferred embodiment, a multiple of 0.5 resonant period Trng of the resonant waveform, and in a preferred embodiment, it is equal to 1.5 resonant period Trng of the resonant waveform.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. The embodiments described are not limited to single use, but may be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A switching control circuit is used for controlling a flyback converter to convert an input power supply to generate an output power supply, wherein the flyback converter comprises a power transformer which is coupled between the input voltage and the output voltage in an electrically insulated mode; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the switching control circuit includes:

a primary side control circuit for generating a primary side switching signal to control the primary side switch in a switching period; and

a secondary side control circuit for generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectification pulse for controlling the secondary side switch to conduct a synchronous rectification time interval to realize secondary side synchronous rectification and a zero voltage switching pulse for controlling the secondary side switch to conduct a zero voltage switching time interval, thereby enabling the primary side switch to realize zero voltage switching;

wherein, in a steady state, the secondary control circuit enables the zero voltage switching pulse according to a first waveform characteristic of a discontinuous conduction mode resonance waveform, and the primary control circuit enables the primary switching signal according to a second waveform characteristic of the discontinuous conduction mode resonance waveform, wherein the second waveform characteristic of the discontinuous conduction mode resonance waveform is later than the first waveform characteristic of the discontinuous conduction mode resonance waveform;

when the output power or the output current of the output power supply rises compared with a steady state, in the current switching period, the primary side control circuit enables the primary side switching signal according to a third waveform characteristic of the discontinuous conduction mode resonance waveform so as to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

2. The switching control circuit of claim 1 wherein the discontinuous conduction mode resonant waveform corresponds to a resonant waveform of a drain-source voltage of the primary switch, wherein the second waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, and the third waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, wherein W is greater than V.

3. The switching control circuit of claim 1, wherein when the output power or the output current of the output power source increases compared to a steady state, the primary-side control circuit controls the primary-side switching signal to disable the primary-side switching signal for a disable period in the current switching cycle, such that the primary-side switching signal and the zero-voltage switching pulse do not overlap for the disable period to prevent the primary-side switch and the secondary-side switch from being turned on simultaneously;

wherein the forbidden time period is related to a rising edge of the primary-side switching signal in a previous switching cycle and a resonant cycle of the discontinuous conduction mode resonant waveform.

4. The switching control circuit of claim 1, wherein the resonant period of the discontinuous conduction mode resonant waveform is related to an inductance value of the primary winding and a stray capacitance value of the primary switch.

5. The switching control circuit of claim 3, wherein the primary-side control circuit generates a turn-on control signal according to the output power for triggering the primary-side switching signal and determining the turn-on time and the turn-on period of the primary side in each switching cycle, wherein the primary-side control circuit generates a pre-disable signal indicating a pre-disable period in each switching cycle;

when the conduction control signal is turned into enable in the pre-prohibition period, the primary side control circuit generates a prohibition signal indicating the prohibition period so as to shield the conduction control signal in the prohibition period and prohibit the triggering of the primary side switching signal;

wherein the pre-inhibit signal is generated according to a rising edge of the primary-side switching signal of a previous one of the switching cycles and the resonant cycle, wherein the pre-inhibit period covers at least the zero-voltage switching pulse of the previous one of the switching cycles.

6. The switching control circuit of claim 3, wherein the conduction control signal is allowed to trigger the primary-side switching signal when the conduction control signal is enabled outside the pre-disable period.

7. The switching control circuit of claim 3, wherein when the disable signal is enabled, the corresponding disable period is clocked according to a resonant synchronization signal associated with the resonant waveform such that the disable period is maintained for at least one of the resonant cycles.

8. The switching control circuit of claim 7, wherein the corresponding inhibit period is clocked with the resonant waveform-related signal after the inhibit signal is enabled, such that after the inhibit period ends, the primary-side switching signal is enabled at a third waveform characteristic of the discontinuous conduction mode resonant waveform, which is later than the second waveform characteristic corresponding to a previous switching cycle, to achieve zero-voltage switching.

9. The switching control circuit of claim 7, wherein the enabling timing of the primary-side switching signal is 1.5 resonant periods away from the zero-voltage switching pulse within the current switching period when the disable signal is enabled.

10. The switching control circuit of claim 5, wherein the primary-side control circuit comprises:

a ramp generating circuit for generating a basic ramp signal at a knee point of the primary-side switching signal in each switching cycle;

a valley selection circuit for sampling and holding the basic ramp signal at a rising edge of the primary side switching signal to generate a valley memory signal, and for generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal have a first offset level and a second offset level corresponding to the basic ramp signal, respectively; and

the circuit comprises a pre-inhibit signal generating circuit, a first ramp signal generating circuit, a second ramp signal generating circuit and a control circuit, wherein the pre-inhibit signal generating circuit is used for comparing the first ramp signal with the basic ramp signal and comparing the second ramp signal with the basic ramp signal to generate the pre-inhibit signal, the pre-inhibit time period corresponds to the period that the basic ramp signal is between the first ramp signal and the second ramp signal, and the pre-inhibit time period is used for judging whether the rising edge of the conduction control signal occurs in the pre-inhibit time period to generate the inhibit signal.

11. The switching control circuit of claim 10, wherein the first offset level and the second offset level are related to the resonant period.

12. The switching control circuit of claim 10, wherein the primary-side control circuit further comprises:

a resonance detection circuit for generating a resonance synchronization signal related to the resonance waveform according to an auxiliary signal generated by an auxiliary winding of the power transformer;

wherein the inhibit signal generating circuit is further configured to clock the inhibit period based on the resonant synchronization signal such that the inhibit period is maintained for at least one of the resonant cycles.

13. A flyback converter for converting an input power to generate an output power, the flyback converter comprising:

a power transformer coupled between the input voltage and the output voltage in an electrically insulated manner;

a primary side switch for switching a primary side winding of the power transformer;

a secondary side switch for switching a secondary side winding of the power transformer;

14. The flyback converter of claim 13, wherein the discontinuous conduction mode resonant waveform corresponds to a resonant waveform of a drain-source voltage of the primary-side switch, wherein the second waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, and the third waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, wherein W is greater than V.

15. The flyback converter of claim 13, wherein when the output power or the output current of the output power supply rises compared to a steady state, the primary-side control circuit controls the primary-side switching signal to disable the primary-side switching signal for a disable period during the current switching cycle, such that the primary-side switching signal and the zero-voltage switching pulse do not overlap for the disable period to prevent the primary-side switch and the secondary-side switch from being turned on simultaneously;

16. The flyback converter of claim 13, wherein the resonant period of the discontinuous conduction mode resonant waveform is related to an inductance of the primary winding and a stray capacitance of the primary switch.

17. The flyback converter of claim 15, wherein the primary-side control circuit generates a turn-on control signal according to the output power for triggering the primary-side switching signal and determining the turn-on time and the turn-on period of the primary side in each switching cycle, wherein the primary-side control circuit generates a pre-disable signal indicating a pre-disable period in each switching cycle;

18. The flyback converter of claim 15, wherein the turn-on control signal is allowed to trigger the primary-side switching signal when the turn-on control signal is asserted outside the pre-inhibit period.

19. The flyback converter of claim 15, wherein the inhibit period is clocked according to a resonant synchronization signal associated with the resonant waveform after the inhibit signal is enabled such that the inhibit period is maintained for at least one of the resonant cycles.

20. The flyback converter of claim 19, wherein the corresponding inhibit period is clocked with the resonant waveform-related signal after the inhibit signal is enabled, such that after the inhibit period ends, the primary-side switching signal is enabled at a third waveform characteristic of the discontinuous conduction mode resonant waveform, the third waveform characteristic being later than the second waveform characteristic corresponding to a previous switching cycle, to achieve zero-voltage switching.

21. A control method for controlling a flyback converter, in order to change an input power and produce an output power, the flyback converter includes a power transformer, couple to the input voltage and the output voltage in the way of electrical insulation; a primary side switch for switching a primary side winding of the power transformer; and a secondary side switch for switching a secondary side winding of the power transformer; the control method comprises the following steps:

generating a primary side switching signal to control the primary side switch in a switching period; and

generating a secondary side switching signal to control the secondary side switch, wherein the secondary side switching signal has a synchronous rectification pulse and a zero voltage switching pulse, the synchronous rectification pulse is used for controlling the secondary side switch to conduct a synchronous rectification time interval so as to realize secondary side synchronous rectification, and the zero voltage switching pulse is used for controlling the secondary side switch to conduct a zero voltage switching time interval, so that the primary side switch realizes zero voltage switching;

wherein, in a steady state, the step of generating the zero-voltage switching pulse comprises:

enabling the zero-voltage switching pulse according to a first waveform characteristic of a discontinuous conduction mode resonant waveform,

wherein, in a steady state, the step of generating the primary side switching signal comprises:

enabling the primary side switching signal according to a second waveform characteristic of the discontinuous conduction mode resonance waveform, wherein the second waveform characteristic of the discontinuous conduction mode resonance waveform is later than the first waveform characteristic of the discontinuous conduction mode resonance waveform; and

when the output power or the output current of the output power supply rises compared with a steady state, in the current switching period, enabling the primary side switching signal according to a third waveform characteristic of the discontinuous conduction mode resonance waveform to prevent the primary side switch and the secondary side switch from being simultaneously conducted, wherein the time point of the third waveform characteristic is later than the time point corresponding to the second waveform characteristic in the current switching period.

22. The method of claim 21, wherein the discontinuous conduction mode resonant waveform corresponds to a resonant waveform of a drain-source voltage of the primary switch, wherein the second waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, and the third waveform characteristic corresponds to a vth valley of the discontinuous conduction mode resonant waveform, wherein W is greater than V.

23. The control method of claim 13, wherein when the output power or the output current of the output power supply rises compared to a steady state, the primary-side switching signal is disabled for a disable period in the current switching cycle, such that the primary-side switching signal and the zero-voltage switching pulse do not overlap for the disable period, thereby preventing the primary-side switch and the secondary-side switch from being turned on simultaneously;

24. The method of claim 21, wherein the resonant period of the discontinuous conduction mode resonant waveform is related to an inductance of the primary winding and a stray capacitance of the primary switch.

25. The control method of claim 23, wherein generating the primary-side switching signal further comprises:

generating a conduction control signal according to the output power supply, for triggering the primary side switching signal and determining the conduction time and the conduction time period of the primary side in each switching period;

generating a pre-inhibit signal indicating a pre-inhibit period in each switching cycle; and

when the conduction control signal is turned into enable in the pre-prohibition period, generating a prohibition signal indicating the prohibition period so as to shield the conduction control signal in the prohibition period and prohibit the triggering of the primary side switching signal;

26. The control method of claim 23, wherein generating the primary-side switching signal further comprises: when the conduction control signal is turned to be enabled outside the pre-forbidding period, the conduction control signal is allowed to trigger the primary side switching signal.

27. The control method of claim 23 wherein the step of generating the primary-side switching signal further comprises: when the inhibit signal is enabled, the corresponding inhibit period is timed according to a resonance synchronous signal related to the resonance waveform, so that the inhibit period at least maintains one resonance period.

28. The control method of claim 27, wherein generating the primary-side switching signal further comprises: and when the inhibition signal is enabled, timing the corresponding inhibition time period by the resonance waveform related signal, so that after the inhibition time period is ended, the primary side switching signal is enabled in a third waveform characteristic of the discontinuous conduction mode resonance waveform to realize zero voltage switching, wherein the third waveform characteristic is later than the second waveform characteristic in the previous switching period.

29. The control method of claim 25, wherein the step of generating the disable signal comprises:

in each switching period, a knee point of the primary side switching signal starts to generate a basic ramp signal;

sampling and holding the basic ramp signal at the rising edge of the primary side switching signal to generate a valley memory signal;

generating a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal respectively have a first offset level and a second offset level corresponding to the basic ramp signal;

comparing the first ramp signal with the base ramp signal, and comparing the second ramp signal with the base ramp signal to generate the pre-inhibit signal, wherein the pre-inhibit period corresponds to a period in which the base ramp signal is between the first ramp signal and the second ramp signal; and

and judging whether the rising edge of the conduction control signal occurs in the pre-inhibition period to generate the inhibition signal.

30. The method of claim 29, wherein the first and second offset levels are related to the resonant period.