TW202201891A - Resonant half-bridge flyback power converter and primary controller circuit and control method thereof - Google Patents
Resonant half-bridge flyback power converter and primary controller circuit and control method thereof Download PDFInfo
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- TW202201891A TW202201891A TW110105469A TW110105469A TW202201891A TW 202201891 A TW202201891 A TW 202201891A TW 110105469 A TW110105469 A TW 110105469A TW 110105469 A TW110105469 A TW 110105469A TW 202201891 A TW202201891 A TW 202201891A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
Description
本發明係有關一種返馳式電源供應電路,特別是指一種諧振半橋返馳電源供應器。本發明也有關於用於諧振半橋返馳電源供應器的控制電路與控制方法。The invention relates to a flyback power supply circuit, in particular to a resonant half-bridge flyback power supply. The present invention also relates to a control circuit and a control method for a resonant half-bridge flyback power supply.
美國專利“US5959850A,不對稱佔空比返馳式轉換器”的先前技術公開了一種具有零電壓切換(ZVS)的半橋返馳式電源供應電路,以實現更高的功率效率。但是,該現有技術的缺點是,由於僅能工作於連續導通模式或是邊界導通模式,因此,在功率轉換器的輕負載期間電源轉換效率很差。本發明提供了一種諧振半橋返馳電源供應器,可操作於不連續導通模式(DCM),且同時還可通過下橋功率開關的控制,同時達成提高重載和輕載操作的電源轉換效率。The prior art of US Patent "US5959850A, Asymmetric Duty Cycle Flyback Converter" discloses a half-bridge flyback power supply circuit with zero voltage switching (ZVS) to achieve higher power efficiency. However, the disadvantage of this prior art is that the power conversion efficiency is poor during light loads of the power converter due to only operating in continuous conduction mode or boundary conduction mode. The present invention provides a resonant half-bridge flyback power supply, which can be operated in discontinuous conduction mode (DCM), and at the same time can be controlled by a lower-bridge power switch to improve power conversion efficiency in heavy-load and light-load operations at the same time .
就其中一個觀點言,本發明提供了一種諧振半橋返馳電源供應器,用以將一輸入電源轉換為一輸出電源,該諧振半橋返馳電源供應器包含:一半橋功率級電路,包括串聯於該輸入電源與一參考電位間之一上橋功率開關與一下橋功率開關,其中該上橋功率開關與該下橋功率開關耦接於一相位節點;一功率變壓器,耦接於該半橋功率級電路與該輸出電源之間;一諧振電容器,與該功率變壓器之一一次側繞組串聯耦接於該相位節點與該輸出電源之間;以及一一次側控制電路,用以根據相關於該輸出電源的一回授訊號而產生一上橋切換訊號與一下橋切換訊號,以分別控制該上橋功率開關與該下橋功率開關,而切換該功率變壓器的一一次側繞組,以將該輸入電源轉換為該輸出電源; 其中該一次側繞組於該上橋功率開關導通時感磁,且於該上橋功率開關轉為不導通後,該一次側控制電路於該下橋切換訊號中產生一諧振切換脈波而導通該下橋功率開關,通過該諧振電容器與該一次側繞組,以諧振方式將感磁時所獲得的能量傳送到該功率變壓器之一二次側繞組,以產生該輸出電源;其中當該輸出電源低於一延遲閾值時,該一次側控制電路根據該輸出電源,於該下橋切換訊號中決定一段延遲期間,且於部分的延遲期間內,控制該上橋功率開關與該下橋功率開關皆不導通,其中該延遲期間與該輸出電源反相關。In one aspect, the present invention provides a resonant half-bridge flyback power supply for converting an input power supply into an output power supply, the resonant half-bridge flyback power supply comprising: a half-bridge power stage circuit, including an upper bridge power switch and a lower bridge power switch connected in series between the input power supply and a reference potential, wherein the upper bridge power switch and the lower bridge power switch are coupled to a phase node; a power transformer is coupled to the half between the bridge power stage circuit and the output power supply; a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; and a primary side control circuit for according to An upper bridge switching signal and a lower bridge switching signal are generated in relation to a feedback signal of the output power, so as to respectively control the upper bridge power switch and the lower bridge power switch, and switch a primary side winding of the power transformer, to convert the input power into the output power; wherein the primary side winding is magnetized when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the primary side control circuit switches on the lower bridge A resonant switching pulse is generated in the signal to turn on the lower bridge power switch, and through the resonant capacitor and the primary side winding, the energy obtained during magnetic induction is transmitted to a secondary side winding of the power transformer in a resonance manner, so as to generating the output power; wherein when the output power is lower than a delay threshold, the primary side control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls the upper Neither the bridge power switch nor the lower bridge power switch is turned on, wherein the delay period is inversely related to the output power.
在一較佳實施例中,當該延遲期間長於一輕載閾值時段時,才於該輕載閾值時段後的該延遲期間內,控制該上橋功率開關與該下橋功率開關皆不導通,其中該輕載閾值時段大於等於0。In a preferred embodiment, when the delay period is longer than a light-load threshold period, neither the upper-bridge power switch nor the lower-bridge power switch is controlled to be turned off during the delay period after the light-load threshold period, The light load threshold period is greater than or equal to 0.
在一較佳實施例中,當該延遲期間長於該輕載閾值時段時,於該延遲期間結束後,該一次側控制電路更於該下橋切換訊號中產生一柔性切換脈波以導通該下橋功率開關一段柔性期間,使得該上橋功率開關於下次導通時達成柔性切換。In a preferred embodiment, when the delay period is longer than the light load threshold period, after the delay period ends, the primary side control circuit further generates a flexible switching pulse in the lower bridge switching signal to turn on the lower The bridge power switch has a flexible period, so that the upper bridge power switch can achieve flexible switching when it is turned on next time.
在一較佳實施例中,該柔性切換對應於該上橋功率開關於下次導通時達成零電壓切換。In a preferred embodiment, the flexible switching corresponds to zero-voltage switching when the upper-bridge power switch is turned on next time.
在一較佳實施例中,該下橋功率開關的導通期間相關於該功率變壓器之去磁期間,且大於等於該功率變壓器之去磁期間。In a preferred embodiment, the conduction period of the low-bridge power switch is related to the demagnetization period of the power transformer, and is greater than or equal to the demagnetization period of the power transformer.
在一較佳實施例中,該一次側控制電路緊接在該上橋切換訊號切換至高位準之前與之後,分別維持該上橋切換訊號與該下橋切換訊號於低位準一段上橋空滯時間(dead time)與一段下橋空滯時間,使得該上橋功率開關與該下橋功率開關各自於下次導通時達成柔性切換,其中於該上橋空滯時間與該下橋空滯時間內,該上橋功率開關與該下橋功率開關皆不導通。In a preferred embodiment, the primary side control circuit maintains the upper bridge switching signal and the lower bridge switching signal at a low level for a period of upper bridge hysteresis immediately before and after the upper bridge switching signal is switched to a high level. Dead time and a lower bridge dead time, so that the upper bridge power switch and the lower bridge power switch respectively achieve flexible switching when they are turned on next time, wherein the upper bridge dead time and the lower bridge dead time Inside, the upper bridge power switch and the lower bridge power switch are both non-conductive.
在一較佳實施例中,該下橋切換訊號之致能先於該上橋切換訊號之致能。In a preferred embodiment, the enabling of the lower bridge switching signal precedes the enabling of the upper bridge switching signal.
在一較佳實施例中,於上橋功率開關導通前,控制該下橋功率開關導通,以對一自舉(bootstrap)電容器充電,其中該自舉電容器用以提供電源予該上橋開關驅動器,該上橋開關驅動器用以驅動該上橋功率開關。In a preferred embodiment, before the upper bridge power switch is turned on, the lower bridge power switch is controlled to be turned on to charge a bootstrap capacitor, wherein the bootstrap capacitor is used to provide power to the upper bridge switch driver , the upper bridge switch driver is used to drive the upper bridge power switch.
在一較佳實施例中,該一次側控制電路更根據一準諧振訊號的一波形特徵而決定該延遲期間,進而決定該下橋切換訊號的該諧振切換脈波的起始時點,其中該準諧振訊號的一準諧振週期相關於該一次側繞組的電感值與該半橋功率級電路的雜散電容值。In a preferred embodiment, the primary side control circuit further determines the delay period according to a waveform characteristic of a quasi-resonant signal, and then determines the starting time of the resonant switching pulse of the lower bridge switching signal, wherein the quasi-resonant switching signal is A quasi-resonant period of the resonant signal is related to the inductance value of the primary side winding and the stray capacitance value of the half-bridge power stage circuit.
在一較佳實施例中,當該輸出電源低於一叢發(burst)閾值時,產生一叢發訊號,其中當該叢發訊號產生時,該延遲期間更包括一叢發期間,以延長該延遲期間。In a preferred embodiment, when the output power is lower than a burst threshold, a burst signal is generated, wherein when the burst signal is generated, the delay period further includes a burst period to extend the delay period.
在一較佳實施例中,該叢發閾值低於該延遲閾值。In a preferred embodiment, the burst threshold is lower than the delay threshold.
就另一個觀點言,本發明也提供了一種一次側控制電路,用於控制一諧振半橋返馳電源供應器,以將一輸入電源轉換為一輸出電源,該諧振半橋返馳電源供應器包括:一半橋功率級電路,包括串聯於該輸入電源與一參考電位間之一上橋功率開關與一下橋功率開關,其中該上橋功率開關與該下橋功率開關耦接於一相位節點;一功率變壓器,耦接於該半橋功率級電路與該輸出電源之間;以及一諧振電容器,與該功率變壓器之一一次側繞組串聯耦接於該相位節點與該輸出電源之間;該一次側控制電路包含:一脈波調變電路,用以根據相關於該輸出電源的一回授訊號而產生一調變訊號;一上橋驅動電路,根據該調變訊號而產生一上橋切換訊號以控制該上橋功率開關;以及一時序控制電路,耦接於該脈波調變電路,用以產生一下橋切換訊號以控制該下橋功率開關,而切換該功率變壓器的一一次側繞組,以將該輸入電源轉換為該輸出電源; 其中該一次側繞組於該上橋功率開關導通時感磁,且於該上橋功率開關轉為不導通後,該時序控制電路於該下橋切換訊號中產生一諧振切換脈波而導通該下橋功率開關,通過該諧振電容器與該一次側繞組,以諧振方式將感磁時所獲得的能量傳送到該功率變壓器之一二次側繞組,以產生該輸出電源;其中當該輸出電源低於一延遲閾值時,該時序控制電路根據該輸出電源,於該下橋切換訊號中決定一段延遲期間,且於部分的延遲期間內,控制該上橋功率開關與該下橋功率開關皆不導通,其中該延遲期間與該輸出電源反相關。In another aspect, the present invention also provides a primary side control circuit for controlling a resonant half-bridge flyback power supply to convert an input power into an output power, the resonant half-bridge flyback power supply comprising: a half-bridge power stage circuit, including an upper-bridge power switch and a lower-bridge power switch connected in series between the input power supply and a reference potential, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power transformer coupled between the half-bridge power stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the The primary side control circuit includes: a pulse modulation circuit for generating a modulation signal according to a feedback signal related to the output power; an upper bridge driving circuit for generating an upper bridge according to the modulation signal a switching signal to control the upper bridge power switch; and a timing control circuit, coupled to the pulse modulation circuit, for generating a lower bridge switching signal to control the lower bridge power switch to switch the power transformers one by one A secondary side winding to convert the input power into the output power; wherein the primary side winding is magnetically induced when the upper bridge power switch is turned on, and after the upper bridge power switch is turned off, the sequence control circuit is in the A resonant switching pulse is generated in the lower bridge switching signal to turn on the lower bridge power switch, and through the resonant capacitor and the primary side winding, the energy obtained during magnetic induction is transmitted to a secondary side of the power transformer in a resonance manner winding to generate the output power; wherein when the output power is lower than a delay threshold, the timing control circuit determines a delay period in the lower bridge switching signal according to the output power, and controls the Neither the upper-bridge power switch nor the lower-bridge power switch is turned on, wherein the delay period is inversely related to the output power.
就另一個觀點言,本發明也提供了一種控制方法,用於控制一諧振半橋返馳電源供應器,以將一輸入電源轉換為一輸出電源,該諧振半橋返馳電源供應器包括:一半橋功率級電路,包括串聯於該輸入電源與一參考電位間之一上橋功率開關與一下橋功率開關,其中該上橋功率開關與該下橋功率開關耦接於一相位節點;一功率變壓器,耦接於該半橋功率級電路與該輸出電源之間;以及一諧振電容器,與該功率變壓器之一一次側繞組串聯耦接於該相位節點與該輸出電源之間;該控制方法包含:根據相關於該輸出電源的一回授訊號而產生一調變訊號;根據該調變訊號而產生一上橋切換訊號與一下橋切換訊號,以分別控制該上橋功率開關與該下橋功率開關,而切換該功率變壓器的一一次側繞組,以將該輸入電源轉換為該輸出電源; 其中控制該上橋功率開關與該下橋功率開關的步驟包括:於該上橋功率開關轉為不導通後,於該下橋切換訊號中產生一諧振切換脈波而導通該下橋功率開關,通過該諧振電容器與該一次側繞組,以諧振方式將該一次側繞組於該上橋功率開關導通而感磁時所獲得的能量傳送到該功率變壓器之一二次側繞組,以產生該輸出電源;當該輸出電源低於一延遲閾值時,根據該輸出電源,於該下橋切換訊號中決定一段延遲期間,且於部分的延遲期間內,控制該上橋功率開關與該下橋功率開關皆不導通,其中該延遲期間與該輸出電源反相關。In another aspect, the present invention also provides a control method for controlling a resonant half-bridge flyback power supply to convert an input power into an output power, the resonant half-bridge flyback power supply comprising: A half-bridge power stage circuit includes an upper-bridge power switch and a lower-bridge power switch connected in series between the input power supply and a reference potential, wherein the upper-bridge power switch and the lower-bridge power switch are coupled to a phase node; a power a transformer coupled between the half-bridge power stage circuit and the output power supply; and a resonant capacitor coupled in series with a primary side winding of the power transformer between the phase node and the output power supply; the control method Including: generating a modulation signal according to a feedback signal related to the output power; generating an upper bridge switching signal and a lower bridge switching signal according to the modulation signal, so as to respectively control the upper bridge power switch and the lower bridge a power switch to switch a primary side winding of the power transformer to convert the input power into the output power; wherein the step of controlling the upper-bridge power switch and the lower-bridge power switch includes: turning the upper-bridge power switch After being turned off, a resonant switching pulse is generated in the lower bridge switching signal to turn on the lower bridge power switch, and the primary side winding is connected to the upper bridge power switch in a resonance manner through the resonant capacitor and the primary side winding. The energy obtained when conducting and magnetic induction is transmitted to a secondary winding of the power transformer to generate the output power; when the output power is lower than a delay threshold, according to the output power, in the lower bridge switching signal A delay period is determined, and during a part of the delay period, both the upper bridge power switch and the lower bridge power switch are controlled to be turned off, wherein the delay period is inversely related to the output power.
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.
本發明中的圖式均屬示意,主要意在表示各電路間之耦接關係,以及各訊號波形之間之關係,至於電路、訊號波形與頻率則並未依照比例繪製。The drawings in the present invention are schematic, mainly intended to represent the coupling relationship between the circuits and the relationship between the signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.
圖1A顯示根據本發明之諧振半橋返馳電源供應器的較佳實施例示意圖(諧振半橋返馳電源供應器1001)。諧振半橋返馳電源供應器1001包含形成半橋功率級電路300的上橋功率開關30和下橋功率開關40,其中上橋功率開關30和下橋功率開關40串聯於輸入電源Vin與一參考電位之間。功率變壓器10和諧振電容器20串聯耦接於半橋功率級電路300的相位節點HB與輸出電源Po之間,其中上橋功率開關30與下橋功率開關40耦接於相位節點HB。功率變壓器10包括一次側繞組NP,二次側繞組NS和輔助繞組NA。一次側繞組NP和二次側繞組NS具有匝數比n。二次側繞組NS和輔助繞組NA具有匝數比m。一次側控制電路100產生上橋切換訊號SH和下橋切換訊號SL,通過半橋功率級電路300來切換功率變壓器10,以在功率變壓器10的二次側產生輸出電源Po。具體而言,一次側繞組NP於上橋功率開關30導通時感磁,且於上橋功率開關30轉為不導通後,一次側控制電路100於下橋切換訊號SL中產生一諧振切換脈波PRES而導通下橋功率開關40時,通過諧振電容器20與一次側繞組NP,以諧振方式將感磁時所獲得的能量傳送到10之二次側繞組NS,以產生輸出電源Po。電阻器60用以檢測功率變壓器10的一次側開關電流IP來產生電流檢測訊號VCS。1A shows a schematic diagram of a preferred embodiment of a resonant half-bridge flyback power supply according to the present invention (resonant half-bridge flyback power supply 1001 ). The resonant half-bridge
在一實施例中,一次側控制電路100響應於回授訊號VFB來產生上橋切換訊號SH和下橋切換訊號SL,回授訊號VFB則根據諧振半橋返馳電源供應器1001的輸出電源Po而產生。具體而言,二次側控制電路200耦接至輸出電源Po,以產生回授訊號VFB,在一實施例中,回授訊號VFB通過光耦合器90耦合到一次側控制電路100。二次側控制電路200還用以產生在功率變壓器10的去磁期間TDS期間驅動同步整流開關70的驅動訊號SG。繞組NA在功率變壓器10的切換期間產生輔助繞組訊號VNA,電阻器51、52進一步衰減該輔助繞組訊號VNA,以產生連接到一次側控制電路100的輔助繞組相關訊號VAUX。In one embodiment, the primary-
圖1B顯示根據本發明之諧振半橋返馳電源供應器中,一次側控制電路100的一具體實施例示意圖(一次側控制電路100)。如圖1B所示一次側控制電路100包括脈寬調變電路101、上橋驅動電路102以及時序控制電路120。在一實施例中,時序控制電路120包括第一計時電路105、SSW(柔性切換)脈波產生電路106、空滯時間產生電路107、107’、 第二計時電路108、下橋控制電路103、延遲訊號電路109、第三計時電路110以及輸出位準感測電路104。1B shows a schematic diagram of a specific embodiment of the primary
第一計時電路105用以根據相關於輸出電源Po的放電電流ID而產生斜坡訊號VC1。SSW脈波產生電路106根據斜坡訊號VC1而產生對應於柔性切換脈波PSSW的訊號S1。空滯時間產生電路107產生訊號S2以提供上橋功率開關30與下橋功率開關40切換之間的空滯時間。脈寬調變電路101與上橋驅動電路102用以根據例如回授訊號VFB與電流感測訊號VCS決定了上橋切換訊號SH的脈寬。空滯時間產生電路107’ 產生訊號S4以提供上橋功率開關30與下橋功率開關40切換之間的空滯時間。第二計時電路108於訊號S4所產生的空滯時間之後,產生斜坡訊號VC5,下橋控制電路103根據斜坡訊號VC5而決定訊號S5的脈寬(對應於諧振切換脈波PRES),且用以結合訊號S1與訊號S5而產生下橋切換訊號SL。第三計時電路110用以根據輔助繞組相關訊號VAUX而決定一準諧振訊號的波谷之時點。延遲訊號電路109則整合斜坡訊號VC1、波谷之時點與訊號S5而產生相關於延遲期間TDLY的訊號S6。輸出位準感測電路104用以根據回授訊號VCOM(對應於輸出電流Io之位準)而決定前述的放電電流ID。The
圖2顯示對應於本發明之圖1A所示的實施例的波形示意圖。當上橋切換訊號SH被致能時(例如為高位準),功率變壓器10被感磁並產生感磁電流IM,其中上橋切換訊號SH的致能期間TW對應於上橋功率開關30的導通期間。當上橋切換訊號SH被禁能時,功率變壓器10被去磁,功率變壓器10在去磁期間TDS期間產生二次側開關電流IS。下橋切換訊號SL的致能期間TSL與功率變壓器10的去磁期間TDS有關,其中下橋切換訊號SL的致能期間TSL對應於下橋功率開關40的導通期間。下橋切換訊號SL的致能期間TSL等於或長於功率變壓器10的去磁期間TDS,以避免功率變壓器10操作於連續導通模式(CCM)。在功率變壓器10的去磁期間TDS期間,產生反射電壓VX並被箝位在諧振電容器20中,其中VX = nVO。FIG. 2 shows a waveform diagram corresponding to the embodiment shown in FIG. 1A of the present invention. When the high-side switching signal SH is enabled (eg, at a high level), the
當上橋切換訊號SH被禁能時(例如轉為低位準),可以接著致能下橋切換訊號SL。當下橋切換訊號SL被禁能時,上橋切換訊號SH可以被致能。在上橋切換訊號SH和下橋切換訊號SL之間具有空滯時間,空滯時間TRH和TRL的時間長度相關於諧振週期,使得上橋功率開關30與下橋功率開關40各自於下次導通時可實現柔性切換(soft switching),或者進一步達成零電壓切換(ZVS, zero voltage switching)。When the high-bridge switching signal SH is disabled (eg, turned to a low level), the low-bridge switching signal SL can then be enabled. When the lower bridge switching signal SL is disabled, the upper bridge switching signal SH can be enabled. There is a dead time between the upper-bridge switching signal SH and the lower-bridge switching signal SL, and the lengths of the dead times TRH and TRL are related to the resonance period, so that the upper-
圖3顯示根據本發明之一實施例的波形示意圖。當輸出電源Po低於延遲閾值時,下橋切換訊號SL包括延遲期間TDLY。當輸出電源Po低於延遲閾值時,隨著輸出電源Po的降低,延遲期間TDLY會隨之增加,且上橋切換訊號SH的頻率降低。需說明的是,前述「當輸出電源Po低於延遲閾值」,在一實施例中,可以指輸出電源Po的功率位準低於延遲閾值,或者,在另一實施例中,特別是在輸出電壓Vo為固定的情況下,可以指輸出電源Po的電流位準低於延遲閾值。FIG. 3 shows a schematic diagram of waveforms according to an embodiment of the present invention. When the output power Po is lower than the delay threshold, the lower bridge switching signal SL includes a delay period TDLY. When the output power Po is lower than the delay threshold, as the output power Po decreases, the delay period TDLY increases accordingly, and the frequency of the high-bridge switching signal SH decreases. It should be noted that the aforementioned "when the output power Po is lower than the delay threshold", in one embodiment, may mean that the power level of the output power Po is lower than the delay threshold, or, in another embodiment, especially when the output When the voltage Vo is fixed, it may mean that the current level of the output power source Po is lower than the delay threshold.
如圖3所示,當輸出電源Po低於延遲閾值時,下橋切換訊號SL會分離為諧振切換脈波PRES和柔性切換脈波PSSW,且在諧振切換脈波PRES和柔性切換脈波PSSW之間產生延遲期間TDLY,如圖3所示,於延遲期間TDLY內,下橋切換訊號SL為低位準(禁能),亦即下橋功率開關40控制為不導通。As shown in Figure 3, when the output power Po is lower than the delay threshold, the lower bridge switching signal SL will be separated into the resonance switching pulse PRES and the flexible switching pulse PSSW, and between the resonance switching pulse PRES and the flexible switching pulse PSSW A delay period TDLY is generated between them. As shown in FIG. 3 , during the delay period TDLY, the lower bridge switching signal SL is at a low level (disabled), that is, the lower
於延遲期間TDLY內,由於功率變壓器10完成去磁,且上橋功率開關30與下橋功率開關40皆控制為不導通,功率變壓器10會與雜散電容產生準諧振,因此可於例如相位節點電壓VHB或輔助繞組相關訊號VAUX上觀察到準諧振的波形。在一實施例中,延遲期間TDLY還根據一次側控制電路100根據準諧振訊號的一波形特徵(例如波谷)的發生時點而決定,以致能下橋切換訊號SL,以實現柔性切換或零電壓切換。前述準諧振訊號的波谷可對應於例如圖3中相位節點電壓VHB的波谷VV1~VVN中的任一個波谷,或者可根據輸出電源Po的位準而決定對應的波谷之序位,其中N為正整數。During the delay period TDLY, since the demagnetization of the
下橋切換訊號SL在準諧振訊號的波谷(例如於VV4)處導通下橋功率開關40,以實現下橋功率開關40的柔性切換或零電壓切換,藉此減小下橋功率開關40的開關損耗。準諧振訊號的準諧振週期TQV(如VV1~ VVN中的任兩個波谷之間的時間長度),相關於功率變壓器10的一次側繞組NP的電感值和半橋功率級電路300的雜散電容值有關,其中雜散電容與上橋功率開關30、下橋功率開關40和功率變壓器10的寄生電容有關。The lower bridge switching signal SL turns on the lower
圖4顯示根據本發明之一實施例的狀態操作波形示意圖。下橋切換訊號SL由訊號S1和訊號S5形成,在一實施例中,下橋切換訊號SL由訊號S1和訊號S5的或邏輯運算而產生 ,其中訊號S1的致能期間對應於TSLB。上橋切換訊號SH對應於訊號S3。在一實施例中,訊號S3的脈波寬度與回授訊號VFB和電流感測訊號VCS的位準有關。訊號S2的脈波寬度確定空滯時間TRH。訊號S4的脈波寬度確定空滯時間TRL。訊號S6的脈波寬度TS6確定延遲期間TDLY,其詳細的關係容後詳述,其中訊號S6的脈波寬度TS6包括第一時段TS6A和第二時段TV。FIG. 4 shows a schematic diagram of a state operation waveform according to an embodiment of the present invention. The lower bridge switching signal SL is formed by the signal S1 and the signal S5. In one embodiment, the lower bridge switching signal SL is generated by the OR logic operation of the signal S1 and the signal S5, wherein the enable period of the signal S1 corresponds to TSLB. The high-bridge switching signal SH corresponds to the signal S3. In one embodiment, the pulse width of the signal S3 is related to the level of the feedback signal VFB and the current sensing signal VCS. The pulse width of the signal S2 determines the dead time TRH. The pulse width of the signal S4 determines the dead time TRL. The pulse width TS6 of the signal S6 determines the delay period TDLY, the detailed relationship thereof will be described in detail later, wherein the pulse width TS6 of the signal S6 includes a first period TS6A and a second period TV.
訊號S1在訊號S3的致能之前被致能,因此下橋切換訊號SL的致能先於上橋切換訊號SH的致能。如圖4所示,在上橋功率開關30導通之前,下橋功率開關40導通,以對提供電源予上橋開關驅動器275的自舉電容器(bootstrap capacitor)277充電(圖7,容後詳述)。The signal S1 is enabled before the signal S3 is enabled, so the lower bridge switching signal SL is enabled before the upper bridge switching signal SH is enabled. As shown in FIG. 4 , before the
如圖4所示,訊號S2在訊號S1的下降沿被致能,接著,訊號S3在訊號S2的下降沿被致能,訊號S4在訊號S3的下降沿被致能,訊號S5在訊號S4的下降沿被致能。As shown in Figure 4, the signal S2 is enabled at the falling edge of the signal S1, then the signal S3 is enabled at the falling edge of the signal S2, the signal S4 is enabled at the falling edge of the signal S3, and the signal S5 is enabled at the falling edge of the signal S4. Falling edge is enabled.
訊號S6在訊號S56的上升沿被致能,其中訊號S56在訊號S5結束之前產生,詳言之,當訊號S5被致能後,訊號S56將在時段TSLA之後產生(即斜坡訊號VC5超過閾值VT5A的時點),因此,在訊號S6的開始與訊號S5的結束之間存在重疊時段T5TH。The signal S6 is enabled at the rising edge of the signal S56, and the signal S56 is generated before the end of the signal S5. Specifically, when the signal S5 is enabled, the signal S56 will be generated after the period TSLA (that is, the ramp signal VC5 exceeds the threshold VT5A). ), therefore, there is an overlap period T5TH between the start of the signal S6 and the end of the signal S5.
斜坡訊號VC1用以確定上橋切換訊號SH和下橋切換訊號SL的切換週期。斜坡訊號VC1的充電時間(如圖4所示的上升時間)確定訊號S1的脈波寬度。斜坡訊號VC1的放電時間(如圖4所示的下降時間)決定訊號S6的第一時段TS6A,根據本發明,在一實施例中,斜坡訊號VC1的放電時間反相關於輸出電源Po,換言之,當輸出電流Io愈低,第一時段TS6A則愈長。訊號S6的第二時段TV相關於準諧振訊號的周期和所對應的波谷序位(VV1~VVN)。The ramp signal VC1 is used to determine the switching period of the upper bridge switching signal SH and the lower bridge switching signal SL. The charging time of the ramp signal VC1 (the rise time shown in Figure 4) determines the pulse width of the signal S1. The discharge time (fall time as shown in FIG. 4 ) of the ramp signal VC1 determines the first period TS6A of the signal S6. According to the present invention, in an embodiment, the discharge time of the ramp signal VC1 is inversely related to the output power Po, in other words, When the output current Io is lower, the first period TS6A is longer. The second period TV of the signal S6 is related to the period of the quasi-resonant signal and the corresponding valley sequence (VV1 ˜VVN).
斜坡訊號VC5用以確定訊號S5的脈波寬度並產生訊號S56。訊號S5的致能啟動斜坡訊號VC5的充電,亦即斜坡訊號VC5自訊號S5的上升沿開始上升。當斜坡訊號VC5高於閾值VT5A時,致能訊號S56。當斜坡訊號VC5高於閾值VT5B時,訊號S5的脈波結束,其中閾值VT5B的位準高於閾值VT5A的位準。The ramp signal VC5 is used to determine the pulse width of the signal S5 and generate the signal S56. The enabling of the signal S5 starts the charging of the ramp signal VC5, that is, the ramp signal VC5 starts to rise from the rising edge of the signal S5. When the ramp signal VC5 is higher than the threshold VT5A, the signal S56 is enabled. When the ramp signal VC5 is higher than the threshold VT5B, the pulse wave of the signal S5 ends, wherein the level of the threshold VT5B is higher than the level of the threshold VT5A.
在一實施例中,由於斜坡訊號VC1的放電時間反相關於輸出電源Po,因此,當諧振半橋返馳電源供應器1001的輸出電源Po(例如輸出電流Io的位準)相對較高,使得斜坡訊號VC1的放電時間短於重疊時段T5TH時(如VC1中的數條虛線下降斜坡的實施例),則訊號S6的脈波寬度TS6將短於重疊時段T5TH(如S6中的數條虛線下降沿的實施例),且訊號S1將重疊與訊號S5。因此,下橋切換訊號SL在上橋切換訊號SH的禁能期間將僅具有一個脈波(如圖2)。在一實施例中,當斜坡訊號VC1的放電時間短於重疊時段T5TH時,將不計時第二時段TV,亦即TS6等於TS6A。In one embodiment, since the discharge time of the ramp signal VC1 is inversely related to the output power Po, the output power Po (eg, the level of the output current Io) of the resonant half-bridge
另一方面,如果諧振半橋返馳電源供應器1001的輸出電源Po相對較低,使得斜坡訊號VC1的放電時間長於重疊時段T5TH(如VC1中的數條實線下降斜坡的實施例),則下橋切換訊號SL將被分離為諧振切換脈波PRES和柔性切換脈波PSSW(圖4),其中諧振切換脈波PRES和柔性切換脈波PSSW分別對應於訊號S1和訊號S5。On the other hand, if the output power Po of the resonant half-bridge
本實施例中,延遲期間TDLY起始自訊號S5的下降沿,其時間長度相關於時段TS6A,而於一實施例中,延遲期間TDLY還包括第二時段TV。In this embodiment, the delay period TDLY starts from the falling edge of the signal S5, and its time length is related to the period TS6A. In one embodiment, the delay period TDLY further includes a second period TV.
由於訊號S6的脈波寬度TS6為延遲期間TDLY的前身,因此,就一觀點而言,訊號S6的脈波寬度TS6也可視為另一延遲期間,當延遲期間TS6A長於輕載閾值時段(對應於重疊時段T5TH)時,在延遲期間TDLY內,上橋功率開關30和下橋功率開關40都截止。需說明的是,本實施例中,延遲期間TS6等於輕載閾值時段(T5TH)與延遲期間TDLY之和。在一實施例中,輕載閾值時段(T5TH)大於等於0。在輕載閾值時段(T5TH)等於0的實施例中,延遲期間TS6重疊於延遲期間TDLY。此外,當延遲期間TS6A長於輕載閾值時段(T5TH)時,延遲期間TDLY才得以存在,亦即大於0。Since the pulse width TS6 of the signal S6 is the predecessor of the delay period TDLY, from a point of view, the pulse width TS6 of the signal S6 can also be regarded as another delay period, when the delay period TS6A is longer than the light load threshold period (corresponding to the light load threshold period) During the overlapping period T5TH), within the delay period TDLY, both the upper-
此外,從一角度而言,在一實施例中,重疊時段T5TH確定了前述的輕載閾值時段。In addition, from an angle, in one embodiment, the overlapping period T5TH determines the aforementioned light load threshold period.
請同時對照圖1B,以下圖5~圖10顯示對應於圖1B實施例之電路方塊的更具體實施例示意圖,圖1B中的一次側控制電路100可用以產生對應於前述的操作。Please refer to FIG. 1B at the same time, the following FIGS. 5 to 10 show schematic diagrams of more specific embodiments of the circuit blocks corresponding to the embodiment of FIG. 1B . The primary
圖5顯示本發明之一次側控制電路的一具體實施例,具體而言,圖5顯示了第一計時電路105與SSW(柔性切換)脈波產生電路106的具體實施例示意圖。請參閱圖5,同時對照圖1B與圖4,第一計時電路105用以產生斜坡訊號VC1,SSW脈波產生電路106則用以產生對應於柔性切換脈波PSSW的訊號S1。當訊號S6被禁能時,充電電流IC通過開關210對電容器230充電而產生斜坡訊號VC1的上升斜坡,當斜坡訊號VC1的位準高於閾值VT1A時,比較器231致能訊號S1,當斜坡訊號VC1的位準高於閾值VT1B時,比較器232重置訊號S1。訊號S1的脈波寬度相關於使上橋功率開關30實現柔性切換或零電壓切換的需求,因此,充電電流IC與電容器230的電容值與閾值VT1A及VT1B可根據上述需求而決定。FIG. 5 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 5 shows a schematic diagram of a specific embodiment of the
當訊號S6致能時,放電電流ID通過開關220以對電容器230放電,在一實施例中,當回授訊號VCOM低於閾值VTH1時(如圖10所示,對應於前述,輸出電源Po低於延遲閾值,容後詳述),放電電流ID隨著輸出電源Po的降低而降低。其中,回授訊號VCOM的位準與回授訊號VFB的位準相關,在一實施例中,回授訊號VCOM的位準與回授訊號VFB的位準正相關於輸出電源Po的輸出電流Io之位準。當回授訊號VCOM低於閾值VTH2時(如圖10所示,對應於前述,輸出電源Po低於叢發閾值,容後詳述),產生叢發訊號BST。在一實施例中,閾值VTH2的位準低於閾值VTH1,亦即叢發閾值低於延遲閾值。當訊號S6致能時,叢發訊號BST將禁能開關210、220並且禁能電容器230的充電和放電,因此,當產生叢發訊號BST時,叢發時段包括在延遲期間TDLY中,並且叢發時段將延長延遲期間TS6的時長,亦同時延長了延遲期間TDLY的時長。When the signal S6 is enabled, the discharge current ID passes through the
圖6顯示本發明之一次側控制電路中,空滯時間產生電路的具體實施例示意圖(空滯時間產生電路107),圖6的空滯時間產生電路107例如對應於圖1B中的107或107’。請參閱圖6,同時對照圖1B與圖4,空滯時間產生電路107用以根據訊號S1或S2而對應產生脈波寬度分別為空滯時間TRH或TRL的訊號S2或S4,其中電流源245的電流和電容器250的電容值決定了空滯時間產生電路107的時間常數,在一實施例中,空滯時間產生電路107的時間常數相關於功率變壓器10的電感和雜散電容所致的諧振週期。FIG. 6 shows a schematic diagram of a specific embodiment of the dead time generating circuit in the primary-side control circuit of the present invention (the dead time generating circuit 107 ). The dead
圖7顯示本發明之一次側控制電路的一具體實施例,具體而言,圖7顯示了脈寬調變電路與上橋驅動電路的具體實施例示意圖(脈寬調變電路101與上橋驅動電路102)。請參閱圖7,同時對照圖1B與圖4,脈寬調變電路101用以產生上橋切換訊號SH,回授訊號VCOM是回授訊號VFB經由電晶體265所產生的位準移位訊號,亦即回授訊號VCOM正相關於回授訊號VFB,且二者相差一近於固定的位準差值。回授訊號VFB的位準與諧振半橋返馳電源供應器1001的輸出電源Po的位準成比例,如前所述,在一實施例中,回授訊號VFB的位準與輸出電源Po的輸出電流位準Io成正比。FIG. 7 shows a specific embodiment of the primary-side control circuit of the present invention. Specifically, FIG. 7 shows a schematic diagram of a specific embodiment of the pulse width modulation circuit and the upper bridge driving circuit (the pulse
訊號S3受訊號S2的下降沿所致能,於訊號S3被致能後,脈波產生器271用以決定訊號S3的最小導通時間。電阻器262、263產生受衰減的VCOM訊號,即回授訊號VCOM’。當電流感測訊號VCS高於回授訊號VCOM’時,比較器260禁能訊號S3。The signal S3 is enabled by the falling edge of the signal S2. After the signal S3 is enabled, the
上橋驅動電路102中,訊號S3通過上橋開關驅動器275產生上橋切換訊號SH。請同時對照圖1A與圖1B,其中電源VDD在下橋功率開關40導通時,通過自舉二極體279對自舉電容器277充電,為上橋開關驅動器275在自舉接地點HGND的基礎下,提供自舉式電源,其中自舉接地點HGND耦接於前述的相位節點HB。In the high-
圖8顯示本發明之一次側控制電路的一具體實施例,具體而言,圖8顯示了第二計時電路與下橋控制電路的具體實施例示意圖(第二計時電路108與下橋控制電路103)。請參閱圖8,同時對照圖1B與圖4,第二計時電路108用以產生斜坡訊號VC5,下橋控制電路103用以產生訊號S5和下橋切換訊號SL。FIG. 8 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 8 shows a schematic diagram of a specific embodiment of the second timing circuit and the lower bridge control circuit (the
第二計時電路108中,訊號S4的下降沿通過邏輯電路281、280(正反器)、292控制開關291不導通,以致能電流源293對電容器290充電,以產生斜坡訊號VC5的上升斜坡,訊號S2則通過邏輯電路282、280、 292控制開關291導通,以重置電容器290。詳言之,正反器280根據訊號S4的下降沿而產生訊號SC5,訊號S2的致能使訊號SC5重置,訊號SC5的致能將使電容器290開始其充電週期。電流源293的電流和電容器290的電容所確定的時間常數,相關於功率變壓器10的去磁期間TDS,換言之,這使得下橋功率開關40的導通期間相關於功率變壓器10之去磁期間。當斜坡訊號VC5的位準高於閾值VT5A時,比較器297生成訊號S56。當斜坡訊號VC5的位準高於閾值VT5B時,比較器295將訊號S5重置。其中閾值VT5B的位準高於閾值VT5A的位準。如圖4所示,閾值VT5B及VT5A的差值與斜坡訊號VC5的上升斜率,決定了訊號S56的脈波寬度T5TH,亦即對應於前述的輕載閾值時段,以及訊號S5與S6的重疊時段T5TH。In the
下橋控制電路103中,訊號SC5的致能通過正反器285使訊號S5致能,訊號S5和訊號S1經由或閘286和下橋開關驅動器288產生下橋切換訊號SL。In the lower
圖9顯示本發明之一次側控制電路的一具體實施例,具體而言,圖9顯示了延遲訊號電路與第三計時電路的具體實施例示意圖(延遲訊號電路109與第三計時電路110)。請參閱圖9,同時對照圖1B與圖4,延遲訊號電路109用以產生延遲訊號S6,第三計時電路110用以產生訊號VlyN。FIG. 9 shows a specific embodiment of the primary side control circuit of the present invention. Specifically, FIG. 9 shows a schematic diagram of a specific embodiment of the delay signal circuit and the third timing circuit (the
延遲訊號電路109中,訊號S56通過正反器350致能訊號S6 。當斜坡訊號VC1放電到低於閾值VT1A時,比較器340將產生訊號S6TV,訊號S6TV用以於以下數種條件下重置訊號S6:(1)如果在S5處於啟用狀態時生成S6TV訊號,則S6TV訊號將立即重置訊號S6。(2)如果在S5已處於禁能狀態時生成S6TV訊號,直到S6TV訊號和VlyN訊號同時致能為止才重置訊號S6。 或者(3)S6TV訊號將啟動計時器330(同時參閱第三計時電路110)。如果無法檢測到準諧振訊號的波谷(VV1- VVN),則一旦計時器330期滿,計時器330將致能訊號VlyN,進而以如(2)的條件重置訊號S6,換言之,計時器330係為逾期定時之用。如圖9所示,介於比較器340與正反器350的重置端之間的電路為實現上述操作的邏輯電路之一實施例。In the
第三計時電路110中,當在S6TV訊號為致能的期間,輔助繞組訊號VNA的波形變為負值時,運算放大器310,電阻器316和鏡像電晶體311、312、315耦合至輔助繞組相關訊號VAUX以產生訊號VNEG,用以示意輔助繞組訊號VNA為負值,其中正反器320用以根據前述方式產生訊號VNEG,訊號S5用以重置訊號VNEG。當輔助繞組相關訊號VAUX高於一正閾值(如0.1V)並且訊號VNEG為致能時,比較器325將產生訊號VlyN,其中訊號VlyN示意輔助繞組訊號VNA的第N個波谷。需說明的是,在如圖3的實施例中,導通下橋功率開關40較佳的時點為對齊輔助繞組訊號VNA的波峰(對應於VHB的波谷),因此,在一實施例中,可於第三計時電路110中,例如但不限於在產生訊號VNEG的訊號路徑上,加上適當的延遲電路,用以將訊號VNEG致能的時間點延遲例如二分之一準諧振週期TQV,而使導通下橋功率開關40的時點為對齊輔助繞組訊號VNA的波峰,以達成較佳之功效。In the
在一實施例中,第三計時電路110還包括狀態電路360,用以閂鎖比較器325的比較結果。In one embodiment, the
圖10顯示本發明之一次側控制電路的一具體實施例,具體而言,圖10顯示了輸出位準感測電路的具體實施例示意圖(輸出位準感測電路104)。請參閱圖10,同時對照圖1B、圖4與圖5,輸出位準感測電路104用以產生相關於輸出電源Po之位準的放電電流ID,同時也用以產生叢發訊號BST。電流源425用以決定放電電流ID的最大值,電流源435用以決定放電電流ID的最小值。當回授訊號VCOM低於閾值VTH1時(即對應於前述輸出電源Po低於延遲閾值),運算放大器410、420,電阻器416和鏡像電晶體411、412、415、421、422、431、432所形成的電流控制子電路,會隨著回授訊號VCOM降低而減小放電電流ID的值,這會使斜坡訊號VC1的下降斜率降低,進而延長了前述的延遲期間。FIG. 10 shows a specific embodiment of the primary-side control circuit of the present invention. Specifically, FIG. 10 shows a schematic diagram of a specific embodiment of the output level sensing circuit (the output level sensing circuit 104 ). Please refer to FIG. 10 , and compare FIGS. 1B , 4 and 5 , the output
此外,當回授訊號VCOM低於閾值VTH2(即對應於前述輸出電源Po低於叢發閾值),比較器430就產生叢發訊號BST,在一實施例中,比較器430可配置為具有遲滯電壓的比較器。In addition, when the feedback signal VCOM is lower than the threshold VTH2 (that is, corresponding to the aforementioned output power Po is lower than the burst threshold), the
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。所說明之各個實施例,並不限於單獨應用,亦可以組合應用,舉例而言,兩個或以上之實施例可以組合運用,而一實施例中之部分組成亦可用以取代另一實施例中對應之組成部件。此外,在本發明之相同精神下,熟悉本技術者可以思及各種等效變化以及各種組合,舉例而言,本發明所稱「根據某訊號進行處理或運算或產生某輸出結果」,不限於根據該訊號的本身,亦包含於必要時,將該訊號進行電壓電流轉換、電流電壓轉換、及/或比例轉換等,之後根據轉換後的訊號進行處理或運算產生某輸出結果。由此可知,在本發明之相同精神下,熟悉本技術者可以思及各種等效變化以及各種組合,其組合方式甚多,在此不一一列舉說明。因此,本發明的範圍應涵蓋上述及其他所有等效變化。The present invention has been described above with respect to the preferred embodiments, but the above-mentioned descriptions are only intended to make it easy for those skilled in the art to understand the content of the present invention, and are not intended to limit the scope of rights of the present invention. The described embodiments are not limited to be used alone, but can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace those in another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. According to the signal itself, when necessary, the signal is subjected to voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion, etc., and then processed or calculated according to the converted signal to generate an output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed and described here. Accordingly, the scope of the present invention should cover the above and all other equivalent changes.
10:功率變壓器 100:一次側控制電路 101:脈寬調變電路 102:上橋驅動電路 103:下橋控制電路 104:輸出位準感測電路 105:第一計時電路 106:SSW脈波產生電路 107, 107’:空滯時間產生電路 108:第二計時電路 109:延遲訊號電路 110:第三計時電路 120:時序控制電路 1001:諧振半橋返馳電源供應器 20:諧振電容器 200:二次側控制電路 210, 220:開關 230:電容器 231, 232, 260:比較器 245:電流源 250:電容器 262, 263:電阻器 265:電晶體 271:脈波產生器 275:上橋開關驅動器 277:自舉電容器 279:自舉二極體 281, 282, 292:邏輯電路 291:開關 293:電流源 290:電容器 280:正反器 285:正反器 286:或閘 288:下橋開關驅動器 297:比較器 30:上橋功率開關 300:半橋功率級電路 310:運算放大器 316:電阻器 311, 312, 315:鏡像電晶體 320:正反器 330:定時器 325, 340:比較器 350:正反器 40:下橋功率開關 410, 420:運算放大器 411, 412, 415, 421, 422, 431, 432:鏡像電晶體 430:比較器 416:電阻器 51, 52, 60:電阻器 70:同步整流開關 90:光耦合器 BST:叢發訊號 HB:相位節點 HGND:自舉接地點 ID:放電電流 IM:感磁電流 Io:輸出電流 IP:一次側開關電流 IS:二次側開關電流 n, m:匝數比 NA:輔助繞組 NP:一次側繞組 NS:二次側繞組 Po:輸出電源 PRES:諧振切換脈波 PSSW:柔性切換脈波 S1, S2, S3, S4, S5, S6, S56, S6TV:訊號 SG:驅動訊號 SH:上橋切換訊號 SL:下橋切換訊號 TDLY:延遲期間 TDS:去磁期間 TQV:準諧振週期 TSL, TW:致能期間 TRH, TRL:空滯時間 TS6:脈波寬度 T5TH, TS6A, TSLA, TSLB, TV:時段 VAUX:輔助繞組相關訊號 VC1, VC5:斜坡訊號 VCS:電流檢測訊號 VFB, VCOM, VCOM’:回授訊號 VHB:相位節點電壓 Vin:輸入電源 VlyN:訊號 VNA:輔助繞組訊號 Vo:輸出電壓 VT1A, VT1B, VT5A, VT5B, VTH1, VTH2:閾值 VV1~VVN:波谷10: Power Transformer 100: Primary side control circuit 101: Pulse width modulation circuit 102: Upper bridge drive circuit 103: Lower bridge control circuit 104: Output level sensing circuit 105: The first timing circuit 106: SSW pulse generation circuit 107, 107’: Dead time generation circuit 108: Second timing circuit 109: Delay signal circuit 110: Third timing circuit 120: Sequence control circuit 1001: Resonant Half-Bridge Flyback Power Supply 20: Resonant capacitor 200: Secondary side control circuit 210, 220: switch 230: Capacitor 231, 232, 260: Comparator 245: Current source 250: Capacitor 262, 263: Resistors 265: Transistor 271: Pulse Generator 275: High-Side Switch Driver 277: Bootstrap capacitor 279: Bootstrap Diode 281, 282, 292: Logic circuits 291: switch 293: Current Source 290: Capacitor 280: Flip-flop 285: Flip-flop 286: or gate 288: Lower Bridge Switch Driver 297: Comparator 30: Upper bridge power switch 300: Half-bridge power stage circuit 310: Operational Amplifier 316: Resistor 311, 312, 315: Mirror transistors 320: Flip-flop 330: Timer 325, 340: Comparator 350: Flip-flop 40: Lower bridge power switch 410, 420: Operational Amplifiers 411, 412, 415, 421, 422, 431, 432: Mirrored transistors 430: Comparator 416: Resistor 51, 52, 60: Resistors 70: Synchronous rectification switch 90: Optocoupler BST: burst signal HB: Phase Node HGND: Bootstrap ground point ID: discharge current IM: Inductive current Io: output current IP: Primary side switch current IS: Secondary side switching current n, m: turns ratio NA: Auxiliary winding NP: Primary winding NS: Secondary winding Po: output power PRES: Resonant switching pulse PSSW: Flexible Switching Pulse S1, S2, S3, S4, S5, S6, S56, S6TV: Signal SG: drive signal SH: Upper bridge switching signal SL: Lower bridge switching signal TDLY: Delay period TDS: During demagnetization TQV: Quasi-resonant period TSL, TW: Enable period TRH, TRL: dead time TS6: Pulse width T5TH, TS6A, TSLA, TSLB, TV: Period VAUX: Auxiliary winding related signal VC1, VC5: Ramp signal VCS: Current detection signal VFB, VCOM, VCOM’: Feedback signal VHB: phase node voltage Vin: input power VlyN: Signal VNA: Auxiliary winding signal Vo: output voltage VT1A, VT1B, VT5A, VT5B, VTH1, VTH2: Threshold VV1~VVN: Valley
圖1A顯示根據本發明之諧振半橋返馳電源供應器的一實施例示意圖。FIG. 1A shows a schematic diagram of an embodiment of a resonant half-bridge flyback power supply according to the present invention.
圖1B顯示根據本發明之諧振半橋返馳電源供應器的一具體實施例示意圖。FIG. 1B shows a schematic diagram of a specific embodiment of a resonant half-bridge flyback power supply according to the present invention.
圖2顯示對應於本發明之圖1A所示的實施例的波形示意圖。FIG. 2 shows a waveform diagram corresponding to the embodiment shown in FIG. 1A of the present invention.
圖3顯示根據本發明之一實施例的波形示意圖。FIG. 3 shows a schematic diagram of waveforms according to an embodiment of the present invention.
圖4顯示根據本發明之一實施例的狀態操作波形示意圖。FIG. 4 shows a schematic diagram of a state operation waveform according to an embodiment of the present invention.
圖5顯示了本發明之一次側控制電路中,第一計時電路與SSW(柔性切換)脈波產生電路的具體實施例示意圖。FIG. 5 shows a schematic diagram of a specific embodiment of the first timing circuit and the SSW (flexible switching) pulse wave generating circuit in the primary side control circuit of the present invention.
圖6顯示本發明之一次側控制電路中,空滯時間產生電路的具體實施例示意圖。FIG. 6 shows a schematic diagram of a specific embodiment of the dead time generating circuit in the primary side control circuit of the present invention.
圖7顯示本發明之一次側控制電路中,脈寬調變電路與上橋驅動電路的具體實施例示意圖。FIG. 7 shows a schematic diagram of a specific embodiment of the pulse width modulation circuit and the upper bridge driving circuit in the primary side control circuit of the present invention.
圖8顯示本發明之一次側控制電路中,第二計時電路與下橋控制電路的具體實施例示意圖。FIG. 8 shows a schematic diagram of a specific embodiment of the second timing circuit and the lower bridge control circuit in the primary side control circuit of the present invention.
圖9顯示本發明之一次側控制電路中,延遲訊號電路與第三計時電路的具體實施例示意圖。FIG. 9 shows a schematic diagram of a specific embodiment of the delay signal circuit and the third timing circuit in the primary side control circuit of the present invention.
圖10顯示本發明之一次側控制電路中,輸出位準感測電路的具體實施例示意圖。FIG. 10 shows a schematic diagram of a specific embodiment of the output level sensing circuit in the primary side control circuit of the present invention.
無none
10:功率變壓器10: Power Transformer
100:一次側控制電路100: Primary side control circuit
1001:諧振半橋返馳電源供應器1001: Resonant Half-Bridge Flyback Power Supply
20:諧振電容器20: Resonant capacitor
200:二次側控制電路200: Secondary side control circuit
30:上橋功率開關30: Upper bridge power switch
300:半橋功率級電路300: Half-bridge power stage circuit
40:下橋功率開關40: Lower bridge power switch
51,52,60:電阻器51, 52, 60: Resistors
70:同步整流開關70: Synchronous rectification switch
90:光耦合器90: Optocoupler
HB:相位節點HB: Phase Node
Io:輸出電流Io: output current
IP:一次側開關電流IP: Primary side switch current
IS:二次側開關電流IS: Secondary side switching current
n,m:匝數比n,m: turns ratio
NA:輔助繞組NA: Auxiliary winding
NP:一次側繞組NP: Primary winding
NS:二次側繞組NS: Secondary winding
Po:輸出電源Po: output power
PRES:諧振切換脈波PRES: Resonant switching pulse
SG:驅動訊號SG: drive signal
SH:上橋切換訊號SH: Upper bridge switching signal
SL:下橋切換訊號SL: Lower bridge switching signal
TDS:去磁期間TDS: During demagnetization
VAUX:輔助繞組相關訊號VAUX: Auxiliary winding related signal
VCS:電流檢測訊號VCS: Current detection signal
VFB:回授訊號VFB: Feedback signal
Vin:輸入電源Vin: input power
VNA:輔助繞組訊號VNA: Auxiliary winding signal
Vo:輸出電壓Vo: output voltage
Claims (30)
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US202063045817P | 2020-06-29 | 2020-06-29 | |
US63/045817 | 2020-06-29 |
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TWI800455B (en) * | 2022-05-20 | 2023-04-21 | 大陸商昂寶電子(上海)有限公司 | Switching power supply control circuit and method |
TWI809716B (en) * | 2022-02-16 | 2023-07-21 | 力林科技股份有限公司 | Asymmetric half-bridge converter |
TWI836980B (en) * | 2023-03-14 | 2024-03-21 | 大陸商昂寶電子(上海)有限公司 | Asymmetric half-bridge flyback converter power supply and its control chip and control method |
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US5353212A (en) * | 1992-04-20 | 1994-10-04 | At&T Bell Laboratories | Zero-voltage switching power converter with ripple current cancellation |
US7518263B2 (en) * | 2004-04-12 | 2009-04-14 | Delta Electronics, Inc. | Time delay control scheme for a power supply with multiple outputs |
JP5048920B2 (en) * | 2004-11-01 | 2012-10-17 | 昌和 牛嶋 | Current resonance type inverter circuit and power control means |
JP2005312284A (en) * | 2005-01-12 | 2005-11-04 | Masakazu Ushijima | Inverter circuit for current resonance discharge tube |
CN102136801B (en) * | 2010-01-21 | 2014-02-19 | 台达电子工业股份有限公司 | Resonant converter and intermittent mode control method thereof |
US8665611B2 (en) * | 2010-04-30 | 2014-03-04 | Infineon Technologies Ag | Controller for a resonant switched-mode power converter |
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ITUB20159679A1 (en) * | 2015-12-21 | 2017-06-21 | St Microelectronics Srl | A POWER CONTROL MODULE FOR AN ELECTRONIC CONVERTER, ITS INTEGRATED CIRCUIT, ELECTRONIC CONVERTER AND PROCEDURE |
US10554136B1 (en) * | 2018-08-03 | 2020-02-04 | Power Integrations, Inc. | Control of secondary switches based on secondary winding voltage in a power converter |
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TWI809716B (en) * | 2022-02-16 | 2023-07-21 | 力林科技股份有限公司 | Asymmetric half-bridge converter |
TWI800455B (en) * | 2022-05-20 | 2023-04-21 | 大陸商昂寶電子(上海)有限公司 | Switching power supply control circuit and method |
TWI836980B (en) * | 2023-03-14 | 2024-03-21 | 大陸商昂寶電子(上海)有限公司 | Asymmetric half-bridge flyback converter power supply and its control chip and control method |
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