TW202043790A - Eye diagram observation device - Google Patents

Eye diagram observation device Download PDF

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TW202043790A
TW202043790A TW108127552A TW108127552A TW202043790A TW 202043790 A TW202043790 A TW 202043790A TW 108127552 A TW108127552 A TW 108127552A TW 108127552 A TW108127552 A TW 108127552A TW 202043790 A TW202043790 A TW 202043790A
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clock
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TW108127552A
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TWI708953B (en
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林有銓
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祥碩科技股份有限公司
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Abstract

Eye diagram observation devices are provided. The eye diagram observation device includes an eye diagram judging circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to the pair of input signals based on a delayed sampling clock. The clock generator includes a voltage to time converter. The voltage to time converter produces a delayed clock based on the voltage value of the input voltage. The clock generator generates a delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and layout area by the voltage to time converter.

Description

眼圖觀測裝置Eye diagram observation device

本發明是有關於一種觀測裝置。且特別是有關於一種用以定義出輸入信號對的眼圖的眼圖觀測裝置。The present invention relates to an observation device. In particular, it relates to an eye diagram observation device for defining the eye diagram of an input signal pair.

眼圖（Eye Diagram）可以用來表示輸入信號對的表現狀態，例如是輸入信號對的同步、輸入信號對的電壓值、輸入信號對的雜訊等狀態。眼圖觀測裝置可以被設置於電子裝置的信號接收端或傳輸介面，藉以對輸入信號對的眼圖進行測量，藉以判斷輸入信號對的狀態。The Eye Diagram can be used to represent the performance status of the input signal pair, such as the synchronization of the input signal pair, the voltage value of the input signal pair, and the noise of the input signal pair. The eye diagram observation device can be installed on the signal receiving end or transmission interface of the electronic device, so as to measure the eye diagram of the input signal pair to determine the state of the input signal pair.

然而，現行的眼圖觀測裝置的取樣時脈的多個不同的延遲大多以多級的環形震盪器來實現。當取樣時脈的多個不同的延遲的需求越多時，環形震盪器所需要的反相器的數量就越多。如此一來，眼圖觀測裝置的佈局面積就越大，消耗功率也就越大。However, the multiple different delays of the sampling clock of the current eye diagram observation device are mostly realized by a multi-stage ring oscillator. When the demand for multiple different delays of the sampling clock increases, the number of inverters required by the ring oscillator increases. In this way, the larger the layout area of the eye diagram observation device, the greater the power consumption.

本發明提供一種節約電源以及減少佈局面積的眼圖觀測裝置。The invention provides an eye diagram observation device that saves power and reduces layout area.

本發明的眼圖觀測裝置用以定義出輸入信號對的眼圖。眼圖觀測裝置包括眼圖判斷電路以及時脈產生器。眼圖判斷電路經配置以接收第一經延遲取樣時脈以及輸入信號對，基於第一經延遲取樣時脈對輸入信號對的第一輸入信號與第二輸入信號進行比較以獲得多個比較結果，並比對上述多個比較結果，藉以獲得對應於輸入信號對的眼圖。時脈產生器耦接於眼圖判斷電路。時脈產生器包括電壓時間轉換器。電壓時間轉換器經配置以依據輸入電壓的電壓值產生經延遲時脈，其中經延遲時脈的延遲時間長度關聯於輸入電壓的電壓值。時脈產生器依據經延遲時脈產生第一經延遲取樣時脈。The eye pattern observation device of the present invention is used to define the eye pattern of the input signal pair. The eye diagram observation device includes an eye diagram judgment circuit and a clock generator. The eye pattern judgment circuit is configured to receive a first delayed sampling clock and an input signal pair, and compare the first input signal and the second input signal of the input signal pair based on the first delayed sampling clock to obtain a plurality of comparison results , And compare the above multiple comparison results to obtain the eye diagram corresponding to the input signal pair. The clock generator is coupled to the eye pattern judgment circuit. The clock generator includes a voltage-to-time converter. The voltage-to-time converter is configured to generate a delayed clock according to the voltage value of the input voltage, wherein the delay time length of the delayed clock is related to the voltage value of the input voltage. The clock generator generates the first delayed sample clock according to the delayed clock.

在本發明的另一眼圖觀測裝置用以定義出輸入信號對的眼圖。眼圖觀測裝置包括眼圖判斷電路以及時脈產生器。眼圖判斷電路經配置以接收參考電壓控制時脈、第一經延遲取樣時脈以及輸入信號對，基於參考電壓控制時脈提供多個參考信號，並且基於第一經延遲取樣時脈使輸入信號對依序與上述多個參考信號進行比較以獲得多個比較結果，並比對上述多個比較結果，藉以獲得對應於輸入信號對的眼圖。時脈產生器耦接於眼圖判斷電路。時脈產生器經配置以產生參考電壓控制時脈以及第一經延遲取樣時脈。時脈產生器包括電壓時間轉換器。電壓時間轉換器經配置以依據輸入電壓的電壓值產生經延遲時脈。經延遲時脈的延遲時間長度關聯於輸入電壓的電壓值。時脈產生器依據經延遲時脈產生第一經延遲取樣時脈。Another eye pattern observation device of the present invention is used to define the eye pattern of the input signal pair. The eye diagram observation device includes an eye diagram judgment circuit and a clock generator. The eye pattern judgment circuit is configured to receive a reference voltage control clock, a first delayed sampling clock, and an input signal pair, provide a plurality of reference signals based on the reference voltage control clock, and make the input signal based on the first delayed sampling clock Comparing the multiple reference signals in sequence to obtain multiple comparison results, and comparing the multiple comparison results to obtain eye patterns corresponding to the input signal pair. The clock generator is coupled to the eye pattern judgment circuit. The clock generator is configured to generate the reference voltage control clock and the first delayed sample clock. The clock generator includes a voltage-to-time converter. The voltage-to-time converter is configured to generate a delayed clock according to the voltage value of the input voltage. The length of the delay time of the delayed clock is related to the voltage value of the input voltage. The clock generator generates the first delayed sample clock according to the delayed clock.

基於上述，眼圖觀測裝置的延遲取樣時脈是由電壓時間轉換器所產生。相較於多級的環形振盪器，電壓時間轉換器會具有較小的電源消耗以及佈局面積。如此一來，節約電源以及較小的佈局面積的眼圖觀測裝置可以被實現。Based on the above, the delayed sampling clock of the eye diagram observation device is generated by the voltage-to-time converter. Compared with a multi-stage ring oscillator, the voltage-to-time converter has smaller power consumption and layout area. In this way, an eye diagram observation device that saves power and has a smaller layout area can be realized.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

請參考圖1，圖1是依據本發明第一實施例繪示的眼圖觀測裝置的框圖。在本實施例中，眼圖觀測裝置100包括眼圖判斷電路110以及時脈產生器120。眼圖判斷電路110接收第一經延遲取樣時脈CLKS1以及輸入信號對。輸入信號對可以是差動信號對。輸入信號對包括第一輸入信號RXP以及第二輸入信號RXN。眼圖判斷電路110基於第一經延遲取樣時脈CLKS1對第一輸入信號RXP以及第二輸入信號RXN進行比較，藉以獲得比較結果CS(1, 1)~CS(1, n)、CS(2, 1)~CS(2, n)。眼圖判斷電路110對比較結果CS(1, 1)~CS(1, n)、CS(2, 1)~CS(2, n)進行比對，藉以獲得對應於輸入信號對的眼圖HEOM。Please refer to FIG. 1, which is a block diagram of an eye diagram observation apparatus according to a first embodiment of the present invention. In this embodiment, the eye pattern observation device 100 includes an eye pattern judgment circuit 110 and a clock generator 120. The eye pattern judgment circuit 110 receives the first delayed sampling clock CLKS1 and the input signal pair. The input signal pair can be a differential signal pair. The input signal pair includes a first input signal RXP and a second input signal RXN. The eye diagram judgment circuit 110 compares the first input signal RXP and the second input signal RXN based on the first delayed sampling clock CLKS1 to obtain the comparison results CS(1, 1)~CS(1, n), CS(2 , 1)~CS(2, n). The eye diagram judgment circuit 110 compares the comparison results CS(1, 1)~CS(1, n), CS(2, 1)~CS(2, n) to obtain the eye diagram HEOM corresponding to the input signal pair .

在本實施例中，時脈產生器120耦接於眼圖判斷電路110。時脈產生器120包括電壓時間轉換器（Voltage to Time Converter，VTC）121。電壓時間轉換器121依據輸入電壓VIN的電壓值產生經延遲時脈CKO。經延遲時脈CKO的延遲時間長度會關聯於輸入電壓VIN的電壓值。時脈產生器120依據經延遲時脈CKO產生第一經延遲取樣時脈CLKS1。In this embodiment, the clock generator 120 is coupled to the eye pattern judgment circuit 110. The clock generator 120 includes a voltage to time converter (VTC) 121. The voltage-to-time converter 121 generates a delayed clock CKO according to the voltage value of the input voltage VIN. The length of the delay time of the delayed clock CKO is related to the voltage value of the input voltage VIN. The clock generator 120 generates the first delayed sample clock CLKS1 according to the delayed clock CKO.

在此值得一提的是，在本實施例中，時脈產生器120會藉由電壓時間轉換器121提供經延遲時脈CKO。相較於多級的環形振盪器，電壓時間轉換器121會具有較小的電源消耗以及佈局面積。如此一來，節約電源以及較小的佈局面積的眼圖觀測裝置100可以被實現。It is worth mentioning that in this embodiment, the clock generator 120 provides the delayed clock CKO through the voltage-to-time converter 121. Compared with a multi-stage ring oscillator, the voltage-to-time converter 121 has smaller power consumption and layout area. In this way, the eye diagram observation device 100 that saves power and has a smaller layout area can be realized.

進一步來說明，請參考圖2，圖2是依據圖1實施例繪示的眼圖觀測裝置的電路示意圖。在本實施例中，除了電壓時間轉換器121，時脈產生器120還包括時脈計數器122以及格式轉換電路123。時脈計數器122接收參考時脈CKS並對參考時脈進行計數以獲得計數值。時脈計數器122可以對參考時脈CKS的上升沿的發生次數或下降沿的發生次數進行計數。在本實施例中，時脈計數器122會被參考時脈CKS的上升沿觸發而遞增計數值。在本實施例中，格式轉換電路123耦接於時脈計數器122以及電壓時間轉換器121。格式轉換電路123接收來自於時脈計數器122所提供的計數值，並依據計數值提供輸入電壓VIN。輸入電壓VIN的電壓值會關聯於計數值。舉例來說，隨著參考時脈CKS的上升沿的數量的增加，時脈計數器122的計數值也會增加，輸入電壓VIN的電壓值也會增加。因此，輸入電壓VIN是漸增電壓。一旦時脈計數器122發生溢位（overflow），則計數值會被重置，輸入電壓VIN的電壓值則會回到初始的預設值。For further explanation, please refer to FIG. 2, which is a schematic circuit diagram of the eye diagram observation device depicted in the embodiment of FIG. 1. In this embodiment, in addition to the voltage-to-time converter 121, the clock generator 120 further includes a clock counter 122 and a format conversion circuit 123. The clock counter 122 receives the reference clock CKS and counts the reference clock to obtain a count value. The clock counter 122 can count the number of occurrences of rising edges or falling edges of the reference clock CKS. In this embodiment, the clock counter 122 is triggered by the rising edge of the reference clock CKS to increment the count value. In this embodiment, the format conversion circuit 123 is coupled to the clock counter 122 and the voltage-to-time converter 121. The format conversion circuit 123 receives the count value provided by the clock counter 122 and provides the input voltage VIN according to the count value. The voltage value of the input voltage VIN is related to the count value. For example, as the number of rising edges of the reference clock CKS increases, the count value of the clock counter 122 also increases, and the voltage value of the input voltage VIN also increases. Therefore, the input voltage VIN is a gradually increasing voltage. Once the clock counter 122 overflows, the count value will be reset, and the voltage value of the input voltage VIN will return to the initial preset value.

在本實施例中，電壓時間轉換器121會依據輸入電壓VIN的電壓值產生經延遲時脈CKO。請參考圖3，圖3是依據本發明一實施例繪示的電壓時間轉換器電路示意圖。在本實施例中，電壓時間轉換器121包括輸入級電路1211、電容C1以及輸出級電路1212。輸入級電路1211會基於外部時脈CKIN將輸入電壓VIN作為轉換電壓VC1。電容C1的第一端耦接於輸入級電路1211以接收轉換電壓VC1。電容C1的第二端耦接於參考低電位（例如是接地）。輸出級電路1212耦接於電容C1的第一端以及輸入級電路1211。輸出級電路1212依據轉換電壓VC1的電壓值以及預設電壓VT的電壓值提供經延遲時脈。In this embodiment, the voltage-to-time converter 121 generates the delayed clock CKO according to the voltage value of the input voltage VIN. Please refer to FIG. 3, which is a schematic diagram of a voltage-to-time converter circuit according to an embodiment of the present invention. In this embodiment, the voltage-to-time converter 121 includes an input stage circuit 1211, a capacitor C1, and an output stage circuit 1212. The input stage circuit 1211 uses the input voltage VIN as the conversion voltage VC1 based on the external clock CKIN. The first end of the capacitor C1 is coupled to the input stage circuit 1211 to receive the converted voltage VC1. The second end of the capacitor C1 is coupled to the reference low potential (for example, ground). The output stage circuit 1212 is coupled to the first end of the capacitor C1 and the input stage circuit 1211. The output stage circuit 1212 provides a delayed clock according to the voltage value of the converted voltage VC1 and the voltage value of the preset voltage VT.

在本實施例中，輸入級電路1211包括反相器N1、第一輸入級電晶體M1、第二輸入級電晶體M2、第三輸入級電晶體M3以及第四輸入級電晶體M4。反相器N1的輸入端用以接收外部時脈CKIN。第一輸入級電晶體M1的第一端用以接收輸入電壓VIN。第一輸入級電晶體M1的第二端耦接於電容C1的第一端。第一輸入級電晶體M1的控制端耦接於反相器N1的輸出端。第二輸入級電晶體M2的第一端耦接於第一輸入級電晶體M1的第二端。第二輸入級電晶體M2的控制端耦接於反相器N1的輸出端。第三輸入級電晶體M3的第一端耦接於第二輸入級電晶體M2的第二端。第三輸入級電晶體M3的第二端耦接於參考低電位。第三輸入級電晶體M3的控制端用以接收偏壓VBN。第三輸入級電晶體M3經配置為電流源。第四輸入級電晶體M4的第一端用以接收參考高電位VDD。第四輸入級電晶體M4的第二端耦接於第二輸入級電晶體M2的第二端。第四輸入級電晶體M4的控制端用以接收外部時脈CKIN。本實施例的第一輸入級電晶體M1可例如是由P型金屬氧化物半導體場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）來實現。本實施例的第二輸入級電晶體M2、第三輸入級電晶體M3以及第四輸入級電晶體M4可例如是由N型MOSFET來實現。In this embodiment, the input stage circuit 1211 includes an inverter N1, a first input stage transistor M1, a second input stage transistor M2, a third input stage transistor M3, and a fourth input stage transistor M4. The input terminal of the inverter N1 is used to receive the external clock CKIN. The first terminal of the first input stage transistor M1 is used to receive the input voltage VIN. The second terminal of the first input stage transistor M1 is coupled to the first terminal of the capacitor C1. The control terminal of the first input stage transistor M1 is coupled to the output terminal of the inverter N1. The first end of the second input stage transistor M2 is coupled to the second end of the first input stage transistor M1. The control terminal of the second input stage transistor M2 is coupled to the output terminal of the inverter N1. The first end of the third input stage transistor M3 is coupled to the second end of the second input stage transistor M2. The second terminal of the third input stage transistor M3 is coupled to the reference low potential. The control terminal of the third input stage transistor M3 is used to receive the bias voltage VBN. The third input stage transistor M3 is configured as a current source. The first terminal of the fourth input stage transistor M4 is used to receive the reference high potential VDD. The second end of the fourth input stage transistor M4 is coupled to the second end of the second input stage transistor M2. The control terminal of the fourth input stage transistor M4 is used to receive the external clock CKIN. The first input-stage transistor M1 of this embodiment can be implemented by, for example, a P-type metal-oxide-semiconductor field-effect transistor (MOSFET). The second input stage transistor M2, the third input stage transistor M3, and the fourth input stage transistor M4 in this embodiment can be implemented by, for example, N-type MOSFETs.

在本實施例中，輸入級電路1211還可以包括緩衝器B1（本發明不限於此）。依據電路設計的需求，緩衝器B1可用以維持或增益輸入電壓VIN。第一輸入級電晶體M1的第一端經由緩衝器B1接收輸入電壓VIN。In this embodiment, the input stage circuit 1211 may also include a buffer B1 (the present invention is not limited to this). According to the requirements of the circuit design, the buffer B1 can be used to maintain or gain the input voltage VIN. The first terminal of the first input stage transistor M1 receives the input voltage VIN via the buffer B1.

在本實施例中，輸出級電路1212包括第一輸出級電晶體M5、第二輸出級電晶體M6、第三輸出級電晶體M7、第四輸出級電晶體M8、第五輸出級電晶體M9以及反相器N2。第一輸出級電晶體M5的第一端用以接收參考高電壓VDD。第一輸出級電晶體M5的控制端用以接收偏壓VBP。第一輸出級電晶體M5經配置為電流源。第二輸出級電晶體M6的第一端耦接於第一輸出級電晶體M5的第二端，第二輸出級電晶體M6的控制端耦接於電容C1的第一端。第三輸出級電晶體M7的第一端耦接於第一輸出級電晶體M5的第二端，第三輸出級電晶體M7的控制端用以接收預設電壓VT。第四輸出級電晶體M8的第一端耦接於第二輸出級電晶體M6的第二端。第四輸出級電晶體M8的第二端耦接於參考低電位。第四輸出級電晶體M8的控制端用以接收外部時脈CKIN。反相器N2的輸入端耦接於第二輸出級電晶體M6的第二端。反相器N2的輸出端被作為電壓時間轉換器的輸出端。第五輸出級電晶體M9的第一端耦接於第三輸出級電晶體M7的第二端。第五輸出級電晶體M9的第二端耦接於參考低電位。第五輸出級電晶體M9的第一端耦接於反相器N2的輸出端。本實施例的第一輸出級電晶體M5、第二輸出級電晶體M6以及第三輸出級電晶體M7可例如是由P型MOSFET來實現。本實施例的第四輸入級電晶體M8以及第五輸入級電晶體M9可例如是由N型MOSFET來實現。In this embodiment, the output stage circuit 1212 includes a first output stage transistor M5, a second output stage transistor M6, a third output stage transistor M7, a fourth output stage transistor M8, and a fifth output stage transistor M9. And inverter N2. The first terminal of the first output stage transistor M5 is used to receive the reference high voltage VDD. The control terminal of the first output stage transistor M5 is used to receive the bias voltage VBP. The first output stage transistor M5 is configured as a current source. The first terminal of the second output stage transistor M6 is coupled to the second terminal of the first output stage transistor M5, and the control terminal of the second output stage transistor M6 is coupled to the first terminal of the capacitor C1. The first terminal of the third output stage transistor M7 is coupled to the second terminal of the first output stage transistor M5, and the control terminal of the third output stage transistor M7 is used to receive the preset voltage VT. The first end of the fourth output stage transistor M8 is coupled to the second end of the second output stage transistor M6. The second terminal of the fourth output stage transistor M8 is coupled to the reference low potential. The control terminal of the fourth output stage transistor M8 is used to receive the external clock CKIN. The input terminal of the inverter N2 is coupled to the second terminal of the second output stage transistor M6. The output terminal of the inverter N2 is used as the output terminal of the voltage-to-time converter. The first end of the fifth output stage transistor M9 is coupled to the second end of the third output stage transistor M7. The second end of the fifth output stage transistor M9 is coupled to the reference low potential. The first terminal of the fifth output stage transistor M9 is coupled to the output terminal of the inverter N2. The first output stage transistor M5, the second output stage transistor M6, and the third output stage transistor M7 in this embodiment can be implemented by, for example, P-type MOSFETs. The fourth input stage transistor M8 and the fifth input stage transistor M9 of this embodiment can be implemented by, for example, N-type MOSFETs.

請同時參考圖3以及圖4，圖4是依據本發明一實施例繪示的波形示意圖。在本實施例中，在時間點t0，外部時脈CKIN被轉態為高邏輯準位。時間點t0之後，第一輸入級電晶體M1被導通以將輸入電壓VIN作為轉換電壓VC1，並將轉換電壓VC1提供到電容C1的第一端。因此，電容C1的第一端的電壓準位被抬升到轉換電壓VC1的電壓準位。第二輸入級電晶體M2被斷開。因此，轉換電壓VC1會被維持。此外，第三輸入級電晶體M3以及第四輸入級電晶體M4被導通。因此，位於第二輸入級電晶體M2的第二端的電壓準位可以被維持。在本實施例中，輸入電壓VIN的電壓值可以被設定為大於參考高電位VDD的電壓值。舉例來說，參考高電位VDD的電壓值為1.05伏特。輸入電壓VIN的電壓值的設定範圍可以被設定為0.8伏特到1.2伏特。Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of waveforms drawn according to an embodiment of the invention. In this embodiment, at time t0, the external clock CKIN is transitioned to a high logic level. After the time point t0, the first input stage transistor M1 is turned on to use the input voltage VIN as the conversion voltage VC1, and the conversion voltage VC1 is provided to the first terminal of the capacitor C1. Therefore, the voltage level of the first terminal of the capacitor C1 is raised to the voltage level of the conversion voltage VC1. The second input stage transistor M2 is disconnected. Therefore, the switching voltage VC1 will be maintained. In addition, the third input stage transistor M3 and the fourth input stage transistor M4 are turned on. Therefore, the voltage level at the second terminal of the second input stage transistor M2 can be maintained. In this embodiment, the voltage value of the input voltage VIN may be set to be greater than the voltage value of the reference high potential VDD. For example, the voltage value of the reference high potential VDD is 1.05 volts. The setting range of the voltage value of the input voltage VIN can be set to 0.8 volts to 1.2 volts.

此時，第三輸出級電晶體M7依據預設電壓VT而被導通。第四輸出級電晶體M8依據高邏輯準位的外部時脈CKIN而被導通。此外，由於轉換電壓VC1被抬升。第二輸出級電晶體M6被斷開。第一輸出級電晶體M5所提供的電流會流經第三輸出級電晶體M7。第二輸出級電晶體M6的第二端的電壓準位為低電壓準位。反相器N2的輸出端的電壓準位被轉態為高電壓準位。因此，經延遲時脈CKO的邏輯準位被轉態為高邏輯準位。At this time, the third output stage transistor M7 is turned on according to the preset voltage VT. The fourth output stage transistor M8 is turned on according to the external clock CKIN of the high logic level. In addition, the switching voltage VC1 is raised. The second output stage transistor M6 is disconnected. The current provided by the first output stage transistor M5 will flow through the third output stage transistor M7. The voltage level of the second terminal of the second output stage transistor M6 is a low voltage level. The voltage level of the output terminal of the inverter N2 is converted to a high voltage level. Therefore, the logic level of the delayed clock CKO is changed to a high logic level.

在時間點t1，外部時脈CKIN由高邏輯準位被轉態為低邏輯準位。在時間點t1之後，第一輸入級電晶體M1以及第四輸入級電晶體M4被斷開，並且第二輸入級電晶體M2被導通。因此，第二輸入級電晶體M2以及第三輸入級電晶體M3會形成具有固定放電電流的放電路徑，並對電容C1的第一端進行放電。因此，轉換電壓VC1的電壓值會被下拉。第四輸出級電晶體M8被斷開。轉換電壓VC1的電壓準位被下拉以導通第二輸出級電晶體M6。然而轉換電壓VC1的電壓準位依舊大於預設電壓VT的情況下，第一輸出級電晶體M5所提供的電流還是會流經第三輸出級電晶體M7。第二輸出級電晶體M6的第二端的電壓準位為低電壓準位。因此，反相器N2的輸出端的電壓準位為高電壓準位。轉換電壓VC1的電壓準位持續被下拉，在時間點t2時轉換電壓VC1的電壓準位小於預設電壓VT。At time t1, the external clock CKIN is changed from a high logic level to a low logic level. After the time point t1, the first input stage transistor M1 and the fourth input stage transistor M4 are turned off, and the second input stage transistor M2 is turned on. Therefore, the second input stage transistor M2 and the third input stage transistor M3 form a discharge path with a fixed discharge current and discharge the first end of the capacitor C1. Therefore, the voltage value of the conversion voltage VC1 will be pulled down. The fourth output stage transistor M8 is disconnected. The voltage level of the converted voltage VC1 is pulled down to turn on the second output stage transistor M6. However, when the voltage level of the converted voltage VC1 is still greater than the preset voltage VT, the current provided by the first output stage transistor M5 will still flow through the third output stage transistor M7. The voltage level of the second terminal of the second output stage transistor M6 is a low voltage level. Therefore, the voltage level of the output terminal of the inverter N2 is a high voltage level. The voltage level of the conversion voltage VC1 is continuously pulled down, and the voltage level of the conversion voltage VC1 is less than the preset voltage VT at the time point t2.

在本實施例中，為了確保第一輸入級電晶體M1在時間點t1被完全地斷開，在第一輸入級電晶體M1的設計上會具有較大的臨界電壓值。第一輸入級電晶體M1的臨界電壓值會大於第一輸出級電晶體M5、第二輸出級電晶體M6以及第三輸出級電晶體M7的臨界電壓值。In this embodiment, in order to ensure that the first input stage transistor M1 is completely disconnected at time t1, the design of the first input stage transistor M1 will have a larger threshold voltage value. The threshold voltage value of the first input stage transistor M1 is greater than the threshold voltage values of the first output stage transistor M5, the second output stage transistor M6, and the third output stage transistor M7.

在時間點t2，第一輸出級電晶體M5所提供的電流會開始流經第二輸出級電晶體M6。第二輸出級電晶體M6的第二端的電壓準位被抬升，進而使反相器N2的輸出端的電壓準位被轉態為低電壓準位。於此同時，第五輸入級電晶體M9被斷開，藉以使第一輸出級電晶體M5所提供的電流能夠完全地流經第二輸出級電晶體M6。在本實施例中，時間點t2與時間點t1之間的時間差即是電壓時間轉換器121對經延遲時脈CKO的下降沿進行延遲的時間長度。At time t2, the current provided by the first output stage transistor M5 will begin to flow through the second output stage transistor M6. The voltage level of the second terminal of the second output stage transistor M6 is raised, so that the voltage level of the output terminal of the inverter N2 is converted to a low voltage level. At the same time, the fifth input stage transistor M9 is disconnected, so that the current provided by the first output stage transistor M5 can completely flow through the second output stage transistor M6. In this embodiment, the time difference between the time point t2 and the time point t1 is the length of time that the voltage-to-time converter 121 delays the falling edge of the delayed clock CKO.

應注意的是，轉換電壓VC1的放電速率會關聯於放電電流以及電容C1的電容值。因此，在具有固定放電電流的前提下，轉換電壓VC1的放電速率是固定的。因此，轉換電壓VC1的電壓值越高，轉換電壓VC1的放電時間越長，電壓時間轉換器121對經延遲時脈CKO的下降沿進行延遲的時間長度也就越長。It should be noted that the discharge rate of the converted voltage VC1 is related to the discharge current and the capacitance value of the capacitor C1. Therefore, under the premise of a fixed discharge current, the discharge rate of the conversion voltage VC1 is fixed. Therefore, the higher the voltage value of the conversion voltage VC1, the longer the discharge time of the conversion voltage VC1, and the longer the time length for the voltage-to-time converter 121 to delay the falling edge of the delayed clock CKO.

請參考圖5，圖5是依據本發明一實施例繪示的經延遲時脈的下降沿的波形示意圖。圖5示出了經延遲時脈CKO的下降沿的延遲可以被調整。Please refer to FIG. 5, which is a schematic diagram of a waveform of the falling edge of a delayed clock according to an embodiment of the present invention. Figure 5 shows that the delay of the falling edge of the delayed clock CKO can be adjusted.

請再回到圖2的實施例，時脈計數器122可以是6位元的計數器（但不以此為限）。因此格式轉換電路123可產生64種不同電壓值的輸入電壓VIN。因此，電壓時間轉換器121可依據時脈計數器122位元數對經延遲時脈CKO進行64種不同的延遲。由此可知，電壓時間轉換器121可以取代多級的環形振盪器。Please return to the embodiment of FIG. 2 again, the clock counter 122 may be a 6-bit counter (but not limited to this). Therefore, the format conversion circuit 123 can generate 64 input voltages VIN with different voltage values. Therefore, the voltage-to-time converter 121 can perform 64 different delays on the delayed clock CKO according to the bit number of the clock counter 122. It can be seen that the voltage-to-time converter 121 can replace a multi-stage ring oscillator.

在本實施例中，時脈產生器120還包括致能時脈產生器124以及邏輯電路125（但本發明不限於此）。在本實施例中，致能時脈產生器124會依據參考時脈CKS以及經延遲時脈CKO產生致能時脈CKEN。邏輯電路125耦接於致能時脈產生器124、電壓時間轉換器121以及眼圖判斷電路110。邏輯電路125對致能時脈CKEN以及經延遲時脈CKO進行邏輯運算以產生第一經延遲取樣時脈CLKS1。In this embodiment, the clock generator 120 further includes an enabling clock generator 124 and a logic circuit 125 (but the invention is not limited to this). In this embodiment, the enabling clock generator 124 generates the enabling clock CKEN according to the reference clock CKS and the delayed clock CKO. The logic circuit 125 is coupled to the enabling clock generator 124, the voltage-to-time converter 121, and the eye pattern judgment circuit 110. The logic circuit 125 performs logic operations on the enabled clock CKEN and the delayed clock CKO to generate the first delayed sample clock CLKS1.

請參考圖2以及圖6，圖6是依據本發明一實施例繪示的致能時脈以及第一經延遲取樣時脈的波形示意圖。在本實施例中，致能時脈產生器124接收參考時脈CKS以及經延遲時脈CKO。經延遲時脈CKO的頻率大於參考時脈CKS的頻率。舉例來說，經延遲時脈CKO的頻率約為1 GHz，參考時脈CKS的頻率約為1 MHz。致能時脈產生器124會對參考時脈CKS進行反相以產生經反相的參考時脈。致能時脈產生器124會經反相的參考時脈與經延遲時脈CKO進行邏輯及（AND）運算以產生致能時脈CKEN。致能時脈CKEN能夠與經延遲時脈CKO的上升沿同步。Please refer to FIG. 2 and FIG. 6. FIG. 6 is a schematic diagram illustrating the waveforms of the enable clock and the first delayed sample clock according to an embodiment of the present invention. In this embodiment, the enabled clock generator 124 receives the reference clock CKS and the delayed clock CKO. The frequency of the delayed clock CKO is greater than the frequency of the reference clock CKS. For example, the frequency of the delayed clock CKO is about 1 GHz, and the frequency of the reference clock CKS is about 1 MHz. The enabled clock generator 124 inverts the reference clock CKS to generate an inverted reference clock. The enabling clock generator 124 performs a logical AND (AND) operation between the inverted reference clock and the delayed clock CKO to generate the enabling clock CKEN. The enabling clock CKEN can be synchronized with the rising edge of the delayed clock CKO.

在本實施例中，邏輯電路125至少包括及邏輯閘A1。及邏輯閘A1的第一輸入端用以接收經延遲時脈CKO。及邏輯閘A1的第二輸入端用以接收致能時脈CKEN。及邏輯閘A1會致能時脈CKEN以及經延遲時脈CKO進行邏輯及（AND）運算以產生第一經延遲取樣時脈CLKS1。In this embodiment, the logic circuit 125 at least includes an AND logic gate A1. The first input terminal of the AND logic gate A1 is used to receive the delayed clock CKO. The second input terminal of the and logic gate A1 is used to receive the enable clock CKEN. The AND logic gate A1 will enable the clock CKEN and the delayed clock CKO to perform an AND operation to generate the first delayed sampling clock CLKS1.

在此值得一提的是，舉例來說，時脈計數器122會被參考時脈CKS的上升沿觸發而遞增計數值。格式轉換電路123會依據計數值以產生輸入電壓VIN。因此格式轉換電路123在時間點t3例如是依據參考時脈CKS的上升沿被觸發以產生輸入電壓VIN。因此，當參考時脈CKS處於高邏輯準位時，輸入電壓VIN的電壓準位可能還沒有達到預期的電壓準位。當參考時脈CKS處於低邏輯準位時，輸入電壓VIN的電壓準位已經達到預期的電壓準位（時間點t4）。由此可知，如果在時間點t3與時間點t4之間的時間區間進行取樣，不穩定的輸入電壓VIN會使經延遲時脈CKO發生不穩定的延遲。本實施例的致能時脈CKEN以及第一經延遲取樣時脈CLKS1在參考時脈CKS處於高邏輯準位時被維持在低邏輯準位。如此一來，眼圖判斷電路110會被確保在輸入電壓VIN處於穩定的電壓準位的時間區間內，基於第一經延遲取樣時脈CLKS1所經歷的多個延遲對第一輸入信號RXP與第二輸入信號RXN進行比較，藉以獲得比較結果。It is worth mentioning here that, for example, the clock counter 122 is triggered by the rising edge of the reference clock CKS to increment the count value. The format conversion circuit 123 generates the input voltage VIN according to the count value. Therefore, the format conversion circuit 123 is triggered to generate the input voltage VIN at the time point t3, for example, according to the rising edge of the reference clock CKS. Therefore, when the reference clock CKS is at a high logic level, the voltage level of the input voltage VIN may not reach the expected voltage level. When the reference clock CKS is at a low logic level, the voltage level of the input voltage VIN has reached the expected voltage level (time t4). It can be seen from this that if sampling is performed in the time interval between the time point t3 and the time point t4, the unstable input voltage VIN will cause an unstable delay of the delayed clock CKO. The enabling clock CKEN and the first delayed sampling clock CLKS1 of this embodiment are maintained at the low logic level when the reference clock CKS is at the high logic level. In this way, the eye pattern judgment circuit 110 is guaranteed to compare the first input signal RXP and the first input signal RXP based on the multiple delays experienced by the first delayed sampling clock CLKS1 during the time interval when the input voltage VIN is at a stable voltage level. The two input signals RXN are compared to obtain the comparison result.

請回到圖2，時脈產生器120還可以包括外部時脈延遲電路126（但本發明不限於此）。外部時脈延遲電路126可以被控制以對外部時脈CKIN的產生時間進行延遲（或，調整），藉以調整第一經延遲取樣時脈CLKS1與輸入信號的相對時間，藉以調整眼圖的水平位置。Please return to FIG. 2, the clock generator 120 may also include an external clock delay circuit 126 (but the invention is not limited to this). The external clock delay circuit 126 can be controlled to delay (or adjust) the generation time of the external clock CKIN, thereby adjusting the relative time between the first delayed sampling clock CLKS1 and the input signal, thereby adjusting the horizontal position of the eye pattern .

在本實施例中，眼圖判斷電路110包括第一計數值產生器111、第二計數值產生器112、邏輯電路113以及反相器114。第一計數值產生器111耦接於時脈產生器120。第一計數值產生器111基於第一經延遲取樣時脈CLKS1在第一輸入信號RXP的電壓準位等於第二輸入信號RXN的電壓準位時獲得比較結果CS(1, 1)~CS(1, n)、CS(2, 1)~CS(2, n)的第一比較結果CS(1, 1)~CS(1, n)，並對各個第一比較結果CS(1, 1)~CS(1, n)的發生次數進行計數，藉以產生對應於各個第一比較結果CS(1, 1)~CS(1, n)的第一計數值CDF(1, 1)~CDF(1, n)。舉例來說，第一計數值CDF(1, 1)對應於第一比較結果CS(1, 1)，第一計數值CDF(1, 2)對應於第一比較結果CS(1, 2)，依此類推。In this embodiment, the eye pattern judgment circuit 110 includes a first count value generator 111, a second count value generator 112, a logic circuit 113, and an inverter 114. The first count value generator 111 is coupled to the clock generator 120. The first count value generator 111 obtains the comparison result CS(1, 1)~CS(1) based on the first delayed sampling clock CLKS1 when the voltage level of the first input signal RXP is equal to the voltage level of the second input signal RXN , n), CS(2, 1)~CS(2, n), the first comparison result CS(1, 1)~CS(1, n), and the first comparison result CS(1, 1)~ The number of occurrences of CS(1, n) is counted to generate the first count value CDF(1, 1)~CDF(1, corresponding to each first comparison result CS(1, 1)~CS(1, n) n). For example, the first count value CDF(1, 1) corresponds to the first comparison result CS(1, 1), the first count value CDF(1, 2) corresponds to the first comparison result CS(1, 2), So on and so forth.

在本實施例中，第二計數值產生器112耦接於時脈產生器120。第二計數值產生器112基於第一經延遲取樣時脈CLKS1在第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值等於一預設值時獲得比較結果CS(1, 1)~CS(1, n)、CS(2, 1)~CS(2, n)的第二比較結果CS(2, 1)~CS(2, n)，並對各個第二比較結果CS(2, 1)~CS(2, n)的發生次數進行計數，藉以產生對應於各個第二比較結果CS(2, 1)~CS(2, n)的第二計數值CDF(2, 1)~CDF(2, n)。舉例來說，第二計數值CDF(2, 1)對應於第二比較結果CS(2, 1)，第二計數值CDF(2, 2)對應於第二比較結果CS(2, 2)，依此類推。In this embodiment, the second count value generator 112 is coupled to the clock generator 120. The second count value generator 112 obtains the comparison result CS() based on the first delayed sampling clock CLKS1 when the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN is equal to a preset value. 1, 1)~CS(1, n), CS(2, 1)~CS(2, n) second comparison result CS(2, 1)~CS(2, n), and compare each second As a result, the occurrence times of CS(2, 1)~CS(2, n) are counted, so as to generate the second count value CDF(2) corresponding to each second comparison result CS(2, 1)~CS(2, n) , 1)~CDF(2, n). For example, the second count value CDF(2, 1) corresponds to the second comparison result CS(2, 1), and the second count value CDF(2, 2) corresponds to the second comparison result CS(2, 2), So on and so forth.

在本實施例中，邏輯電路113耦接於第一計數值產生器111以及第二計數值產生器112。邏輯電路113依據第一計數值CS(1, 1)~CS(1, n)與第二計數值CS(2, 1)~CS(2, n)提供眼圖資訊。反相器114耦接於時脈產生器120。反相器114對第一經延遲取樣時脈CLKS1進行反相以產生第二經延遲取樣時脈CLKS2。In this embodiment, the logic circuit 113 is coupled to the first count value generator 111 and the second count value generator 112. The logic circuit 113 provides eye pattern information according to the first count value CS(1, 1)~CS(1, n) and the second count value CS(2, 1)~CS(2, n). The inverter 114 is coupled to the clock generator 120. The inverter 114 inverts the first delayed sampling clock CLKS1 to generate a second delayed sampling clock CLKS2.

關於第一計數值產生器111，第一計數值產生器111包括第一比較單元1111、第一格式轉換電路1112、第一取樣電路1113、第一計數器1114以及第一計數值輸出器1115。第一比較單元1111耦接於時脈產生器120。在本實施例中，第一比較單元1111接收第一經延遲取樣時脈CLKS1、第一輸入信號RXP以及第二輸入信號RXN，並基於第一經延遲取樣時脈CLKS1在第一輸入信號RXP的電壓準位等於第二輸入信號RXN的電壓準位時獲得比較結果CS(1, 1)~CS(1, n)。舉例來說，在第一經延遲取樣時脈CLKS1經歷第一延遲，第一比較單元1111對第一輸入信號RXP的電壓準位等於第二輸入信號RXN的電壓準位時獲得比較結果CS(1, 1)。在經歷第一延遲之後的第二延遲，第一比較單元1111對第一輸入信號RXP的電壓準位等於第二輸入信號RXN的電壓準位時獲得比較結果CS(1, 2)，依此類推。以比較結果CS(1, 1)為例，比較結果CS(1, 1)會基於第一經延遲取樣時脈CLKS1的多個觸發獲得比較結果CS(1, 1)的多個判斷結果。進一步舉例來說，當第一經延遲取樣時脈CLKS1經歷第一延遲時，如果第一輸入信號RXP的電壓準位明顯不同於（明顯大於或明顯小於）第二輸入信號RXN的電壓準位，比較結果CS(1, 1)會包括多個大致相同的判斷結果。在另一方面，如果第一輸入信號RXP的電壓準位相近於第二輸入信號RXN的電壓準位，則比較結果CS(1, 1)會包括多個不同的判斷結果。Regarding the first count value generator 111, the first count value generator 111 includes a first comparison unit 1111, a first format conversion circuit 1112, a first sampling circuit 1113, a first counter 1114, and a first count value outputter 1115. The first comparison unit 1111 is coupled to the clock generator 120. In this embodiment, the first comparison unit 1111 receives the first delayed sampling clock CLKS1, the first input signal RXP, and the second input signal RXN, and based on the first delayed sampling clock CLKS1 in the first input signal RXP When the voltage level is equal to the voltage level of the second input signal RXN, the comparison result CS(1, 1)~CS(1, n) is obtained. For example, when the first delayed sampling clock CLKS1 undergoes a first delay, the first comparison unit 1111 obtains the comparison result CS(1) when the voltage level of the first input signal RXP is equal to the voltage level of the second input signal RXN. , 1). After the second delay after the first delay, the first comparison unit 1111 obtains the comparison result CS(1, 2) when the voltage level of the first input signal RXP is equal to the voltage level of the second input signal RXN, and so on . Taking the comparison result CS(1, 1) as an example, the comparison result CS(1, 1) will obtain multiple judgment results of the comparison result CS(1, 1) based on multiple triggers of the first delayed sampling clock CLKS1. For further example, when the first delayed sampling clock CLKS1 undergoes the first delay, if the voltage level of the first input signal RXP is significantly different (significantly greater or significantly smaller than) the voltage level of the second input signal RXN, The comparison result CS(1, 1) will include multiple judgment results that are roughly the same. On the other hand, if the voltage level of the first input signal RXP is close to the voltage level of the second input signal RXN, the comparison result CS(1, 1) will include multiple different determination results.

在本實施例中，第一格式轉換電路1112耦接於第一比較單元1111將比較結果CS(1, 1)~CS(1, n)分別轉換為第一比較邏輯結果。第一格式轉換電路1112可以將類比信號格式的比較結果CS(1, 1)~CS(1, n)分別轉換為數位格式的第一比較邏輯結果。也就是，第一格式轉換電路1112可以將類比信號格式的比較結果CS(1, 1)~CS(1, n)的上述多個大致相同的判斷結果分別轉換為數位格式的第一比較邏輯結果。第一取樣電路1113耦接於反相器114以及第一格式轉換電路1112。第一取樣電路1113基於第二經延遲取樣時脈CLKS2對第一比較邏輯結果進行取樣，藉以提供對應於比較結果CS(1, 1)~CS(1, n)的第一取樣結果。第一取樣電路1113是依據第二經延遲取樣時脈CLKS2的多個上升沿提供第一取樣結果。也就是說，第一計數值產生器111是基於第一經延遲取樣時脈CLKS1所經歷的多個延遲依序獲得比較結果CS(1, 1)~CS(1, n)，並對應於上述多個延遲的多個下降沿依序提供關聯於比較結果CS(1, 1)~CS(1, n)的第一取樣結果。在本實施例中，第一取樣電路1113可以至少包括及邏輯閘A2。及邏輯閘A2的第一輸入端接於第一格式轉換電路1112。及邏輯閘A2的第二輸入端接於反相器114的輸出端。及邏輯閘A2的輸出端用以提供對應於第一比較結果CS(1, 1)~CS(1, n)的第一取樣結果。In this embodiment, the first format conversion circuit 1112 is coupled to the first comparison unit 1111 to convert the comparison results CS(1, 1)~CS(1, n) into first comparison logic results, respectively. The first format conversion circuit 1112 can convert the comparison results CS(1, 1)~CS(1, n) of the analog signal format into the first comparison logic result in the digital format, respectively. That is, the first format conversion circuit 1112 can convert the above-mentioned multiple substantially the same determination results of the analog signal format comparison results CS(1, 1)~CS(1, n) into the first comparison logic results in the digital format. . The first sampling circuit 1113 is coupled to the inverter 114 and the first format conversion circuit 1112. The first sampling circuit 1113 samples the first comparison logic result based on the second delayed sampling clock CLKS2, so as to provide the first sampling result corresponding to the comparison results CS(1, 1)~CS(1, n). The first sampling circuit 1113 provides the first sampling result according to the multiple rising edges of the second delayed sampling clock CLKS2. That is, the first count value generator 111 sequentially obtains the comparison results CS(1, 1)~CS(1, n) based on the multiple delays experienced by the first delayed sampling clock CLKS1, and corresponds to the above The multiple falling edges of multiple delays sequentially provide the first sampling results associated with the comparison results CS(1, 1)~CS(1, n). In this embodiment, the first sampling circuit 1113 may include at least an AND logic gate A2. The first input terminal of the AND logic gate A2 is connected to the first format conversion circuit 1112. The second input terminal of the AND logic gate A2 is connected to the output terminal of the inverter 114. The output terminal of the AND logic gate A2 is used to provide the first sampling result corresponding to the first comparison result CS(1, 1)~CS(1, n).

第一計數器1114耦接於第一取樣電路1113。第一計數器1114計數第一取樣結果以獲得關聯於第一比較結果CS(1, 1)~CS(1, n)的第一計數值CDF(1, 1)~CDF(1, n)。舉例來說，第一計數器1114會獲得關聯於第一比較結果CS(1, 1)的第一比較邏輯結果的特定邏輯值（例如是邏輯1）的第一計數值CDF(1, 1)，並獲得關聯於第一比較結果CS(1, 2)的第一比較邏輯結果的特定邏輯值（例如是邏輯1）的第一計數值CDF(1, 2)，依此類推。The first counter 1114 is coupled to the first sampling circuit 1113. The first counter 1114 counts the first sampling result to obtain the first count value CDF(1, 1)~CDF(1, n) associated with the first comparison result CS(1, 1)~CS(1, n). For example, the first counter 1114 will obtain the first count value CDF(1, 1) of the specific logic value (for example, logic 1) of the first comparison logic result of the first comparison result CS(1, 1), And obtain the first count value CDF(1, 2) of the specific logic value (for example, logic 1) of the first comparison logic result associated with the first comparison result CS(1, 2), and so on.

第一計數值輸出器1115耦接於第一計數器1114。第一計數值輸出器1115接收第一計數值CDF(1, 1)~CDF(1, n)並反應於第一計數器1114的控制以輸出第一計數值CDF(1, 1)~CDF(1, n)。第一計數值輸出器1115會依序輸出第一計數值CDF(1, 1)~CDF(1, n)。舉例來說，第一計數器1114可提供一控制信號以指示第一計數值輸出器1115依序輸出第一計數值CDF(1, 1)~CDF(1, n)。在本實施例中，控制信號的發生的時間點可以是與致能時脈CKEN的下降沿的時間點一致，因此第一計數值輸出器1115會在致能時脈CKEN的下降沿的時間點輸出第一計數值CDF(1, 1)~CDF(1, n)。在一些實施例中，第一計數值輸出器1115可以由至少一個正反器來實現。在一些實施例中，第一計數值輸出器1115可以由至少一個正反器來實現。The first count value output unit 1115 is coupled to the first counter 1114. The first count value output device 1115 receives the first count value CDF(1, 1)~CDF(1, n) and reacts to the control of the first counter 1114 to output the first count value CDF(1, 1)~CDF(1 , n). The first count value output device 1115 sequentially outputs the first count values CDF(1, 1)~CDF(1, n). For example, the first counter 1114 may provide a control signal to instruct the first count value output device 1115 to sequentially output the first count values CDF(1, 1)~CDF(1, n). In this embodiment, the time point of the occurrence of the control signal may be the same as the time point of the falling edge of the enabling clock CKEN. Therefore, the first count value output device 1115 will be at the time point of the falling edge of the enabling clock CKEN. Output the first count value CDF(1, 1)~CDF(1, n). In some embodiments, the first count value output unit 1115 may be implemented by at least one flip-flop. In some embodiments, the first count value output unit 1115 may be implemented by at least one flip-flop.

關於第二計數值產生器112，第二計數值產生器112包括第二比較單元1121、第二格式轉換電路1122、第二取樣電路1123、第二計數器1124以及第二計數值輸出器1125。第二比較單元1121耦接於時脈產生器。第二比較單元1121接收第一經延遲取樣時脈CLKS1、第一輸入信號RXP以及第二輸入信號RXN，並基於第一經延遲取樣時脈對第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值的絕對值等於預設值時獲得第二比較結果CS(2, 1)~CS(2, n)。在本實施例中，上述的預設值可例如是1毫伏特（mV），但本發明並不限於此。舉例來說，當第一經延遲取樣時脈CLKS1經歷第一延遲時，第二比較單元1121在第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值的絕對值等於預設值時獲得比較結果CS(2, 1)。在第二延遲，第二比較單元1121在第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值的絕對值等於預設值時獲得比較結果CS(2, 2)，依此類推。以比較結果CS(2, 1)為例，比較結果CS(2, 1)會基於第一經延遲取樣時脈CLKS1的多個觸發獲得比較結果CS(2, 1)的多個判斷結果。進一步舉例來說，當第一經延遲取樣時脈CLKS1經歷第一延遲時，如果第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值的絕對值明顯不同於（明顯大於或明顯小於）預設值，比較結果CS(2, 1)會包括多個大致相同的判斷結果。在另一方面，如果第一輸入信號RXP的電壓準位與第二輸入信號RXN的電壓準位的差值的絕對值接近預設值，則比較結果CS(2, 1)會包括多個不同的判斷結果。Regarding the second count value generator 112, the second count value generator 112 includes a second comparison unit 1121, a second format conversion circuit 1122, a second sampling circuit 1123, a second counter 1124, and a second count value outputter 1125. The second comparison unit 1121 is coupled to the clock generator. The second comparison unit 1121 receives the first delayed sampling clock CLKS1, the first input signal RXP, and the second input signal RXN, and based on the first delayed sampling clock voltage level and the second input of the first input signal RXP The second comparison result CS(2, 1)~CS(2, n) is obtained when the absolute value of the difference of the voltage level of the signal RXN is equal to the preset value. In this embodiment, the aforementioned preset value may be, for example, 1 millivolt (mV), but the invention is not limited to this. For example, when the first delayed sampling clock CLKS1 undergoes the first delay, the second comparing unit 1121 is the absolute value of the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN Get the comparison result CS(2, 1) when it is equal to the preset value. In the second delay, the second comparison unit 1121 obtains the comparison result CS(2, 2) when the absolute value of the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN is equal to the preset value ,So on and so forth. Taking the comparison result CS(2, 1) as an example, the comparison result CS(2, 1) will obtain multiple judgment results of the comparison result CS(2, 1) based on multiple triggers of the first delayed sampling clock CLKS1. For further example, when the first delayed sampling clock CLKS1 undergoes the first delay, if the absolute value of the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN is significantly different from ( Obviously greater or less than) the preset value, the comparison result CS(2, 1) will include multiple judgment results that are roughly the same. On the other hand, if the absolute value of the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN is close to the preset value, the comparison result CS(2, 1) will include multiple differences. The result of the judgment.

在本實施例中，第二格式轉換電路1122耦接於該第二比較單元1121將比較結果CS(2, 1)~CS(2, n)分別轉換為第二比較邏輯結果。第二格式轉換電路1122可以將類比信號格式的比較結果CS(2, 1)~CS(2, n)分別轉換為數位格式的第二比較邏輯結果。也就是，第二格式轉換電路1122可以將類比信號格式的比較結果CS(2, 1)~CS(2, n)的判斷結果分別轉換為數位格式的第二比較邏輯結果。第二取樣電路1123耦接於反相器114以及第二格式轉換電路1122。第二取樣電路1123基於第二經延遲取樣時脈CLKS2對第二比較邏輯結果進行取樣，藉以提供對應於比較結果CS(1, 1)~CS(1, n)的第二取樣結果。第二取樣電路1123是依據第二經延遲取樣時脈CLKS2的上升沿提供第二取樣結果。也就是說，第二計數值產生器112是在第一經延遲取樣時脈CLKS1的下降沿獲得比較結果CS(2, 1)~CS(2, n)，並基於第一經延遲取樣時脈CLKS1所經歷的多個延遲的多個下降沿提供關聯於比較結果CS(2, 1)~CS(2, n)的第二取樣結果。在本實施例中，第二取樣電路1123可以至少包括及邏輯閘A3。及邏輯閘A3的第一輸入端接於第二格式轉換電路1122。及邏輯閘A3的第二輸入端接於反相器114的輸出端。及邏輯閘A3的輸出端用以提供對應於第二比較結果CS(2, 1)~CS(2, n)的第二取樣結果。In this embodiment, the second format conversion circuit 1122 is coupled to the second comparison unit 1121 to convert the comparison results CS(2, 1)~CS(2, n) into second comparison logic results, respectively. The second format conversion circuit 1122 can convert the comparison results CS(2, 1)~CS(2, n) of the analog signal format into the second comparison logic results in the digital format, respectively. That is, the second format conversion circuit 1122 can convert the judgment results of the comparison results CS(2, 1) to CS(2, n) of the analog signal format into the second comparison logic results in the digital format, respectively. The second sampling circuit 1123 is coupled to the inverter 114 and the second format conversion circuit 1122. The second sampling circuit 1123 samples the second comparison logic result based on the second delayed sampling clock CLKS2, so as to provide the second sampling result corresponding to the comparison result CS(1, 1)~CS(1, n). The second sampling circuit 1123 provides the second sampling result according to the rising edge of the second delayed sampling clock CLKS2. That is, the second count value generator 112 obtains the comparison results CS(2, 1)~CS(2, n) at the falling edge of the first delayed sampling clock CLKS1, and is based on the first delayed sampling clock The multiple falling edges of the multiple delays experienced by CLKS1 provide the second sampling result related to the comparison results CS(2, 1)~CS(2, n). In this embodiment, the second sampling circuit 1123 may at least include an AND logic gate A3. The first input terminal of the AND logic gate A3 is connected to the second format conversion circuit 1122. The second input terminal of the AND logic gate A3 is connected to the output terminal of the inverter 114. The output terminal of the logic gate A3 is used to provide the second sampling result corresponding to the second comparison result CS(2, 1)~CS(2, n).

第二計數器1124耦接於第二取樣電路1123。第二計數器1124計數第二取樣結果以獲得關聯於第二比較結果CS(2, 1)~CS(2, n)的第二計數值CDF(2, 1)~CDF(2, n)。舉例來說，第二計數器1124會獲得關聯於第二比較結果CS(2, 1)的第二比較邏輯結果的特定邏輯值（例如是邏輯1）的第二計數值CDF(2, 1)，並獲得關聯於第二比較結果CS(2, 2)的第二比較邏輯結果的特定邏輯值（例如是邏輯1）的第二計數值CDF(2, 2)，依此類推。The second counter 1124 is coupled to the second sampling circuit 1123. The second counter 1124 counts the second sampling result to obtain the second count value CDF(2, 1)~CDF(2, n) associated with the second comparison result CS(2, 1)~CS(2, n). For example, the second counter 1124 will obtain the second count value CDF(2, 1) of the specific logic value (for example, logic 1) of the second comparison logic result of the second comparison result CS(2, 1), And obtain the second count value CDF(2, 2) of the specific logic value (for example, logic 1) of the second comparison logic result associated with the second comparison result CS(2, 2), and so on.

第二計數值輸出器1125耦接於第二計數器1124。第二計數值輸出器1125接收第二計數值CDF(2, 1)~CDF(2, n)並反應於第二計數器1124的控制以輸出第二計數值CDF(2, 1)~CDF(2, n)。第二計數值輸出器1125會依序輸出第二計數值CDF(2, 1)~CDF(2, n)。舉例來說，第二計數器1124可提供一控制信號以指示第二計數值輸出器1125依序輸出第二計數值CDF(2, 1)~CDF(2, n)。在本實施例中，控制信號的發生的時間點可以是與致能時脈CKEN的下降沿的時間點一致，因此第二計數值輸出器1125會在致能時脈CKEN的下降沿的時間點輸出第二計數值CDF(2, 1)~CDF(2, n)。在一些實施例中，第二計數值輸出器1125可以由至少一個正反器來實現。The second count value output unit 1125 is coupled to the second counter 1124. The second count value output device 1125 receives the second count value CDF(2, 1)~CDF(2, n) and reacts to the control of the second counter 1124 to output the second count value CDF(2, 1)~CDF(2 , n). The second count value output device 1125 sequentially outputs the second count values CDF(2, 1)~CDF(2, n). For example, the second counter 1124 may provide a control signal to instruct the second count value output device 1125 to sequentially output the second count values CDF(2, 1)~CDF(2, n). In this embodiment, the time point when the control signal occurs may be the same as the time point of the falling edge of the enable clock CKEN. Therefore, the second count value output unit 1125 will be at the time point of the falling edge of the enable clock CKEN. Output the second count value CDF(2, 1)~CDF(2, n). In some embodiments, the second count value output unit 1125 may be implemented by at least one flip-flop.

關於邏輯電路113，舉例來說，邏輯電路113會在第一延遲依據第一計數值CDF(1, 1)與第二計數值CDF(2, 1)的差異提供對應於第一延遲的眼圖的第一部分資訊。邏輯電路113可以對第一計數值CDF(1, 1)與第二計數值CDF(2, 1)進行邏輯互斥（XOR）運算以提供第一部分資訊。邏輯電路113會在第二延遲依據第一計數值CDF(1, 2)與第二計數值CDF(2, 2)進行邏輯互斥運算以提供第二部分資訊，依此類推，邏輯電路113可以分別在多個延遲（如，基於第一經延遲取樣時脈CLKS1所經歷的多個延遲）提供眼圖的多個部分資訊。本實施例的第一計數值CDF(1, 1)~CDF(1, n)以及第二計數值CDF(2, 1)~CDF(2, n)可以分別被視為累積分佈函數（cumulative distribution function）。而上述的眼圖的多個部分資訊分別可以被視為機率密度函數（probability density function）。Regarding the logic circuit 113, for example, the logic circuit 113 provides an eye pattern corresponding to the first delay according to the difference between the first count value CDF(1, 1) and the second count value CDF(2, 1) at the first delay The first part of the information. The logic circuit 113 may perform a logical mutual exclusion (XOR) operation on the first count value CDF(1, 1) and the second count value CDF(2, 1) to provide the first part of information. The logic circuit 113 performs a logical mutual exclusion operation based on the first count value CDF(1, 2) and the second count value CDF(2, 2) in the second delay to provide the second part of information, and so on, the logic circuit 113 can Provide multiple partial information of the eye diagram at multiple delays (eg, multiple delays based on the first delayed sampling clock CLKS1). The first count value CDF(1, 1)~CDF(1, n) and the second count value CDF(2, 1)~CDF(2, n) in this embodiment can be regarded as cumulative distribution functions (cumulative distribution functions). function). The multiple parts of the above-mentioned eye diagram can be regarded as probability density functions.

眼圖判斷電路110還包括眼圖形成單元115。眼圖形成單元115藉由多個部分資訊整合成對應於輸入信號對的一維眼圖HEOM。在一些實施例中，眼圖形成單元115可配置於眼圖觀測電路100的外部。本發明並不以眼圖判斷電路包括眼圖形成單元為限。The eye pattern judgment circuit 110 further includes an eye pattern forming unit 115. The eye pattern forming unit 115 integrates a plurality of partial information into a one-dimensional eye pattern HEOM corresponding to the input signal pair. In some embodiments, the eye pattern forming unit 115 may be configured outside the eye pattern observation circuit 100. The present invention is not limited to the eye pattern judgment circuit including the eye pattern forming unit.

請同時參考圖2以及圖7，圖7是依據本發明第一實施例所繪示的眼圖。在本實施例中，在一些延遲中，當輸入信號對的第一輸入信號RXP的電壓準位以及第二輸入信號RXN的電壓準位的差值的絕對值為預設值時，第二計數值會明顯大於第一計數值。因此，邏輯電路113會提供非零的部分資訊。在一些延遲中，當輸入信號對的第一輸入信號RXP的電壓準位等於第二輸入信號RXN的電壓準位時，第一計數值會明顯大於第二計數值。因此，邏輯電路113也會提供非零的部分資訊。在其他的延遲中，第一計數值會等於第二計數值。因此，邏輯電路113也會提供零的部分資訊。眼圖形成單元115可形成一維眼圖HEOM。除此之外，眼圖形成單元115還可以依據零的部分資訊的數量來測量眼圖的「開眼」狀況。Please refer to FIG. 2 and FIG. 7 at the same time. FIG. 7 is an eye diagram according to the first embodiment of the present invention. In this embodiment, in some delays, when the absolute value of the difference between the voltage level of the first input signal RXP and the voltage level of the second input signal RXN of the input signal pair is a preset value, the second counts The value will be significantly greater than the first count value. Therefore, the logic circuit 113 provides non-zero partial information. In some delays, when the voltage level of the first input signal RXP of the input signal pair is equal to the voltage level of the second input signal RXN, the first count value will be significantly greater than the second count value. Therefore, the logic circuit 113 also provides non-zero partial information. In other delays, the first count value will be equal to the second count value. Therefore, the logic circuit 113 also provides partial information of zero. The eye pattern forming unit 115 may form a one-dimensional eye pattern HEOM. In addition, the eye pattern forming unit 115 can also measure the "eye opening" condition of the eye pattern according to the amount of zero partial information.

在一些實施例中，依據第一比較單元1111以及第二比較單元1121的電路態樣的需求，眼圖判斷電路110還可以包括時脈格式轉換電路116（本發明並不限於此）。時脈格式轉換電路116會將第一經延遲取樣時脈CLKS1產生第一經延遲取樣時脈CLKS1的互補時脈。並將第一經延遲取樣時脈CLKS1以及互補時脈提供到第一比較單元1111以及第二比較單元1121。In some embodiments, according to the requirements of the circuit configuration of the first comparing unit 1111 and the second comparing unit 1121, the eye pattern determining circuit 110 may further include a clock format conversion circuit 116 (the invention is not limited to this). The clock format conversion circuit 116 generates a complementary clock of the first delayed sample clock CLKS1 from the first delayed sample clock CLKS1. The first delayed sampling clock CLKS1 and the complementary clock are provided to the first comparing unit 1111 and the second comparing unit 1121.

請參考圖8，圖8是依據本發明第二實施例繪示的眼圖觀測裝置的方塊圖。在本實施例中，眼圖觀測裝置200包括眼圖判斷電路210以及時脈產生器220。眼圖判斷電路210接收參考電壓控制時脈CLKVR、第一經延遲取樣時脈CLKS1以及輸入信號對。輸入信號對可以是差動信號對。輸入信號對包括第一輸入信號RXP以及第二輸入信號RXN。眼圖判斷電路210會基於參考電壓控制時脈CLKVR提供多個參考信號VR，並且基於第一經延遲取樣時脈CLKS1使輸入信號對依序與上述多個參考信號VR進行比較以獲得比較結果CS(1, 1)~CS(n, m)。眼圖判斷電路210比對比較結果CS(1, 1)~CS(n, m)，藉以獲得對應於輸入信號對的眼圖2DEOM。Please refer to FIG. 8, which is a block diagram of an eye diagram observation apparatus according to a second embodiment of the present invention. In this embodiment, the eye pattern observation device 200 includes an eye pattern judgment circuit 210 and a clock generator 220. The eye pattern judgment circuit 210 receives the reference voltage control clock CLKVR, the first delayed sampling clock CLKS1, and the input signal pair. The input signal pair can be a differential signal pair. The input signal pair includes a first input signal RXP and a second input signal RXN. The eye pattern judgment circuit 210 provides multiple reference signals VR based on the reference voltage control clock CLKVR, and compares the input signal pair with the multiple reference signals VR sequentially based on the first delayed sampling clock CLKS1 to obtain the comparison result CS (1, 1)~CS(n, m). The eye pattern judgment circuit 210 compares the comparison results CS(1, 1)~CS(n, m) to obtain the eye pattern 2DEOM corresponding to the input signal pair.

在本實施例中，時脈產生器220耦接於眼圖判斷電路210。時脈產生器220產生參考電壓控制時脈CLKVR以及第一經延遲取樣時脈CLKS1。時脈產生器220包括電壓時間轉換器221。電壓時間轉換器221依據輸入電壓VIN的電壓值產生經延遲時脈CKO。經延遲時脈CKO的延遲時間長度會關聯於輸入電壓VIN的電壓值。時脈產生器220依據經延遲時脈CKO產生第一經延遲取樣時脈CLKS1。In this embodiment, the clock generator 220 is coupled to the eye pattern judgment circuit 210. The clock generator 220 generates the reference voltage control clock CLKVR and the first delayed sampling clock CLKS1. The clock generator 220 includes a voltage-to-time converter 221. The voltage-to-time converter 221 generates a delayed clock CKO according to the voltage value of the input voltage VIN. The length of the delay time of the delayed clock CKO is related to the voltage value of the input voltage VIN. The clock generator 220 generates the first delayed sample clock CLKS1 according to the delayed clock CKO.

在此值得一提的是，在本實施例中，時脈產生器220會藉由電壓時間轉換器221提供經延遲時脈CKO。相較於多級的環形振盪器，電壓時間轉換器221會具有較小的電源消耗以及佈局面積。如此一來，節約電源以及較小的佈局面積的眼圖觀測裝置200可以被實現。It is worth mentioning here that, in this embodiment, the clock generator 220 provides the delayed clock CKO through the voltage-to-time converter 221. Compared with a multi-stage ring oscillator, the voltage-to-time converter 221 has smaller power consumption and layout area. In this way, the eye diagram observation device 200 that saves power and has a smaller layout area can be realized.

進一步來說明，請參考圖9，圖9是依據圖8實施例繪示的眼圖觀測裝置的電路示意圖。在本實施例中，除了電壓時間轉換器221，時脈產生器220還包括時脈計數器222以及格式轉換電路223。電壓時間轉換器221、時脈計數器222以及格式轉換電路223之間的協同操作的實施細節可以由第一實施例獲致足夠的教示，因此恕不在此重述。同理可知，時脈計數器222可以是6位元的計數器（但不以此為限）。因此，電壓時間轉換器221可依據時脈計數器222位元數對經延遲時脈CKO進行64種不同的延遲。由此可知，電壓時間轉換器221可以取代多級的環形振盪器。For further explanation, please refer to FIG. 9. FIG. 9 is a schematic circuit diagram of the eye diagram observation device according to the embodiment of FIG. 8. In this embodiment, in addition to the voltage-to-time converter 221, the clock generator 220 also includes a clock counter 222 and a format conversion circuit 223. The implementation details of the cooperative operation among the voltage-to-time converter 221, the clock counter 222, and the format conversion circuit 223 can be sufficiently taught by the first embodiment, and therefore will not be repeated here. In the same way, the clock counter 222 may be a 6-bit counter (but not limited to this). Therefore, the voltage-to-time converter 221 can perform 64 different delays on the delayed clock CKO according to the bit number of the clock counter 222. It can be seen that the voltage-to-time converter 221 can replace a multi-stage ring oscillator.

而與第一實施例不同的是，時脈計數器222還能夠藉由計數值的溢位產生參考電壓控制時脈CLKVR。也就是說，一旦時脈計數器222發生溢位（overflow），則計數值會被重置，並且參考電壓控制時脈CLKVR的邏輯值會被轉態。舉例來說，時脈計數器222是具有6位元的計數器。參考時脈CKS的頻率約為1 MHz，參考電壓控制時脈CLKVR的頻率約為16 kHz。Unlike the first embodiment, the clock counter 222 can also generate a reference voltage control clock CLKVR through the overflow of the count value. In other words, once the clock counter 222 overflows, the count value will be reset, and the logic value of the reference voltage control clock CLKVR will be changed. For example, the clock counter 222 is a counter with 6 bits. The frequency of the reference clock CKS is about 1 MHz, and the frequency of the reference voltage control clock CLKVR is about 16 kHz.

在本實施例中，時脈產生器還包括致能時脈產生器224以及邏輯電路225（但本發明不限於此）。致能時脈產生器224以及邏輯電路225的實施細節可以由第一實施例獲致足夠的教示，因此恕不在此重述。如此一來，致能時脈CKEN以及第一經延遲取樣時脈CLKS1的波形如圖6所示。In this embodiment, the clock generator further includes an enabling clock generator 224 and a logic circuit 225 (but the invention is not limited to this). The implementation details of the enabling clock generator 224 and the logic circuit 225 can be sufficiently taught by the first embodiment, so they will not be repeated here. In this way, the waveforms of the enabling clock CKEN and the first delayed sampling clock CLKS1 are shown in FIG. 6.

在本實施例中，時脈產生器220還可以包括外部時脈延遲電路226（但本發明不限於此）。外部時脈延遲電路226的實施細節可以由第一實施例獲致足夠的教示，因此恕不在此重述。In this embodiment, the clock generator 220 may also include an external clock delay circuit 226 (but the invention is not limited to this). The implementation details of the external clock delay circuit 226 can be sufficiently taught by the first embodiment, so it will not be repeated here.

在本實施例中，眼圖判斷電路210包括參考信號產生電路211以及比較單元212。參考信號產生電路211耦接於時脈產生器220。參考信號產生電路211接收時脈產生器220所提供的參考電壓控制時脈CLKVR，並且基於參考電壓控制時脈CLKVR產生參考信號。比較單元212耦接於時脈產生器220以及參考信號產生電路211。比較單元212接收輸入信號對以及多個參考信號VR。比較單元212基於第一經延遲取樣時脈CLKS1使輸入信號對依序與多個參考信號VR進行比較以獲得比較結果CS(1, 1)~CS(n, m)。舉例來說，比較單元212會基於第一經延遲取樣時脈CLKS1的第一延遲接收第一輸入信號RXP、第二輸入信號RXN以及多個參考信號VR的第一參考信號。比較單元212會基於第一經延遲取樣時脈CLKS1的第二延遲接收第一輸入信號RXP、第二輸入信號RXN以及多個參考信號VR的第二參考信號。In this embodiment, the eye pattern judgment circuit 210 includes a reference signal generation circuit 211 and a comparison unit 212. The reference signal generating circuit 211 is coupled to the clock generator 220. The reference signal generating circuit 211 receives the reference voltage control clock CLKVR provided by the clock generator 220, and generates a reference signal based on the reference voltage control clock CLKVR. The comparison unit 212 is coupled to the clock generator 220 and the reference signal generation circuit 211. The comparison unit 212 receives the input signal pair and multiple reference signals VR. The comparison unit 212 sequentially compares the input signal pair with a plurality of reference signals VR based on the first delayed sampling clock CLKS1 to obtain a comparison result CS(1, 1)~CS(n, m). For example, the comparison unit 212 receives the first input signal RXP, the second input signal RXN, and the first reference signal of the multiple reference signals VR based on the first delay of the first delayed sampling clock CLKS1. The comparison unit 212 receives the first input signal RXP, the second input signal RXN, and the second reference signal of a plurality of reference signals VR based on the second delay of the first delayed sampling clock CLKS1.

在本實施例中，參考信號產生電路211可以是8位元的參考信號產生電路（但不以此為限）。參考信號產生電路211可基於參考電壓控制時脈CLKVR產生256種不同電壓值的參考信號。舉例來說，參考信號產生電路211在參考電壓控制時脈CLKVR的第一上升沿提供多個參考信號VR的第一參考信號，並將第一參考信號提供到比較單元212。參考信號產生電路211在參考電壓控制時脈CLKVR的第二上升沿提供多個參考信號VR的第二參考信號，並將第二參考信號提供到比較單元212。In this embodiment, the reference signal generating circuit 211 may be an 8-bit reference signal generating circuit (but not limited to this). The reference signal generating circuit 211 can generate 256 reference signals with different voltage values based on the reference voltage control clock CLKVR. For example, the reference signal generating circuit 211 provides a first reference signal of a plurality of reference signals VR at the first rising edge of the reference voltage control clock CLKVR, and provides the first reference signal to the comparison unit 212. The reference signal generating circuit 211 provides a second reference signal of a plurality of reference signals VR at the second rising edge of the reference voltage control clock CLKVR, and provides the second reference signal to the comparison unit 212.

在本實施例中，當比較單元212接收到多個參考信號VR的第一參考信號時，比較單元212會基於第一經延遲取樣時脈CLKS1經歷第一延遲對第一輸入信號RXP的電壓值、第二輸入信號RXN的電壓值與第一參考信號的電壓值進行比較以獲得比較結果CS(1, 1)。比較單元212基於第一經延遲取樣時脈CLKS1所提供的第二延遲對第一輸入信號RXP的電壓值、第二輸入信號RXN的電壓值與第一參考信號的電壓值進行比較以獲得比較結果CS(1, 2)，依此類推。因此，當比較單元212接收到第一參考信號時，會基於第一經延遲取樣時脈CLKS1獲得比較結果CS(1, 1)~CS(1, m)。在本實施例中，比較結果CS(1, 1)~CS(1, m)可以是用以指示第一輸入信號RXP的電壓值、第二輸入信號RXN的電壓值大於第一參考信號時的結果。以比較結果CS(1, 1)為例，比較結果CS(1, 1)會基於第一經延遲取樣時脈CLKS1的多個觸發獲得比較結果CS(1, 1)的多個判斷結果。進一步舉例來說，當第一經延遲取樣時脈CLKS1經歷第一延遲時，如果第一輸入信號RXP的電壓值明顯大於或明顯小於第一參考信號的電壓值，則比較結果CS(1, 1)會包括多個大致相同的判斷結果。在另一方面，如果第一輸入信號RXP的電壓值接近第一參考信號的電壓值，則比較結果CS(1, 1)會包括多個不同的判斷結果。In this embodiment, when the comparison unit 212 receives the first reference signal of the multiple reference signals VR, the comparison unit 212 will compare the voltage value of the first input signal RXP based on the first delayed sampling clock CLKS1 undergoing a first delay. , The voltage value of the second input signal RXN is compared with the voltage value of the first reference signal to obtain the comparison result CS(1, 1). The comparison unit 212 compares the voltage value of the first input signal RXP, the voltage value of the second input signal RXN and the voltage value of the first reference signal based on the second delay provided by the first delayed sampling clock CLKS1 to obtain a comparison result CS(1, 2), and so on. Therefore, when the comparison unit 212 receives the first reference signal, it will obtain the comparison results CS(1, 1)~CS(1, m) based on the first delayed sampling clock CLKS1. In this embodiment, the comparison results CS(1, 1)~CS(1, m) can be used to indicate the voltage value of the first input signal RXP, and the voltage value of the second input signal RXN is greater than the first reference signal. result. Taking the comparison result CS(1, 1) as an example, the comparison result CS(1, 1) will obtain multiple judgment results of the comparison result CS(1, 1) based on multiple triggers of the first delayed sampling clock CLKS1. For further example, when the first delayed sampling clock CLKS1 undergoes the first delay, if the voltage value of the first input signal RXP is significantly larger or significantly smaller than the voltage value of the first reference signal, the comparison result CS(1, 1 ) Will include multiple judgment results that are roughly the same. On the other hand, if the voltage value of the first input signal RXP is close to the voltage value of the first reference signal, the comparison result CS(1, 1) may include a plurality of different determination results.

接下來，當比較單元212接收到多個參考信號VR的第二參考信號時，會基於第一經延遲取樣時脈CLKS1獲得比較結果CS(2, 1)~CS(2, m)。接下來，當比較單元212接收到多個參考信號VR的第三參考信號時，會基於第一經延遲取樣時脈CLKS1獲得比較結果CS(3, 1)~CS(3, m)，依此類推。如此一來，比較單元212能夠獲得比較結果CS(1, 1)~CS(n, m)。Next, when the comparison unit 212 receives the second reference signal of the multiple reference signals VR, it will obtain the comparison result CS(2, 1)~CS(2, m) based on the first delayed sampling clock CLKS1. Next, when the comparison unit 212 receives the third reference signal of the multiple reference signals VR, it will obtain the comparison result CS(3, 1)~CS(3, m) based on the first delayed sampling clock CLKS1, and accordingly analogy. In this way, the comparison unit 212 can obtain the comparison results CS(1, 1)~CS(n, m).

在一些實施例中，多個參考信號VR可以分別是差動信號。比較單元212可以對第一輸入信號RXP的電壓值與多個參考信號VR的第一差動信號進行比較，並且對第二輸入信號RXN的電壓值與多個參考信號VR的第二差動信號進行比較，藉以獲得比較結果CS(1, 1)~CS(n, m)。本發明並不以多個參考信號VR的信號形式與比較方式為限。In some embodiments, the multiple reference signals VR may be differential signals, respectively. The comparing unit 212 may compare the voltage value of the first input signal RXP with the first differential signal of the plurality of reference signals VR, and compare the voltage value of the second input signal RXN with the second differential signal of the plurality of reference signals VR. Perform comparison to obtain the comparison result CS(1, 1)~CS(n, m). The present invention is not limited to the signal form and comparison mode of the multiple reference signals VR.

在本實施例中，眼圖判斷電路還包括格式轉換電路213、反相器214、取樣電路215、計數器216以及計數值輸出器217。格式轉換電路213耦接於比較單元212。格式轉換電路214將比較結果CS(1, 1)~CS(n, m)分別轉換為多個比較邏輯結果。反相器214耦接於時脈產生器。反相器214對第一經延遲取樣時脈CLKS1進行反相以產生第二經延遲取樣時脈CLKS2。取樣電路215耦接於反相器214以及格式轉換電路213。取樣電路215基於第二經延遲取樣時脈CLKS2對多個比較邏輯結果進行取樣，藉以提供多個取樣結果。計數器216耦接於取樣電路215。計數器216計數取樣結果以獲得關聯於多個比較邏輯結果的計數值CDF(1, 1)~CDF(n, m)。計數值輸出器217耦接於計數器216。計數值輸出器217接收計數值CDF(1, 1)~CDF(n, m)並反應於計數器216的控制以輸出計數值CDF(1, 1)~CDF(n, m)。在一些實施例中，計數值輸出器217可以由至少一個正反器來實現。In this embodiment, the eye pattern judgment circuit further includes a format conversion circuit 213, an inverter 214, a sampling circuit 215, a counter 216, and a count value output unit 217. The format conversion circuit 213 is coupled to the comparison unit 212. The format conversion circuit 214 converts the comparison results CS(1, 1)~CS(n, m) into multiple comparison logic results, respectively. The inverter 214 is coupled to the clock generator. The inverter 214 inverts the first delayed sampling clock CLKS1 to generate a second delayed sampling clock CLKS2. The sampling circuit 215 is coupled to the inverter 214 and the format conversion circuit 213. The sampling circuit 215 samples a plurality of comparison logic results based on the second delayed sampling clock CLKS2 to provide a plurality of sampling results. The counter 216 is coupled to the sampling circuit 215. The counter 216 counts the sampling results to obtain the count values CDF(1, 1)~CDF(n, m) associated with the multiple comparison logic results. The count value output unit 217 is coupled to the counter 216. The count value output device 217 receives count values CDF(1, 1)~CDF(n, m) and responds to the control of the counter 216 to output count values CDF(1, 1)~CDF(n, m). In some embodiments, the count value output unit 217 may be implemented by at least one flip-flop.

舉例來說，格式轉換電路213會依據比較結果CS(1, 1)提供對應於比較結果CS(1, 1)的比較邏輯結果。格式轉換電路213可以將類比信號格式的比較結果CS(1, 1)轉換為數位格式的比較邏輯結果。取樣電路215基於第二經延遲取樣時脈CLKS2對對應於比較結果CS(1, 1)的比較邏輯結果進行取樣，藉以提供對應於比較結果CS(1, 1)的第一取樣結果。取樣電路215是依據第二經延遲取樣時脈CLKS2的上升沿提供第一取樣結果。也就是說，眼圖判斷電路是基於第一經延遲取樣時脈CLKS1所經歷的多個延遲依序獲得比較結果CS(1, 1)~CS(1, n)，並對應於第一經延遲取樣時脈CLKS1的多個下降沿依序提供關聯於比較結果CS(1, 1)~CS(1, n)的取樣結果。計數器216計數上述的取樣結果以獲得關聯於比較結果CS(1, 1)的計數值CDF(1, 1)。計數值輸出器217接收計數值CDF(1, 1)並反應於計數器216的控制以輸出計數值CDF(1, 1)。舉例來說，計數器216可提供一控制信號以指示計數值輸出器217輸出計數值CDF(1, 1)。在本實施例中，控制信號的發生的時間點可以是與致能時脈CKEN的下降沿的時間點一致，因此計數值輸出器217會在致能時脈CKEN的下降沿的時間點輸出計數值CDF(1, 1)。同理可推，眼圖判斷電路210可依序獲得關聯於比較結果CS(1, 2)~CS(n, m)的計數值CDF(1, 2)~CDF(n, m)，並依序輸出計數值CDF(1, 2)~CDF(n, m)。For example, the format conversion circuit 213 provides a comparison logic result corresponding to the comparison result CS(1, 1) according to the comparison result CS(1, 1). The format conversion circuit 213 can convert the comparison result CS(1, 1) in the analog signal format into the comparison logic result in the digital format. The sampling circuit 215 samples the comparison logic result corresponding to the comparison result CS(1, 1) based on the second delayed sampling clock CLKS2, so as to provide the first sampling result corresponding to the comparison result CS(1, 1). The sampling circuit 215 provides the first sampling result according to the rising edge of the second delayed sampling clock CLKS2. In other words, the eye diagram judgment circuit obtains the comparison results CS(1, 1)~CS(1, n) sequentially based on the multiple delays experienced by the first delayed sampling clock CLKS1, and corresponds to the first delayed sampling The multiple falling edges of the sampling clock CLKS1 sequentially provide sampling results related to the comparison results CS(1, 1)~CS(1, n). The counter 216 counts the aforementioned sampling results to obtain the count value CDF(1, 1) associated with the comparison result CS(1, 1). The count value output unit 217 receives the count value CDF(1, 1) and responds to the control of the counter 216 to output the count value CDF(1, 1). For example, the counter 216 may provide a control signal to instruct the count value output device 217 to output the count value CDF(1, 1). In this embodiment, the time point when the control signal occurs may be the same as the time point of the falling edge of the enable clock CKEN, so the count value output 217 will output the counter at the time point of the falling edge of the enable clock CKEN. Value CDF(1, 1). In the same way, the eye diagram judgment circuit 210 can sequentially obtain the count values CDF(1, 2)~CDF(n, m) associated with the comparison results CS(1, 2)~CS(n, m), and follow Sequence output count value CDF(1, 2)~CDF(n, m).

在本實施例中，取樣電路215可以至少包括及邏輯閘A5。及邏輯閘A5的第一輸入端接於格式轉換電路213。及邏輯閘A5的第二輸入端接於反相器214的輸出端。及邏輯閘A5的輸出端用以提供對應於比較結果CS(1, 1)的取樣結果。In this embodiment, the sampling circuit 215 may include at least an AND logic gate A5. The first input terminal of the AND logic gate A5 is connected to the format conversion circuit 213. The second input terminal of the AND logic gate A5 is connected to the output terminal of the inverter 214. The output terminal of the and logic gate A5 is used to provide the sampling result corresponding to the comparison result CS(1, 1).

在本實施例中，眼圖觀測裝置200還用以儲存計數值輸出器217所輸出的計數值CDF(1, 1)~CDF(n, m)。眼圖觀測裝置200可以對計數值CDF(1, 1)~CDF(n, m)進行佈局。眼圖觀測裝置200可以藉由記憶單元來儲存計數值CDF(1, 1)~CDF(n, m)。眼圖觀測裝置200比對計數值CDF(1, 1)~CDF(n, m)，藉以獲得對應於該輸入信號對的眼圖。In this embodiment, the eye diagram observation device 200 is also used to store the count values CDF(1, 1)~CDF(n, m) output by the count value output unit 217. The eye diagram observation device 200 can arrange the count values CDF(1, 1)~CDF(n, m). The eye diagram observation device 200 can store count values CDF(1, 1)~CDF(n, m) through a memory unit. The eye pattern observation device 200 compares the count values CDF(1, 1)~CDF(n, m) to obtain the eye pattern corresponding to the input signal pair.

進一步來說明，請同時參考圖8以及圖10A，圖10A是依據本發明第二實施例所繪示的計數值的佈局示意圖。眼圖觀測裝置200可以對計數值CDF(1, 1)~CDF(n, m)進行佈局。在本實施例中，計數值CDF(1, 1)~CDF(1, m)會被佈局為同一列，藉以表示計數值CDF(1, 1)~CDF(1, m)為依據輸入信號對以及第一參考信號所產生。計數值CDF(2, 1)~CDF(2, m)會被佈局為同一列，藉以表示計數值CDF(2, 1)~CDF(2, m)為依據輸入信號對以及第二參考信號所產生，依此類推。For further explanation, please refer to FIG. 8 and FIG. 10A at the same time. FIG. 10A is a schematic diagram of the layout of the count value according to the second embodiment of the present invention. The eye diagram observation device 200 can arrange the count values CDF(1, 1)~CDF(n, m). In this embodiment, the count values CDF(1, 1)~CDF(1, m) will be arranged in the same column, so as to represent the count values CDF(1, 1)~CDF(1, m) based on the input signal pair And the first reference signal is generated. The count values CDF(2, 1)~CDF(2, m) will be laid out in the same column to indicate that the count values CDF(2, 1)~CDF(2, m) are based on the input signal pair and the second reference signal. Generated, and so on.

在本實施例中，計數值CDF(1, 1)、CDF(2, 1)、…、CDF(n, 1)會被佈局為同一行，藉以表示計數值CDF(1, 1)、CDF(2, 1)、…、CDF(n, 1)為基於第一經延遲取樣時脈CLKS1的第一延遲所產生。計數值CDF(1, 2)、CDF(2, 2)、…、CDF(n, 2)會被佈局為同一行，藉以表示計數值CDF(1, 2)、CDF(2, 2)、…、CDF(n, 2)為基於第一經延遲取樣時脈CLKS1的第二延遲所產生，依此類推。本實施例的計數值CDF(1, 1)~CDF(n, m)可以分別被視為累積分佈函數。以時脈計數器222是6位元的計數器並且參考信號產生電路211是8位元的參考信號產生電路為例，m會等於64，n會等於256。也就是說，佈局是具有256列與64行的陣列。In this embodiment, the count values CDF(1, 1), CDF(2, 1), ..., CDF(n, 1) will be laid out in the same row to represent the count values CDF(1, 1), CDF( 2, 1),..., CDF(n, 1) are generated based on the first delay of the first delayed sampling clock CLKS1. The count values CDF(1, 2), CDF(2, 2),..., CDF(n, 2) will be laid out in the same row to represent the count values CDF(1, 2), CDF(2, 2),... , CDF(n, 2) is generated based on the second delay of the first delayed sampling clock CLKS1, and so on. The count values CDF(1, 1)~CDF(n, m) in this embodiment can be regarded as cumulative distribution functions, respectively. Taking the clock counter 222 as a 6-bit counter and the reference signal generating circuit 211 as an 8-bit reference signal generating circuit as an example, m would be equal to 64 and n would be equal to 256. In other words, the layout is an array with 256 columns and 64 rows.

請同時參考圖8、圖10A以及圖10B，圖10B是依據本發明第二實施例所繪示的眼圖。本實施例的眼圖2DEOM會依據圖10A所示的計數值CDF(1, 1)~CDF(n, m)的佈局被產生。在本實施例中，眼圖觀測裝置200會對計數值CDF(1, 1)以及計數值CDF(2, 1)減法運算以獲得計數值CDF(1, 1)與計數值CDF(2, 1)的差值的絕對值。上述的絕對值可以被視為部分資訊PDF(1, 1)。眼圖觀測裝置200會對計數值CDF(1, 2)以及計數值CDF(2, 2)減法運算以獲得計數值CDF(1, 2)與計數值CDF(2, 2)的差值的絕對值。上述的絕對值可以被視為部分資訊PDF(1, 2)，依此類推。如此一來，眼圖觀測裝置200依據計數值CDF(1, 1)~CDF(n, m)提供部分資訊PDF(1, 1)~PDF(n-1, m)，並依據部分資訊PDF(1, 1)~PDF(n-1, m)產生眼圖2DEOM。本實施例的眼圖2DEOM具有255列與64行的畫素。部分資訊PDF(1, 1)~PDF(n-1, m)分別可以被視為機率密度函數。部分資訊PDF(1, 1)~PDF(n-1, m)分別具有對應於上述的絕對值的表示結果。Please refer to FIG. 8, FIG. 10A and FIG. 10B at the same time. FIG. 10B is an eye diagram according to the second embodiment of the present invention. The eye pattern 2DEOM of this embodiment is generated according to the layout of the count values CDF(1, 1)~CDF(n, m) shown in FIG. 10A. In this embodiment, the eye pattern observation device 200 subtracts the count value CDF(1, 1) and the count value CDF(2, 1) to obtain the count value CDF(1, 1) and the count value CDF(2, 1). ) Is the absolute value of the difference. The above absolute value can be regarded as partial information PDF(1, 1). The eye diagram observation device 200 subtracts the count value CDF(1, 2) and the count value CDF(2, 2) to obtain the absolute value of the difference between the count value CDF(1, 2) and the count value CDF(2, 2) value. The above absolute value can be regarded as partial information PDF(1, 2), and so on. In this way, the eye diagram observation device 200 provides partial information PDF(1, 1)~PDF(n-1, m) according to the count value CDF(1, 1)~CDF(n, m), and according to the partial information PDF( 1, 1)~PDF(n-1, m) produces eye diagram 2DEOM. The eye pattern 2DEOM of this embodiment has 255 columns and 64 rows of pixels. Part of the information PDF(1, 1)~PDF(n-1, m) can be regarded as probability density functions respectively. The partial information PDF(1, 1)~PDF(n-1, m) respectively have the representation results corresponding to the above-mentioned absolute values.

在部分資訊PDF(1, 1)~PDF(n-1, m)中，數值等於0（或接近0）的部分資訊表示對應的畫素上存在輸入信號對的部分波形的機率極低。在部分資訊PDF(1, 1)~PDF(n-1, m)中，數值越大的部分資訊則表示對應的畫素上存在輸入信號對的部分波形的機率越高。如此一來，部分資訊PDF(1, 1)~PDF(n-1, m)的數值可表示出輸入信號對的波形的狀況。也就是說，眼圖觀測裝置200可依據部分資訊PDF(1, 1)~PDF(n-1, m)的結果測量輸入信號對的眼圖。並依據部分資訊PDF(1, 1)~PDF(n-1, m)的結果判斷輸入信號對的狀況。Among the partial information PDF(1, 1)~PDF(n-1, m), the partial information whose value is equal to 0 (or close to 0) indicates that the probability of the partial waveform of the input signal pair on the corresponding pixel is extremely low. Among the partial information PDF(1, 1)~PDF(n-1, m), the greater the value of the partial information, the higher the probability that the partial waveform of the input signal pair exists on the corresponding pixel. In this way, the value of partial information PDF(1, 1)~PDF(n-1, m) can indicate the waveform status of the input signal pair. In other words, the eye diagram observation device 200 can measure the eye diagram of the input signal pair according to the results of the partial information PDF(1, 1)~PDF(n-1, m). And judge the status of the input signal pair based on the results of partial information PDF(1, 1)~PDF(n-1, m).

請回到圖9，在一些實施例中，依據比較單元212的電路態樣的需求，眼圖判斷電路210還可以包括時脈格式轉換電路218（本發明並不限於此）。時脈格式轉換電路218會將第一經延遲取樣時脈CLKS1產生第一經延遲取樣時脈CLKS1的互補時脈。並將第一經延遲取樣時脈CLKS1以及互補時脈提供到比較單元212。Referring back to FIG. 9, in some embodiments, according to the requirements of the circuit configuration of the comparing unit 212, the eye pattern judgment circuit 210 may further include a clock format conversion circuit 218 (the present invention is not limited to this). The clock format conversion circuit 218 generates a complementary clock of the first delayed sample clock CLKS1 from the first delayed sample clock CLKS1. The first delayed sampling clock CLKS1 and the complementary clock are provided to the comparison unit 212.

綜上所述，本發明的眼圖觀測裝置的延遲取樣時脈是由電壓時間轉換器所產生。相較於多級的環形振盪器，電壓時間轉換器會具有較小的電源消耗以及佈局面積。如此一來，節約電源以及較小的佈局面積的眼圖觀測裝置可以被實現。In summary, the delayed sampling clock of the eye diagram observation device of the present invention is generated by the voltage-time converter. Compared with a multi-stage ring oscillator, the voltage-to-time converter has smaller power consumption and layout area. In this way, an eye diagram observation device that saves power and has a smaller layout area can be realized.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100、200:眼圖觀測裝置 110、210:眼圖判斷電路 111:第一計數值產生器 1111:第一比較單元 1112:第一格式轉換電路 1113:第一取樣電路 1114:第一計數器 1115:第一計數值輸出器 112:第二計數值產生器 1121:第二比較單元 1122:第二格式轉換電路 1123:第二取樣電路 1124:第二計數器 1125:第二計數值輸出器 113:邏輯電路 114:反相器 115:眼圖形成單元 116:時脈格式轉換電路 120、220:時脈產生器 121、221:電壓時間轉換器 1211:輸入級電路 1212:輸出級電路 122、222:時脈計數器 123、223:格式轉換電路 124、224:致能時脈產生器 125、225:邏輯電路 126、226:外部時脈延遲電路 211:參考信號產生電路 212:比較單元 213:格式轉換電路 214:反相器 215:取樣電路 216:計數器 217:計數值輸出器 218:時脈格式轉換電路 A1、A2、A3、A4、A5:及邏輯閘 B1:緩衝器 C1:電容 CDF(1,1)~CDF(1,n)、CDF(2,1)~CDF(2,n)、CDF(1,2)~CDF(n,m):計數值 CKEN:致能時脈 CKO:經延遲時脈 CLKS1:第一經延遲取樣時脈 CLKVR:參考電壓控制時脈 CS(1,1)~CS(1,n)、CS(2,1)~CS(2,n)、CS(1,1)~CS(n,m):比較結果 HEOM、2DEOM:眼圖 M1:第一輸入級電晶體 M2:第二輸入級電晶體 M3:第三輸入級電晶體 M4:第四輸入級電晶體 M5:第一輸出級電晶體 M6:第二輸出級電晶體 M7:第三輸出級電晶體 M8:第四輸出級電晶體 M9:第五輸出級電晶體 N1、N2:反相器 PDF(1,1)~PDF(n-1,m):部分資訊 RXN:第二輸入信號 RXP:第一輸入信號 t0、t1、t2、t3、t4、t5、t6:時間點 VBN、VBP:偏壓 VC1:轉換電壓 VDD:參考高電位 VIN:輸入電壓 VR:多個參考信號 VT:預設電壓100, 200: Eye diagram observation device 110, 210: Eye diagram judgment circuit 111: The first count value generator 1111: The first comparison unit 1112: The first format conversion circuit 1113: The first sampling circuit 1114: first counter 1115: The first count value output device 112: The second count value generator 1121: second comparison unit 1122: Second format conversion circuit 1123: Second sampling circuit 1124: second counter 1125: The second count value output device 113: Logic Circuit 114: inverter 115: Eye pattern formation unit 116: Clock format conversion circuit 120, 220: clock generator 121, 221: voltage time converter 1211: input stage circuit 1212: output stage circuit 122, 222: clock counter 123, 223: format conversion circuit 124, 224: enable clock generator 125, 225: logic circuit 126, 226: External clock delay circuit 211: Reference signal generation circuit 212: comparison unit 213: format conversion circuit 214: inverter 215: sampling circuit 216: Counter 217: Count value output device 218: Clock format conversion circuit A1, A2, A3, A4, A5: and logic gate B1: Buffer C1: Capacitance CDF(1,1)~CDF(1,n), CDF(2,1)~CDF(2,n), CDF(1,2)~CDF(n,m): count value CKEN: Enabling Clock CKO: Delayed clock CLKS1: The first delayed sampling clock CLKVR: reference voltage control clock CS(1,1)~CS(1,n), CS(2,1)~CS(2,n), CS(1,1)~CS(n,m): comparison result HEOM, 2DEOM: eye diagram M1: first input stage transistor M2: second input stage transistor M3: third input stage transistor M4: fourth input stage transistor M5: first output stage transistor M6: second output stage transistor M7: The third output stage transistor M8: fourth output stage transistor M9: fifth output stage transistor N1, N2: inverter PDF(1,1)~PDF(n-1,m): some information RXN: second input signal RXP: the first input signal t0, t1, t2, t3, t4, t5, t6: time point VBN, VBP: Bias voltage VC1: Conversion voltage VDD: reference high potential VIN: input voltage VR: multiple reference signals VT: preset voltage

圖1是依據本發明第一實施例繪示的眼圖觀測裝置的方塊圖。 圖2是依據圖1實施例繪示的眼圖觀測裝置的電路示意圖。 圖3是依據本發明一實施例繪示的電壓時間轉換器電路示意圖。 圖4是依據本發明一實施例繪示的波形示意圖。 圖5是依據本發明一實施例繪示的經延遲時脈的波形示意圖。 圖6是依據本發明一實施例繪示的致能時脈以及第一經延遲取樣時脈的波形示意圖。 圖7是依據本發明第一實施例所繪示的眼圖。 圖8是依據本發明第二實施例繪示的眼圖觀測裝置的方塊圖。 圖9是依據圖8實施例繪示的眼圖觀測裝置的電路示意圖。 圖10A是依據本發明第二實施例所繪示的計數值的佈局示意圖。 圖10B是依據本發明第二實施例所繪示的眼圖。Fig. 1 is a block diagram of an eye diagram observation device according to a first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of the eye diagram observation device according to the embodiment of FIG. 1. 3 is a schematic diagram of a voltage-to-time converter circuit according to an embodiment of the invention. FIG. 4 is a schematic diagram of waveforms drawn according to an embodiment of the invention. FIG. 5 is a schematic diagram illustrating a waveform of a delayed clock according to an embodiment of the invention. 6 is a schematic diagram of the waveforms of the enabled clock and the first delayed sample clock according to an embodiment of the present invention. Fig. 7 is an eye diagram according to the first embodiment of the present invention. FIG. 8 is a block diagram of an eye diagram observation device according to a second embodiment of the present invention. FIG. 9 is a schematic circuit diagram of the eye diagram observation device depicted in the embodiment of FIG. 8. FIG. 10A is a schematic diagram of the layout of the count value according to the second embodiment of the present invention. FIG. 10B is an eye diagram drawn according to the second embodiment of the invention.

100:眼圖觀測裝置 100: Eye diagram observation device

110:眼圖判斷電路 110: Eye diagram judgment circuit

120:時脈產生器 120: clock generator

121:電壓時間轉換器 121: voltage time converter

CKO:經延遲時脈 CKO: Delayed clock

CLKS1:第一經延遲取樣時脈 CLKS1: The first delayed sampling clock

CS(1,1)~CS(1,n)、CS(2,1)~CS(2,n):比較結果 CS(1,1)~CS(1,n), CS(2,1)~CS(2,n): comparison result

HEOM:眼圖 HEOM: Eye Diagram

RXN:第二輸入信號 RXN: second input signal

RXP:第一輸入信號 RXP: the first input signal

VIN:輸入電壓 VIN: input voltage

Claims (20)

一種眼圖觀測裝置，用以定義出一輸入信號對的一眼圖，包括： 一眼圖判斷電路，經配置以接收一第一經延遲取樣時脈以及該輸入信號對，基於該第一經延遲取樣時脈對該輸入信號對的一第一輸入信號與一第二輸入信號進行比較以獲得多個比較結果，並比對該些比較結果，藉以獲得對應於該輸入信號對的該眼圖；以及 一時脈產生器，耦接於該眼圖判斷電路，包括： 一電壓時間轉換器，經配置以依據一輸入電壓的電壓值產生一經延遲時脈，其中該經延遲時脈的延遲時間長度關聯於該輸入電壓的電壓值， 其中該時脈產生器依據該經延遲時脈產生該第一經延遲取樣時脈。An eye diagram observation device used to define an eye diagram of an input signal pair, including: An eye pattern judgment circuit configured to receive a first delayed sampling clock and the input signal pair, and perform a first input signal and a second input signal of the input signal pair based on the first delayed sampling clock Compare to obtain a plurality of comparison results, and compare the comparison results to obtain the eye diagram corresponding to the input signal pair; and A clock generator, coupled to the eye diagram judgment circuit, includes: A voltage-to-time converter configured to generate a delayed clock according to the voltage value of an input voltage, wherein the delay time of the delayed clock is related to the voltage value of the input voltage, The clock generator generates the first delayed sample clock according to the delayed clock. 如申請專利範圍第2項所述的眼圖觀測裝置，其中該電壓時間轉換器包括： 一輸入級電路，經配置以基於一外部時脈將該輸入電壓作為一轉換電壓； 一電容，該電容的第一端耦接於該輸入級電路以接收該轉換電壓，該電容的第二端耦接於一參考低電位；以及 一輸出級電路，耦接於該輸入級電路以及該電容的第一端，經配置以依據該轉換電壓的電壓值以及一預設電壓的電壓值提供該經延遲時脈。According to the eye diagram observation device described in item 2 of the scope of patent application, the voltage-time converter includes: An input stage circuit configured to use the input voltage as a conversion voltage based on an external clock; A capacitor, the first end of the capacitor is coupled to the input stage circuit to receive the converted voltage, and the second end of the capacitor is coupled to a reference low potential; and An output stage circuit, coupled to the input stage circuit and the first end of the capacitor, is configured to provide the delayed clock according to the voltage value of the converted voltage and the voltage value of a predetermined voltage. 如申請專利範圍第2項所述的眼圖觀測裝置，其中該輸入級電路包括： 一反相器，該反相器的輸入端用以接收該外部時脈； 一第一輸入級電晶體，該第一輸入級電晶體的第一端用以接收該輸入電壓，該第一輸入級電晶體的第二端耦接於該電容的第一端，該第一輸入級電晶體的控制端耦接於該反相器的輸出端； 一第二輸入級電晶體，該第二輸入級電晶體的第一端耦接於該第一輸入級電晶體的第二端，該第二輸入級電晶體的控制端耦接於該反相器的輸出端； 一第三輸入級電晶體，該第三輸入級電晶體的第一端耦接於該第二輸入級電晶體的第二端，該第三輸入級電晶體的第二端耦接於該參考低電位，該第三輸入級電晶體的控制端用以接收一偏壓，其中該第三輸入級電晶體經配置為一電流源；以及 一第四輸入級電晶體，該第四輸入級電晶體的第一端用以接收一參考高電位，該第四輸入級電晶體的第二端耦接於該第二輸入級電晶體的第二端，該第四輸入級電晶體的控制端用以接收該外部時脈。According to the eye diagram observation device described in item 2 of the scope of patent application, the input stage circuit includes: An inverter, the input terminal of the inverter is used to receive the external clock; A first input stage transistor, the first terminal of the first input stage transistor is used to receive the input voltage, the second terminal of the first input stage transistor is coupled to the first terminal of the capacitor, the first The control terminal of the input stage transistor is coupled to the output terminal of the inverter; A second input stage transistor, the first terminal of the second input stage transistor is coupled to the second terminal of the first input stage transistor, and the control terminal of the second input stage transistor is coupled to the inverter The output terminal of the device; A third input stage transistor, the first end of the third input stage transistor is coupled to the second end of the second input stage transistor, and the second end of the third input stage transistor is coupled to the reference Low potential, the control terminal of the third input stage transistor is used to receive a bias voltage, wherein the third input stage transistor is configured as a current source; and A fourth input stage transistor, the first terminal of the fourth input stage transistor is used to receive a reference high potential, the second terminal of the fourth input stage transistor is coupled to the second input stage transistor The second terminal, the control terminal of the fourth input stage transistor is used to receive the external clock. 如申請專利範圍第2項所述的眼圖觀測裝置，其中該輸出級電路包括： 一第一輸出級電晶體，該第一輸出級電晶體的第一端用以接收一參考高電壓，該第一輸出級電晶體的控制端用以接收一偏壓，其中該第一輸出級電晶體經配置為一電流源； 一第二輸出級電晶體，該第二輸出級電晶體的第一端耦接於該第一輸出級電晶體的第二端，該第二輸出級電晶體的控制端耦接於該電容的第一端； 一第三輸出級電晶體，該第三輸出級電晶體的第一端耦接於該第一輸出級電晶體的第二端，該第三輸出級電晶體的控制端用以接收該預設電壓； 一第四輸出級電晶體，該第四輸出級電晶體的第一端耦接於該第二輸出級電晶體的第二端，該第四輸出級電晶體的第二端耦接於該參考低電位，該第四輸出級電晶體的控制端用以接收該外部時脈； 一反相器，該反相器的輸入端耦接於該第二輸出級電晶體的第二端，該反相器的輸出端被作為該電壓時間轉換器的輸出端；以及 一第五輸出級電晶體，該第五輸出級電晶體的第一端耦接於該第三輸出級電晶體的第二端，該第五輸出級電晶體的第二端耦接於該參考低電位，該第五輸出級電晶體的第一端耦接於耦接於該反相器的輸出端。According to the eye diagram observation device described in item 2 of the scope of patent application, the output stage circuit includes: A first output stage transistor, the first terminal of the first output stage transistor is used to receive a reference high voltage, the control terminal of the first output stage transistor is used to receive a bias voltage, wherein the first output stage The transistor is configured as a current source; A second output stage transistor, the first terminal of the second output stage transistor is coupled to the second terminal of the first output stage transistor, and the control terminal of the second output stage transistor is coupled to the capacitor First end A third output stage transistor, the first terminal of the third output stage transistor is coupled to the second terminal of the first output stage transistor, and the control terminal of the third output stage transistor is used to receive the preset Voltage; A fourth output stage transistor, the first end of the fourth output stage transistor is coupled to the second end of the second output stage transistor, and the second end of the fourth output stage transistor is coupled to the reference Low potential, the control terminal of the fourth output stage transistor is used to receive the external clock; An inverter, the input terminal of the inverter is coupled to the second terminal of the second output stage transistor, and the output terminal of the inverter is used as the output terminal of the voltage-to-time converter; and A fifth output stage transistor, the first end of the fifth output stage transistor is coupled to the second end of the third output stage transistor, and the second end of the fifth output stage transistor is coupled to the reference At a low level, the first terminal of the fifth output stage transistor is coupled to the output terminal coupled to the inverter. 如申請專利範圍第1項所述的眼圖觀測裝置，其中該時脈產生器還包括： 一時脈計數器，經配置以接收一參考時脈，並對該參考時脈進行計數以獲得一計數值；以及 一格式轉換電路，耦接於該時脈計數器以及該電壓時間轉換器，經配置以接收該計數值，並依據該計數值提供該輸入電壓， 其中該輸入電壓的電壓值關聯於該計數值。In the eye diagram observation device described in item 1 of the scope of patent application, the clock generator further includes: A clock counter configured to receive a reference clock and count the reference clock to obtain a count value; and A format conversion circuit, coupled to the clock counter and the voltage-to-time converter, configured to receive the count value and provide the input voltage according to the count value, The voltage value of the input voltage is associated with the count value. 如申請專利範圍第5項所述的眼圖觀測裝置，其中該時脈產生器還包括： 一致能時脈產生器，經配置以依據該參考時脈以及該經延遲時脈產生一致能時脈；以及 一邏輯電路，耦接於該致能時脈產生器、該電壓時間轉換器以及該眼圖判斷電路，經配置以對該致能時脈以及該經延遲時脈進行邏輯運算以產生該第一經延遲取樣時脈。According to the eye diagram observation device described in item 5 of the scope of patent application, the clock generator further includes: A consistent energy clock generator configured to generate a consistent energy clock based on the reference clock and the delayed clock; and A logic circuit, coupled to the enabled clock generator, the voltage-time converter, and the eye diagram judgment circuit, is configured to perform logic operations on the enabled clock and the delayed clock to generate the first The sampling clock is delayed. 如申請專利範圍第1項所述的眼圖觀測裝置，其中該眼圖判斷電路包括： 一第一計數值產生器，耦接於該時脈產生器，經配置以基於該第一經延遲取樣時脈在該第一輸入信號的電壓準位等於該第二輸入信號的電壓準位時獲得該些比較結果的多個第一比較結果，並對該些第一比較結果的發生次數進行計數，藉以產生多個第一計數值； 一第二計數值產生器，耦接於該時脈產生器，經配置以基於該第一經延遲取樣時脈在該第一輸入信號的電壓準位與該第二輸入信號的電壓準位的差值的絕對值等於一預設值時獲得該些比較結果的多個第二比較結果，並對該些第二比較結果的發生次數進行計數，藉以產生多個第二計數值；以及 一邏輯電路，耦接於該第一計數值產生器以及該第二計數值產生器，經配置以依據該些第一計數值與該些第二計數值提供眼圖資訊。According to the eye diagram observation device described in item 1 of the scope of patent application, the eye diagram judgment circuit includes: A first count value generator, coupled to the clock generator, configured to be based on the first delayed sampling clock when the voltage level of the first input signal is equal to the voltage level of the second input signal Obtaining a plurality of first comparison results of the comparison results, and counting the number of occurrences of the first comparison results, so as to generate a plurality of first count values; A second count value generator, coupled to the clock generator, configured to be based on the voltage level of the first input signal and the voltage level of the second input signal based on the first delayed sampling clock When the absolute value of the difference is equal to a preset value, obtain a plurality of second comparison results of the comparison results, and count the occurrence times of the second comparison results to generate a plurality of second count values; and A logic circuit is coupled to the first count value generator and the second count value generator, and is configured to provide eye pattern information according to the first count values and the second count values. 如申請專利範圍第7項所述的眼圖觀測裝置，其中該眼圖判斷電路包括： 一反相器，耦接於該時脈產生器，經配置以對該第一經延遲取樣時脈進行反相以產生一第二經延遲取樣時脈。According to the eye diagram observation device described in item 7 of the scope of patent application, the eye diagram judgment circuit includes: An inverter, coupled to the clock generator, is configured to invert the first delayed sample clock to generate a second delayed sample clock. 如申請專利範圍第8項所述的眼圖觀測裝置，其中該第一計數值產生器包括： 一第一比較單元，耦接於該時脈產生器，經配置以接收該第一經延遲取樣時脈、該第一輸入信號以及該第二輸入信號，並基於該第一經延遲取樣時脈在該第一輸入信號的電壓準位等於該第二輸入信號的電壓準位時獲得該些比較結果的該些第一比較結果； 一第一格式轉換電路，耦接於該第一比較單元，經配置以將該些第一比較結果分別轉換為多個第一比較邏輯結果； 一第一取樣電路，耦接於該反相器以及該第一格式轉換電路，經配置以基於該第二經延遲取樣時脈對該些第一比較邏輯結果進行取樣，藉以提供對應於該些第一比較結果的多個第一取樣結果；以及 一第一計數器，耦接於該第一取樣電路，經配置以計數該第一取樣結果以獲得關聯於該些第一比較結果的該些第一計數值； 一第一計數值輸出器，耦接於該第一計數器，經配置以接收該些第一計數值並反應於該第一計數器的控制輸出該些第一計數值。According to the eye diagram observation device described in item 8 of the scope of patent application, the first count value generator includes: A first comparison unit, coupled to the clock generator, configured to receive the first delayed sample clock, the first input signal, and the second input signal, and based on the first delayed sample clock Obtaining the first comparison results of the comparison results when the voltage level of the first input signal is equal to the voltage level of the second input signal; A first format conversion circuit, coupled to the first comparison unit, configured to convert the first comparison results into a plurality of first comparison logic results; A first sampling circuit, coupled to the inverter and the first format conversion circuit, is configured to sample the first comparison logic results based on the second delayed sampling clock, so as to provide corresponding A plurality of first sampling results of the first comparison result; and A first counter, coupled to the first sampling circuit, configured to count the first sampling result to obtain the first count values associated with the first comparison results; A first count value output device is coupled to the first counter, and is configured to receive the first count values and output the first count values in response to the control of the first counter. 如申請專利範圍第8項所述的眼圖觀測裝置，其中該第二計數值產生器包括： 一第二比較單元，耦接於該時脈產生器，經配置以接收該第一經延遲取樣時脈、該第一輸入信號以及該第二輸入信號，並基於該第一經延遲取樣時脈在該第一輸入信號的電壓準位與該第二輸入信號的電壓準位的差值的絕對值等於一預設值時獲得該些比較結果的該些第二比較結果； 一第二格式轉換電路，耦接於該第二比較單元，經配置以將該些第二比較結果分別轉換為多個第二比較邏輯結果； 一第二取樣電路，耦接於該反相器以及該第二格式轉換電路，經配置以基於該第二經延遲取樣時脈對該些第二比較邏輯結果進行取樣，藉以提供對應於該些第二比較結果的多個第二取樣結果； 一第二計數器，耦接於該第二取樣電路，經配置以計數該些第二取樣結果以獲得關聯於該些第二比較結果的該些第二計數值；以及 一第二計數值輸出器，耦接於該第二計數器，經配置以接收該些第二計數值並反應於該第二計數器的控制輸出該些第二計數值。According to the eye diagram observation device described in item 8 of the scope of patent application, the second count value generator includes: A second comparison unit, coupled to the clock generator, configured to receive the first delayed sample clock, the first input signal, and the second input signal, and based on the first delayed sample clock Obtaining the second comparison results of the comparison results when the absolute value of the difference between the voltage level of the first input signal and the voltage level of the second input signal is equal to a preset value; A second format conversion circuit, coupled to the second comparison unit, configured to convert the second comparison results into a plurality of second comparison logic results; A second sampling circuit, coupled to the inverter and the second format conversion circuit, is configured to sample the second comparison logic results based on the second delayed sampling clock, so as to provide data corresponding to the Multiple second sampling results of the second comparison result; A second counter, coupled to the second sampling circuit, configured to count the second sampling results to obtain the second count values associated with the second comparison results; and A second count value output device is coupled to the second counter, and is configured to receive the second count values and output the second count values in response to the control of the second counter. 一種眼圖觀測裝置，用以定義出一輸入信號對的一眼圖，包括： 一眼圖判斷電路，經配置以接收一參考電壓控制時脈、一第一經延遲取樣時脈以及該輸入信號對，基於該參考電壓控制時脈提供多個參考信號，並且基於該第一經延遲取樣時脈使該輸入信號對依序與該些參考信號進行比較以獲得多個比較結果，並比對該些比較結果，藉以獲得對應於該輸入信號對的該眼圖；以及 一時脈產生器，耦接於該眼圖判斷電路，經配置以產生該參考電壓控制時脈以及該第一經延遲取樣時脈，其中該時脈產生器包括： 一電壓時間轉換器，經配置以依據一輸入電壓的電壓值產生一經延遲時脈，其中該經延遲時脈的延遲時間長度關聯於該輸入電壓的電壓值， 其中該時脈產生器依據該經延遲時脈產生該第一經延遲取樣時脈。An eye diagram observation device used to define an eye diagram of an input signal pair, including: An eye diagram judgment circuit configured to receive a reference voltage control clock, a first delayed sampling clock, and the input signal pair, provide multiple reference signals based on the reference voltage control clock, and based on the first delayed The sampling clock enables the input signal pair to be sequentially compared with the reference signals to obtain a plurality of comparison results, and the comparison results are compared to obtain the eye diagram corresponding to the input signal pair; and A clock generator, coupled to the eye pattern judgment circuit, configured to generate the reference voltage control clock and the first delayed sample clock, wherein the clock generator includes: A voltage-to-time converter configured to generate a delayed clock according to the voltage value of an input voltage, wherein the delay time of the delayed clock is related to the voltage value of the input voltage, The clock generator generates the first delayed sample clock according to the delayed clock. 如申請專利範圍第11項所述的眼圖觀測裝置，其中該電壓時間轉換器包括： 一輸入級電路，經配置以基於一外部時脈將該輸入電壓作為一轉換電壓； 一電容，該電容的第一端耦接於該輸入級電路以接收該轉換電壓，該電容的第二端耦接於一參考低電位；以及 一輸出級電路，耦接於該輸入級電路以及該電容的第一端，經配置以依據該轉換電壓的電壓值以及一預設電壓的電壓值提供該經延遲時脈。According to the eye diagram observation device described in item 11 of the scope of patent application, the voltage-time converter includes: An input stage circuit configured to use the input voltage as a conversion voltage based on an external clock; A capacitor, the first end of the capacitor is coupled to the input stage circuit to receive the converted voltage, and the second end of the capacitor is coupled to a reference low potential; and An output stage circuit, coupled to the input stage circuit and the first end of the capacitor, is configured to provide the delayed clock according to the voltage value of the converted voltage and the voltage value of a predetermined voltage. 如申請專利範圍第12項所述的眼圖觀測裝置，其中該輸入級電路包括： 一反相器，該反相器的輸入端用以接收該外部時脈； 一第一輸入級電晶體，該第一輸入級電晶體的第一端用以接收該輸入電壓，該第一輸入級電晶體的第二端耦接於該電容的第一端，該第一輸入級電晶體的控制端耦接於該反相器的輸出端； 一第二輸入級電晶體，該第二輸入級電晶體的第一端耦接於該第一輸入級電晶體的第二端，該第二輸入級電晶體的控制端耦接於該反相器的輸出端； 一第三輸入級電晶體，該第三輸入級電晶體的第一端耦接於該第二輸入級電晶體的第二端，該第三輸入級電晶體的第二端耦接於該參考低電位，該第三輸入級電晶體的控制端用以接收一偏壓，其中該第三輸入級電晶體經配置為一電流源。 一第四輸入級電晶體，該第四輸入級電晶體的第一端用以接收一參考高電位，該第四輸入級電晶體的第二端耦接於該第二輸入級電晶體的第二端，該第四輸入級電晶體的控制端用以接收該外部時脈；以及According to the eye diagram observation device described in item 12 of the scope of patent application, the input stage circuit includes: An inverter, the input terminal of the inverter is used to receive the external clock; A first input stage transistor, the first terminal of the first input stage transistor is used to receive the input voltage, the second terminal of the first input stage transistor is coupled to the first terminal of the capacitor, the first The control terminal of the input stage transistor is coupled to the output terminal of the inverter; A second input stage transistor, the first terminal of the second input stage transistor is coupled to the second terminal of the first input stage transistor, and the control terminal of the second input stage transistor is coupled to the inverter The output terminal of the device; A third input stage transistor, the first end of the third input stage transistor is coupled to the second end of the second input stage transistor, and the second end of the third input stage transistor is coupled to the reference At a low level, the control terminal of the third input stage transistor is used for receiving a bias voltage, wherein the third input stage transistor is configured as a current source. A fourth input stage transistor, the first terminal of the fourth input stage transistor is used to receive a reference high potential, the second terminal of the fourth input stage transistor is coupled to the second input stage transistor Two terminals, the control terminal of the fourth input stage transistor is used to receive the external clock; and 如申請專利範圍第12項所述的眼圖觀測裝置，其中該輸出級電路包括： 一第一輸出級電晶體，該第一輸出級電晶體的第一端用以接收一參考高電壓，該第一輸出級電晶體的控制端用以接收一偏壓，其中該第一輸出級電晶體經配置為一電流源； 一第二輸出級電晶體，該第二輸出級電晶體的第一端耦接於該第一輸出級電晶體的第二端，該第二輸出級電晶體的控制端耦接於該電容的第一端； 一第三輸出級電晶體，該第三輸出級電晶體的第一端耦接於該第一輸出級電晶體的第二端，該第三輸出級電晶體的控制端用以接收該預設電壓； 一第四輸出級電晶體，該第四輸出級電晶體的第一端耦接於該第二輸出級電晶體的第二端，該第四輸出級電晶體的第二端耦接於該參考低電位，該第四輸出級電晶體的控制端用以接收該外部時脈； 一反相器，該反相器的輸入端耦接於該第二輸出級電晶體的第二端，該反相器的輸出端被作為該電壓時間轉換器的輸出端；以及 一第五輸出級電晶體，該第五輸出級電晶體的第一端耦接於該第三輸出級電晶體的第二端，該第五輸出級電晶體的第二端耦接於該參考低電位，該第五輸出級電晶體的第一端耦接於耦接於該反相器的輸出端。The eye diagram observation device as described in item 12 of the scope of patent application, wherein the output stage circuit includes: A first output stage transistor, the first terminal of the first output stage transistor is used to receive a reference high voltage, the control terminal of the first output stage transistor is used to receive a bias voltage, wherein the first output stage The transistor is configured as a current source; A second output stage transistor, the first terminal of the second output stage transistor is coupled to the second terminal of the first output stage transistor, and the control terminal of the second output stage transistor is coupled to the capacitor First end A third output stage transistor, the first terminal of the third output stage transistor is coupled to the second terminal of the first output stage transistor, and the control terminal of the third output stage transistor is used to receive the preset Voltage; A fourth output stage transistor, the first end of the fourth output stage transistor is coupled to the second end of the second output stage transistor, and the second end of the fourth output stage transistor is coupled to the reference Low potential, the control terminal of the fourth output stage transistor is used to receive the external clock; An inverter, the input terminal of the inverter is coupled to the second terminal of the second output stage transistor, and the output terminal of the inverter is used as the output terminal of the voltage-to-time converter; and A fifth output stage transistor, the first end of the fifth output stage transistor is coupled to the second end of the third output stage transistor, and the second end of the fifth output stage transistor is coupled to the reference At a low level, the first terminal of the fifth output stage transistor is coupled to the output terminal coupled to the inverter. 如申請專利範圍第11項所述的眼圖觀測裝置，其中該時脈產生器還包括： 一時脈計數器，經配置以接收一參考時脈，並對該參考時脈進行計數以獲得一計數值；以及 一格式轉換電路，耦接於該時脈計數器以及該電壓時間轉換器，經配置以接收該計數值，並依據該計數值提供該輸入電壓， 其中該輸入電壓的電壓值關聯於該計數值。For the eye diagram observation device described in item 11 of the scope of patent application, the clock generator further includes: A clock counter configured to receive a reference clock and count the reference clock to obtain a count value; and A format conversion circuit, coupled to the clock counter and the voltage-to-time converter, configured to receive the count value and provide the input voltage according to the count value, The voltage value of the input voltage is associated with the count value. 如申請專利範圍第15項所述的眼圖觀測裝置，其中該時脈計數器還藉由該計數值的溢位產生該參考電壓控制時脈。According to the eye diagram observation device described in claim 15, wherein the clock counter also generates the reference voltage control clock through the overflow of the count value. 如申請專利範圍第15項所述的眼圖觀測裝置，其中該時脈產生器還包括： 一致能時脈產生器，經配置以依據該參考時脈以及該經延遲時脈產生一致能時脈；以及 一邏輯電路，耦接於該致能時脈產生器、該電壓時間轉換器以及該眼圖判斷電路，經配置以對該致能時脈以及該經延遲時脈進行邏輯運算以產生該第一經延遲取樣時脈。As the eye diagram observation device described in item 15 of the scope of patent application, the clock generator further includes: A consistent energy clock generator configured to generate a consistent energy clock based on the reference clock and the delayed clock; and A logic circuit, coupled to the enabled clock generator, the voltage-time converter, and the eye diagram judgment circuit, is configured to perform logic operations on the enabled clock and the delayed clock to generate the first The sampling clock is delayed. 如申請專利範圍第11項所述的眼圖觀測裝置，其中該眼圖判斷電路包括： 一參考信號產生電路，耦接於該時脈產生器，經配置以接收該參考電壓控制時脈，基於該參考電壓控制時脈產生該些參考信號；以及 一比較單元，耦接於該時脈產生器以及該參考信號產生電路，經配置以接收該輸入信號對以及該些參考信號，並基於該第一經延遲取樣時脈使該輸入信號對依序與該些參考信號進行比較以獲得該些比較結果。According to the eye diagram observation device described in item 11 of the scope of patent application, the eye diagram judgment circuit includes: A reference signal generating circuit, coupled to the clock generator, configured to receive the reference voltage control clock, and generate the reference signals based on the reference voltage control clock; and A comparison unit, coupled to the clock generator and the reference signal generating circuit, configured to receive the input signal pair and the reference signals, and sequence the input signal pairs based on the first delayed sample clock Compare with the reference signals to obtain the comparison results. 如申請專利範圍第18項所述的眼圖觀測裝置，其中該眼圖判斷電路還包括： 一格式轉換電路，耦接於該比較單元，經配置以將該些比較結果分別轉換為多個比較邏輯結果； 一反相器，耦接於該時脈產生器，經配置以對該第一經延遲取樣時脈進行反相以產生一第二經延遲取樣時脈； 一取樣電路，耦接於該反相器以及該格式轉換電路，經配置以基於該第二經延遲取樣時脈對該些比較邏輯結果進行取樣，藉以提供多個取樣結果； 一計數器，耦接於該取樣電路，經配置以計數該取樣結果以獲得關聯於該些比較結果的多個計數值；以及 一計數值輸出器，耦接於該計數器，經配置以接收該些計數值並反應於該計數器的控制輸出該些計數值。As the eye diagram observation device described in item 18 of the scope of patent application, the eye diagram judgment circuit further includes: A format conversion circuit, coupled to the comparison unit, configured to convert the comparison results into a plurality of comparison logic results; An inverter, coupled to the clock generator, configured to invert the first delayed sampling clock to generate a second delayed sampling clock; A sampling circuit, coupled to the inverter and the format conversion circuit, configured to sample the comparison logic results based on the second delayed sampling clock to provide multiple sampling results; A counter, coupled to the sampling circuit, configured to count the sampling results to obtain a plurality of count values related to the comparison results; and A count value output device is coupled to the counter and is configured to receive the count values and output the count values in response to the control of the counter. 如申請專利範圍第19項所述的眼圖觀測裝置，其中該眼圖判斷電路儲存該計數值輸出器所輸出的關聯於該些比較結果的多個計數值，並比對該些計數值，藉以獲得對應於該輸入信號對的該眼圖。For the eye pattern observation device described in item 19 of the scope of patent application, the eye pattern judgment circuit stores a plurality of count values output by the count value output device related to the comparison results, and compares the count values, To obtain the eye diagram corresponding to the input signal pair.
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