TWI250484B

TWI250484B - Low voltage differential signal clock data recovery device and method thereof

Info

Publication number: TWI250484B
Application number: TW93117809A
Authority: TW
Inventors: Chua-Chin Wang; Chau-Yang Shiau
Original assignee: Univ Nat Sun Yat Sen; Au Optronics Corp
Priority date: 2004-06-18
Filing date: 2004-06-18
Publication date: 2006-03-01
Also published as: TW200601213A

Abstract

The present invention relates to a low voltage differential signal (LVDS) clock data recovery device and a method thereof. The clock data recovery device receives a reference signal and a data signal, and the signal variation track of a data signal forms an eye diagram. The clock signal recovery device includes a phase lock loop (PLL), a double-edge tracking circuit and an eye center generator. The PLL is used to generate a plurality of PLL output signals; the double-edge tracking circuit is used to receive at least part of the plural PLL output signals to generate a left boundary signal of eye diagram and a right boundary signal of eye diagram. The eye center generator outputs an eye center signal corresponding to the eye center in accordance with the left boundary signal of eye diagram and the right boundary signal of eye diagram, thereby generating a plurality of sampled data signals with different phases.

Description

1250484 五、發明說明（1) 【發明所屬之技術領域】本發明係有關於一種低電壓差動信號（low voltage differential Signai，lVDS)之時脈資料回復裝置及其方法’尤其是關於一利用相位領先落後偵測器與相位内插器作為低電壓差動信號之時脈資料回復裝置的設計。【先前技術】自從LCD榮幕問世之後，採用低電壓差動信號（1〇w yoljage differential signal，LVDS)在主機與顯示器間傳运貝料#唬已成為最常用的方式。低電壓差動信號 (^VDS)跟傳統單端信號的差異在於其具有低電壓且省電 f特性。但隨著資料信號的高速傳送，造成了資料信號的資料信號同步的困難。許多種架構被提出來。例如先前古认> t ~ 便假設信號在傳輸時，呈現項取的架構在設計時 ^ ^ ^ ^ ^ 呈現出的眼圖分布情形是對稱的。仁故種假汉下設計出來的電路雖铁〜，無法避免通道隨環境影響而有;^ ^貫㉟應用上卻材質差異造成的影響。又如另一斤：：椹：如戶”傳輸線的的準_性而使用了所謂超取樣 ’、&、、了提四資料“號料信號讀了好幾次再做判斷，$二，，方式是將一筆資時，意味著讀取資料的速度必須次貝料的尚速傳輸倍，這樣一方面需要更高速的電貝口傳輸在快上好幾電磁干擾（EMI )效應，另一方’不但耗電，而且帶來料的正確性又降低了。面在高速資料讀取時資1250484 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a clock signal recovery device for a low voltage differential signal (lVDS) and a method thereof, particularly regarding a utilization phase The leading backward detector and phase interpolator are designed as clock data recovery devices for low voltage differential signals. [Prior Art] Since the advent of the LCD screen, the use of low-voltage differential signals (LVDS) to transport beryllium between the host and the display has become the most common method. The difference between the low voltage differential signal (^VDS) and the conventional single-ended signal is that it has a low voltage and saves power f characteristics. However, with the high-speed transmission of data signals, it is difficult to synchronize the data signals of the data signals. A variety of architectures have been proposed. For example, the previous recognition of > t ~ assumes that when the signal is transmitted, the architecture of the presentation item is symmetric at the design time ^ ^ ^ ^ ^. The circuit designed by the fake kind of fake Han is iron ~, can not avoid the channel with the influence of the environment; ^ ^ 35 application but the effect of material differences. Another example is the jin:: 椹: the use of the so-called "super-sampling" of the transmission line, and the use of the so-called "data" signal read several times and then judge, $ two, The way is to make a time, which means that the speed of reading data must be twice as fast as that of the shell. Therefore, on the one hand, a higher speed electric port is required to transmit several electromagnetic interference (EMI) effects, and the other side is not only Power consumption, and the correctness of the materials is reduced. In the case of high-speed data reading

TW1748F(友達）.ptd 1250484 五、發明說明（2) 【發明内容】信有=於此，本發明的目的就是在提供一種低電壓差動 2 =脈資料回復裝置及其方法，可使得資料信號經過的中心雨之後，仍然可以將資料信號的讀取位置至於眼圖步的置。可改善傳輸資料信號時所造成的雜訊與不同率。σ題。使得接收資料信號的正確性提高與降低錯誤資料！jii明的目的，提出-種低電壓差動信號之時脈 -資料信號。資==復裝置接收一外部參考信號與回復裝置勺紅14 u屬於低電壓差動信號。時脈信號位置信號ii;;相L路、一雙邊追蹤電路與一眼圖中心輸出多個鎖相收外部參考信號，以率舆外部來考，出^旎。夕個鎖相迴路輸出信號的頻係分別具有不二的f率相肖。且多個鎖相迴路輸出信號個鎖相迴路輸出ίί雙邊追蹤電路接收至少部分之多位置信號與眼η據：料信號出眼圖左邊界電路用以接收至少號。眼圖中心位置信號產生眼圖左邊界位置心::個鎖相迴路輸出信號，並根據心位置信號。圖右邊界位置信號產生-眼圖中位置信號以輸出資料信號：更根據眼圖中心資料回復的方 =出一種低電壓差動信號之時脈復裝置用以接收回=置。時脈信號回唬與—貧料信號。時脈信號 .TW1748F(友達）.ptd 第6頁 l25〇484TW1748F (Friends). ptd 1250484 V. Inventive Description (2) [Description of Information] The present invention is directed to providing a low voltage differential 2 = pulse data recovery device and method thereof, which can make a data signal After the passing of the central rain, the reading position of the data signal can still be set to the eye step. It can improve the noise and different rate caused by transmitting data signals. σ question. Improve the correctness of the received data signal and reduce the error data! The purpose of jii is to propose a clock of the low voltage differential signal - the data signal.资 == The complex device receives an external reference signal and the reply device spoon red 14 u belongs to the low voltage differential signal. The clock signal position signal ii;; the phase L path, a bilateral tracking circuit and an eye diagram center output a plurality of lock phase external reference signals to rate the external test. The frequency of the output signals of the phase-locked loops has a different f-rate phase. And multiple phase-locked loop output signals, phase-locked loop output ίί bilateral tracking circuit receives at least part of the position signal and the eye η data: the material signal exits the left edge of the eye. The circuit is used to receive at least the number. Eye center position signal generation Eye left position of the eye:: A phase-locked loop output signal, and according to the heart position signal. The signal at the right edge of the figure generates a position signal in the eye diagram to output the data signal: the side that is replied according to the center of the eye diagram data = the clock of a low voltage differential signal. The device is used to receive back = set. The clock signal returns to the 贫 and the poor material signal. Clock signal .TW1748F ( AUO ).ptd Page 6 l25〇484

資料邊緣產生器、一雙邊追姦丛Φ攸。擁4息Μ的A雨的 A 五、發明說明⑶ S ί i ί包括一鎖相迴路、括=路與一眼圖中心位置信_ _ 一 & _ ^ ^ ^ ^ ^ ^ ^ 圖右、臭ΐ控制電路、—眼圖左邊界位置信號產生器與一眼輪出容伽μ 生器。鎖相迴路接收外部參考信號以號以輪出^目^輸出信號。資料邊緣產生器接收資料信少部分多個‘相t $二眼圖左邊界位置信號產生器接收至，輪出輪：==號以產生一左相位 ;置信號。眼圖中心位輪出—眼圖右邊界省相迴路輪出信號，並依據目^喜路接收至少部分多個 =位置信號以輸出一眼，位置信號與眼圖右 :成一眼圖，本發=ϊ;。而資料信號的號。去-輪出對應至眼圖的一中心位署去係用使時脈信號相1*位，，t比較脈波信號的相位與左柏的眼圖中心位置信付到眼圖左邊界位置传/、位内插輸出信號的 d”内插輪出“位，？由比較脈波信號的找出眼圖的中心位[並眼圖右邊界位置：二：ϋ'ι。最後根據眼圖中二圖的中心位置產生眼 5唬之夕個相位不同之取樣作狭位置信號，輸出次4丨信號的頻率與外部參考信號的丄其中，些鎖相迴路；= 出信號係具有不同之相位。其巧率而些鎖 -一^ 右外部參考信號的一Ϊ 顶 74SFY 友達).ptd 1250484The data edge generator, a bilateral chasing cluster Φ攸. A rain of A 4, invention description (3) S ί i ί includes a phase-locked loop, including = road and an eye center position letter _ _ a & _ ^ ^ ^ ^ ^ ^ ^ right, stinky ΐ Control circuit, - eye left position signal generator and one eye wheel output gamma generator. The phase-locked loop receives the external reference signal with a number to output the signal. The data edge generator receives the data signal. A small number of multiple 'phase t $ digraphs left boundary position signal generators receive to, the wheel:== number to generate a left phase; set the signal. The center of the eye diagram is rotated - the right edge of the eye is rotated by the phase loop circuit, and at least part of the position signal is received according to the eye path to output one eye, the position signal and the eye diagram right: into an eye diagram, the hair = Oh; And the number of the data signal. Going-rounding a center position corresponding to the eye diagram to make the clock signal phase 1* bit, t comparing the phase of the pulse signal with the left eye position of the left eye to the left boundary position of the eye diagram /, bit interpolated output signal d" interpolated round out "bit,? Find the center of the eye diagram by comparing the pulse signal [the right edge position of the eye diagram: two: ϋ 'ι. Finally, according to the center position of the two images in the eye diagram, a sample with different phase of the eye is generated as a narrow position signal, and the frequency of the fourth signal and the external reference signal are outputted, and some phase-locked loops are formed; Have a different phase. Its clever rate and some locks - a ^ right external reference signal for a top 74SFY AUO).ptd 1250484

號週期係對應至資料信號的數’則二個相鄰之些鎖相迴度。 n個資料位元區間，η係為正整路輪出信號之相位差為360/2η 特徵、和優點能更明顯易並配合所附圖式，作詳細說為讓本發明之上述目的懂，下文特舉一較佳實施例明如下：【實施方式】在本實施例中，低電壓差動信號（low v〇ltage signal，UDS)的時脈區間具有7個的資料區間，即疋在一個低電壓差動信號（[几幻的時脈區有7筆資料。實施例中輸入的外部參考信號⑽的脈範圍為20〜100 MHz，而傳送的資料位元率則為uQ〜7〇〇 Mbps。在本發明中使用一相位内插器。相位内插器的作用是將二個輸入的信號做相位内插，並且可由輸入的控制俨號將相位内插後的信號做相位增加或減少的調整。口請參照第1圖，其繪示乃依照本發明一較佳實施例的一種低電壓差動信號之時脈資料回復裝置的方塊圖。時脈資料回復裝置20 0接收外部參考信號〇F與資料信號D。資料信號D係屬於低電壓差動信號（LVDS)，具有7個的"資料區間。时脈佗號回復裝置2 〇〇包括一鎖相迴路2 q 1 (p l l )、一資料邊緣產生器204(data edge generator)、一雙邊追蹤 generator)。雙邊追蹤電路2〇2包括一重置控制電路 11 B _ 11 S 1 1 I I 1 TW1748F(友達）.Ptd 第8頁電路202與一眼圖中心位置信號產生電路2〇3(eye center 1250484 發明說明（5) (reset control circuit)205、一眼圖左邊界位置信號產生态206與一眼圖右邊界位置信號產生器207。鎖相趣路 20 1接收外部參考信號〇F以輸出多個鎖相迴路輸出信號 CLK。資料邊緣產生器2〇4接收資料信號d以輸出〆脈波信號P。眼圖左邊界位置信號產生器2〇6接收至少部分之多個鎖=迴路輸出信號CLK與脈波信號p以產生一左相位内插輪出信號S-PI-L(未繪圖1中）與輸出一眼圖左邊界位置信號^ LW、。眼圖右邊界位置信號產生器2 0 7接收至少部分多個鎖 ^，路輸出偵號CLK與脈波信號p以產生一右相位内插輪出仏遽S — PI-R(未繪圖1中）與輸出一眼圖右邊界位置信號 RW Y眼圖中心位置信號產生電路2 0 3接收至少部分多個鎖才目迴路輸出信號CLK，並依據眼圖左邊界位置信號LW與眼图1邊界位置k號RW以輸出一眼圖中心位置信號CE(未緣二g中^。^育料信號D的信號變化軌跡形成一眼圖。本發位^疋使日守脈信號回復裝置2 0 0輸出對應至眼圖的一中心位盘3艮圖中心位置信號α。先藉由比較脈波信號p的相 1^ m相位内插輪出信號S PI L的相位，以得到眼圖左邊界位置信骑τ w ^ 插輪出广LW。再藉由比較脈波信號P的相位與右相伋内 RW ^接二號S〜P 1〜R的相位，以得到眼圖右邊界位置信號信號Rw考再依據眼圖左邊界位置信號LW與眼圖右邊界位置生目^圖中找出眼圖的中心位置。並根據眼圖的中心位置產產生^ ，置信號CE。最後根據眼圖中心位置信號CE，鎖相i /路^號多個相位不同之取樣信號。其中，多個雨出L號CLK的頻率與外部參考信號0F的頻率相五、發明說明（6) ::個！：迴路輪出信職係分別具有不同之相信號參=號〇:的-信號週期係對應至資料輸出信號之二ΐ = Γθ，，則二個相鄰之些鎖相迴糊接下來，請表第q圖〇/甘211度/ η在本發明實施例係為7。構圖。*圖^ f 其繪不乃時脈資料回復裝置的結施例的一種時部份分別進一步說明本發明之較佳實過通道傳幹之/ f回復裝置2GG。如何使得資料信號D經眼圖仍然可以將資料信號D的取樣信號至於施電路0 明先^ 第2圖，其繪示乃鎖相迴路的實電路圖。其中’鎖相迴路2〇1包括一偏壓產生器 enerator) 301、一相位頻率比較器（pFD) 3〇2、一充放電電路（charge pufflp) 3〇3、一複製偏壓電路（Repiica B二μ) 304、一電壓控制震盪器（vc〇) 3〇5、一第一組差動化號轉單端信號電路（DSC)3〇6〜312。相位頻率比較器 302用以比較該外部參考信號〇F與多個鎖相迴路輸出信號 CLK之一’以產生一充電/放電控制信號。充放電電路 303，係根據充電/放電控制信號以得到一第一輸出電壓。複製偏壓電路3 0 4係複製第一輸出電壓，以得到一第二輪出電壓。電壓控制震盪器305根據第一輸出電壓與第二輸出電壓輸出多個鎖相迴路輸出信號CLK。由於LVDS傳送的參考時脈，在一個週期内會傳送7個位元（bits)，所以在這個電壓控制震盪器3 0 5架構中使用7個差動信號轉單端信號電路3 0 6〜312。這7個差動信號轉單端信號電路306〜The number period corresponds to the number of data signals and then two adjacent phase locks. n data bit intervals, η is the positive phase of the round-trip signal phase difference of 360 / 2 η characteristics, and the advantages can be more obvious and fit with the drawings, in detail to make the above objectives of the present invention understand, In the following, a preferred embodiment is as follows: [Embodiment] In this embodiment, a clock interval of a low voltage differential signal (UDS) has seven data intervals, that is, one in a Low-voltage differential signal ([There are seven data in the octave clock area. The external reference signal (10) input in the embodiment has a pulse range of 20 to 100 MHz, and the transmitted data bit rate is uQ~7〇〇. Mbps. A phase interpolator is used in the present invention. The phase interpolator functions to phase interpolate the two input signals, and the phase-interpolated signal can be phase-increasing or decreasing by the input control apostrophe. Please refer to FIG. 1 , which is a block diagram of a clock data recovery device for a low voltage differential signal according to a preferred embodiment of the present invention. The clock data recovery device 20 0 receives an external reference signal. 〇F and data signal D. Data The signal D belongs to the low voltage differential signal (LVDS) and has seven " data intervals. The clock nickname recovery device 2 includes a phase locked loop 2q1 (pll), a data edge generator 204 ( Data edge generator), a bilateral tracking generator). The bilateral tracking circuit 2〇2 includes a reset control circuit 11 B _ 11 S 1 1 II 1 TW1748F ( AUO). Ptd page 8 circuit 202 and an eye center position signal generating circuit 2 〇 3 (eye center 1250484 invention description ( 5) (reset control circuit) 205, an eye left position signal generation state 206 and an eye right boundary position signal generator 207. The lock phase circuit 20 1 receives an external reference signal 〇F to output a plurality of phase locked loop output signals CLK. The data edge generator 2〇4 receives the data signal d to output the chirp pulse signal P. The left edge position signal generator 2〇6 of the eye diagram receives at least a part of the lock=loop output signal CLK and the pulse signal p to Generating a left phase interpolated round-trip signal S-PI-L (not drawn 1) and outputting an eye left boundary position signal ^ LW. The eye right border position signal generator 2 0 7 receives at least a portion of the plurality of locks ^ The road outputs the detection signal CLK and the pulse signal p to generate a right phase interpolation wheel 仏遽S_PI-R (not drawn 1) and outputs an eye right boundary position signal RW Y eye center position signal generation circuit 2 0 3 Receive at least some of the locks The eye loop outputs a signal CLK and outputs an eye center position signal CE according to the left boundary position signal LW of the eye diagram and the boundary position k number RW of the eye diagram 1 (the signal change track of the feed signal D is not formed. One eye diagram. The hair position signal 疋日日日信号信号信号 2 2 2 2 2 2 2 2 2 输出输出输出输出输出输出日日守守守守守守守守守守守守日日日日日日日日日日日Interpolating the phase of the signal S PI L to obtain the left edge position of the eye diagram, the signal riding τ w ^ the insertion wheel and the wide LW. By comparing the phase of the pulse signal P with the right phase, the RW ^ is connected to the second S ~P 1~R phase to obtain the right border position signal signal Rw of the eye diagram and then find the center position of the eye diagram according to the left edge position signal LW of the eye diagram and the right boundary position of the eye diagram. The center position of the figure produces ^, set the signal CE. Finally, according to the eye center position signal CE, the phase-locked i / road ^ number of different phases of the sampling signal. Among them, the frequency of the multiple L CLK frequency and external reference Frequency of signal 0F phase five, invention description (6) :: one!: circuit round out of the letter system There are different phase signals = = 〇: - the signal period corresponds to the data output signal of ΐ = Γ θ, then the two adjacent lock phase replies, please see the table q / Gan 211 The degree / η is 7 in the embodiment of the present invention. The composition is a time portion of the embodiment of the clock data recovery device, which further illustrates the preferred real channel propagation of the present invention. /f replies to the device 2GG. How to make the data signal D through the eye diagram can still send the sampling signal of the data signal D to the circuit 0. First, the second picture, which shows the real circuit diagram of the phase-locked loop. Wherein the 'phase-locked loop 2〇1 includes a bias generator generator 301', a phase frequency comparator (pFD) 3〇2, a charge and discharge circuit (charge pufflp) 3〇3, and a replica bias circuit (Repiica) B 2 μ) 304, a voltage controlled oscillator (vc〇) 3〇5, a first group of differential number to single-ended signal circuit (DSC) 3〇6~312. The phase frequency comparator 302 is configured to compare the external reference signal 〇F with one of the plurality of phase-locked loop output signals CLK' to generate a charge/discharge control signal. The charge and discharge circuit 303 is configured to obtain a first output voltage according to the charge/discharge control signal. The replica bias circuit 306 replicates the first output voltage to obtain a second turn-on voltage. The voltage controlled oscillator 305 outputs a plurality of phase locked loop output signals CLK according to the first output voltage and the second output voltage. Since the reference clock transmitted by LVDS transmits 7 bits in one cycle, 7 differential signals are used in this voltage controlled oscillator 3 0 5 architecture to switch to single-ended signal circuits 3 0 6 to 312. . The seven differential signals are transferred to the single-ended signal circuit 306~

TW1748F(友達）.Ptd 第10頁 1250484 五、發明說明（7) 31 2在本施實例通稱第一 312。電壓控制震iJ3〇5、動上號轉單端信號電路3〇卜 CLK將會等間隔的落在每」筆夕二，目迴路輸出信號個延遲級的第—組差二二Ί貧料區間’且由這7 出可產生14個相位（多H轉早知信號電路306〜312輸 CLK ρ0 Γί. ρβ夕個鎖相迴路輸出信號CLK所包括的 CLK-N6) 此存丨7° =丨-彳4唬週期係對應至n個資料位元區間，η在 = /2η产V目/之多個鎖相迴路輪出信號CLK之相位差 ί m ^ °山鎖相迴路輸出信號c l κ更經過第一組差 η轉早、信號電路306〜312可得到單端信_〜 0^Dn _ =(多個鎖相迴路輪出信號CLK更包括單端信〜 D〇〜/D6)。請參照第ίο圖，其繪示乃差動信號轉單端信號電路的一較佳實施電路。因此，藉由電壓控制震盪器305與第一組差動信號轉單端信號電路3〇6〜312 產生多個鎖相迴路輸出信號CLK。使得多個鎖相迴路輸出信號CLK包括差動信號CLK_p〇〜ακ —p6、CLK —㈣〜 CLKJ6與單端信號D〇〜D6、/D〇〜/D6。而單端信號d〇〜 D6 的電壓為準為一般的數位信號的電壓位準，而差動1§號(：1^_?〇〜CLK 一 P6、CLK 一 N0 〜CLK —N6 為低電壓差動信號的電壓位準。第二部份，請參照第3圖，其繪示乃資料邊緣產生器，雙邊追縱電路的實施電路圖。眼圖左邊界位置信號產生器20 6包括一第一的相位領先落後偵測器（phase ear ly/late detector-L)402 與一第一相位内插器（phaseTW1748F (Friends). Ptd Page 10 1250484 V. Description of Invention (7) 31 2 is referred to as the first 312 in this example. Voltage control vibration iJ3〇5, moving the number to the single-ended signal circuit 3 〇 CLK will be equally spaced every second, the first loop difference of the output loop of the target loop 'And 14 out of 14 can produce 14 phases (multi-H turn to early signal circuit 306~312 to CLK ρ0 Γί. ρβ CLK-N6 included in the phase-locked loop output signal CLK) This is 7° =丨-彳4唬 period corresponds to n data bit intervals, η is = /2η V target / phase difference of multiple phase-locked loops CLK signal ί m ^ ° mountain phase-locked loop output signal cl κ After the first group difference η turns early, the signal circuits 306 312 312 can obtain a single-ended signal _~ 0^Dn _ = (the plurality of phase-locked loops CLK signal further includes a single-ended signal ~ D 〇 ~ / D6). Please refer to the figure ί, which shows a preferred implementation circuit of the differential signal to single-ended signal circuit. Therefore, a plurality of phase locked loop output signals CLK are generated by the voltage controlled oscillator 305 and the first set of differential signal to single-ended signal circuits 3〇6 to 312. The plurality of phase-locked loop output signals CLK are included in the differential signal CLK_p〇~ακ_p6, CLK_(four)~CLKJ6 and the single-ended signals D〇~D6, /D〇~/D6. The voltage of the single-ended signal d〇~D6 is the voltage level of the general digital signal, and the differential 1§ (:1^_?〇~CLK-P6, CLK-N0~CLK-N6 is the low voltage The voltage level of the differential signal. For the second part, please refer to Fig. 3, which is a circuit diagram of the implementation of the data edge generator and the bilateral tracking circuit. The eye left position signal generator 20 6 includes a first Phase ear ly/late detector-L 402 and a first phase interpolator (phase

TW1748F(友達）.ptd 第11頁 1250484 五、發明說明（8) interpolator-L)405。眼圖右邊界位置信號產生器2 07包括一第二的相位領先落後偵測器（p h a s e e a r 1 y / 1 a t e detector-R)404 與一第二相位内插器（phase interpolator-R)406。第一相位内插器405用以接收至少部分之差動信號（至少部分之差動信號CLK_P0〜CLK_P6、 CLK一NO〜CLK — N6)與眼圖左邊界位置信號LW，以輸出一左相位内插輸出信號S一 P I 一L。第二相位内插器4 0 6用以接收至少部分之差動信號（至少部分之差動信號CLK_P0〜 CLK—P6、CLK— N0〜CLK — N6)與眼圖右邊界位置信號rw，以輸出一右相位内插輸出信號S 一 P I 一 R。換句話說，第一相位内插裔4 0 5與第二相位内插器4 0 6的作用是將二個輸入的信號（至少部分之差動信號CLK_P0〜CLK__P6、CLKJ〇〜 CLK一N6)做相位内插，且可由輸入的控制信號（即眼圖左邊界位置信號LW與眼圖右邊界位置信號RW)將相位内插後的信號（左相位内插輸出信號s 一P I 一L、右相位内插輸出信號 S一PI一R)做相位增加或減少的調整。進一步說明，請參日召第4圖，其繪示乃相位内插器的實施電路圖。以第^胃圖^的”第二相位内插器405而言’輸入端CLK1、/ CLK1接到多個鎖相迴路輸入信號CLK中之差動信號CLKj6、cu μ，而另一輸入端CLK2、/ CLK2接到多個鎖相迴路輸入信號CLK中之差動信號CLK_P0、CLK_N0。另外w[i]、/ w[i] ? . _ 〇〜11 ’則代表可以控制其流經電流的開關。當開關^通的數目越多時則流經電流越大，就可以控制信號上升的快慢，達到控制相位的目的。以第3圖的第—相位内差器j〇5TW1748F ( AUO).ptd Page 11 1250484 V. Description of the invention (8) interpolator-L) 405. The eye right border position signal generator 2 07 includes a second phase leading backward detector (p h a s e e a r 1 y / 1 a t e detector-R) 404 and a second phase interpolator-R 406. The first phase interpolator 405 is configured to receive at least a portion of the differential signals (at least a portion of the differential signals CLK_P0 CLK_P6, CLK_NO CLK — N6) and the left edge position signal LW of the eye to output a left phase Insert the output signal S - PI - L. The second phase interpolator 406 is configured to receive at least a portion of the differential signals (at least a portion of the differential signals CLK_P0 CLK CLK-P6, CLK — N0 CLK — N — N6) and the right edge position signal rw of the eye to output A right phase interpolates the output signal S - PI - R. In other words, the first phase interpolator 4 0 5 and the second phase interpolator 4 0 6 function to input two input signals (at least part of the differential signals CLK_P0 CLK__P6, CLKJ 〇 CLK CLK N6) Phase interpolation is performed, and the phase-interpolated signal can be input by the input control signal (ie, the left-eye position signal LW of the eye diagram and the right-side position signal RW of the eye diagram) (left phase interpolation output signal s - PI - L, right The phase interpolated output signal S-PI-R) is adjusted for phase increase or decrease. For further explanation, please refer to the fourth drawing, which shows the implementation circuit diagram of the phase interpolator. In the second phase interpolator 405 of the first embodiment, the input terminals CLK1, /CLK1 are connected to the differential signals CLKj6, cu μ of the plurality of phase-locked loop input signals CLK, and the other input terminal CLK2 / CLK2 is connected to the differential signals CLK_P0, CLK_N0 in the input signal CLK of multiple phase-locked loops. In addition, w[i], / w[i] ? . _ 〇~11 ' represents the switch that can control the current flowing through it. When the number of switches is larger, the current flowing through the current is larger, and the speed of the signal rise can be controlled to achieve the purpose of controlling the phase. The phase-internal difference j〇5 of Fig. 3

TW1748F(友達）.ptd 1250484 五、發明說明（9) 而言，其 W[i]、/ W[i]接收到 6 - bit shift register —l 的輸出作為控制。請同時參照第5圖，其繪乃示第一相位内差器405模擬的輸出波形圖。曲線<〇>、<1>、<2>、<3> 分別是電壓控制震盪器3 0 5的輸出信號之多個鎖相迴路輸入信號CLK中之差動信號CLK_P0、CLK —PI、CLK —P2、 CLK—P3 ’而曲線A、B、C、D、E是由多個鎖相迴路輸入信號CLK 中之差動信號CLK_N6、CLK_P6、CLK —P〇、CLK J0 的二组差動信號經相位内插後的輸出信號。而曲線A:6 - bit shift register-L輸出有5個1時的情形。曲線B:6 - bit shift register- L輸出有4個1時的情形。曲線C:6 - bit shift register-L輸出有3個1時的情形。曲線D:6 - bit shift register-L輸出有2個1時的情形。曲線E : 6-bi t shi f t register-L輸出有1個1時的情形。所以差動信號CLK-P0〜CLK一P1中間，可分為6個區^，亦即可分成6個相位。第一相位領先落後偵測器40 2包括第一位移暫存器4〇7 (6-bit shift register-L)。第二相位領先落後债測器 402 包括第二位移暫存器 408 ( 6-bit shift r*egist^。第一相位領先落後偵測器402比較脈波信號p的相位與乂相位内插輸出信號S — PI—L的相位，第二相位領先落後偵二哭 404比較脈波信號p的相位與右相位内插輪出信號s — p丨的相位。也就是第一相位領先落後偵測器4〇2與第"二相位先落後偵測器404用來比較二個輸入信號的相位，直比_ 後的結果分別儲存在第一位移暫存器4〇7與第二位移暫^TW1748F (Friends).ptd 1250484 V. Inventive Note (9), W[i], /W[i] receives the output of 6-bit shift register-1 as control. Please refer to FIG. 5 at the same time, which is an output waveform diagram simulated by the first phase internal difference 405. The curves <〇>, <1>, <2>, <3> are the differential signals CLK_P0, CLK of the plurality of phase-locked loop input signals CLK of the output signals of the voltage-controlled oscillators 300, respectively -PI, CLK - P2, CLK - P3 ' and the curves A, B, C, D, E are the differential signals CLK_N6, CLK_P6, CLK - P 〇, CLK J0 of the input signal CLK from the plurality of phase-locked loops The output signal of the group differential signal after phase interpolation. Curve A: The 6-bit shift register-L output has five 1s. Curve B: The 6-bit shift register-L output has four 1s. Curve C: The 6-bit shift register-L output has three 1s. Curve D: The 6-bit shift register-L output has two 1s. Curve E: 6-bi t shi f t register-L output has 1 case. Therefore, in the middle of the differential signal CLK-P0~CLK-P1, it can be divided into six regions, and can be divided into six phases. The first phase leading backward detector 40 2 includes a 6-bit shift register (L). The second phase leading backward debt detector 402 includes a second shift register 408 (6-bit shift r*egist^. The first phase leading backward detector 402 compares the phase of the pulse signal p with the phase-interpolated output signal S — PI—L phase, the second phase leading backwards, the second crying 404, the phase of the pulse signal p, and the phase of the right phase interpolating wheel signal s — p丨. That is, the first phase leading backward detector 4 〇2 and the second phase first backward detector 404 are used to compare the phases of the two input signals, and the results of the direct ratio _ are stored in the first displacement register 4〇7 and the second displacement temporarily.

1250484 五、發明說明（10) Γ一08相/二千位移暫存器407與第二位移暫存器408並決定位要妗加、咸T\05、第二相位内插器406下-次的輸出相邊ϊ =動/第一相位領先落後娜402產 404產生Λ Λ . K — L1與第二相位領先落後偵測器 :Λ二制信號CLK-R1分別會使得第-位移 I w盥目m喜两/暫存輸出眼圖左邊界位置信號 J艮圖右邊界位置信號RW。第— ==㈣接收眼圖左邊界位置信號咖位置k 5虎RW以輸出往目尽同由立々去 ς ΡΤ τ盘士士移動的左相位内插輸出信號插輸出信號”1-R，亦即使得眼圖左、 n篦一番罢在内縮。相反的’重置控制電路20 5產生的 :f f : Ϊ 號CU —L2與第二重置信號CLK-R2會使得第的ί Ϊ :後偵測器4 〇 2與第二相位領先落後偵測器4 0 4 艮Γ心移動，亦即使得眼圖左、右邊界的 i二：？種往内縮、往外張的方式，可以得 ^衷^變時眼圖張開最小的左、右邊界。請參照第6 m:信號CLK-L1、CLK—R1、CLK_L2、clk_r2 跟眼圖左、右邊界的關係圖。 #&土、進v來&尋找眼®左邊邊界的方式為，當資料气化發生在眼圖左邊的範圍日夺，即是資料信齡變化相位内插輪出信號S-PI-L的右邊，則第-相 ΓίΓΐ 402藉由眼圖左邊界位置信號控制第二：f器Τ的輸出會減1，使得左相位内插輸出信號 --、目位^曰加，成為新的左相位内插輸出信號1250484 V. Description of the invention (10) The first 08 phase/two thousand displacement register 407 and the second displacement register 408 determine the bit to be added, the salt T\05, and the second phase interpolator 406 The output phase edge ϊ = motion / first phase lead behind the Na 402 production 404 generated Λ K K - L1 and the second phase leading backward detector: Λ 制 signal CLK-R1 will make the first displacement I w 分别M m two / temporary storage output eye left boundary position signal J 艮 right boundary position signal RW. The first - == (four) receiving the left edge position of the eye diagram signal coffee position k 5 tiger RW to output the same purpose to the same direction from the vertical ς ΡΤ τ 盘士士moving left phase interpolation output signal insertion output signal "1-R, That is, the eye diagram is left and n篦 is inflated. The opposite 'reset control circuit 20 5 produces: ff : Ϊ CU — L2 and the second reset signal CLK-R2 will make the first ί : After the detector 4 〇 2 and the second phase leading backward detector 4 0 4 艮Γ heart movement, that is, the i 2 of the left and right borders of the eye diagram: the way of inward retraction, outward extension, can The eye diagram opens the smallest left and right borders. Please refer to the 6th m: signal CLK-L1, CLK_R1, CLK_L2, clk_r2 and the left and right borders of the eye diagram. #& The way to find the left edge of the eye is: when the data vaporization occurs in the range to the left of the eye diagram, that is, the right side of the data age change phase interpolating signal S-PI-L, then The first phase Γ Γΐ 402 is controlled by the left edge position signal of the eye diagram: the output of the f Τ is decremented by 1, so that the left phase interpolates the output signal --- Becomes the new interpolated output signal phase left

1250484 五、發明說明（11) s/iVT，就是說脈波信號p的相位落後左相位内插輸出二PI—L的相位，則第一相位領先落後摘測器2〇6控制弟？:：内插器405 ’使得新的左相位内插輸出信號匕一 P I — L的相位增加。第3圓右由貝料说D支化的位置是在帛一相位内插器4 0 5經過 #3圖中的/ —差動信號轉單端信號電路（dsc_l)4 左邊’此時眼圖左邊會進入鎖住狀態( 狀 =3圖中的DFF —L1❺輸出所控制），使得左相位内插輸出h號S — PI L的相位不變。告目p岡士 i 須由下-欠眘牛Λ 左邊進入鎖住狀態， ::: 第一相位内插器405輸出左相位 >音务=* D號^1-1的右邊’也就是說脈波信號ρ的相位 :先左相位内插輸出信號S — PI—L的相位，才會解除鎖住狀化的=Ϊ,二哥找眼圖右邊邊界的方式為，資料信號D變化的位置疋在右相位内插輸出信號、pi R的左邊。 Ϊ位SI;憤測器4〇4藉由眼圖右邊界位置信刪控制一第一位移暫存器408輸出會加1，使得古 S-PI—R的相位減少，成為新的眼圖吏： = = = 波仏號P的相位領先左相位内插輸出信號s pi r的相位兄，氏 : = 先落後偵測器2〇7控制第二相位内插器4〇6，使付新的左相位内插輸出信號^耵^的相位減少。 W Λ資料信一號〇變化的位置是在第二相位内插器406經過 f /的太的毐第一差士動信號轉單端信號電路（DSC — L)410輸出 4口號的右邊，此時眼圖右邊合i隹人媒才r 口石違曰進入鎖住狀態（這個鎖住狀1250484 V. Description of invention (11) s/iVT, that is to say, the phase of the pulse signal p lags behind the left phase interpolated output. The phase of the second PI-L, the first phase leads the backward stalker 2〇6 control brother? The ::interpolator 405' causes the phase of the new left phase interpolated output signal 匕一 P I - L to increase. The third circle right is said by the shell material that the position of the D branch is in the first phase interpolator 4 0 5 through the #3 diagram / - differential signal to single-ended signal circuit (dsc_l) 4 left 'this eye diagram The left side will enter the locked state (like = DFF in the figure - L1 ❺ output control), so that the phase of the left phase interpolation output h number S - PI L does not change. The spectacle p gangs i must be locked from the left - under the cautious ox, the left side enters the locked state, ::: the first phase interpolator 405 outputs the left phase > the voice = * D the right side of the ^ 1-1 'that is Say the phase of the pulse wave signal ρ: the phase of the first left phase interpolated output signal S - PI - L will be unlocked = Ϊ, the second brother finds the right edge of the eye diagram, the data signal D changes Position 疋 in the right phase interpolates the output signal, to the left of pi R . Ϊ position SI; the anger detector 4 〇 4 by the right edge position of the eye map, the output of the first displacement register 408 will be increased by 1, so that the phase of the ancient S-PI-R is reduced, becoming a new eye 吏: = = = phase of the wave P is ahead of the phase of the left phase interpolated output signal s pi r brother: = first behind the detector 2〇7 controls the second phase interpolator 4〇6, making a new The phase of the left phase interpolated output signal ^耵^ is reduced. The position of the Λ 信信〇是是是 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 406 At the right of the eye, the right side of the eye is smashed into the locked state (this locked shape)

12504841250484

恶由第3圖中的DFF-R1的輪出所輸出信號S一PI 一R的相位不變。去，使得右相位内插須由下次資料信號D變化出現田&_圖右邊進入鎖住狀態，相位内插輸出信號s — pi—R的左—相位内插器405輸出右相位落後左相位内插輸—出信’ 說脈波信號P的住狀態。 —^ -L的相位，才會解除鎖然而，當資料信號D變化完全邊，例如鎖相迴咖接收的=邊或右變時或資料信號D變化的位置—直:C的脈頻率改The phase of the output signal S_PI_R is unchanged by the rotation of DFF-R1 in Fig. 3. Go, so that the right phase interpolation must be changed by the next data signal D. The right side of the field & _ enters the locked state, and the phase interpolated output signal s — pi — R of the left-phase interpolator 405 outputs the right phase behind the left. Phase interpolation input - message 'speaks' the state of the pulse signal P. The phase of -^ -L will unlock the lock. However, when the data signal D changes completely, for example, the phase or the right of the phase change is received or the position of the data signal D changes - straight: the pulse frequency of C is changed.

ΓίΓ二立内插器405或406無法對準眼圖的邊界因為 ί; 4=器4』7與第二位移暫存器408的輸入端χι與χ2 ΓΛ , HUNTER) ^ # ^ ::位移暫存器408另外的信號輪入來源。計數 m第τ3圖中的"_6送出—個脈波信號作；第-重 ί與第二重置信號CU，。由計數器提供的信 ^，其作用跟由資料信號D變化產生作為夕個鎖相迴路出信號CLK信號的作用不同，ΓίΓ Erli interpolator 405 or 406 cannot be aligned with the boundary of the eye diagram because ί; 4=4"7 and the input of the second displacement register 408 are χι and χ2 ΓΛ , HUNTER) ^ # ^ :: Additional signals from register 408 are clocked into the source. Counting m in the τ3 diagram, "_6 sends out a pulse signal; the first-weight and the second reset signal CU. The signal provided by the counter has a different effect from the change of the data signal D as a signal of the CLK signal of the phase-locked loop circuit.

=RCr^R)笛提供的第一重置信號CU-L2與第二重置信號 jK_R2不文第3圖中的DFF-L1與DFF-R1鎖住狀態的影變，輸入第—位移暫存器407與第二位移暫存器408，使侍第一相位内插器4 〇 5、第二相位内插器4 〇 6的輸出往遠離眼圖邊界的方向移動。換句話說，重置控制電路2〇5，用以於固疋期間後’重置眼圖左邊界位置信號產生器2 〇 6=RCr^R) The first reset signal CU-L2 and the second reset signal jK_R2 provided by the flute are not affected by the locked state of DFF-L1 and DFF-R1 in Fig. 3, and the input first displacement is temporarily stored. The 407 and the second shift register 408 move the outputs of the first phase interpolator 4 〇5 and the second phase interpolator 〇6 in a direction away from the boundary of the eye. In other words, the reset control circuit 2〇5 is used to reset the eye left position signal generator 2 〇 6 after the solid state period

12504841250484

及眼，右邊界位置信號產生器2 〇 7。〇第二部分’請參照第7圖，其繪示乃眼圖中心位置信號產生電路的實施電路圖。眼圖中心位置信號產生電路 203 包括一第三相位内插器（center phase interpolator) 901與一電壓控制延遲電路（vcdl)9〇2。第三相位内插器 9。0 1用以依據眼圖左邊界位置信號』、眼圖右邊界位置信唬RW與至少部分之至少部分之差動信號CLK_p〇〜 CLK —P6 ' CLK一NO〜CLK — N6，以產生眼圖中心位置信號 CE °電壓控制延遲電路9〇2，根據眼圖中心位置信號CE產生複數個相位不同之取樣信號。進一步說明，第三相位内插器9 0 1所接收到的眼圖左邊界位置信號Lw與眼圖右邊界位置信號RW經過第三相位内插器9 〇 1產生位於眼圖中心的資料取樣信號，再由7級的電壓控制延遲電路902輸出，去取樣每一個輸入時脈區間内的7筆資料。在這裡因為共有 24個控制信號，所以第三相位内插器9〇 1做相位内插的信號是差動信號CLK — P0〜CLK — P6、CLK —N0〜CLK —N6中的間隔信號（例如CLK — P5、CLK一P0)。而第一相位内插器405與第二相位内插器4 0 6因只有1 2個控制信號，所以做相位内插的信號是差動信號CLK_P0〜CLK_P6、CLK —N0〜CLKJ6 的相鄰信號（例如CLK一P5、CLK — P6)。請參照第8圖，其繪乃原取樣信號與藉由本發明產生的取樣信號的比較圖。藉由程式模擬資料信號D經過傳輸之後，資料區間的位置落後時脈信號區間對應的位置，亦即資料信號D變化一直在眼圖的左邊。原先資料取樣位置為D1，經過本發明之電路And the eye, the right boundary position signal generator 2 〇 7. 〇 Part 2 'Please refer to Figure 7, which shows the circuit diagram of the implementation of the eye center position signal generation circuit. The eye center position signal generating circuit 203 includes a third phase interpolator 901 and a voltage control delay circuit (vcdl) 9〇2. The third phase interpolator 9. 0 1 is used according to the left edge position signal of the eye diagram, the right border position signal RW of the eye diagram and at least part of at least part of the differential signal CLK_p 〇 CLK CLK — P6 ' CLK — NO 〜 CLK — N6 to generate an eye center position signal CE ° voltage control delay circuit 9〇2, and generate a plurality of sampling signals having different phases according to the eye center position signal CE. Further, the eye left boundary position signal Lw and the eye right border position signal RW received by the third phase interpolator 902 generate a data sampling signal at the center of the eye through the third phase interpolator 9 〇1. Then, the voltage control delay circuit 902 of the 7th stage outputs, and samples 7 data in each input clock interval. Here, since there are 24 control signals, the phase interpolation signal of the third phase interpolator 9〇1 is the interval signal in the differential signal CLK_P0~CLK_P6, CLK_N0~CLK-N6 (for example) CLK — P5, CLK — P0). Since the first phase interpolator 405 and the second phase interpolator 406 have only 12 control signals, the signals for phase interpolation are adjacent signals of the differential signals CLK_P0 CLK_P6 and CLK —N0 CLK CLKJ6. (eg CLK-P5, CLK-P6). Referring to Figure 8, a comparison of the original sampled signal with the sampled signal produced by the present invention is shown. After the program analog data signal D is transmitted, the position of the data interval falls after the position corresponding to the clock signal interval, that is, the data signal D changes to the left of the eye diagram. The original data sampling position is D1, and the circuit of the present invention

TW1748F(友達）.ptd 第17頁 1250484 五、發明說明（14) 後可將取樣位置移 (setup time)比原為資料取樣的設定料。本發明上述實相位領先落後偵測時脈資料回復裝置輸之後，仍然可以位置，可改善傳輸題，使得接收資料綜上所述，雖然其並非用以限定本發明之精神和範本發明之保護範圍準。施例所器與相的設計將資料資料信信號的然本發本發明圍内，當視後揭露之位内插 ’可以信號的號時所正確性明已以 ’任何當可作附之申時脈資器作為解決資讀取位造成的提高與一較佳熟習此各種之請專利為Bj，可看出新取樣位置β1的設定時間先單純鎖項迴路產生的時脈信號D1作時間時間*，因此可以更正確的讀到資料回復裝置，利用低電壓差動信號之料信號經過通道傳置至於眼圖的中心雜訊與不同步的問降低錯誤率。實施例揭露如上，技藝者，在不脫離更動與潤飾，因此範圍所界定者為TW1748F (Friends).ptd Page 17 1250484 V. Inventive Note (14) The sampling position can be set later than the original data sampling setting. After the real phase leading backward detection clock data recovery device of the present invention can still be positioned, the transmission problem can be improved, so that the receiving data is comprehensive, although it is not intended to limit the scope of the present invention and the scope of protection of the invention. quasi. The design of the device and the phase of the application is to send the data of the information signal to the invention. When the position of the post-exposure is inserted, the correctness of the signal can be used. As a result of the improvement of the reading position of the time processor and a better familiarity of the various patents as Bj, it can be seen that the set time of the new sampling position β1 is the time signal of the clock signal D1 generated by the simple locking circuit. *, so the data recovery device can be read more correctly, and the material signal of the low voltage differential signal is transmitted through the channel to the center of the eye image and the asynchronous noise is reduced. The embodiment discloses that, as the skilled person does not deviate from the change and retouching, the scope is defined by

1250484 圖式簡單說明第1圖繪示乃依照本發明_ 差動信號之時脈資料回 —較佳貝施例的一種低電壓第2圖緣示乃鎖相迴V的置第3圖繪示乃資斜、喜緣的貝靶電路圖。電路圖。、；、、、產生斋與雙邊追蹤電路的實施目：内插器的實施電路圖。第6圖繪示 7位内1器4 05模擬的輸出波形圖。跟眼圖左、右邊ΛΐΚ1。、· —R1、C_ 圖。回乃眼圖中心位置信號產生電路的實施電路第8圖纟會示乃馬號的比較圖。、’彳§號與藉由本發明產生的取樣信第9圖纷示只士 _ 第10圖綠示心動貝：回:九置，結構圖。電路。 a k轉早端h號電路的一較佳實施圖式標號說明 200 :時脈資料回復裝置 2 〇 1 ··鎖相迴路 202 :雙邊追縱電路 203 :眼圖中心位置信號產生電路 204 :資料邊緣產生器 205 :重置控制電路 2〇6 :眼圖左邊界位置信號產生器1250484 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a clock signal of a differential signal according to the present invention. A low voltage of the preferred embodiment is shown in FIG. 3, which is a phase lock return V. It is a circuit diagram of the shell target of the slanting and happy edge. Circuit diagram. ,;,,, and the implementation of the circuit and the bilateral tracking circuit. Objective: The circuit diagram of the implementation of the interpolator. Figure 6 shows the output waveform of the 7-bit analog 4 05 analog. ΛΐΚ1 with the left and right sides of the eye. , · —R1, C_ diagram. The implementation circuit of the signal generating circuit at the center of the eye is shown in Fig. 8. The comparison chart of the horse is shown. , '彳§号 and the sampling letter produced by the present invention. Figure 9 shows the _ _ 10th green display heartbeat: back: nine sets, structure diagram. Circuit. A preferred embodiment of the ak to early h circuit No. 200 description: clock data recovery device 2 〇 1 · phase locked circuit 202: bilateral tracking circuit 203: eye center position signal generating circuit 204: data edge Generator 205: reset control circuit 2〇6: eye diagram left boundary position signal generator

TW1748F(友達）.ptd 第19頁 1250484 圖式簡單說明 207 眼圖右邊界位置信號產生器 301 偏壓產生器 302 相位頻率比較器 303 充放電電路 304 複製偏壓電路 305 電壓控制震盪器 402 第一的相位領先落後偵測器 404 第二的相位領先落後偵測器 405 第一相位内插器 406 第二相位内插器 407 第一位移暫存器 408 第二位移暫存器 306〜312、409、410 :差動信號轉單端信號電路 9 0 1 ··第三相位内插器 902 :電壓控制延遲電路TW1748F (友达).ptd Page 19 1250484 Schematic description 207 Eye right position signal generator 301 Bias generator 302 Phase frequency comparator 303 Charge and discharge circuit 304 Copy bias circuit 305 Voltage control oscillator 402 One phase leading backward detector 404 second phase leading backward detector 405 first phase interpolator 406 second phase interpolator 407 first displacement register 408 second displacement register 306~312, 409, 410: differential signal to single-ended signal circuit 9 0 1 · · third phase interpolator 902 : voltage control delay circuit

TW1748F(友達）.ptd 第20頁TW1748F ( AUO).ptd第20页

Claims

1250484 /、、申請專利範圍脈信1 號回了Λ電接壓信號之時脈信號回復裝置，^ ，係屬於該低電壓差動信號，該時脈赵加—鎖相迴路，係用以接收該外部來考俨铼鎖相迴路輸出信號，該些鎖相路二二輪出複分別I: 的頻率相同，而該些鎖相迴路輪出ii 刀別具有不同之相位；别出指唬係 . 雙邊追蹤電路’係接收至少部分之該此锆士、信號，並根據該資料信號所產生之一脈波；號】：路輪 :=，出信?虎，以輸出一眼圖左邊界位步:：二^ 右邊界位置信號；以及眼圖一眼圖中心位置信號產生電路，係用以目迴路輸出純，該眼圖中心位置信號J = 玉依據該眼圖左邊界位置信號與該眼圖右邊界位啤路 ^眼圖中心位置信號，該眼圖中心位置信號產生^ 根據該眼圖中心位置信號輸出該資料信號之複數個更同之一取樣信號。位不 2·如申請專利範圍第1項之裝置，其中，該鎖相迴敗包括：號一相位頻率比較器，係用以比較該外部參考信號與該些鎖相迴路輸出信號之一，以產生一充電/放電控制信、Μ 充放電電路，係根據該充電/放電控制信號以得1250484 /,, the patent application scope of the pulse letter No. 1 back to the clock signal recovery device of the electric signal, ^, belongs to the low voltage differential signal, the clock Zhao Jia - phase-locked loop, is used to receive The external reference to the phase-locked loop output signal, the two phases of the phase-locked circuit are the same as the frequency of the I: respectively, and the phase-locked loops have different phases of the ii-knife; The bilateral tracking circuit 'receives at least part of the zirconium, the signal, and generates a pulse according to the data signal; number:: road wheel: =, writes a letter to the tiger, to output a left edge position of the eye diagram ::2^ right boundary position signal; and eye diagram one eye center position signal generation circuit, which is used for the eye loop output pure, the eye center position signal J = jade according to the eye left position signal and the eye right The boundary position beer road ^ eye center position signal, the eye center position signal generation ^ outputs a plurality of more identical sampling signals of the data signal according to the eye center position signal. The device of claim 1, wherein the phase-locked return includes: a phase-frequency comparator for comparing the external reference signal with one of the phase-locked loop output signals to Generating a charge/discharge control signal, a charge and discharge circuit, based on the charge/discharge control signal

第21頁 TW1748F(友達）.ptd 1250484 六、f請專利範圍一第一輸出電壓；以得到一二複製偏壓電路，係複製第二輪出電壓，·以及乐輸出電壓，一電壓控制震盪哭，技4日4去_ 輸出電壓輪出該些鎖；迴路輸匕二一輪出電璧與該第二震盈器更包括串接之複數個差動U轉單：：：電壓控制 :的-第—組差動信號轉單端们虎電㉟“電路所構狀態時，m且差動信號轉|端信；電U迴路於鎖相迴路輸出信號，若該外部 u 輪出該些至n個資料位元區間，n #為正敕數；：的：f週期係對應相迴路輸出信號之相二=度則-個相鄰之該Μ 電路4包括如申請專利範圍第3項之裝置，其，’該雙邊追蹤邊緣ίΠί;ί生器，係用以接收該資料信號，該資料一生的根據該資料信號之邊緣產生一脈波作號· 些鎖：邊，置信號產生器，係接收至工；分之該位詈作 *出仏號與該脈波信號，以輸出該眼圖左邊界 °〜’該眼圖左邊界位置信號產生器包括：鎖相迴败二第一相位内插器，係用以接收至少部分之該些雨出信號與該眼圖左邊界位置信號，以輪出一左相位内Mawtu X輸出左 —第一相位領先落後债測器’係用以接收該脈波口 ^、至少部分之該些鎖相與迴路輸出信號與該左相位内Page 21 TW1748F ( AUO). ptd 1250484 VI, f please patent range a first output voltage; to get a two copy bias circuit, copy the second round of output voltage, · and music output voltage, a voltage control oscillation Cry, skill 4th 4 go _ output voltage turns out the locks; loop output 匕 2 rounds of power 璧 and the second oscillator also includes a series of differential U-turns::: voltage control: - the first group of differential signals to the single-ended us Tiger 35 "circuit state, m and differential signal turn | terminal letter; electric U loop in the phase-locked loop output signal, if the external u wheel out To n data bit intervals, n # is a positive number;:: f period is the phase of the phase loop output signal corresponding to the second degree = then the adjacent one of the circuit 4 includes the third item of the patent application scope The device, the 'bilateral tracking edge' is used to receive the data signal, and the data generates a pulse wave according to the edge of the data signal for a lifetime. Some locks: edge, set signal generator, Receiving the work; dividing the position by the * nickname and the pulse signal to The left edge position of the eye diagram is reduced to: the left edge position signal generator of the eye diagram comprises: a phase lock returning first phase interpolator for receiving at least part of the rainout signals and a left boundary of the eye diagram Position signal to rotate the left phase of the Mawtu X output left - the first phase leading backward debt detector is used to receive the pulse port ^, at least part of the phase lock and loop output signals and the left phase

1250484 六、申請專利範圍插輪出信號，以輪出該内插器依據該眼圖左邊界：=以信號’該信號； |位置^號调整該左相位一眼圖右邊界位些鎖相迴路輸出_ δ〜產生态，係接收i少位置信號，該脈波信號，以輪出該眼一第眼圖右邊界位置信號產生器包括：輪出信號與該眼圖右==少：相位内插輪出信號；及置l旒，以奸咕一第二相位領先落後偵測器，係田以接 « k、至少部分之該4b ’、輪出俨觫^ —貝w、路輪出信號與該右七旒以輪出該眼圖右邊界位置传妒，兮第號；以及口右還界位置^旎調整該右相位内、重置控制電路，用以於一固定期間後，涵左邊界位置^號產生器及該眼圖右邊界位置信韻 5·如申請專利範圍第4項之裝置，其中f驾位置信號產生電路包括：第二相位内插器，係用以接收該眼圖左邊號、該眼圖右邊界位置信號與至少部分之該些韻出信號，以產生該眼圖中心位置信號；以及一電壓控制延遲電路，根據該眼圖中心位置複數個相位不同之該取樣信號。 6 ·如申請專利範圍第5項之裝置，其中，該第一相位内插輸出部分之該圖右邊界分之該些輸出一右收該脈波相位内插二相位内插輸出信置該眼圖 >產生器。眼圖中心界位置信相迴路輸信號產生. 重置控制 1250484 六、申請專利範圍電路包括一個計數器，該計數器係接收該資料信號，當該計數器於該固定期間内接收固定個數之該資料信號後，該重置控制電路輸出一第一重置信號與一第二重置信號至該眼圖左邊界位置信號產生器及該眼圖右邊界位置信號產生器。 7·如申請專利範圍第6項之裝置，其中，該第一相位領先落後偵測器根據二個該些鎖相迴路輸出訊號產生一第一區間俏號’該第一區間信號致能時，該第一相位領先落後偵測器比較該脈波信號的相位與該左相位内插輸出信號的相位，若該脈波信號的相位落後該左相位内插輸出信號的相位，則該第一相位領先落後偵測器控制該第一相位内插器’使得該左相位内插輸出信號的相位增加，反之，則不改變該左相位内插輸出信號的相位。 8·如申請專利範圍第7項之裝置，其中，該第一相位領先落後偵測器接收該第一重置信號，當該第一重置信號致能時’則眼圖左邊界位置信號控制該第一相位内插器，使得該左相位内插輸出信號的相位減少。 9二如申請專利範圍第6項之裝置，其中，該第二相位領，落後偵測器根據二個該些鎖相迴路輪出訊號產生/第〔門仏s虎該第_區間信號致能時，該第二相位領先’备後偵測器比較該脈波信號的相位與該右相位内插輸出信號的相位，若該脈波信號的相位領先該左相位内插輸出信號的1位，則該第二相位領先落後偵測器控第二相位内插器，使得該右相位内插輸出信號的相位減=，反之，則1250484 VI. Applying for the patent range to insert the signal, to rotate the interpolator according to the left boundary of the eye diagram: = adjust the left phase of the left phase of the left phase of the phase-locked loop output by the signal 'the signal; _ δ ~ generation state, receiving i less position signal, the pulse wave signal to rotate the eye to the right eye position of the first eye position signal generator comprises: the wheel out signal and the eye picture right == less: phase interpolation Turn out the signal; and set l旒, to sneak a second phase leading backward detector, the field to pick up «k, at least part of the 4b', turn out 俨觫^-bei w, road round out signal and The right seventh 旒轮旒该 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Position ^ generator and the right boundary position of the eye diagram 5: The device of claim 4, wherein the driving position signal generating circuit comprises: a second phase interpolator for receiving the left side of the eye Number, the right border position signal of the eye diagram and at least part of Yun the plurality of signals to generate the center of the eye location signals; and a voltage controlled delay circuit, a plurality of different phases of the sampled signal according to the position of the center of the eye. 6. The device of claim 5, wherein the first phase interpolating output portion of the right edge of the graph is divided into the output and the right is received by the pulse phase interpolating the two-phase interpolated output signal to the eye Figure > Generator. The eye center position position signal loop signal is generated. Reset control 1250484 6. The patent scope circuit includes a counter that receives the data signal, and receives a fixed number of the data signal during the fixed period. Thereafter, the reset control circuit outputs a first reset signal and a second reset signal to the eye left boundary position signal generator and the eye right border position signal generator. 7. The device of claim 6, wherein the first phase leading backward detector generates a first interval message according to the output signals of the two phase locked loops, wherein the first interval signal is enabled. The first phase leading backward detector compares the phase of the pulse signal with the phase of the left phase interpolated output signal. If the phase of the pulse signal lags behind the phase of the left phase interpolated output signal, the first phase The leading backward detector controls the first phase interpolator 'to increase the phase of the left phase interpolated output signal, and vice versa, does not change the phase of the left phase interpolated output signal. 8. The device of claim 7, wherein the first phase leading backward detector receives the first reset signal, and when the first reset signal is enabled, the left edge position signal control of the eye diagram The first phase interpolator reduces the phase of the left phase interpolated output signal. 9) The device of claim 6, wherein the second phase collar and the trailing detector generate the signal according to the two phase-locked loops, and the first threshold is enabled. The second phase leads the 'pre-detector to compare the phase of the pulse signal with the phase of the right phase interpolated output signal. If the phase of the pulse signal leads the 1-bit of the left phase interpolated output signal, Then the second phase leads the backward detector to control the second phase interpolator, so that the phase of the right phase interpolated output signal is reduced by minus, otherwise,

1250484 六、申請專利範圍不改變# 文為右相位内插輸出信號的相位。位領1弁如申請專利範圍第9項之裝置，其中’該第-士號致能則器接收該第二重置信號，當該第二重〜置仁器、，丄ΞΓ艮圖右邊界位置信號控制該第二相：3 丨，該右相位内插輸出信號的相位增加。4内插邊緣產生；！：專圍第4項之之裝置，其中，該資料第-輪入；；延；電路、—互斥間，該互斥閑具有端接收該U一輸入端與一輪出#，該延遲電路Jr Z貝枓’該延遲電路路的— 亥弟二輪入端接收該資料柒耦接該弟一輪入輸出1該脈波信號。 ^^唬，該互斥閉之該輪出端於-2脈：tjf㊁動信號之時脈信號回復的方法，用外部參考信號與—資U時脈信號回復褒置用以接收用 j相迴路、—資哭該時脈信號回復裝置包妾：：電:位-置：圖”生電路，^邊以::括電？與1圖信號產生器：：2，置信號產生器與_眼圖右：f控制以輪出H:號，該資料邊緣產；C出複數少部分哕此f 唬，該眼圖左邊界π w /DQ接該資料信號位心：出信號=:==器接收至邊界位置信號：眼圖左邊界位置；產二-左相 -~位内指輸出信號與輪：― HV174SF(友達）.Ptd 第25頁 1250484 “、申請專利範圍 —___— —___ 右邊界位置信號，該部分該些鎖相迴路輸出:〜位置信號產生電路接收至少 ”路依據該眼圖左邊二；且該眼圖中心位置刪 k以產生一眼圖中心位。唬與該眼圖右邊界位置信跡形成一眼圖，該方法包^ ^，該資料信號的信號變化軌 a•藉由比較該脈波作龍的相I，得到該：邊u只目位與該左相位内插輸出信 % b.藉由比較該脈波信立置信號；犰的相位，得到該眼圖右邊u»目位與該右相位内插輸出信 c.藉由該眼圖左邊界位置二5信號；唬，找出該眼圖的中心位 ^唬與該眼圖右邊界位置信生該眼圖中心位置信號；以及並根據該眼圖的中心位置產 d•根據該眼圖中心位個相位不同之一取樣信號；a唬，產生該資料信號之複數其中’該些鎖相迴路輪屮 =的頻率相同，而該些鎖相以==部參考信位，输出仏说係具有不同之相料信號L ’個若資該：位部參號的-信號^ 該些鎖相、枓凡區間，n係為正整數，則二個相鄰之、、 <路輸出信號之相位差為360/2n度。該會署3·如如申請專利範圍第12項之方法’其中’該方法使户卞:制電路具有一個計數器，該計數器係接收該資料後當一固定期間内接個數“資料 μ重置控制電路分別輸出一弟一重置信號與_第1250484 VI. Scope of application for patents No change # The text is the phase of the right phase interpolated output signal. The device of claim 9, wherein the first-signal enabler receives the second reset signal, and when the second weight is placed, the right border of the map The position signal controls the second phase: 3 丨, the phase of the right phase interpolated output signal increases. 4 interpolation edge generation;! : the device of the fourth item, wherein the data is first-rounded; the extension; the circuit, the mutual exclusion, the mutually exclusive idle end receives the U-input and the round-out #, the delay circuit Jr Z Bellow's the delay circuit - the Haidi two-input receiver receives the data and couples the pulse to the output of the pulse. ^^唬, the method of recovering the clock signal of the two-pulse: tjf two-signal signal from the end of the mutex is used to receive the j-phase loop with the external reference signal and the U-clock signal recovery device. , - crying the clock signal recovery device package:: electricity: bit - set: map "sheng circuit, ^ side to:: include electricity? and 1 map signal generator:: 2, set signal generator and _ eye Right: f control to rotate the H: number, the edge of the data is produced; C is a small part of the complex number 哕, the left edge of the eye is π w / DQ connected to the data signal center: the signal =:== Received to the boundary position signal: the left boundary position of the eye diagram; the production second-left phase-~bit inner finger refers to the output signal and the wheel: ― HV174SF ( AUO). Ptd Page 25 1250484 “, patent application scope — ___ — — ___ right border Position signal, the part of the phase-locked loop outputs: - the position signal generating circuit receives at least "the road according to the left side of the eye diagram; and the center position of the eye diagram deletes k to generate an eye center position. 唬 and the right border of the eye diagram The location trace forms an eye diagram, and the method includes ^^, the signal change track of the data signal a•borrow Comparing the phase I of the pulse wave to obtain the edge: the edge u only the target bit and the left phase interpolated output letter % b. by comparing the pulse wave standing signal; the phase of the ,, obtaining the right side of the eye diagram » the target position and the right phase interpolated output signal c. by the left boundary position of the eye diagram, the second 5 signal; 唬, find the center position of the eye diagram and the right boundary position of the eye diagram to generate the eye center a position signal; and according to the center position of the eye diagram, d: sampling a signal according to one of the phases of the center of the eye; a唬, generating a plurality of the data signal, wherein the frequency of the phase-locked loop rim= The same, and the phase locks have the reference signal of the == part, and the output 仏 says that there are different phase signals L 'single: the signal of the bit part parameter - the phase lock, the interval, n The system is a positive integer, and the phase difference between the two adjacent, < road output signals is 360/2n degrees. The Department 3, as in the method of claim 12, wherein 'the method makes the household The circuit has a counter that receives the data and receives the number during a fixed period. Information μ reset control circuit outputs a reset signal to a brother of _

第26頁 1250484 /、、申请專利範圍 :重置信號至該眼圖左邊界位置信號產生器及該眼圖右邊界位置信號產生器。 1 4·如申晴專利範圍第1 3項之方法，其中，該方法使 1眼圖左邊界位置信號產生器更包括一第一相位領先落後 ί測!5與一第一相位内插器，該第-相位領先落後偵測器珣出:亥眼圖左邊界位置信號，該第一相位内插器根據該眼圖左邊界位置信號以輪出該左相位内插輸出信號。 ^ 1 5 · +如申請專利範圍第1 4項之方法，其中，該方法步驟a中’藉由該第一相位領先落後偵測器比較該脈波信號的相位與該左相位内插輸出信號的相位，當該脈波信號的相位落後該左相位内插輪出信號的相位，則增加該左相位 1插輸出信號的相位，反之，則不改變該左相位内插輸出信號的相位。 16·如=請專利範圍第丨5項之方法，其中，根據該第相位項先落後偵測裔輪出之該眼圖左邊界位置信號增加該左相位内插輸出信號的相位。口曰一申請專利範圍第16項之方法，其中，根據該第一重置指號減少該左相位内插輸出信號的相位。 18·如申請專利範圍第1 7項之方法，其中，該眼圖左邊界位置信號對應該眼圖的一左邊界。 19·如申請專利範圍第18項之方法，其中，該方法使該眼圖右邊界位置信號產生器更包括一第二相位領先落後偵測器與一第二相位内插器，該第二相位領先落後偵測器輸出該眼圖右邊界位置信號，該第二相位内插器根據該眼Page 26 1250484 /, patent application scope: reset signal to the left edge position signal generator of the eye diagram and the right position signal generator of the eye diagram. 1 4. The method of claim 13, wherein the method further comprises a first phase leading signal generator comprising a first phase leading backwards, and a first phase interpolator, The first phase leading backward detector detects: a left edge position signal of the eye diagram, and the first phase interpolator rotates the left phase interpolation output signal according to the left boundary position signal of the eye. ^ 1 5 · + The method of claim 14, wherein in the method step a, 'the phase of the pulse signal is compared with the left phase interpolated output signal by the first phase leading backward detector The phase is such that when the phase of the pulse signal lags behind the phase of the left phase interpolating wheel signal, the phase of the left phase 1 interpolated output signal is increased, and conversely, the phase of the left phase interpolated output signal is not changed. 16. The method of claim 5, wherein the phase of the left phase interpolated output signal is increased according to the left phase position signal of the eye diagram that the first phase term is behind. The method of claim 16, wherein the phase of the left phase interpolated output signal is reduced according to the first reset indicator. 18. The method of claim 17, wherein the left boundary position signal of the eye corresponds to a left boundary of the eye. The method of claim 18, wherein the method further comprises: the second phase leading edge detector and the second phase interpolator, the second phase The leading backward detector outputs a right boundary position signal of the eye, and the second phase interpolator according to the eye

TW1748F(友達）.ptd 第27頁 1250484 —一1〜六、申請專利範園圖右邊界位置信號以輪 20·如申社直如〜 μ右相位内插輸出信號。驟b中，藉由該第乾圍第19項之方法’其中，該方法牛的相位與該右相位内插立二先落後偵測器比較該脈波信號^ 相位領先該右相：，號的相位’當該脈波信號的内插輸出信號的相& 信號的相位，則減少該右相位信號的相位。反之，則不改變該右相位内插輪出二相【領項之方法…，根據該第該右相位内插輸出;^:二:該眼圖右邊界位置信號減少一 22·二如申請專利範圍第21項之方法，其 — 二1信號增加該右相位内插輸出信號的：位。χ “第 .如申請專利範圍第22項之方法，直中，# 邊界位置信號對應該眼圖的一右邊界。-中肖眼圖右 2 4.。如申請專利範圍第23項之方法其中，診的輸出信號與該第二相位内插器的輸出;:铲將4 決定該眼圖最小的該左邊界與該右邊界。 “虎將可 —25.如申請專利範圍第24項之方法其中，該 :亡該重置電路以使該第一相位内插器之該左相位内插 ^唬的巧位與該第二相位内插器之該右相位内插輸出‘ 號的相位遠離該眼圖的相位中心移動。 ° 2 6·如申請專利範圍第2 5項之方法，直中，該方該眼圖中心位置信號產生電路包括_第三相位内：哭盘二電壓控制延遲電路，第三相位内插器耦接該電壓控制延遲第28頁 TW1748F(友達）.Ptd 1250484 六、申請專利範圍電路。 2 7·如申請專利範圍第2 6項之方法，其中，該方法步驟c中’藉由該第三相位内插器接至少收部分該些鎖相迴路輪出信號’並根據該眼圖左邊界位置信號與該眼圖右邊界位置信號以輸出該眼圖中心位置信號。 2 8·如申請專利範圍第2 7項之方法，其中，該方法步驟c中，藉由該電壓控制延遲電路接收該眼圖中心位置信號輸出該資料信號之複數個相位號。以接收一資料信號與_外^ j =知脈資料回復的方法，用變化執跡形成一眼圖，該資=考信號，該資料信號的信號間，該方法係用以在該i ^ 2號包括七個資料位元區位置信號，該方法包括：的一中心位置產生一眼圖中心 a ·藉由該外部參考信鍊，、些鎖相信號的頻率與該外部表以產生複數個鎖相信號，該鎖相迴路輸出信號係具有尤j考仏號的頻率相同，而該些 β个同之^ . b·藉由在該資料信號由古、 ’ 為高位準的位置產生一脈诔=位準變為低位準與低位準變 c·藉由相鄰的二個該些出信號負相彳§號產生一左相位内插輸 d·藉由另外相鄰的二個# 插輸出信號； μ t鎖相信號產生一右相位内 e·藉由比較該脈波信蜆的號的相位，找出該眼圖的_ + 位與該左相位内插輸出信左邊界；TW1748F (友达).ptd Page 27 1250484 —1~6. Apply for a patent. The right border position signal is round. 20·If Shenshe is as straight as ~ μ right phase interpolates the output signal. In the step b, by the method of the 19th item of the traverse, wherein the phase of the method is compared with the phase of the right phase interpolated by the first detector, the pulse signal is phased to lead the right phase: Phase 'When the pulse signal interpolates the phase of the output signal and the phase of the signal, the phase of the right phase signal is reduced. Conversely, the right phase interpolation wheel does not change the two phases [the method of the collar item... according to the first right phase interpolation output; ^: two: the right border position signal of the eye diagram is reduced by one 22·2 as claimed The method of claim 21, wherein the two 1 signal increases the bit of the right phase interpolated output signal. χ “#. For the method of claim 22, the straight line, # boundary position signal corresponds to a right boundary of the eye diagram. - The middle eye diagram is right 2 4. As in the method of claim 23, The output signal of the diagnosis and the output of the second phase interpolator; the shovel 4 determines the left boundary of the eye diagram and the right boundary. "The tiger will be -25. , the reset circuit is such that the phase of the left phase interpolation of the first phase interpolator and the phase of the right phase interpolation output of the second phase interpolator are far from the eye The phase center of the graph moves. ° 2 6 · If the method of claim 25, the method of the eye center position signal generation circuit includes: _ third phase: crying disk two voltage control delay circuit, third phase interpolator coupling Connect the voltage control delay on page 28 TW1748F (AUO). Ptd 1250484 VI. Apply for a patent range circuit. The method of claim 26, wherein in the method step c, 'the third phase interpolator is connected to at least a portion of the phase-locked loops to turn off the signal' and according to the eye diagram The boundary position signal and the eye right border position signal output the eye center position signal. The method of claim 27, wherein in the method step c, the voltage control delay circuit receives the eye center position signal to output a plurality of phase numbers of the data signal. In order to receive a data signal and _ external ^ j = know pulse data reply method, use the change to form an eye diagram, the resource = test signal, the signal of the data signal, the method is used in the i ^ 2 Including seven data bit position signals, the method includes: a center position to generate an eye center a · by the external reference chain, the frequency of the phase lock signals and the external table to generate a plurality of phase lock signals The phase-locked loop output signal has the same frequency as the 仏仏 , and the β 同 ^ ^ 藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉藉The quasi-low-level and low-level quasi-change c· generates a left-phase interpolation input d by the adjacent two negative signals of the signals · §, and outputs signals by two adjacent adjacent plugs; μ The t phase-locked signal generates a right phase. e. by comparing the phase of the pulse signal signal, finding the _+ bit of the eye diagram and the left boundary of the left phase interpolation output signal;

1250484 六、申請專利範圍 f .藉由比較該脈波信號的相位與該右相位内插輸出信號的相位，找出該眼圖的一右邊界；以及 d.藉由相隔的二個該些鎖相信號、該左邊界與該右邊界，找出該眼圖的中心位置，並在該眼圖的中心位置產生該眼圖中心位置信號；其中，該些鎖相信號的相位分別對應該資料信號之該七個資料位元區間；其中，該眼圖中心位置信號係用以做為該資料信號之取樣信號。1250484 6. Patent application range f. Find a right boundary of the eye by comparing the phase of the pulse signal with the phase of the right phase interpolation output signal; and d. by the two locks separated by a phase signal, the left boundary and the right boundary, finding a center position of the eye diagram, and generating a center position signal of the eye diagram at a center position of the eye diagram; wherein phases of the phase lock signals respectively correspond to the data signals The seven data bit intervals; wherein the eye center position signal is used as a sampling signal of the data signal.

TW1748F(友達）.ptd 第30頁TW1748F ( AUO).ptd第30页