TW202038437A - Line bending control for memory applications - Google Patents

Line bending control for memory applications Download PDF

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TW202038437A
TW202038437A TW108142704A TW108142704A TW202038437A TW 202038437 A TW202038437 A TW 202038437A TW 108142704 A TW108142704 A TW 108142704A TW 108142704 A TW108142704 A TW 108142704A TW 202038437 A TW202038437 A TW 202038437A
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deflection
reducing
memory cell
character
character line
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TWI837224B (en
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戈倫 布泰爾
思魯提 湯貝爾
可里伊許特克
克林帕 派崔克 凡
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美商蘭姆研究公司
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Abstract

A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.

Description

記憶體應用之線撓曲控制Line deflection control for memory applications

本申請案請求以下優先權：於2018年11月30日提交之美國臨時申請案第62/773,689號。上方引用之申請案的整體揭示內容通過引用於此納入。This application claims the following priority: US Provisional Application No. 62/773,689 filed on November 30, 2018. The entire disclosure of the application cited above is hereby incorporated by reference.

本揭露相關於基板處理系統，且更特別是，相關於在記憶體應用中控制線撓曲的方法。The present disclosure is related to substrate processing systems, and more particularly, to methods of controlling wire deflection in memory applications.

此處所提供之先前技術描述係為了一般性呈現本揭露之背景的目的。本案列名發明人的工作成果，在此先前技術段落中所述範圍以及不適格為申請時先前技術的實施態樣，不明示或暗示承認為對抗本揭露內容的先前技術。The prior art description provided here is for the purpose of generally presenting the background of this disclosure. The work results of the inventors listed in this case, the scope and ineligibility described in this prior art paragraph are the implementation aspects of the prior art at the time of application, and are not expressly or implicitly recognized as prior art against the content of this disclosure.

諸如膝上型電腦、平板電腦、智慧型手機等等的電子裝置包含諸如動態隨機存取記憶體（DRAM）或垂直NAND（VNAND）記憶體的記憶體。記憶體一般係以包含記憶單元之積體電路（IC）加以實施。隨著電子裝置尺寸上持續縮小且使用更多資料，記憶體單元的成本、密度及存取速度變得更加重要。因此，特徵尺寸已顯著縮小且深寬比已提高。Electronic devices such as laptop computers, tablet computers, smart phones, etc. include memory such as dynamic random access memory (DRAM) or vertical NAND (VNAND) memory. Memory is generally implemented as an integrated circuit (IC) containing memory cells. As electronic devices continue to shrink in size and use more data, the cost, density, and access speed of memory units become more important. Therefore, the feature size has been significantly reduced and the aspect ratio has been improved.

在諸如半導體晶圓之基板上進行沉積及／或蝕刻的基板處理系統一般包含具有支座的處理腔室。在處理過程中基板係配置於該支座上。可將包含一或更多前驅物的處理氣體混合物引入處理腔室，以在基板上沉積一層或是蝕刻基板。在某些基板處理系統中，可將射頻（RF）電漿在處理腔室中引燃及／或可將支座上的RF偏壓用以激發化學反應。A substrate processing system that performs deposition and/or etching on a substrate such as a semiconductor wafer generally includes a processing chamber with a support. The substrate is arranged on the support during the processing. A processing gas mixture containing one or more precursors can be introduced into the processing chamber to deposit a layer on the substrate or to etch the substrate. In some substrate processing systems, radio frequency (RF) plasma can be ignited in the processing chamber and/or the RF bias on the support can be used to stimulate chemical reactions.

一種減少在記憶體單元中字元線撓曲的方法，包含：（a）提供一基板，該基板包括複數字元線，該複數字元線係配置成與彼此相鄰並在複數電晶體上方；（b）使用一沉積製程在該複數字元線上沉積一層膜；（c）在沉積該層膜之後，量測字元線撓曲；（d）將該字元線撓曲與一預定範圍相比較；（e）基於該字元線撓曲，調整該沉積製程之成核延遲及晶粒尺寸的至少其中一者；及（f）使用一或更多基板分別重複（b）到（e）一或更多次，直到該字元線撓曲在該預定範圍內。A method for reducing the deflection of character lines in a memory cell includes: (a) providing a substrate, the substrate including complex number element lines, the complex number element lines are arranged adjacent to each other and above the plurality of transistors; (B) Use a deposition process to deposit a layer of film on the complex digital element line; (c) after depositing the layer of film, measure the character line deflection; (d) the character line deflection to a predetermined range Compare; (e) adjust at least one of the nucleation delay and grain size of the deposition process based on the deflection of the character line; and (f) repeat (b) to (e) using one or more substrates One or more times, until the character line is deflected within the predetermined range.

在其他特徵中，（e）包含調整該沉積製程之溫度及壓力的至少其中一者，以調整該成核延遲。該層膜係選自由鉬、鎢、釕、及鈷所組成之群組。In other features, (e) includes adjusting at least one of the temperature and pressure of the deposition process to adjust the nucleation delay. The film is selected from the group consisting of molybdenum, tungsten, ruthenium, and cobalt.

在其他特徵中，該方法包含在該複數字元線及該層膜之間配置一內襯層。該內襯層包含氮化鈦。該沉積製程之該溫度係在（e）中調整。該沉積製程之該壓力係在（e）中調整。該沉積製程之該溫度及該壓力係在（e）中調整。該沉積製程之該溫度係在（e）中降低以提高該成核延遲。該沉積製程之該壓力係在（e）中降低以提高該成核延遲。該沉積製程之該溫度及該壓力係在（e）中降低以提高該成核延遲。In other features, the method includes arranging an inner liner layer between the complex number element line and the film. The liner layer contains titanium nitride. The temperature of the deposition process is adjusted in (e). The pressure of the deposition process is adjusted in (e). The temperature and pressure of the deposition process are adjusted in (e). The temperature of the deposition process is lowered in (e) to increase the nucleation delay. The pressure of the deposition process is reduced in (e) to increase the nucleation delay. The temperature and the pressure of the deposition process are reduced in (e) to increase the nucleation delay.

在其他特徵中，（e）包含：若是該字元線撓曲大於該預定範圍，則提高該成核延遲。在其他特徵中，（e）包含：若是該字元線撓曲小於該預定範圍，則降低該成核延遲。In other features, (e) includes: if the deflection of the character line is greater than the predetermined range, increasing the nucleation delay. In other features, (e) includes: if the deflection of the character line is smaller than the predetermined range, reducing the nucleation delay.

在其他特徵中，（e）包含使用一抑制劑物種以調整該成核延遲。該抑制劑物種係選自由分子氮及氨所組成之群組。該抑制劑物種之濃度係在（e）中增加以提高該成核延遲。該抑制劑物種的暴露時間係在（e）中增加以提高該成核延遲。該抑制劑物種之濃度及暴露時間係在（e）中增加以提高該成核延遲。Among other features, (e) includes the use of an inhibitor species to adjust the nucleation delay. The inhibitor species is selected from the group consisting of molecular nitrogen and ammonia. The concentration of the inhibitor species is increased in (e) to increase the nucleation delay. The exposure time of the inhibitor species is increased in (e) to increase the nucleation delay. The concentration and exposure time of the inhibitor species are increased in (e) to increase the nucleation delay.

在其他特徵中，（e）包括調整前驅物化學品或改變前驅物之混合物以調整該成核延遲。在其他特徵中，（e）包括使用溫度及壓力的至少其中一者來控制晶粒尺寸。Among other features, (e) includes adjusting precursor chemicals or changing the mixture of precursors to adjust the nucleation delay. Among other features, (e) includes using at least one of temperature and pressure to control the grain size.

在其他特徵中，（e）包括使用不純物來控制晶粒尺寸。在其他特徵中，（e）包括使用原位氣體來控制晶粒尺寸及膜粗糙度。Among other features, (e) includes the use of impurities to control grain size. Among other features, (e) includes the use of in-situ gas to control grain size and film roughness.

本揭露的更進一步可應用領域從實施方式章節、所請專利範圍以及圖式將變得顯而易見。實施方式章節與特定示例僅意欲說明性之目的，並不意圖限制本揭露之範疇。Further applicable fields of this disclosure will become apparent from the implementation section, the scope of the patent application, and the drawings. The implementation chapters and specific examples are intended for illustrative purposes only, and are not intended to limit the scope of this disclosure.

基板處理系統可用以製造諸如包含複數記憶體單元之記憶體的積體電路。隨著深寬比升高以及臨界尺寸縮小，在製造過程中可能出現問題。舉例而言，諸如在VNAND及DRAM記憶體單元中之字元線的高深寬比特徵部可能在字元線上之膜沉積的過程中經歷撓曲。該撓曲可造成各種問題，諸如字元線相關於其他特徵部的對準、效能變化、及／或其他缺陷。The substrate processing system can be used to manufacture integrated circuits such as memory including a plurality of memory cells. As the aspect ratio increases and the critical dimension shrinks, problems may arise in the manufacturing process. For example, high aspect ratio features such as word lines in VNAND and DRAM memory cells may experience deflection during film deposition on the word lines. This flexure can cause various problems, such as alignment of character lines with other features, performance changes, and/or other defects.

本揭露相關於在膜沉積過程中減少基板的高深寬比特徵部之撓曲的方法。舉例而言，該方法可用以減少在諸如VNAND及DRAM的記憶體單元中相鄰字元線的撓曲。線撓曲係由於在膜沉積（金屬／介電質）過程中的應力及材料的黏著力而發生。The present disclosure is related to a method for reducing the deflection of high aspect ratio features of a substrate during film deposition. For example, this method can be used to reduce the deflection of adjacent word lines in memory cells such as VNAND and DRAM. Line deflection occurs due to stress and material adhesion during film deposition (metal/dielectric).

該方法包含調變沉積製程的成核延遲以控制字元線撓曲。舉例而言，該方法包含選擇用於膜沉積的製程參數。一般將諸如溫度及壓力的製程參數優化以提供具有小晶粒尺寸及低成核延遲的平滑膜。然而，在小特徵部尺寸及高深寬比的情況下，線撓曲在沉積平滑膜時發生。The method includes adjusting the nucleation delay of the deposition process to control character line deflection. For example, the method includes selecting process parameters for film deposition. Generally, process parameters such as temperature and pressure are optimized to provide a smooth film with small grain size and low nucleation delay. However, in the case of small feature size and high aspect ratio, line deflection occurs when the smoothing film is deposited.

根據本揭露的方法包含：選擇沉積製程參數、沉積膜、以及量測線撓曲。在某些範例中，若是線撓曲係在預定範圍外，則調整（例如降低）溫度及／或壓力以將成核延遲及晶粒尺寸提高來提供較粗糙之膜。在某些範例中，將溫度調整在從300°C到700°C的範圍內。在某些範例中，將壓力調整在從5托到80托的範圍內。The method according to the present disclosure includes: selecting deposition process parameters, depositing film, and measuring line deflection. In some examples, if the line deflection is outside the predetermined range, the temperature and/or pressure are adjusted (for example, lowered) to delay nucleation and increase the grain size to provide a rougher film. In some examples, the temperature is adjusted in the range from 300°C to 700°C. In some examples, the pressure is adjusted in the range from 5 Torr to 80 Torr.

用此方式沉積膜，以填充為代價減少線撓曲。以新的溫度及壓力值再次進行沉積製程並量測線撓曲。將此製程重複直到線撓曲在預定容許度內。在某些範例中，根據本揭露的方法可顯著降低在諸如VNAND及DRAM記憶體單元之記憶體裝置中的字元線的線撓曲。Depositing the film in this way reduces wire deflection at the expense of filling. Perform the deposition process again with the new temperature and pressure values and measure the line deflection. This process is repeated until the wire deflection is within a predetermined tolerance. In some examples, the method according to the present disclosure can significantly reduce the line deflection of character lines in memory devices such as VNAND and DRAM memory cells.

現在參考圖1至5，顯示了在層沉積過程中的字元線撓曲的範例。在圖1中，基板100包含下層114（包含電晶體）及複數字元線112。在某些範例中，複數字元線112係諸如DRAM記憶體單元之記憶體單元的一部分，其包含電容器及電晶體。複數字元線提供到電晶體閘極的連結。複數字元線112控制在電晶體通道中的電流流動。在某些範例中，內襯層113係配置在複數字元線112上作為在金屬沉積之前的障蔽層。僅為舉例，內襯層113可由氮化鈦（TiN）所製成。在某些範例中，複數字元線112可包含由諸如SiO2 的介電質所製成的外層118及由諸如矽（Si）的材料119所製成的內層（如圖1中以虛線顯示之相鄰字元線120，但為了清楚起見在其他地方省略），但可使用其他配置。Referring now to FIGS. 1 to 5, examples of character line deflection during layer deposition are shown. In FIG. 1, the substrate 100 includes a lower layer 114 (including a transistor) and complex digital element lines 112. In some examples, the complex number cell line 112 is a part of a memory cell such as a DRAM memory cell, which includes a capacitor and a transistor. The complex number element wire provides the connection to the transistor gate. The complex number element line 112 controls the flow of current in the transistor channel. In some examples, the liner layer 113 is disposed on the complex number element line 112 as a barrier layer before metal deposition. For example only, the lining layer 113 may be made of titanium nitride (TiN). In some examples, the complex number element line 112 may include an outer layer 118 made of a dielectric material such as SiO 2 and an inner layer made of a material 119 such as silicon (Si) (shown in dashed lines in FIG. 1 The adjacent character line 120 is shown, but omitted elsewhere for clarity), but other configurations can be used.

在複數字元線112之間的間隔係預界定的。舉例而言，複數字元線112可以在複數字元線112之間以均勻間隔d1加以製造。在其他範例中，在某些複數字元線112之間可界定不同間隔。通常期望的是在進行額外處理之後，在複數字元線112之間保持預界定之間隔，以與其他特徵部維持對準，以預防短路及／或以維持諸如電阻及/或電容的效能參數。The interval between the plural element lines 112 is predefined. For example, the complex number element lines 112 can be manufactured with a uniform interval d1 between the complex number element lines 112. In other examples, different intervals may be defined between certain complex number cell lines 112. It is generally desirable to maintain a predefined interval between the complex number cell lines 112 after additional processing to maintain alignment with other features, to prevent short circuits and/or to maintain performance parameters such as resistance and/or capacitance .

在圖2中，將層116沉積以填充在複數字元線112之間的間隙。在某些範例中，層116包含鎢（W）、釕（Ru）、鈷（Co）、或鉬（Mo）。在某些範例中，內襯層113及層116係使用原子層沉積（ALD）加以沉積。在其他範例中，使用化學氣相沉積（CVD）或其他沉積製程。在某些範例中，可使用電漿以在沉積過程中增強化學反應。在某些範例中，選擇用於層116的沉積製程參數以產生下列特徵：層116係保形的且具有低成核延遲及小晶粒尺寸。換句話說，通常期望的是將平滑膜沉積在複數字元線112上而非較粗糙的膜。在某些範例中，可在層116及複數字元線112之間沉積一或更多內襯層。In FIG. 2, a layer 116 is deposited to fill the gaps between the complex cell lines 112. In some examples, the layer 116 includes tungsten (W), ruthenium (Ru), cobalt (Co), or molybdenum (Mo). In some examples, the liner layer 113 and the layer 116 are deposited using atomic layer deposition (ALD). In other examples, chemical vapor deposition (CVD) or other deposition processes are used. In some examples, plasma can be used to enhance chemical reactions during the deposition process. In some examples, the deposition process parameters for layer 116 are selected to produce the following characteristics: layer 116 is conformal and has low nucleation delay and small grain size. In other words, it is generally desirable to deposit a smooth film on the complex cell line 112 instead of a rougher film. In some examples, one or more liner layers may be deposited between the layer 116 and the complex cell lines 112.

在圖3中，由於層116係以這些特徵加以沉積，因此線撓曲可能發生。該複數字元線112其中一些朝向複數字元線112的相鄰一者撓曲，而複數字元線112其他者則遠離複數字元線112的相鄰一者撓曲。因此，不再維持預界定之間距。在圖4中，進行額外沉積以填充在複數字元線112之間的間隙。In FIG. 3, since layer 116 is deposited with these features, line deflection may occur. Some of the complex number element lines 112 bend towards the adjacent one of the complex number element lines 112, and the others of the complex number element lines 112 are bent away from the adjacent one of the complex number element lines 112. Therefore, the predefined distance is no longer maintained. In FIG. 4, additional deposition is performed to fill the gaps between the complex cell lines 112.

在圖5中，可進行蝕刻及／或其他製程以將複數字元線112的上部表面及／或材料119之頂部表面裸露（以允許接觸）。沉積額外層（未顯示）並接觸材料119。如可見的，在複數字元線112相鄰者之間的距離d2及d3彼此不同且與d1不同。當沉積額外層時，可發生錯準。此外，諸如電阻及電容的效能參數可因複數字元線112之間的間距變化而有不良影響。In FIG. 5, etching and/or other processes may be performed to expose the upper surface of the complex number cell 112 and/or the top surface of the material 119 (to allow contact). An additional layer (not shown) is deposited and contacts the material 119. As can be seen, the distances d2 and d3 between neighbors of the complex number element line 112 are different from each other and different from d1. When depositing additional layers, misalignment can occur. In addition, performance parameters such as resistance and capacitance may have an adverse effect due to changes in the spacing between the complex digital element lines 112.

現在參考圖6至10，顯示了用於在層沉積的過程中減少字元線撓曲的範例方法。在圖6中，基板600包含下層114及複數字元線112。在複數字元線112之間的間隔係預界定的。舉例而言，複數字元線112係在複數字元線112之間以均勻間隔d1加以製造。在其他範例中，在複數字元線112某些之間可界定不同間隔。通常期望的是在進行額外處理之後，在複數字元線112之間保持預界定之間隔，以與其他特徵部維持對準，以預防短路及／或以維持諸如電阻及/或電容的效能參數。Referring now to Figures 6 to 10, exemplary methods for reducing character line deflection during layer deposition are shown. In FIG. 6, the substrate 600 includes a lower layer 114 and complex number cell lines 112. The interval between the plural element lines 112 is predefined. For example, the complex number element wires 112 are manufactured with a uniform interval d1 between the complex number element wires 112. In other examples, different intervals may be defined between some of the plural element lines 112. It is generally desirable to maintain a predefined interval between the complex number cell lines 112 after additional processing to maintain alignment with other features, to prevent short circuits and/or to maintain performance parameters such as resistance and/or capacitance .

在圖7中，將層116沉積以填充在複數字元線112之間的間隙。在某些範例中，層616係使用原子層沉積（ALD）、化學氣相沉積（CVD）或其他沉積製程加以沉積。在某些範例中，可使用電漿以在沉積過程中增強化學反應。在某些範例中，選擇用於層616的沉積製程參數以產生下列特徵：層616係保形的且具有高成核延遲及大晶粒尺寸。如將在下方更進一步說明的，使用高成核延遲以及大晶粒尺寸來沉積膜將導致較粗糙之膜的特性，但將避免線撓曲。換句話說，此處所述之方法違背在複數字元線112上沉積平滑膜的通常目標。In FIG. 7, a layer 116 is deposited to fill the gaps between the complex cell lines 112. In some examples, layer 616 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some examples, plasma can be used to enhance chemical reactions during the deposition process. In some examples, the deposition process parameters for layer 616 are selected to produce the following characteristics: layer 616 is conformal and has high nucleation delay and large grain size. As will be explained further below, the use of high nucleation delay and large grain size to deposit the film will result in the characteristics of a rougher film, but will avoid line deflection. In other words, the method described here goes against the usual goal of depositing a smooth film on the complex cell line 112.

在圖8中，由於層616係以這些特徵加以沉積，因此將線撓曲顯著地減少。在圖9中，進行額外沉積以填充在複數字元線112之間的間隙。In FIG. 8, since the layer 616 is deposited with these features, the wire deflection is significantly reduced. In FIG. 9, additional deposition is performed to fill the gaps between the complex cell lines 112.

在圖10中，可進行蝕刻及／或另一製程以將複數字元線112的上部表面裸露。如在圖10中可見的，可將額外層（未顯示）沉積於上部表面1010上且可能需要與材料119之頂部表面對準。如可見的，將在複數字元線112相鄰者之間的預界定距離（例如此例中的d1）加以維持。因此，當沉積額外層時，可維持基本上的對準。此外，諸如電阻及電容的效能參數不會因複數字元線112之間的間距變化而（如同在圖1至5的那樣）有不良影響。In FIG. 10, etching and/or another process may be performed to expose the upper surface of the complex digital element line 112. As can be seen in FIG. 10, an additional layer (not shown) may be deposited on the upper surface 1010 and may need to be aligned with the top surface of the material 119. As can be seen, the predefined distance between the neighbors of the complex number element line 112 (for example, d1 in this example) is maintained. Therefore, when additional layers are deposited, substantial alignment can be maintained. In addition, performance parameters such as resistance and capacitance will not be adversely affected by changes in the spacing between the complex digital element lines 112 (as in FIGS. 1 to 5).

現在參考圖11，顯示了在諸如字元線之特徵部上沉積一層時，減少該特徵部的撓曲的方法1100。方法1100包括：在1110，選擇用於沉積膜的製程參數。一般係將諸如溫度及壓力的該製程參數優化以提供具有小晶粒尺寸及低成核延遲的平滑膜。然而，在小特徵部尺寸及高深寬比的情況下，當沉積平滑膜時會發生線撓曲。Referring now to FIG. 11, a method 1100 for reducing the deflection of a feature such as a character line when a layer is deposited on the feature is shown. The method 1100 includes, at 1110, selecting process parameters for depositing the film. Generally, the process parameters such as temperature and pressure are optimized to provide a smooth film with small grain size and low nucleation delay. However, in the case of small feature size and high aspect ratio, line deflection occurs when the smooth film is deposited.

在選擇製程參數之後，該方法包含在1114沉積膜。在1118，量測線撓曲並與預定之範圍比較。若是線撓曲係在如在1118所決定之預定範圍以外，則調整成核延遲及／或晶粒尺寸。在某些範例中，將在沉積過程中使用之溫度或壓力如此處所述地改變，但下方描述其他方法。After selecting the process parameters, the method includes depositing a film at 1114. At 1118, the measurement line is deflected and compared with a predetermined range. If the line deflection is outside the predetermined range as determined by 1118, adjust the nucleation delay and/or the grain size. In some examples, the temperature or pressure used in the deposition process is changed as described here, but other methods are described below.

舉例而言，當線撓曲高於預定範圍時，則降低壓力及／或溫度。在1126以該調整再次進行製程。該方法回到1118並再次量測線撓曲。可將此製程重複一或更多次直到線撓曲在如在1118所決定之預定範圍內。換句話說，可將膜粗糙度及線撓曲的平衡最佳化。當1118為真，則將製程用於生產基板。For example, when the wire deflection is higher than a predetermined range, the pressure and/or temperature are reduced. At 1126, the process is performed again with this adjustment. The method returns to 1118 and measures the line deflection again. This process can be repeated one or more times until the wire deflection is within a predetermined range as determined by 1118. In other words, the balance of film roughness and line deflection can be optimized. When 1118 is true, the process is used to produce the substrate.

現在參考圖12A及12B，在沉積過程中降低溫度會提高成核延遲、晶粒尺寸、及膜粗糙度。因此，減少了字元線撓曲。在圖12A中，曲線圖描繪在不同溫度，鉬厚度作為ALD循環的函數。在此例中，較高的溫度對應於590°C而較低的溫度對應於550°C。如可見的，較低溫度的成核延遲相對於較高溫度而言是上升的（在此例中係從約33 ALD循環到約62 ALD循環）。晶粒尺寸及膜粗糙度亦提高。在某些範例中，字元線撓曲從9.6奈米減少到1.7奈米。在圖12B中，曲線圖描繪在不同溫度，鉬電阻率作為厚度的函數。不同溫度具有大約相同的電阻。Referring now to FIGS. 12A and 12B, lowering the temperature during the deposition process increases the nucleation delay, grain size, and film roughness. Therefore, character line deflection is reduced. In Figure 12A, the graph depicts the thickness of molybdenum as a function of ALD cycles at different temperatures. In this example, the higher temperature corresponds to 590°C and the lower temperature corresponds to 550°C. As can be seen, the nucleation delay at lower temperatures increases relative to higher temperatures (in this example, from about 33 ALD cycles to about 62 ALD cycles). The grain size and film roughness are also improved. In some examples, the character line deflection was reduced from 9.6 nm to 1.7 nm. In Figure 12B, the graph depicts the resistivity of molybdenum as a function of thickness at different temperatures. Different temperatures have approximately the same resistance.

現參考圖13A及13B，在沉積過程中將壓力降低會提高成核延遲、晶粒尺寸、及膜粗糙度。因此，減少了字元線撓曲。在圖13A中，曲線圖描繪在不同壓力，鉬厚度作為ALD循環的函數。在此例中，較高的壓力對應於60托而較低的壓力對應於40托。如可見的，較低壓力的成核延遲相對於較高壓力而言是上升的（在此例中係從約39 ALD循環到約59 ALD循環）。晶粒尺寸及膜粗糙度亦提高。在某些範例中，字元線撓曲從9.9奈米減少到1.6奈米。在圖13B中，曲線圖描繪在不同壓力，鉬電阻率作為厚度的函數。不同壓力具有大約相同的電阻。Referring now to FIGS. 13A and 13B, reducing the pressure during the deposition process will increase the nucleation delay, grain size, and film roughness. Therefore, character line deflection is reduced. In Figure 13A, the graph depicts the thickness of molybdenum as a function of ALD cycles at different pressures. In this example, a higher pressure corresponds to 60 Torr and a lower pressure corresponds to 40 Torr. As can be seen, the nucleation delay at lower pressures is increased relative to higher pressures (in this example from about 39 ALD cycles to about 59 ALD cycles). The grain size and film roughness are also improved. In some examples, the character line deflection was reduced from 9.9 nm to 1.6 nm. In Figure 13B, the graph depicts the resistivity of molybdenum as a function of thickness at different pressures. Different pressures have approximately the same resistance.

如可理解的，溫度及壓力改變的組合可用以提高成核延遲、晶粒尺寸、及粗糙度並減少線撓曲。As can be appreciated, the combination of temperature and pressure changes can be used to increase nucleation delay, grain size, and roughness and reduce wire deflection.

儘管上方所闡述之範例說明了藉由改變溫度及／或壓力來調變成核延遲，存在其他方式以調變成核延遲。舉例而言，成核延遲可藉由以下方式來調變：選擇不同沉積製程（原子層沉積（ALD）、化學氣相沉積（CVD）、或電漿輔助（PE）ALD）、針對傳導層選擇不同導體（鉬（Mo）、鎢（W）、釕（Ru）、或鈷（Co））或不同前驅物、在沉積製程之前或沉積製程過程中引入不純物來以改變晶粒尺寸或成核延遲、或是在沉積之前使用諸如分子氮（N2 ）或氨（NH3 ）的表面處理。該表面處理可包含電漿的使用。Although the example described above illustrates the adjustment to nuclear delay by changing temperature and/or pressure, there are other ways to adjust to nuclear delay. For example, the nucleation delay can be adjusted by the following methods: choose different deposition processes (atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma assisted (PE) ALD), select the conductive layer Different conductors (molybdenum (Mo), tungsten (W), ruthenium (Ru), or cobalt (Co)) or different precursors, introducing impurities before or during the deposition process to change the grain size or nucleation delay Or use surface treatment such as molecular nitrogen (N 2 ) or ammonia (NH 3 ) before deposition. The surface treatment may include the use of plasma.

當使用ALD製程時，在膜成長可以開始之前，前驅物分子需要化學性吸附於表面。表面包括前驅物分子可吸附的有限成核部位。當這些部位被也可以吸附於表面但與前驅物分子幾乎不相互作用的分子所競爭性遮擋時，該等部位不再能夠用於前驅物吸附。When using the ALD process, the precursor molecules need to be chemically adsorbed on the surface before the film growth can begin. The surface includes limited nucleation sites where precursor molecules can adsorb. When these parts are competitively blocked by molecules that can also adsorb on the surface but hardly interact with precursor molecules, these parts can no longer be used for precursor adsorption.

藉由改變抑制劑分子的濃度，可控制成核延遲，並從而控制膜粗糙度及線撓曲。諸如分子氮（N2 ）或氨（NH3 ）的小的含氮分子可為有效的抑制劑。在其他範例中，可使用諸如聯胺或有機肼的較大的含氮分子。由於立體阻礙的額外效應，較大分子作為抑制劑係更強效的。By changing the concentration of inhibitor molecules, the nucleation delay can be controlled, and thus the film roughness and line deflection can be controlled. Small nitrogen-containing molecules such as molecular nitrogen (N 2 ) or ammonia (NH 3 ) can be effective inhibitors. In other examples, larger nitrogen-containing molecules such as hydrazine or organic hydrazine can be used. Due to the additional effect of steric hindrance, larger molecules are more potent as inhibitors.

上述某些範例以平滑膜開始，再降低溫度及／或壓力直到達到所欲之線撓曲閾值。在其他範例中，該方法最初可以較粗糙的膜進行，且可將溫度及／或壓力提升直到到達所欲之線撓曲量。換句話說，在線撓曲及粗糙度之間的所欲之取捨可從平滑到粗糙加以確定或是從粗糙到較不粗糙加以確定。舉例而言，可使用預定閾值範圍。將字元線撓曲與預定閾值範圍相比較。若是字元線撓曲小於預定閾值範圍，則將成核延遲降低直到字元線撓曲在預定閾值範圍內。若是字元線撓曲大於預定閾值範圍，則將成核延遲提高直到字元線撓曲在預定閾值範圍內。Some of the above examples start with a smooth film, and then lower the temperature and/or pressure until the desired line deflection threshold is reached. In other examples, the method can be performed initially with a rougher film, and the temperature and/or pressure can be increased until the desired amount of wire deflection is reached. In other words, the desired choice between line deflection and roughness can be determined from smooth to rough or rough to less rough. For example, a predetermined threshold range can be used. The character line deflection is compared with a predetermined threshold range. If the deflection of the character line is less than the predetermined threshold range, the nucleation delay is reduced until the deflection of the character line is within the predetermined threshold range. If the deflection of the character line is greater than the predetermined threshold range, the nucleation delay is increased until the deflection of the character line is within the predetermined threshold range.

前述本質僅是用以說明性描述，而非意欲限制此處揭露內容、其應用、或用途。本揭露之廣泛教示可以多種形式實行。因此，儘管本揭露包含特定例子，然而由於經由研讀附圖、說明書以及以下專利申請範圍，其他調整將變得顯而易見，因此本揭露之真實範疇不應僅限於此。應了解的是，在不改變本揭露的原理之下，方法中的一或更多步驟可以不同順序（或同時）執行。再者，儘管上述每個實施例具有特定特徵，可將相對於本揭露之任一實施例描述的這些特徵的任何一或更多者在其他實施例中任一者的特徵中實施、及／或將其與其他實施例中任一者的特徵結合實施，就算此結合並未被明確描述。換言之，所述之實施例並不互斥，且將一或更多實施例彼此置換仍在本揭露之範疇內。The foregoing essence is only used for illustrative description, and is not intended to limit the content disclosed herein, its application, or use. The extensive teachings of this disclosure can be implemented in many forms. Therefore, although the present disclosure contains specific examples, other adjustments will become apparent after studying the drawings, the specification, and the scope of the following patent applications. Therefore, the true scope of the present disclosure should not be limited to this. It should be understood that, without changing the principle of the present disclosure, one or more steps in the method can be executed in a different order (or simultaneously). Furthermore, although each of the above embodiments has specific features, any one or more of these features described with respect to any embodiment of the present disclosure can be implemented in the features of any of the other embodiments, and/ Or it can be implemented in combination with the features of any of the other embodiments, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and replacing one or more embodiments with each other is still within the scope of the present disclosure.

使用各種用語描述之部件之間（例如，在模組、電路元件、半導體層等等之間）的空間及功能關係，包含「連接」、「契合」、「耦合」、「毗連」、「相鄰」、「在頂部」、「上方」、「下方」、以及「設置」。除非明確的描述為「直接」，當在上述揭露中描述第一與第二部件之間的關係時，該關係可以是在該第一與第二部件之間沒有其他中介部件存在的直接關係，也可以是在該第一與第二部件之間（空間上或功能上）存在一或多個中介部件的間接關係。如此處所使用，用語至少為A、B及C其中之一應被解釋為使用非排他性的「或者」表示邏輯（A或B或C），並且不應解釋為「至少A其中之一、至少B其中之一以及至少C其中之一」。Use various terms to describe the spatial and functional relationships between components (for example, between modules, circuit components, semiconductor layers, etc.), including "connection", "fitting", "coupling", "connection", "phase" Neighbor, "at the top", "above", "below", and "set" Unless it is explicitly described as “direct”, when the relationship between the first and second components is described in the above disclosure, the relationship may be a direct relationship between the first and second components without other intermediary components. It may also be that there is an indirect relationship (spatially or functionally) between one or more intermediate components between the first and second components. As used here, the term at least one of A, B, and C should be interpreted as using the non-exclusive "or" to indicate logic (A or B or C), and should not be interpreted as "at least one of A, at least B One of them and at least one of C".

d1:均勻間隔 d2:距離 d3:距離 100:基板 112:複數字元線 113:內襯層 114:下層 116:層 118:外層 119:材料 120:相鄰字元線 600:基板 616:層 1010:上部表面d1: evenly spaced d2: distance d3: distance 100: substrate 112: complex number element line 113: inner lining 114: Lower 116: layer 118: Outer layer 119: Material 120: Adjacent character line 600: substrate 616: layer 1010: upper surface

從實施方式章節與隨附圖式將變得更了解本揭露，其中：We will learn more about this disclosure from the implementation section and accompanying drawings, in which:

圖1至5係基板之範例的側面剖面圖，該基板包含記憶體單元的字元線、在字元線上之層的沉積、以及字元線的撓曲；Figures 1 to 5 are side cross-sectional views of an example of a substrate, the substrate including the character lines of the memory cell, the deposition of layers on the character lines, and the deflection of the character lines;

圖6至10係根據本揭露內容基板之範例的側面剖面圖，該基板包含記憶體單元的字元線以及在字元線上之層的沉積，其中字元線的撓曲顯著減少；6 to 10 are side cross-sectional views of an example of a substrate according to the present disclosure. The substrate includes the character lines of the memory cell and the deposition of layers on the character lines, in which the deflection of the character lines is significantly reduced;

圖11係用於在字元線上沉積一層時減少字元線撓曲的範例方法的流程圖；11 is a flowchart of an exemplary method for reducing the deflection of the character line when depositing a layer on the character line;

圖12A係描繪在不同溫度，鉬厚度作為ALD循環之函數的曲線圖；Figure 12A is a graph depicting the thickness of molybdenum as a function of ALD cycles at different temperatures;

圖12B係描繪在不同溫度，鉬電阻率作為厚度之函數的曲線圖；Figure 12B is a graph depicting the resistivity of molybdenum as a function of thickness at different temperatures;

圖13A係描繪在不同壓力，鉬厚度作為ALD循環之函數的曲線圖；以及Figure 13A is a graph depicting the thickness of molybdenum as a function of ALD cycles at different pressures; and

圖13B係描繪在不同壓力，鉬電阻率作為厚度之函數的曲線圖。Figure 13B is a graph depicting the resistivity of molybdenum as a function of thickness at different pressures.

在該等圖式中，索引號碼可重複使用以表明相似及／或相同部件。In these drawings, the index number can be reused to indicate similar and/or identical parts.

Claims (22)

一種減少在記憶體單元中字元線撓曲的方法，包含： （a）提供一基板，該基板包括複數字元線，該複數字元線係配置成與彼此相鄰並在複數電晶體上方； （b）使用一沉積製程在該複數字元線上沉積一層膜； （c）在沉積該層膜之後，量測字元線撓曲； （d）將該字元線撓曲與一預定範圍相比較； （e）基於該字元線撓曲，調整該沉積製程之成核延遲及晶粒尺寸的至少其中一者；及 （f）使用一或更多基板分別重複（b）到（e）一或更多次，直到該字元線撓曲在該預定範圍內。A method to reduce the deflection of character lines in memory cells, including: (A) Providing a substrate, the substrate including a complex number element line, the complex number element line is arranged to be adjacent to each other and above the plurality of transistors; (B) Use a deposition process to deposit a film on the complex digital element line; (C) After depositing the film, measure the deflection of the character line; (D) Compare the deflection of the character line with a predetermined range; (E) Adjusting at least one of the nucleation delay and grain size of the deposition process based on the deflection of the character line; and (F) Repeat (b) to (e) one or more times using one or more substrates, until the character line is deflected within the predetermined range. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包含調整該沉積製程之溫度及壓力的至少其中一者，以調整該成核延遲。The method for reducing the deflection of character lines in a memory cell according to claim 1, wherein (e) includes adjusting at least one of the temperature and pressure of the deposition process to adjust the nucleation delay. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中該層膜係選自由鉬、鎢、釕、及鈷所組成之群組。The method for reducing the deflection of character lines in a memory cell as claimed in claim 1, wherein the film is selected from the group consisting of molybdenum, tungsten, ruthenium, and cobalt. 如請求項1之減少在記憶體單元中字元線撓曲的方法，更包括在該複數字元線及該層膜之間配置一內襯層。For example, the method for reducing the deflection of the character line in the memory cell of claim 1 further includes arranging an inner lining layer between the complex number element line and the film. 如請求項4之減少在記憶體單元中字元線撓曲的方法，其中該內襯層包含氮化鈦。As claimed in claim 4, the method for reducing the deflection of character lines in a memory cell, wherein the lining layer includes titanium nitride. 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該溫度係在（e）中調整。The method for reducing the deflection of the character line in the memory cell as in claim 2, wherein the temperature of the deposition process is adjusted in (e). 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該壓力係在（e）中調整。The method for reducing the deflection of the character line in the memory cell as in claim 2, wherein the pressure of the deposition process is adjusted in (e). 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該溫度及該壓力係在（e）中調整。The method for reducing the deflection of the character line in the memory cell as in claim 2, wherein the temperature and the pressure of the deposition process are adjusted in (e). 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該溫度係在（e）中降低以提高該成核延遲。The method for reducing the deflection of character lines in a memory cell as claimed in claim 2, wherein the temperature of the deposition process is lowered in (e) to increase the nucleation delay. 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該壓力係在（e）中降低以提高該成核延遲。The method for reducing the deflection of the character line in the memory cell as in claim 2, wherein the pressure of the deposition process is reduced in (e) to increase the nucleation delay. 如請求項2之減少在記憶體單元中字元線撓曲的方法，其中該沉積製程之該溫度及該壓力係在（e）中降低以提高該成核延遲。The method for reducing character line deflection in a memory cell as claimed in claim 2, wherein the temperature and the pressure of the deposition process are reduced in (e) to increase the nucleation delay. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包含若是該字元線撓曲大於該預定範圍，則提高該成核延遲。For example, the method for reducing the deflection of the character line in the memory cell of claim 1, wherein (e) includes increasing the nucleation delay if the deflection of the character line is greater than the predetermined range. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包含若是該字元線撓曲小於該預定範圍，則降低該成核延遲。For example, the method for reducing the deflection of the character line in the memory cell of claim 1, wherein (e) includes reducing the nucleation delay if the deflection of the character line is less than the predetermined range. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包含使用一抑制劑物種以調整該成核延遲。Such as claim 1, the method for reducing the deflection of character lines in a memory cell, wherein (e) includes using an inhibitor species to adjust the nucleation delay. 如請求項14之減少在記憶體單元中字元線撓曲的方法，其中該抑制劑物種係選自由分子氮及氨所組成之群組。Such as the method for reducing the deflection of character lines in a memory cell of claim 14, wherein the inhibitor species is selected from the group consisting of molecular nitrogen and ammonia. 如請求項14之減少在記憶體單元中字元線撓曲的方法，其中該抑制劑物種之濃度係在（e）中增加以提高該成核延遲。The method for reducing the deflection of character lines in a memory cell as in claim 14, wherein the concentration of the inhibitor species is increased in (e) to increase the nucleation delay. 如請求項14之減少在記憶體單元中字元線撓曲的方法，其中該抑制劑物種的暴露時間係在（e）中增加以提高該成核延遲。The method for reducing the deflection of character lines in a memory cell as in claim 14, wherein the exposure time of the inhibitor species is increased in (e) to increase the nucleation delay. 如請求項14之減少在記憶體單元中字元線撓曲的方法，其中該抑制劑物種之濃度及暴露時間係在（e）中增加以提高該成核延遲。For example, the method for reducing the deflection of the character line in the memory cell of claim 14, wherein the concentration and exposure time of the inhibitor species are increased in (e) to increase the nucleation delay. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包括調整前驅物化學品或改變前驅物之混合物以調整該成核延遲。For example, the method for reducing the deflection of character lines in a memory cell in claim 1, wherein (e) includes adjusting precursor chemicals or changing the mixture of precursors to adjust the nucleation delay. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包括使用溫度及壓力的至少其中一者來控制晶粒尺寸。Such as the method for reducing the deflection of character lines in a memory cell in claim 1, wherein (e) includes using at least one of temperature and pressure to control the die size. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包括使用不純物來控制晶粒尺寸。For example, the method for reducing the deflection of the character line in the memory cell in claim 1, where (e) includes using impurities to control the grain size. 如請求項1之減少在記憶體單元中字元線撓曲的方法，其中（e）包括使用原位氣體來控制晶粒尺寸及膜粗糙度。Such as the method for reducing the deflection of the character line in the memory cell in claim 1, wherein (e) includes using in-situ gas to control the grain size and film roughness.
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