CN114743974A - Deposition method of polysilicon and manufacturing method of contact plug - Google Patents

Deposition method of polysilicon and manufacturing method of contact plug Download PDF

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Publication number
CN114743974A
CN114743974A CN202110020532.1A CN202110020532A CN114743974A CN 114743974 A CN114743974 A CN 114743974A CN 202110020532 A CN202110020532 A CN 202110020532A CN 114743974 A CN114743974 A CN 114743974A
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Prior art keywords
deposition
silicon
deposition method
stage
bit line
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CN202110020532.1A
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Inventor
崔锺武
金成基
熊文娟
蒋浩杰
李亭亭
崔恒玮
罗英
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202110020532.1A priority Critical patent/CN114743974A/en
Publication of CN114743974A publication Critical patent/CN114743974A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a deposition method of polysilicon and a manufacturing method of bit line/storage node contact plugs. A method of depositing polycrystalline silicon, comprising: providing a semiconductor structure to be deposited with polycrystalline silicon; placing the semiconductor structure in a deposition furnace, heating to T1, keeping constant temperature, and performing first-stage silicon deposition at constant temperature; then heating to T2 at a certain rate, and continuously depositing silicon in the heating process to finish the second stage of silicon deposition; continuing to maintain the temperature at T2, maintaining the constant temperature, and performing third-stage silicon deposition at the constant temperature; wherein the ranges of T1 and T2 are both 300-650 ℃, and T2 is more than T1. The invention has higher step coverage rate when being used for deposition in the groove, and the deposition efficiency is greatly improved compared with the prior art because partial silicon deposition is completed in the temperature rise process.

Description

Deposition method of polysilicon and manufacturing method of contact plug
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a deposition method of polycrystalline silicon and a manufacturing method of bit line/storage node contact plugs.
Background
In the manufacturing process of a DRAM (Dynamic Random Access Memory) device, a polysilicon (poly) is deposited to form contact films such as a Bit line contact (Bit line contact) conductive structure and a Storage node contact (Storage node contact) conductive structure, which are generally called "plugs". As integrated circuits shrink in size, the demand for contact resistance of polysilicon plugs increases. If the polysilicon is not well buried during deposition, contact resistance may increase or voids may be generated, resulting in a decrease in device yield and quality.
In order to improve the filling uniformity of polysilicon in the prior art, multi-stage constant temperature deposition is usually adopted, for example, as shown in a trend graph of temperature change with time in fig. 1, after the temperature is increased from room temperature to t1, the constant temperature is maintained, the first stage silicon deposition is performed, then the temperature is increased to t2, the constant temperature is maintained, the second stage silicon deposition is performed, finally the temperature is increased to t3, the constant temperature is maintained, and the third stage silicon deposition is performed. Although the method can improve the step coverage rate, the process time is too long, and the production efficiency is low.
Therefore, the invention is especially provided.
Disclosure of Invention
The invention mainly aims to provide a deposition method of polycrystalline silicon, which has higher step coverage rate when used for deposition in a groove, and greatly improves the deposition efficiency compared with the prior art because partial silicon deposition is completed in the temperature rising process.
In order to achieve the above object, the present invention provides the following technical solutions.
A method of depositing polysilicon, comprising:
providing a semiconductor structure to be deposited with polycrystalline silicon;
placing the semiconductor structure in a deposition furnace, heating to T1, keeping constant temperature, and performing first-stage silicon deposition at constant temperature;
then heating to T2 at a certain rate, and continuously depositing silicon in the heating process to finish the second stage of silicon deposition;
continuing to maintain the temperature at T2, maintaining the constant temperature, and performing third-stage silicon deposition at the constant temperature;
wherein the ranges of T1 and T2 are both 300-650 ℃, and T2 is more than T1.
The invention adopts a staged heating deposition method, and can achieve the following technical effects.
Reducing holes: the density of silicon atom bonding can be increased by using staged heating deposition, so that holes or gaps are reduced;
and (3) improving the step coverage rate: the staged heating is beneficial to orderly and gradually decomposing the silicon source, so that the film thickness of the cross-step position can be basically consistent with that of the flat position, and the film uniformity is improved;
the deposition efficiency is improved: because the deposition in the intermediate stage is carried out along with the temperature rise process and the heat preservation time is needed, compared with the prior art, the total time is shortened, and the deposition efficiency is improved.
The deposition method of the invention can be used in any field requiring low resistance, high density and high uniformity of polysilicon, such as the manufacture of bit line/storage node contact plugs in typical DRAM.
Compared with the prior art, the invention achieves the following technical effects:
(1) reducing polysilicon holes;
(2) the step coverage rate is improved;
(3) the deposition efficiency is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic flow chart of a process for depositing polysilicon according to the prior art;
FIG. 2 is a schematic diagram of a DRAM structure according to the present invention;
fig. 3 is a schematic flow chart of the process for depositing polysilicon according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
As shown in the DRAM structure of fig. 2, a bit line contact plug 104 and a storage node contact plug 105 are shown, and material characteristics such as resistance and uniformity of the two plugs are critical to the electrical performance of the device. The present invention improves the plug deposition method in view of both high step coverage and high production efficiency.
The formation of the bit line contact hole will be described below with reference to the drawings.
The device isolation structure 103 and the buried transistor are first formed on the silicon substrate 101. The isolation structure is used to isolate the active region of the device. The buried transistor includes a buried gate 102 and an active region. The active region is isolated by an isolation structure. The method for forming the buried gate 102 may include etching the substrate using a patterned photolithography method to form a buried gate trench; then forming a grid oxide layer; then partially filling to form word lines. Next, an insulating layer is formed, and the insulating layer is etched by a patterning method until an active region in the substrate is exposed, thereby forming a bit line contact hole in the insulating layer. Then, the substrate with the bit line contact hole is cleaned. The substrate is then placed in a deposition furnace in preparation for deposition of the polysilicon.
Deposition of polysilicon in the bit line contact holes may then be performed to form bit line contact plugs.
Usually with an inert gas (nitrogen N) prior to deposition2Etc.), then adopting the flow shown in fig. 3, firstly heating to T1, keeping the temperature constant, and carrying out first-stage silicon deposition at the constant temperature; heating to T2 at a certain rate, and continuously depositing silicon during the heating process to complete the second stage of silicon deposition; the temperature was kept at T2, held constant and the third stage of silicon deposition was carried out at constant temperature. Wherein, the ranges of T1 and T2 are both 300-650 ℃, common typical silicon sources can be decomposed within the temperature range, and T2 is more than T1. Because the deposition in the intermediate stage is carried out along with the temperature rise process and the heat preservation time is required, compared with the prior art, the total time is shortened, the deposition efficiency is improved, and the problems of holes and low step coverage rate are improved.
In the polysilicon deposition process, the specific ranges of T1 and T2 are usually adjusted according to the required targets of film thickness, step coverage, process time, film compactness and the like, and for a typical DRAM bit line contact hole, T1 is 300-400 ℃, and T2 is 400-650 ℃.
In some preferred embodiments, the temperature rise rate during the second stage silicon deposition is 3-8 ℃/min, including but not limited to 3 ℃/min, 4 ℃/min, 5 ℃/min, 6 ℃/min, 7 ℃/min, 8 ℃/min, and the like.
In addition, the material of the polysilicon contact film can be amorphous silicon (amorphous silicon) or crystalline silicon, and the method for depositing the polysilicon contact film can be a Low Pressure Chemical Vapor Deposition (LPCVD) method, an Atomic Layer Deposition (ALD) method, a composite method of atomic layer Seed (Seed) deposition and LPCVD, or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The polysilicon film can be in-situ phosphorus (P) or in-situ boron (B) doped polysilicon, and the silicon source can be typical silicon sources such as monosilane, dichlorosilane, disilane, diisopropylaminosilane, bis (tert-butylamino) silane, bis (diethylamino) silane, hexachlorodisilane, tris (dimethylamino) silane, butylaminosilane, diethylaminosilane, dipropylaminosilane, hexaethylaminodisilane and the like.
After depositing polysilicon in the bit line contact hole, the bit line body may continue to be formed. And forming a barrier layer, a metal layer and a cover layer on the whole semiconductor substrate, etching the cover layer, the metal layer, the barrier layer and the bit line contact plug, thereby forming a bit line main body stack, and finally forming side walls on two sides of the bit line main body stack.
Storage node contact holes are formed next.
After the bit line is manufactured, the isolation layer above the semiconductor substrate is etched by taking the bit line main body and the side wall as masks until the active region is exposed, and a groove is formed. A dielectric layer may be formed in the trench and then photolithography may be performed to form a storage node contact hole exposing the active region. The structure may then be fed into a deposition furnace ready to be filled with polysilicon to form storage node contact plugs.
Similarly, an inert gas (nitrogen N) is used prior to deposition2Etc.), then adopting the flow shown in fig. 3, firstly raising the temperature to T1, then keeping the temperature constant, and carrying out first-stage silicon deposition at the constant temperature; heating to T2 at a certain rate, and continuously depositing silicon during the heating process to complete the second stage of silicon deposition; the temperature was kept at T2, held constant, and a third stage of silicon deposition was carried out at constant temperature. Wherein the ranges of T1 and T2 are 300-6Typical silicon sources that are common at 50 ℃ all decompose in this temperature range and T2 > T1. Similarly, the specific ranges of T1 and T2 are usually adjusted according to the required targets of film thickness, step coverage, process time, film compactness and the like, and for a typical DRAM storage node contact hole, T1 is 300-400 ℃, and T2 is 400-650 ℃.
Similarly, in some preferred embodiments, the temperature rise rate during the second stage silicon deposition is 3-8 deg.C/min, including but not limited to 3 deg.C/min, 4 deg.C/min, 5 deg.C/min, 6 deg.C/min, 7 deg.C/min, 8 deg.C/min, etc.
The polysilicon contact film in the storage node contact hole can be amorphous silicon (amorphous silicon) or crystalline silicon, and the mode of depositing the polysilicon contact film can be a low-pressure chemical vapor deposition (LPCVD) mode or an Atomic Layer Deposition (ALD) mode or a composite mode of atomic layer Seed (Seed) deposition and LPCVD mode or a Plasma Enhanced Chemical Vapor Deposition (PECVD) mode. The polysilicon film can be in-situ phosphorus (P) or in-situ boron (B) doped polysilicon, and the silicon source can be typical silicon sources such as monosilane, dichlorosilane, disilane, diisopropylaminosilane, bis (tert-butylamino) silane, bis (diethylamino) silane, hexachlorodisilane, tris (dimethylamino) silane, butylaminosilane, diethylaminosilane, dipropylaminosilane, hexaethylaminodisilane and the like.
Fabrication of the contact pads and capacitors may then be further performed to complete the fabrication of the DRAM cell.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A method of depositing polycrystalline silicon, comprising:
providing a semiconductor structure to be deposited with polycrystalline silicon;
placing the semiconductor structure in a deposition furnace, heating to T1, keeping constant temperature, and performing first-stage silicon deposition at constant temperature;
then heating to T2 at a certain rate, and continuously depositing silicon in the heating process to finish the second stage of silicon deposition;
continuing to maintain the temperature at T2, maintaining the constant temperature, and performing third-stage silicon deposition at the constant temperature;
wherein the ranges of T1 and T2 are both 300-650 ℃, and T2 is more than T1.
2. The deposition method of claim 1, wherein T1 is 300-400 ℃.
3. The deposition method of claim 2, wherein T2 is 400-650 ℃.
4. The deposition method according to any one of claims 1 to 3, wherein the temperature rise rate during the second stage of silicon deposition is 3 to 8 ℃/min.
5. The deposition method of claim 1, wherein the first, second, and third phase silicon depositions are each independently B or P doped silicon.
6. The deposition method of claim 1 or 5, wherein the first, second and third stages of silicon deposition each independently employ CVD, ALD or LPCVD.
7. The deposition method of claim 1, wherein the first, second, and third phase silicon depositions each independently employ at least one of the following silicon sources: monosilane, dichlorosilane, disilane, diisopropylaminosilane, bis (tert-butylamino) silane, bis (diethylamino) silane, hexachlorodisilane, tris (dimethylamino) silane, butylaminosilane, diethylaminosilane, dipropylaminosilane, hexaethylaminodisilane.
8. The deposition method of claim 1, wherein the semiconductor structure is a DRAM bit line contact hole or a DRAM storage node contact hole.
9. A method for forming a bit line contact plug, comprising:
bit line contact holes are formed on a semiconductor substrate,
depositing polysilicon into the bit line contact hole by using the deposition method of any one of claims 1 to 8;
the semiconductor structure is a semiconductor substrate comprising a bit line contact hole.
10. A method for fabricating a storage node contact plug, comprising:
a storage node contact hole is formed on a semiconductor substrate,
depositing polysilicon into the storage node contact hole by using the deposition method according to any one of claims 1 to 8;
the semiconductor structure is a semiconductor substrate comprising a storage node contact hole.
CN202110020532.1A 2021-01-07 2021-01-07 Deposition method of polysilicon and manufacturing method of contact plug Pending CN114743974A (en)

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CN202110020532.1A CN114743974A (en) 2021-01-07 2021-01-07 Deposition method of polysilicon and manufacturing method of contact plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110020532.1A CN114743974A (en) 2021-01-07 2021-01-07 Deposition method of polysilicon and manufacturing method of contact plug

Publications (1)

Publication Number Publication Date
CN114743974A true CN114743974A (en) 2022-07-12

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