TW202021092A - 用於混合接合的後化學機械研磨處理 - Google Patents
用於混合接合的後化學機械研磨處理 Download PDFInfo
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- TW202021092A TW202021092A TW108125399A TW108125399A TW202021092A TW 202021092 A TW202021092 A TW 202021092A TW 108125399 A TW108125399 A TW 108125399A TW 108125399 A TW108125399 A TW 108125399A TW 202021092 A TW202021092 A TW 202021092A
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Abstract
裝置及技術包括用於穿過堆疊且接合之結構而形成開口的製程步驟。藉由在接合層之平坦化(藉由化學機械研磨(CMP)或類似者)後且在接合前預先蝕刻貫穿製備之晶粒之一或多層來形成開口。舉例而言,在接合晶粒以形成構件之前,穿透待接合之晶粒的一或多個層蝕刻所述開口。
Description
以下描述係關於積體電路(「IC」)。更特定言之,以下描述係關於製造IC晶粒及晶圓。
優先權主張及相關申請之交互參照
本申請案依據35 U.S.C. §119(e)(1)主張2019年7月15日提交的美國非臨時申請案第16/511,394號及2018年7月26日提交的美國臨時申請案第62/703,727號之權益,所述申請案中之每一者在此以其全文引用之方式併入。
微電子元件常包含半導體材料(諸如,矽或砷化鎵)之薄板,通常叫作半導體晶圓。晶圓可被形成以包括在晶圓之表面上及/或部分嵌入於晶圓內的多個積體晶片或晶粒。與晶圓分開之晶粒通常提供為個別、預封裝之單元。在一些封裝設計中,將晶粒黏著至基板或晶片載體,基板或晶片載體又黏著至諸如印刷電路板(PCB)之電路面板。舉例而言,許多晶粒提供於適合於表面黏著之封裝中。
封裝之半導體晶粒亦可以「堆疊式」佈置來提供,其中例如在電路板或其他載體上提供封裝,且將另一封裝黏著於第一封裝之上。所述佈置可允許許多不同晶粒或裝置黏著於電路板上之單一佔據面積內,且可進一步有助於藉由提供封裝之間的短互連而進行之高速操作。通常,此互連距離可僅比晶粒自身之厚度稍大。為了在晶粒封裝之堆疊內達成互連,用於機械及電連接之互連結構可提供於每一晶粒封裝(惟最頂部封裝除外)之兩側(例如,面)上。
另外,可按三維佈置來堆疊晶粒或晶圓,作為各種微電子包裝方案之部分。此可包括將一或多個晶粒、裝置及/或晶圓之層堆疊於較大基底晶粒、裝置、晶圓、基板或類似者上,以垂直或水平佈置來堆疊多個晶粒或晶圓,及兩者之各種組合。
可使用各種接合技術(包括直接介電質接合)、非黏著性技術(諸如,ZiBond®)或混合接合技術(諸如,DBI®)來在堆疊之佈置中接合晶粒或晶圓,ZiBond®及DBI®皆可購自Invensas Bonding Technologies公司(前身為Ziptronix公司),其為一Xperi公司(例如,見美國專利第6,864,585號及第7,485,968號,其全部併入本文中)。接合之晶粒或晶圓之各別配合表面常包括內嵌之傳導性互連結構,或類似者。在一些實例中,接合表面經佈置及對準,使得在接合期間結合來自各別表面之傳導性互連結構。結合之互連結構形成在堆疊之晶粒或晶圓之間的連續傳導性互連件(用於訊號、電力等)。
可存在實施堆疊之晶粒或晶圓佈置之多種難題。當使用直接接合或混合接合技術接合堆疊之晶粒時,通常需要待接合的晶粒之表面極其平坦、平滑且清潔。舉例而言,一般而言,所述表面在表面拓撲中應具有非常低之變異數(variance)(亦即,奈米級變異數),使得所述表面緊密地配合以形成持久之接合。
在接合表面處之傳導性互連結構可稍微凹陷,恰好在接合表面之絕緣材料下方。在接合表面下方的凹陷之量可由裝置或應用之尺寸容差、規格或實體限制來決定。可使用化學機械研磨(CMP)製程或類似者製備將該混合表面用於與另一晶粒、晶圓或其他基板接合。
另外,在一些應用中,需要在接合表面上或旁或在接合表面處之空穴內形成打線接合襯墊、測試襯墊或其他結構,以在接合後常自堆疊且接合之裝置之外接取。可使用開口或空穴創造用於感測器應用之接取口、物理性及電性接取(例如,用於線接合、測試、電連接等)、低阻抗、低損失連接、空橋(air bridges)等等。透過堆疊且接合之晶粒、晶圓及基板來形成空穴以容納所述結構、連接、接取口及為了其他目的可能是有問題的,特別是,當所要之空穴具有較細間距及/或顯著深度時。
本發明揭露代表性技術及裝置,包括用於經由堆疊且接合之結構形成孔、空穴、開口、凹陷及類似者(下文,「開口」)之製程步驟。其中特別關注的是如上論述的使用直接接合及混合接合技術(無黏著劑)形成之密切接合之結構。在各種具體實例中,藉由在接合層之平坦化(藉由化學機械研磨(CMP)或類似者)後且在接合前預先蝕刻貫穿製備之晶圓或晶粒之一或多層來形成開口。舉例而言,在接合晶粒以形成構件前,穿透待接合晶粒的一或多個層蝕刻開口。
在各種實施中,一種微電子構件包含:第一基板,其具有具無機介電材料或絕緣體之經平坦化拓撲之接合表面;及第一多個導電性特徵,其內嵌於介電層中,其中一個表面暴露於該第一基板之該接合表面處;及第二基板,其具有具無機介電材料或絕緣體之經平坦化拓撲之接合表面,該接合表面接合至該第一基板之該接合表面。該第二基板包括內嵌於該介電層中之第二多個導電性特徵,其中一個表面暴露於該第二基板之該接合表面處,該第二多個導電性特徵接合至該第一多個導電性特徵。第一多個導電性特徵與第二多個導電性特徵直接接合,例如,使用混合接合技術或類似者,而不使用焊料或其他添加之接合材料。術語「傳導性(導電性)特徵」之使用將在本文中用以具體地指所述直接接合傳導性特徵。
與所述直接接合導電性特徵分開之一或多個導電性接觸襯墊安置於該第二基板之絕緣層內且在該第二基板之該接合表面下方。該一或多個導電性接觸襯墊可安置於該第一多個導電性特徵及該第二多個導電性特徵之周界外部或內部,或在一或多個指定區中。所述導電性接觸襯墊可包括不同於所述導電性特徵之任一傳導性結構,其可用作用於打線接合、端子、測試襯墊、球柵等等之傳導性互連件。
在一個晶粒或晶圓之「傳導性特徵」可具有在第二直接接合之晶粒或晶圓上之匹配或配合傳導性特徵之情況下,為了晶粒至晶粒、晶圓至晶圓或晶粒至晶圓直接接合之目的,「接觸襯墊」是不匹配的。舉例而言,一個晶粒或晶圓之接觸襯墊通常不具有待直接接合至第二接合之晶粒或晶圓上之配合接觸襯墊。另外,接觸襯墊通常與傳導性特徵在不同(例如,「較低」)之晶粒或晶圓層上,且可安置或內埋於該晶粒或晶圓之接合表面下方。
在一實施中,該微電子構件進一步包含在該第二基板之絕緣層中之一或多個二級開口,其與該一或多個導電性接觸墊對準。該一或多個二級開口自該第二基板之該接合表面延伸至該一或多個導電性接觸襯墊,從而提供至該一或多個導電性接觸襯墊之通路。
在另一實施中,該微電子構件進一步包含在該第一基板之絕緣層中之一或多個一級開口,其與該一或多個二級開口且與該導電性接觸墊對準。該一或多個一級開口延伸至該一或多個二級開口,從而提供至該一或多個導電性接觸襯墊之通路。
在另一實施中,該微電子構件進一步包含在該第一基板之基底層中之一或多個三級開口,其與該第一基板之該絕緣層中的該一或多個一級開口且與該導電性接觸墊對準。該一或多個三級開口自該第一基板之外表面延伸至該一或多個一級開口,從而提供自該第一基板之該外表面至該一或多個導電性接觸襯墊之通路。
在一具體實例中,該微電子構件包含安置於該一或多個二級開口、該一或多個一級開口及該一或多個三級開口中之一或多者內且電耦接至該一或多個導電性接觸襯墊之一或多個導電性結構。
在另一實施中,一種微電子構件包含:第一基板,其具有具經平坦化拓撲之一接合表面,具有在該第一基板之該接合表面處之第一多個導電性特徵;及第二基板,其具有具一經平坦化拓撲之接合表面,該接合表面接合至該第一基板之該接合表面。第二多個導電性特徵安置於該第二基板之該接合表面處,且接合至該第一多個導電性特徵,同時以第一程度不對準於該第一多個導電性特徵。一或多個導電性接觸襯墊安置於該第二基板之一絕緣層內且在該第二基板之該接合表面下方。該一或多個導電性接觸襯墊安置於該第一多個導電性特徵及該第二多個導電性特徵之一周界外部,或在一或多個指定區中。該第二基板之該絕緣層中之一或多個二級開口與該一或多個導電性接觸襯墊對準,且該一或多個二級開口自該第二基板之該接合表面延伸至該一或多個導電性接觸襯墊。該第一基板之該絕緣層中之一或多個一級開口以第一程度不對準於該一或多個二級開口,且該一或多個一級開口延伸至該一或多個二級開口且提供至該一或多個導電性接觸襯墊之通路。
在額外實施中,一種微電子構件包含:第一基板,其具有混合接合表面,該混合接合表面包含在其中具有一或多個金屬特徵之絕緣體材料及經平坦化拓撲;及第二基板,其具有混合接合表面,該混合接合表面包含具有內嵌於其中之一或多個金屬特徵之絕緣體材料,具有經平坦化拓撲,且接合至該第一基板之該混合接合表面。該第二基板之該一或多個金屬特徵接合至該第一基板之該一或多個金屬特徵。空穴安置於該第一基板與該第二基板之間的接合接頭處,在該接合接頭處,該第一基板之該混合接合表面與該第二基板之該混合接合表面進行接觸。該空穴至少由在該第一基板之該混合接合表面中之凹陷形成。連續密封件由該第一基板之該一或多個金屬特徵及該第二基板之該一或多個金屬特徵形成,且安置圍繞在該接合接頭處的該空穴之一周邊。
參考電及電子組件及變化之載體來論述各種實施及佈置。雖然提到了具體組件(亦即,晶粒、晶圓、積體電路(IC)晶片晶粒、基板等),但此並不意欲為限制性,且係為了易於論述及說明方便。參考晶圓、晶粒、基板或類似者論述之技術及裝置適用於可經耦接以相互界面連接、與外部電路、系統、載體及類似者界面連接的任何類型之或任何數目個電組件、電路(例如,積體電路(IC)、混合電路、ASICS、記憶體裝置、處理器等)、組件群組、經封裝組件、結構(例如,晶圓、面板、板、PCB等)及類似者。所述不同組件、電路、群組、封裝、結構及類似者中之每一者可一般地被稱作「微電子組件」。為了簡單起見,除非另有指定,否則接合至另一組件之組件將在本文中被稱作「晶粒」。
此發明內容並不意欲給出全面描述。以下使用多個實例更詳細地解釋實施。雖然在此處及下文論述各種實施及實例,但藉由組合個別實施及實例之特徵及元件,另外實施例及範例可以是可能的。
綜述
經圖案化金屬及諸如氧化矽之無機介電材料層通常設置於晶粒、晶圓或其他基板(下文,「晶粒」)上,作為混合接合,或DBI®
表面層。介電層通常高度平坦(通常達nm級粗糙度),其中金屬層(例如,內嵌之傳導性特徵)在氧化物表面處或凹陷於該氧化物表面正下方。在氧化物下方的凹陷之量通常由尺寸容差、規格或實體限制來決定。可使用化學機械研磨(CMP)步驟來製備該混合表面用於與另一晶粒、晶圓或其他基板接合。
本文中揭露之裝置及技術允許在CMP步驟後進一步蝕刻氧化物(或其他絕緣層)以在該接合層中或穿過該接合層形成開口、空穴或凹陷。所述開口或凹陷允許形成或接取特徵或結構,諸如,打線接合襯墊、測試襯墊、晶粒空穴等等。形成所述空穴可意謂在CMP步驟後但在接合前需要蝕刻至混合接合表面層內之額外開口。可使用所述空穴創造用於感測器應用(例如,DNA分析)之接取口、物理性及電性接取(例如,用於測試、線接合、電連接等)、低阻抗、低損失連接、空橋及類似者。
本文中描述之技術可用於在接合前在個別晶粒或晶圓中形成較淺空穴、凹陷或開口,藉此避免必須在接合後在晶粒或晶圓兩者中蝕刻較深之單一空穴。相較於接合後可能有氧化物蝕刻,此製程導致更清潔之接合襯墊表面及更細的間距能力。此外,該製程亦允許在頂部及底部晶圓或晶粒中形成具有不同尺寸之空穴。舉例而言,溝槽開口可形成於底部晶粒中,且點狀開口可形成於頂部晶粒中,或反之亦然。替代地,形成於底部晶粒中之開口可比形成於頂部晶粒中之開口大,或反之亦然(見圖29至圖32)。
如將瞭解,此空穴蝕刻技術亦可改良用於微機電系統(MEMS)或其他感測器應用之金屬密封環或電接觸。本文中描述之技術亦經由在晶粒單一化之前切割道蝕刻之製程來改良接合。此藉由減少切屑來改良切割,且改良在該領域中之電晶體可靠性。
圖1至圖33例示用於形成及製備各種微電子組件(諸如,晶粒102)以用於接合(諸如,用於無黏著劑之直接接合)之代表性裝置及製程。所述製程包括在微電子組件上提供接合表面(諸如,接合表面108),或在一些實例(圖中未示)中提供兩個接合表面,從而提供內嵌至接合表面內的傳導性互連特徵或結構,修復或減輕由於處理或缺陷而在接合表面中的銹蝕、表面凹陷及類似者,在接合表面中預先蝕刻一或多個開口,藉由直接接合在接合表面處之微電子組件來形成微電子構件,等等。
本文所描述製程之次序並不意欲解釋為限制性,且可按任意次序組合所述製程中所描述之製程區塊的任何數目個來實施所述製程或替代製程。另外,在不脫離本文中描述的主題之精神及範圍之情況下,可自任何所述製程中刪除個別區塊。另外,在不脫離本文中描述的主題之範圍之情況下,所述製程可在任何合適硬體、軟體、韌體或其組合中實施。在替代實施中,其他技術可以各種組合包括於所述製程中,且保持處於本揭露內容之範圍內。
分別參考圖1及圖2以及製程100及200,可使用各種技術來形成代表性「晶粒」102,以包括基底基板104及絕緣或介電層106。基底基板104可由矽、鍺、玻璃、石英、介電表面、直接或間接能隙半導體材料或層或另一合適材料加上通常被稱作後端製程(BEOL)層的在絕緣介電質中之金屬佈線之多個層組成。絕緣層106沈積或形成於基板104上,且可由無機介電材料層(諸如,氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、金剛石狀材料、玻璃、陶瓷、玻璃陶瓷及類似者)組成。舉例而言,絕緣層106可為BEOL之最後一個層,或經具體地沈積以用於混合接合之額外層。
晶粒102之接合表面108可包括傳導性特徵110,諸如,互連結構,其內嵌至絕緣層106內且經佈置使得來自對置晶粒102之各別接合表面108的傳導性特徵110可在接合期間配合及結合(若需要)。結合之傳導性特徵110可形成在堆疊之晶粒102之間的連續傳導性互連件(用於訊號、電力等)。
鑲嵌製程(或類似者)可用以在絕緣層106中形成內嵌之傳導性特徵110。傳導性特徵110可由金屬(例如,銅等)或其他傳導性材料或材料之組合組成,且包括結構、跡線、襯墊、圖案等等。傳導性特徵110可包括於絕緣層106中以提供電及/或熱路徑,或可替代地被配置以經由使用額外襯墊或所謂的虛設襯墊、跡線、圖案或類似者來抵消接合表面108之金屬化。在形成傳導性特徵110後,可平坦化(例如,經由CMP)晶粒102的暴露之表面(包括絕緣層106及傳導性特徵110),以形成平坦接合表面108。
如在圖1及圖2中展示,在製程100及200之區塊A處,晶粒102之一或多個接合表面108(包括內嵌之互連結構110)可被平坦化(使用化學機械研磨(CMP)或類似者)來製備接合表面108以用於接合。形成接合表面108包括整飾接合表面108以符合介電粗糙度規格及金屬層(例如,銅等)凹陷規格,以接合製備表面108用於直接接合。換言之,使接合表面108盡可能平坦且平滑地形成,具有非常微小之表面拓撲差異。諸如化學機械研磨(CMP)之各種習知製程可用以達成低表面粗糙度。此製程提供導致晶粒102之間的可靠接合之平坦、平滑接合表面108。
在一些情況下,如在圖1製程100區塊A中所展示,傳導性特徵110之暴露之表面可相對於接合表面108有意地凹陷,例如,至深度「d1」,以允許材料膨脹,特別在加熱之退火期間(若將要執行此操作)。在其他情況下,如在圖2製程200區塊A中所展示,可超越凹陷規格來形成傳導性特徵110之暴露之表面,且該表面可突出於接合表面108上方至高度「d2」,以允許在稍後處理期間的傳導性特徵110之氧化。舉例而言,此可藉由介電層106之選擇性蝕刻來實現。
在研磨或其他製程步驟(諸如,在研磨步驟後在接合層108中形成一開口)期間,在接合層108處之傳導性特徵110可改變(例如,變得經氧化)且變得不在所要的規格中。此例示於圖1及圖2製程100及200區塊B處,其中氧化展示於112處。
可調整傳導性特徵110,如在圖1及圖2製程100及200區塊C處展示,以改良隨後接合及電連接。該調整可藉由傳導性特徵110之選擇性濕式蝕刻來達成,例如,藉由選擇性溶解形成於傳導性特徵110上之金屬氧化物(例如,氧化銅)之化學蝕刻,或藉由修整CMP製程,或類似者。在調整之後,傳導性特徵110相對於接合表面108之凹陷在規格(例如,「d3」及「d4」)之容差內。
實例具體實例
參看圖3,展示微電子構件300,其包含至少兩個直接接合(例如,無黏著劑)之晶粒102及302。替代地,微電子組件302可包含晶圓,或其他基板,或類似者。然而,微電子組件302包括安置於晶粒102周界之外的一或多個接觸襯墊306。
兩個晶粒102及302之內嵌之導電性特徵110(例如,混合接合襯墊等)延伸至晶粒102及302之接合表面108,且接合在一起,從而形成接合互連結構304。在一具體實例中,第一晶粒102可如上在製程100或200處所描述來形成。
歸罪於晶粒302之絕緣層106中的開口308,晶粒302之接觸襯墊306(亦即,暴露之非混合傳導性襯墊)經由晶粒302之接合表面108暴露。如上所論述,接觸襯墊306可用於關於晶粒302之測試、線接合、其他電連接等等。在一些具體實例中,傳導性塗層310(例如包含鎳、金或其他金屬)可安置於接觸襯墊306上以保護接觸襯墊306不被氧化、腐蝕或類似者。
在一實施中,第二晶粒302可如在製程400中所描述來形成,包括在將第二晶粒302接合至第一晶粒102前形成開口308。替代地,在具有結構300之一些具體實例中,在接合至第一晶粒102後,開口308可形成於第二晶粒302中。
參看圖4製程400(亦見圖33之文字流程圖,其補充圖4及圖5之圖形流程圖),在區塊A,晶粒302經形成及製備以用於直接接合,包括在基底基板104上形成絕緣層106,在絕緣層106中形成一或多個傳導性特徵110,及如上所述形成高度平坦之接合層108。在一實施中,製程400包括在絕緣層106內形成內埋之接觸襯墊306。
在區塊B,製程400包括在接合表面108上形成圖案化之抗蝕劑層402,其中抗蝕劑層402中之經圖案化間隙在內埋之接觸襯墊306上對準。視情況,若需要,圖案化之抗蝕劑層402可包括在切割道上之間隙。在區塊C,製程400包括經由抗蝕劑層402中之間隙蝕刻絕緣層106,從而形成開口308以暴露內埋之接觸襯墊306。
參看圖5,在區塊D,若需要,製程400視情況包括用保護性金屬層310(例如,鎳、金、銀、焊接等)覆蓋露出之接觸襯墊306,以保護接觸襯墊306。保護性層310可使用例如無電電鍍或另一技術(若需要,諸如,浸鍍或類似者)來塗覆。
在區塊E,製程400包括自接合表面108移除抗蝕劑402。舉例而言,抗蝕劑402可使用濕式剝離,接著以氧電漿灰化來移除。在一些情況中,抗蝕劑402移除步驟可使傳導性特徵110之表面氧化(例如,形成銅的氧化物404)。取決於氧化物404之量,傳導性特徵110之表面可突出於接合表面108上方,如在圖5中展示。
在區塊F,製程400包括自傳導性特徵110移除氧化物404。舉例而言,氧化物404可為約1 nm至100 nm厚。替代地,在一些情況中,氧化可更厚。在任一情況中,控制材料移除之速率(包括移除氧化物404之速率,以及移除傳導性特徵110之金屬(例如,銅等)中之一些以遵守凹陷規格之速率)可具有重要性。舉例而言,移除正確量之材料可避免必須重新製造晶粒302,包括重新形成絕緣層106及/或傳導性特徵110。遺憾地,使用常用技術中之許多者,可能易於過度蝕刻材料。
在各種具體實例中,使用受控制之選擇性蝕刻技術來移除氧化物404,此可包括藉由稀釋配方(諸如,硫酸或磺酸與水之1 : 20比率)來蝕刻氧化物404。替代地,可使用具有針對研磨障壁層(諸如,在鑲嵌製程期間,在銅沈積前沈積至絕緣層106之空穴內的障壁層)而調配之漿料的輕CMP來選擇性移除氧化物404。然而,對於奈米級材料移除,使用化學蝕刻可更易於受控制。作為藉由受控制之材料移除進行的氧化物404移除步驟之部分,可達成用於傳導性特徵110之指定凹陷。
參看圖5A至圖5C,作為製程400之替代步驟,或除了在區塊D至F中之製程步驟之外,一或多個可選層亦可沈積於暴露之接觸襯墊306(及保護性金屬層310)上,此可包括將該(等)層沈積於晶粒302之接合表面108上。舉例而言,在一些情況中,歸因於耦接至電路或暴露之接合襯墊之傳導性特徵110的雙金屬效應及光伏效應,可體驗到在一些傳導性特徵110上的蝕刻之電化學增強。所述效應可導致接觸襯墊306之腐蝕。
在一些情況中,(參看圖5A,在區塊G),大致10 nm至200 nm之氧化物及/或障壁金屬之層502可沈積於晶粒302之接合表面108及接觸襯墊306(包括保護性金屬層310)上。如在區塊H展示,CMP(或類似者)可用以重新暴露在接合表面108上之傳導性特徵110。層502保持處於接觸襯墊306上。在區塊I,第一晶粒或晶圓102直接接合至第二晶粒302,無黏著劑。
參看圖5B,在區塊J,在第二晶粒302接合至第一晶粒或晶圓102後,可使第一晶粒或晶圓102之頂部基底層104變薄。在區塊K,將一經圖案化之抗蝕劑層402塗覆至晶粒102之頂表面,其中抗蝕劑中之間隙在需要移除基底層104之位置處(例如,在開口602上,以及其他如所需要之位置)。在區塊L,在晶圓或晶粒102之基底層104中蝕刻開口以接取接觸襯墊306。晶粒102之基底層104中的開口可形成為與晶粒102及晶粒302中之任一者或兩者之絕緣層106中的開口相同之大小,或其可比晶粒102及/或晶粒302中之配合開口大或小。
參看圖5C,在區塊M,藉由在晶圓或晶粒102之基底層104中創造的開口,接觸襯墊306上之薄層502可藉由簡短之毯覆式乾蝕刻或類似技術來移除。接著,如在區塊N處所展示,可移除光阻402。舉例而言,可使用濕式剝離來移除抗蝕劑402。所得微電子構件500展示於區塊N。
參看圖6,展示微電子構件600,其包含至少兩個直接接合(例如,無黏著劑)之晶粒102及302。替代地,微電子組件102及302可包含兩個晶粒、兩個晶圓、一個晶粒與一個晶圓,或其他基板,或類似者。然而,微電子組件302包括安置於晶粒102周界內部的一或多個接觸襯墊306。
兩個晶粒102及302之內嵌之傳導性特徵110(例如,混合接合襯墊等)延伸至晶粒102及302之接合表面108,且接合在一起,從而形成接合互連結構304。在一具體實例中,第一晶粒102可如在製程700處所描述來形成。
參看圖7及製程400,在區塊A,晶粒102經形成及製備以用於直接接合,包括在基底基板104上形成絕緣層106,在絕緣層106中形成一或多個傳導性特徵110,及如上所述形成高度平坦之接合層108(例如使用CMP)。在各種實施中,對晶圓執行區塊A,且可在單切前執行製程700之步驟(若需要)。
在區塊B處,製程700包括在接合表面108上形成圖案化之抗蝕劑層402,其中一旦晶粒102與302對準且接合,則抗蝕劑層402中之經圖案化間隙在絕緣層106之對應於用於晶粒302中之內埋之接觸襯墊306的位置之一部分上對準。視情況,晶粒102中之開口可形成為與晶粒302中之開口相同的大小,或其可比晶粒302中之配合開口大或小。視情況,若需要,圖案化之抗蝕劑層402可包括在切割道上之間隙。在區塊C,製程700包括經由抗蝕劑層402中之間隙蝕刻絕緣層106(及若需要,基底基板104中之一些),從而形成絕緣層106中之開口702。
參看圖8,在區塊D,製程700包括自接合表面108移除抗蝕劑402。舉例而言,抗蝕劑402可使用濕式剝離,接著以氧電漿灰化來移除。在一些情況中,抗蝕劑402移除步驟可使傳導性特徵110之表面氧化(例如,形成銅的氧化物404)。取決於氧化物404之量,傳導性特徵110之表面可突出於接合表面108上方,如在圖8中展示。
在區塊E,製程700包括使用具有針對研磨障壁層而調配之漿料之CMP製程或類似者及/或如上所述之濕式蝕刻製程自傳導性特徵110移除氧化物404,同時控制在傳導性特徵110上的材料之移除速率。舉例而言,使用選擇性蝕刻技術來移除氧化物404,此可包括藉由稀釋配方(諸如,硫酸或磺酸與水之1 : 20比率)來蝕刻氧化物404。作為藉由受控制之材料移除進行的氧化物404移除步驟之部分,可達成用於傳導性特徵110之指定凹陷。
在一些情況中,舉例而言,歸因於雙金屬效應及光伏效應,可體驗到在一些傳導性特徵110上的蝕刻之電化學增強。在所述情況中,可將10 nm至200 nm之氧化物及/或障壁金屬沈積於接合表面108及接觸襯墊306上。CMP(或類似者)可用以重新暴露在接合表面108上之傳導性特徵110。
在一實施中,第二晶粒302可如在製程900中所描述來形成,包括在將第二晶粒302接合至第一晶粒102前在晶粒302之絕緣層106中形成開口。
參看圖9製程900,在區塊A,晶粒302經形成及製備以用於直接接合,包括在基底基板104上形成絕緣層106,在絕緣層106中形成一或多個傳導性特徵110,及如上所述形成高度平坦之接合層108。在一實施中,製程900包括在絕緣層106內形成內埋之接觸襯墊306。在各種實施中,對晶圓執行區塊A,且可在單切前執行製程900之步驟(若需要)。
在區塊B,製程900包括在接合表面108上形成圖案化之抗蝕劑層402,其中抗蝕劑層402中之經圖案化間隙在內埋之接觸襯墊306上對準。視情況,若需要,圖案化之抗蝕劑層402可包括在切割道上之間隙。在區塊C,製程900包括經由抗蝕劑層402中之間隙蝕刻絕緣層106,從而形成開口308以暴露內埋之接觸襯墊306。
參看圖10,在區塊D,若需要,製程900視情況包括用保護性金屬層310(例如,鎳、金、銀、焊接等)塗覆露出之接觸襯墊306,以保護接觸襯墊306。保護性層310可使用例如無電電鍍或另一技術(若需要,諸如,浸鍍或類似者)來塗覆。
在區塊E,製程900包括自接合表面108移除抗蝕劑402。舉例而言,抗蝕劑402可使用濕式剝離,接著以氧電漿灰化來移除。在一些情況中,抗蝕劑402移除步驟可使傳導性特徵110之表面氧化(例如,形成銅的氧化物404)。取決於氧化物404之量,傳導性特徵110之表面可突出於接合表面108上方,如在圖10中展示。
在區塊F,製程900包括使用CMP製程及/或如上所述之濕式蝕刻製程自傳導性特徵110移除氧化物404,同時控制在傳導性特徵110上的材料之移除速率。舉例而言,使用選擇性蝕刻技術來移除氧化物404,此可包括藉由稀釋配方(諸如,硫酸(或磺酸)與水之1 : 20比率)或具有針對研磨障壁層而調配之漿料的輕CMP或類似者來蝕刻氧化物404。作為藉由受控制之材料移除進行的氧化物404移除步驟之部分,可達成用於傳導性特徵110之指定凹陷。
在一些情況中,舉例而言,歸因於雙金屬效應及光伏效應,可體驗到在一些傳導性特徵110上的蝕刻之電化學增強。在所述情況中,可將大致10 nm至200 nm之氧化物及/或障壁金屬沈積於接合表面108上及接觸襯墊306(圖中未示)上。CMP(或類似者)可用以重新暴露在接合表面108上之傳導性特徵110。在將第二晶粒302接合至第一晶粒102後,可經由在第一晶粒102中創造之開口來接取接觸襯墊306,且可藉由乾式蝕刻露出接觸襯墊306。
返回參看圖6,將製備之晶粒102與302在各者之接合表面108處的直接接合產生微電子構件600。如所展示,晶粒302中之開口308與晶粒102中之開口702組合以在接觸襯墊306上方形成空穴602。在一些具體實例中,第一晶粒102之基底基板104(例如,其可包含矽)可蝕刻於空穴602及接觸襯墊306上方以提供自微電子構件600外對接觸襯墊306之接取(若需要)。在所述具體實例中,單獨蝕刻穿過基底層104係較佳地用來蝕刻穿過晶粒102之基底層104及絕緣層106,同時將第一晶粒102接合至第二晶粒302。在絕緣層106已經移除之情況下,蝕刻穿過單一層104更容易得多,此改良製造製程。另外,此可導致在接觸襯墊306上比當蝕刻穿過晶粒102之基底層104及絕緣層106兩者時將可能的間距開口細的間距開口。此外,若需要,此允許在兩個晶粒102及302中之每一者內的不同大小及形狀之開口接合在一起。
參看圖11,展示用於形成微電子構件1200之製程1100,該微電子構件包含至少兩個直接接合(例如,無黏著劑)之晶粒102及302。替代地,微電子組件302可包含晶圓,或其他基板,或類似者。然而,微電子組件302包括安置於晶粒102周界內部的一或多個接觸襯墊306。
兩個晶粒102及302之內嵌之傳導性特徵110(例如,混合接合襯墊等)延伸至晶粒102及302之接合表面108,且接合在一起,從而形成接合互連結構304。在一具體實例中,第一晶粒102可如上在製程700處所描述來形成,且第二晶粒302可如上在製程900處所描述來形成因此,製程1100開始於微電子構件600或類似者,其中第一晶粒102可具有比第二晶粒302小、大或實質上與第二晶粒302相同大小之佔據面積。在一些情況中,第一晶粒102與第二晶粒302可實質上對準,或其可輕微不對準,但在混合接合容差內。
參看圖11,在區塊A,展示一實例微電子構件,諸如,先前論述之微電子構件600。在區塊B,製程1100包括如所需的使第一晶粒102之頂部基底晶圓104變薄。在區塊C,製程1100包括在第一晶粒102之基底層104上形成經圖案化抗蝕劑層1102,其中抗蝕劑層1102中之經圖案化間隙在基底層104之對應於需要移除基底層104之部分的位置之部分上對準,包括例如在晶粒302中之空穴602及內埋之接觸襯墊306上、在晶粒102之非主動區上,以及按需要在晶粒102之其他區上。
參看圖21,在區塊D,製程1100包括蝕刻晶粒102之基底層104之材料(例如,矽等)以露出在下方之區,包括在第二晶粒302中之接觸襯墊306(或空穴602中之其他結構)。如所展示,活性基底材料(例如,矽)島狀物1202可留在晶粒102之主動區中的晶粒102之頂表面上。在區塊E,製程1100包括自基底層104移除抗蝕劑1102。舉例而言,抗蝕劑1102可使用濕式剝離,接著以氧電漿灰化來移除。如所展示,此產生微電子元件1200。在區塊F,製程1100可包括可選步驟,其中基底材料島狀物1202可電絕緣及/或EMI屏蔽,或經類似操作。在影像感測器、雷射、發光二極體(LED)等之情況中,可將一抗反射塗層1204或類似者塗覆至島狀物1202。
參看圖13,展示用於形成微電子構件1302之製程1300,該微電子構件包含至少兩個直接接合(例如,無黏著劑)之晶粒102及302。替代地,微電子組件302可包含晶圓,或其他基板,或類似者。然而,微電子組件302包括安置於晶粒102周界內部的一或多個接觸襯墊306。
兩個晶粒102及302之內嵌之傳導性特徵110(例如,混合接合襯墊等)延伸至晶粒102及302之接合表面108,且接合在一起,從而形成接合互連結構304。在一具體實例中,第一晶粒102可如上在製程700處所描述來形成,且第二晶粒302可如上在製程900處所描述來形成因此,製程1300開始於微電子構件600或類似者,其中第一晶粒102可具有比第二晶粒302小、大或實質上與第二晶粒302相同大小之佔據面積。在一些情況中,第一晶粒102與第二晶粒302可實質上對準,或其可輕微不對準,但在混合接合容差內。
在區塊A,展示一實例微電子構件,諸如,先前論述之微電子構件600。在區塊B處,製程1300包括在第一晶粒102之基底層104上形成圖案化之抗蝕劑層1102,其中抗蝕劑層1102中之經圖案化間隙在絕緣層104之對應於用於晶粒302中之空穴602及內埋之接觸襯墊306的位置之一部分上對準。另外,如在區塊B處所展示,可將抗蝕劑沈積於其他位置處,諸如,在晶粒302之接合層108之預定部分處,或類似者。將抗蝕劑置放於額外位置處以防止在所述位置處的材料之蝕刻。
在區塊C,製程1300包括蝕刻晶粒102之基底層104之材料(例如,矽等)以露出在第二晶粒302中之接觸襯墊306。在區塊D,製程1300包括自基底層104移除抗蝕劑1102。舉例而言,抗蝕劑1102可使用濕式剝離,接著以氧電漿灰化來移除。如所展示,此產生微電子元件1302。
額外具體實例
參看圖14,展示用於形成微電子構件1500之製程1400。在各種具體實例中,自製備之晶粒102形成構件1500,其具有如所需的安置於晶粒102內(例如,內嵌於絕緣層106內,且在一些情況中延伸至基底基板104內)之金屬密封環1402。在一些實例中,完工之構件1500之氣密性可基於密封環1402之尺寸。
如在製程100或200中所描述來製備晶粒102,例如,使用鑲嵌製程(或類似者)形成密封環1402。構件1500亦包括一或多個空穴1404,其可終止於絕緣層106內部、終止於絕緣層106與基底層104之界面處或延伸穿過絕緣層106,且可至少部分亦延伸穿過晶粒102之基底層104。因此,構件1500良好地適合於具有空穴之應用,諸如,MEMS、感測器及類似者。構件1500可經形成及製備用於直接接合至另一晶粒、晶圓、基板或類似者或另一構件(諸如,如本文中所描述之另一構件1500)。
在區塊A,製程1400包括如所需的平坦化第一晶粒102之混合接合表面108,例如使用CMP製程。在區塊B處,製程1400包括在第一晶粒102之接合表面108上形成圖案化之抗蝕劑層402,其中抗蝕劑層402中之經圖案化間隙在絕緣層104之對應於用於形成空穴1404的位置之一部分上對準。舉例而言,空穴1404可形成於密封環1402之周界內部。
在區塊C,製程1400包括蝕刻絕緣層106之材料(例如,氧化物、矽等)(部分或完全),及視情況,部分蝕刻至晶粒102之基底層104內達所要的深度以形成一或多個空穴1404。
參看圖15,在區塊D,製程1400包括自接合表面108移除抗蝕劑402。舉例而言,抗蝕劑402可使用濕式剝離,接著以氧電漿灰化來移除。在一些情況中,抗蝕劑402移除步驟可使密封環1402之表面氧化(例如,形成銅的氧化物404)。取決於氧化物404之量,密封環1402之表面可突出於接合表面108上方,如在圖15中所展示。
在區塊E,製程1400包括使用CMP製程及/或如上所述之濕式蝕刻製程自密封環1402移除氧化物404,同時控制在密封環1402上的材料之移除速率。舉例而言,使用選擇性蝕刻技術來移除氧化物404,此可包括藉由稀釋配方(諸如,硫酸與水之1 : 20比率)、具有針對研磨障壁層而調配之漿料的修整CMP或類似者來蝕刻氧化物404。作為藉由受控制之材料移除進行的氧化物404移除步驟之部分,可達成用於密封環1402(若適用)之指定凹陷。
在一些情況中,舉例而言,歸因於雙金屬效應及光伏效應,可體驗到在一些密封環1402上的蝕刻之電化學增強。在所述情況中,可將大致10 nm至200 nm之氧化物及/或障壁金屬沈積於接合表面108上。舉例而言,具有障壁層漿料之CMP(或類似者)可用以修整研磨及重新暴露在接合表面108上之密封環1402。必須仔細地避免在絕緣層106與密封環1402會合時使其邊緣變圓(例如,銹蝕)。製程1400之結果為微電子元件1500,如所展示,其準備用於直接接合。
參看圖16及圖17,展示用於在晶粒102單切前切割道蝕刻之製程1600。在各種具體實例中,可如在製程100或200中所描述來形成及製備晶圓1602,例如,使用鑲嵌製程(或類似者)以形成一或多個傳導性特徵110(或密封環1402等)。在區塊A,製程1600包括如所需的平坦化混合接合表面108,例如使用CMP製程。在區塊B處,製程1600包括在晶圓1602之晶粒102之接合表面108上形成圖案化之抗蝕劑層402,其中抗蝕劑層402中之經圖案化間隙在絕緣層106之對應於用於晶粒102單切的切割道1604之一部分上對準。舉例而言,切割道1604安置於晶圓1602之形成之晶粒102之間。
在區塊C,製程1600包括蝕刻晶粒102之絕緣層104及基底層104之材料(例如,氧化物、矽等),至所要的深度以形成切割道1604通道或凹陷1606。
參看圖17,在區塊D,製程1600包括自接合表面108移除抗蝕劑402。舉例而言,抗蝕劑402可使用濕式剝離,接著以氧電漿灰化來移除。在一些情況中,抗蝕劑402移除步驟可使傳導性特徵110(或例如密封環1402)之表面氧化(例如,形成銅的氧化物404)。取決於氧化物404之量,傳導性特徵110之表面可突出於接合表面108上方,如在圖17中展示。
在區塊E,製程1600包括使用CMP製程及/或如上所述之濕式蝕刻製程自傳導性特徵110移除氧化物404,同時控制在傳導性特徵110上的材料之移除速率。舉例而言,使用選擇性蝕刻技術來移除氧化物404,此可包括藉由稀釋配方(諸如,硫酸與水之1 : 20比率)或藉由具有針對研磨障壁層而調配之漿料的輕CMP或類似者來蝕刻氧化物404。作為藉由受控制之材料移除進行的氧化物404移除步驟之部分,可達成用於傳導性特徵110(若適用)之指定凹陷。
在一些情況中,舉例而言,歸因於雙金屬效應及光伏效應,可體驗到在一些傳導性特徵110上的蝕刻之電化學增強。在所述情況中,可將大致10 nm至200 nm之氧化物及/或障壁金屬沈積於接合表面108上。舉例而言,具有障壁層漿料之CMP(或類似者)可用以修整研磨及重新暴露在接合表面108上之傳導性特徵110。必須仔細地避免在絕緣層106與傳導性特徵110會合時使其邊緣變圓(例如,銹蝕)。
在區塊F,作為一選項,若需要,可將保護性塗層1702塗覆至接合表面,以及在切割道凹陷1606內塗覆。該保護性塗層可在單一化成個別晶圓102期間保護接合表面108,單一化發生於切割道凹陷1606內。
在各種具體實例中,晶圓(諸如,晶圓1602)、晶粒(諸如,晶粒102及302)及具有混合接合表面108之其他基板等等可在長期儲存導致金屬特徵(諸如,傳導性特徵110、密封環1402及類似者)之一些氧化後經修整研磨。修整研磨可包括使用CMP製程及/或如本文中所描述之濕式蝕刻,同時控制在金屬特徵上的材料之移除速率。舉例而言,使用選擇性蝕刻技術來移除氧化,此可包括藉由稀釋配方(諸如,硫酸與水之1 : 20比率)、具有針對研磨障壁層而調配之漿料的修整研磨或類似者來蝕刻氧化物。作為藉由受控制之材料移除進行的氧化移除步驟之部分,可恢復用於金屬特徵(若適用)之指定凹陷。
在一些情況中,舉例而言,歸因於雙金屬效應及光伏效應,可體驗到在一些金屬特徵上的蝕刻之電化學增強。在所述情況中,可將大致10 nm至200 nm之氧化物及/或障壁金屬沈積於接合表面108上。舉例而言,具有障壁層漿料之CMP(或類似者)可用以修整研磨及重新暴露在接合表面108上之金屬特徵。必須仔細地避免在絕緣層106與金屬特徵會合時使其邊緣變圓(例如,銹蝕)。在修整研磨後,製備晶圓、晶粒、基板等用於直接接合。
額外實例構件
參看圖18至圖32,在各種具體實例中,可基於或相關於構件300、600、1302、1500等等形成各種微電子構件。換言之,各種微電子構件包含兩個或更多個直接接合之晶粒102及/或302、晶圓1602、基板及類似者按各種組合之構件。
參看圖18,在區塊A,展示微電子構件1800,其包含具有安置於晶粒102周界之內部之一或多個接觸襯墊306的構件600。構件1800包括穿過晶粒102之基底層104蝕刻的開口,以露出第二晶粒302中之接觸襯墊306及空穴602,如在圖12區塊E中所展示。
如在圖18中所展示,在一些情況中,第一晶粒102與第二晶粒302(及各別傳導性特徵110)可實質上對準,或其可輕微不對準,但在混合接合容差內。第一晶粒102與第二晶粒302中之開口702與308亦可稍微不對準,但仍形成空穴602,且仍提供至接觸襯墊306之充分接取。
視情況,如在區塊B中所展示,一或多個傳導性互連結構1802可電耦接至接觸襯墊306,以提供自構件1800之頂部至接觸襯墊306之電接取。舉例而言,在一些情況中,傳導性互連結構1802可突出於晶粒102之基底層104之頂部上方。
在一具體實例中,如在圖19處展示,構件1800之第一晶粒102可具有比第二晶粒302小的佔據面積。在另一具體實例中,如亦在圖19中所展示,並非所有空穴602皆可包括傳導性互連結構1802。至接觸襯墊306之通路可為自空穴602內部,或類似者。
在一具體實例中,如在圖20處展示,微電子構件2000可包含構件300,其中構件2000之第一晶粒102具有比第二晶粒302小的佔據面積,且其中第二晶粒302之非混合接觸襯墊306安置於第一晶粒102之周界之外。在一替代實施中,構件200包括電耦接至接觸襯墊306之一或多個傳導性互連結構1802,以提供自構件2000之頂部至接觸襯墊306之電接取。
在一具體實例中,如在圖21處展示,微電子構件2100可包含構件1200,其中構件2000之第一晶粒102具有比第二晶粒302小、大的佔據面積或實質上與第二晶粒302相同大小之佔據面積,且其中第二晶粒302之非混合接觸襯墊306安置於第一晶粒102之周界之內部。另外,第一晶粒102包括藉由在晶粒102之非主動區中蝕刻掉晶粒102之頂部基底層104而形成之島狀物1202。舉例而言,活性基底材料(例如,矽)島狀物1202可留在晶粒102之主動區中的晶粒102之頂表面上。在一些具體實例中,基底材料島狀物1202可經電絕緣及/或EMI屏蔽,或類似者。在影像感測器、雷射、發光二極體(LED)等之情況中,可將抗反射塗層塗覆至島狀物1202。
在一替代具體實例中,如在圖22處所展示,構件2100包括在第一晶粒102之暴露之絕緣層106上的至少一個金屬層2202。在各種實例中,金屬層2202可按需要提供EMI保護、熱消散或其他功能。
在另一替代具體實例中,如在圖23處所展示,構件2100可包括在空穴602中之一或多者中的沈積之金屬2302,其電耦接至接觸襯墊306以用於至接觸襯墊306之互連。舉例而言,在一些情況中,在進行所要的互連時,為了方便,一端子2304(諸如,焊球或類似者)可耦接至沈積之金屬2302。
參看圖24至圖26,展示具有空穴1404及密封環1402之直接接合之構件2400。在各種實施中,構件2400由無黏著劑直接接合(例如,混合接合)之至少一對構件1500形成。在如圖24中展示之一具體實例中,構件1500中之每一者之空穴1404穿過絕緣層106且部分穿過基底層104蝕刻。在各種替代具體實例中,空穴1404可比蝕刻至另一構件1500'內多或少地蝕刻至構件1500中之一者內。見以下針對一些實例蝕刻深度選項。
在一個實例中,如在圖25中所展示,蝕刻至第一構件1500內而不蝕刻至第二構件1500'內之空穴1404。在圖25之圖式中展示之實例蝕刻深度係穿過絕緣層106,且部分至基底層104內。替代地,蝕刻深度可部分地僅穿過絕緣層106,或穿過絕緣層106但不至基底層104內。在替代具體實例中,可將空穴1404蝕刻至第二構件1500'內且不至第一構件1500內(見以上針對實例蝕刻深度選項)。另外,如在圖26中所展示,構件2400可包括黏著於空穴1404內部之一或多個組件2602(例如,組件、結構、電路、元件等)。由於構件2400包括密封環1402,因此可氣密性地密封空穴1404,從而提供用於各種感測器、MEMS或類似者之理想環境。
參看圖27至圖28,在另一具體實例中,構件2700包含構件2400,其中第二構件1500'具有比第一構件1500之佔據面積大的佔據面積。在實例中,第二構件1500'包括在第一構件155之周界外的周邊接合襯墊2702,其可用於線接合2704或類似之電連接。構件之空穴1404可包括一或多個組件2602,且歸因於存在密封環1402,空穴1404可經氣密性地密封。又,構件2700可包括一或多個傳導性特徵110用於在構件2700內及至外部組件之電互連,例如,使用一矽穿孔(例如,TSV)2706或類似者。
如在圖28中所展示,可堆疊多個構件2700以形成構件2800。替代地,如所展示,多個構件2700中之至少一或多個可不包括在構件1500及/或1500'中之一者上的基底層104。如所展示,所述構件可包括密封環1402以及傳導性特徵110(所述構件經佈置以藉由或不藉由通孔2706而將構件2700電耦接在一起)。
參看圖29至圖32,展示微電子構件2900,其包含具有安置於晶粒102周界之內部的一或多個接觸襯墊306之構件500。舉例而言,圖29及圖31展示微電子構件2900,其具有安置於構件2900之兩個主動區(2902與2904)之間的接觸襯墊306。因此,接觸襯墊306可安置於並非必要地在晶粒102及302之周邊處的預選定區處。舉例而言,接觸襯墊306可安置於晶粒102及302之主動區之周界內。構件2900包括穿過晶粒102之基底層104及絕緣層106以及晶粒302之絕緣層106蝕刻之開口,以露出空穴602及第二晶粒302中之接觸襯墊306。
圖30例示構件2900或類似者之俯視圖,展示接觸襯墊306可呈傳導性條或其他成形結構之形式。舉例而言,堆疊之動態隨機存取記憶體(DRAM)構件常在晶粒302之中心條(或類似位置)中具有TSV。此佈置亦可供其他構件使用。
如在圖31處所展示,第一晶粒102之基底層104及絕緣層106以及晶粒302之絕緣層106中的蝕刻之開口(形成用於接取接觸襯墊306之空穴602)需要完全對準。另外,如在圖32處所展示,第一晶粒102之基底層104及絕緣層106與晶粒302之絕緣層106中的蝕刻之開口可具有不同大小、形狀、佔據面積等等。舉例而言,如在圖32處所展示,第一晶粒102之基底層104中的開口3202可包含暴露第一晶粒102及/或第二晶粒302之絕緣層106的第一形狀(例如,對於此實例,為矩形,但可包含任何幾何或不規則形狀)。另外,在第一晶粒102及第二晶粒302之絕緣層106中的開口3204及3206可包含暴露第二晶粒302之接觸襯墊306的相同或不同形狀(例如,在此實例中,為橢圓形及矩形,但可包含任何幾何或不規則形狀)。
在各種具體實例中,與本文中描述之製程步驟相比,可修改或消除一些製程步驟。
本文中描述之技術、組件及裝置不限於圖1至圖28之圖示,且在不脫離本揭露內容之範圍之情況下,可應用於與其他電組件包括在一起之其他設計、類型、佈置及構造。在一些情況中,可使用額外或替代組件、技術、順序或製程來實施本文中描述之技術。另外,所述組件及/或技術可按各種組合佈置及/或組合,同時導致類似或大致相同結果。
結論
雖然已按具體針對結構特徵及/或方法動作之語言來描述本揭露內容之實施,但應理解,所述實施未必限於所描述之具體特徵或動作。而是,所述具體特徵及動作經揭露為實施實例裝置及技術之代表性形式。
100:製程
102:第一晶粒
104:基底基板/基底層
106:絕緣層/介電層
108:接合表面/接合層
110:傳導性特徵
112:氧化
200:製程
300:結構
302:第二晶粒
304:接合互連結構
306:接觸襯墊
308:開口
310:保護性金屬層
400:製程
402:抗蝕劑層/抗蝕劑
404:氧化物
500:微電子構件
502:薄層
600:微電子構件
602:空穴
700:製程
702:開口
900:製程
1100:製程
1102:抗蝕劑層/抗蝕劑
1200:構件
1202:島狀物
1204:抗反射塗層
1300:製程
1302:微電子構件
1400:製程
1402:金屬密封環
1404:空穴
1500:構件
1500':第二構件
1600:製程
1602:晶圓
1604:切割道
1606:切割道凹陷
1702:保護性塗層
1800:微電子構件
1802:傳導性互連結構
2000:微電子構件
2100:微電子構件
2202:金屬層
2302:沈積之金屬
2304:端子
2400:構件
2602:組件
2700:構件
2702:周邊接合襯墊
2704:線接合
2706:矽穿孔
2800:構件
2900:微電子構件
2902:主動區
2904:主動區
3202:開口
3204:開口
3206:開口
d1:深度
d2:高度
d3:規格
d4:規格
參看附圖闡述詳細描述。在所述圖中,參考編號之最左邊數字識別參考編號第一次出現之圖。不同圖中之相同參考編號之使用指示類似或相同項目。
為了此論述,在圖中例示之裝置及系統展示為具有大量組件。如本文中描述的裝置及/或系統之各種實施可包括較少組件,且保持處於本揭露內容之範圍內。替代地,裝置及/或系統之其他實施可包括額外組件,或描述之組件之各種組合,且保持處於本揭露內容之範圍內。
圖1及圖2展示根據具體實例的例示用於製備接合表面之實例製程之實例圖形流程圖。
圖3展示根據具體實例的自堆疊且接合之裝置形成之實例構件,其具有混合接合襯墊及周邊襯墊。
圖4及圖5例示根據一具體實例的展示用於形成圖3之構件之裝置中之一者的實例製程之圖形流程圖。
圖5A至圖5C例示根據具體實例的為在圖4及圖5中描述之實例製程之可選步驟。
圖6展示根據具體實例的自堆疊且接合之裝置形成之實例構件,其具有混合接合襯墊及在晶粒周界內部之周邊襯墊。
圖7及圖8例示根據具體實例的展示用於形成圖6之構件之裝置中之一者的實例製程之圖形流程圖。
圖9及圖10例示根據具體實例的展示用於形成圖6之構件之裝置中之另一者的實例製程之圖形流程圖。
圖11及圖12例示根據具體實例的展示用於自堆疊且接合之裝置形成之實例構件的實例製程之圖形流程圖,該構件具有混合接合襯墊及在晶粒周界內部之周邊襯墊。
圖13例示根據具體實例的展示用於自堆疊且接合之裝置形成之實例構件的實例製程之圖形流程圖,該構件具有混合接合襯墊及在晶粒周界內部之周邊襯墊。
圖14及圖15例示根據具體實例的展示用於形成具有密封環或接觸混合接合表面之空穴的實例製程之圖形流程圖。
圖16及圖17例示根據具體實例的展示用於在單一化前為了切割道而蝕刻晶圓的實例製程之圖形流程圖。
圖18至圖23展示根據各種具體實例的自堆疊且接合之裝置形成之構件之實例,其具有混合接合襯墊及周邊襯墊。
圖24至圖26展示根據各種具體實例的自堆疊且接合之裝置形成之構件之實例,其具有內部空穴及密封環。
圖27展示根據具體實例的自堆疊且接合之裝置形成之構件之實例,其具有混合接合襯墊及密封環及在晶粒周界外之至少一個周邊襯墊。
圖28展示根據具體實例的自多個堆疊且接合之裝置形成之構件之實例,其具有混合接合襯墊及密封環。
圖29至圖32展示根據各種具體實例的具有穿過微電子構件之層的蝕刻開口之範例性堆疊且接合之微電子構件。
圖33為根據具體實例的用於製造晶粒以用於接合之範例製程之流程圖。
102:晶粒
104:基底基板
106:絕緣層/介電層
108:接合表面/接合層
110:傳導性特徵
300:微電子構件
302:微電子組件
304:接合互連結構
306:接觸襯墊
308:開口
310:保護性金屬層
Claims (39)
- 一種微電子構件,包含: 第一基板,其具有接合表面,該第一基板之該接合表面具有經平坦化拓撲; 在該第一基板之該接合表面處的第一多個導電性特徵; 第二基板,其具有接合表面,該第二基板之該接合表面具有經平坦化拓撲且接合至該第一基板之該接合表面; 第二多個導電性特徵,其在該第二基板之該接合表面處且接合至該第一多個導電性特徵;及 一或多個導電性接觸襯墊,其安置於該第二基板之絕緣層內且在該第二基板之該接合表面下方,該一或多個導電性接觸襯墊安置於與該第一多個導電性特徵及該第二多個導電性特徵不同之一區中。
- 如請求項1所述之微電子構件,進一步包含在該第二基板之該絕緣層中之一或多個二級開口,其與該一或多個導電性接觸襯墊對準,該一或多個二級開口從該第二基板之該接合表面延伸至該一或多個導電性接觸襯墊,從而提供至該一或多個導電性接觸襯墊之通路。
- 如請求項2所述之微電子構件,進一步包含在該第一基板之絕緣層中之一或多個一級開口,其與該一或多個二級開口及與所述導電性接觸襯墊對準,該一或多個一級開口延伸至該一或多個二級開口,從而提供至該一或多個導電性接觸襯墊之通路。
- 如請求項3所述之微電子構件,其中該一或多個一級開口具有佔據面積,該佔據面積具有與該一或多個二級開口不同的大小及/或形狀。
- 如請求項3所述之微電子構件,進一步包含在該第一基板之基底層中之一或多個三級開口,其與該第一基板之該絕緣層中之該一或多個一級開口及與所述導電性接觸襯墊對準,該一或多個三級開口從該第一基板之外表面延伸至該一或多個一級開口,從而提供從該第一基板之該外表面外至該一或多個導電性接觸襯墊之通路。
- 如請求項5所述之微電子構件,進一步包含安置於該一或多個二級開口、該一或多個一級開口及該一或多個三級開口中之一或多者內且電耦接至該一或多個導電性接觸襯墊的一或多個導電性結構。
- 如請求項6所述之微電子構件,進一步包含端子組件,其耦接至所述導電性結構中之一或多者且被配置以提供從該第一基板之該外表面外至該一或多個導電性接觸襯墊之電通路。
- 如請求項6所述之微電子構件,其中所述導電性結構中之一或多者突出於該第一基板之該外表面外。
- 如請求項5所述之微電子構件,其中該一或多個三級開口具有佔據面積,所述佔據面積具有與該一或多個一級開口及/或該一或多個二級開口不同之大小及/或形狀。
- 如請求項1所述之微電子構件,進一步包含電耦接至所述導電性接觸襯墊中之一或多者的一或多個導電性互連件。
- 如請求項1所述之微電子構件,進一步包含安置於該第一基板之被暴露外表面上的至少一個金屬層,其被配置以用於電磁干擾(EMI)保護及/或用於熱消散。
- 如請求項1所述之微電子構件,進一步包含保護性金屬塗層,其安置於該一或多個導電性接觸襯墊之被暴露表面上。
- 如請求項1所述之微電子構件,其中該第一基板之佔據面積小於該第二基板之佔據面積。
- 如請求項1所述之微電子構件,其中該一或多個導電性接觸襯墊安置於該第一基板之周界內。
- 如請求項1所述之微電子構件,其中該一或多個導電性接觸襯墊安置於該第一基板之周界外。
- 如請求項1所述之微電子構件,其中該一或多個導電性接觸襯墊安置於該微電子構件之兩個或更多個主動區之間及/或該微電子構件之一或多個主動區內。
- 如請求項1所述之微電子構件,其中該第二多個中之所述導電性特徵以第一程度不對準於該第一多個中之所述導電性特徵。
- 如請求項1所述之微電子構件,其中該第一基板包含分開的主動區域之多個島狀物。
- 如請求項1所述之微電子構件,其中該第一基板之該接合表面使用無黏著劑、室溫、共價鍵合技術被接合至該第二基板之該接合表面。
- 一種微電子構件,包含: 第一基板,其具有接合表面,該第一基板之該接合表面具有經平坦化拓撲; 在該第一基板之該接合表面處的第一多個導電性特徵; 第二基板,其具有一接合表面,該第二基板之該接合表面具有經平坦化拓撲且接合至該第一基板之該接合表面; 在該第二基板之該接合表面處的第二多個導電性特徵,其接合至該第一多個導電性特徵,同時以第一程度不對準於該第一多個導電性特徵; 一或多個導電性接觸襯墊,其安置於該第二基板之絕緣層內且在該第二基板之該接合表面下方,該一或多個導電性接觸襯墊安置於該第一多個導電性特徵及該第二多個導電性特徵之周界內部或外部; 在該第二基板之該絕緣層中的一或多個二級開口,其與該一或多個導電性接觸襯墊對準,該一或多個二級開口自該第二基板之該接合表面延伸至該一或多個導電性接觸襯墊;及 在該第一基板之絕緣層中的一或多個一級開口,其以該第一程度不對準於該一或多個二級開口,該一或多個一級開口延伸至該一或多個二級開口且提供至該一或多個導電性接觸襯墊之通路。
- 如請求項20所述之微電子構件,進一步包含在該第一基板之基底層中之一或多個三級開口,其與該第一基板之該絕緣層中之該一或多個一級開口對準,該一或多個三級開口從該第一基板之一外表面延伸至該一或多個一級開口,從而提供自該第一基板之該外表面外至該一或多個導電性接觸襯墊之通路。
- 如請求項21所述之微電子構件,進一步包含安置於該一或多個二級開口、該一或多個一級開口及該一或多個三級開口中之一或多者內且電耦接至該一或多個導電性接觸襯墊之一或多個導電性結構。
- 如請求項20所述之微電子構件,其中該第一基板之佔據面積小於該第二基板之佔據面積。
- 一種微電子構件,包含: 第一基板,其具有混合接合表面,該混合接合表面包含在其中具有一或多個金屬特徵之絕緣體材料,該混合接合表面具有經平坦化拓撲; 第二基板,其具有混合接合表面,該混合接合表面包含具有內嵌於其中之一或多個金屬特徵之絕緣體材料,該第二基板之該混合接合表面具有經平坦化拓撲且接合至該第一基板之該混合接合表面,其中該第二基板之該一或多個金屬特徵接合至該第一基板之該一或多個金屬特徵; 空穴,其安置於該第一基板與該第二基板之間的接合接頭處,在該接合接頭處,該第一基板之該混合接合表面與該第二基板之該混合接合表面進行接觸,該空穴至少由在該第一基板之該混合接合表面中的凹陷所形成;及 連續密封件,其由接合至該第二基板之該一或多個金屬特徵的該第一基板之該一或多個金屬特徵所形成,安置於圍繞在該接合接頭處的該空穴之周邊。
- 如請求項24所述之微電子構件,進一步包含安置於該空穴內的微電子組件、電路或感測器中之一或多者。
- 如請求項24所述之微電子構件,進一步包含第三基板,其具有混合接合表面,該混合接合表面包含具有內嵌於其中之一或多個金屬特徵之絕緣體材料,該第三基板之該混合接合表面具有經平坦化拓撲且接合至該第一基板,其中該第三基板之該一或多個金屬特徵接合至該第一基板之所述金屬特徵中之一或多者。
- 如請求項26所述之微電子構件,其中該空穴為第一空穴,且其中該第三基板包括安置於該第一基板與該第三基板之間的接合接頭處之第二空穴,在該第二空穴處,該第三基板之該混合接合表面與該第一基板進行接觸,該第二空穴至少由在該第三基板之該混合接合表面中的凹陷形成。
- 如請求項24所述之微電子構件,其中該空穴由在該第一基板之該混合接合表面中的該凹陷及在該第二基板之該混合接合表面中的另一凹陷形成。
- 如請求項24所述之微電子構件,其中該第一基板之該一或多個金屬特徵以第一程度與該第二基板之該一或多個金屬特徵相互偏移。
- 如請求項24所述之微電子構件,其中該第二基板之佔據面積比該第一基板之佔據面積大,且其中該第二基板包括安置於在該第一基板之周界外的該第二基板之該混合接合表面處之一或多個導電性接觸襯墊,該一或多個導電性接觸襯墊被配置以將該第二基板電互連至不同於該第一基板之元件。
- 如請求項24所述之微電子構件,其中該第一基板之該一或多個金屬特徵自該第一基板之該接合表面延伸至該第一基板之該絕緣體材料外,及/或該第二基板之該一或多個金屬特徵自該第二基板之該接合表面延伸至該第二基板之該絕緣體材料外且至該第二基板之基底層內。
- 一種方法,包含: 提供具有混合接合表面之基板,該混合接合表面包含具有一或多個金屬特徵之絕緣體材料,該混合接合表面具有經平坦化拓撲,該基板包括安置於該基板之該絕緣體材料內且在該混合接合表面下方的一或多個導電性接觸襯墊,該一或多個導電性接觸襯墊安置於該一或多個金屬特徵之周界外; 研磨該混合接合表面;及 穿過該混合接合表面蝕刻出該絕緣體材料中之一或多個開口以暴露該一或多個導電性接觸襯墊。
- 如請求項32所述之方法,進一步包含在對應於該基板之切割道的位置處在該基板中蝕刻凹陷,以準備將該基板單一化成多個晶粒。
- 如請求項32所述之方法,進一步包含在該蝕刻後修整研磨該一或多個金屬特徵之暴露表面。
- 如請求項32所述之方法,進一步包含: 在該混合接合表面上形成圖案化的抗蝕劑層; 蝕刻該絕緣體材料之未由該抗蝕劑層覆蓋的區域;及 自該混合接合表面移除該抗蝕劑層。
- 如請求項35所述之方法,進一步包含在蝕刻該絕緣體材料之未由該抗蝕劑層覆蓋的所述區域後,自該一或多個金屬特徵之暴露表面移除氧化物。
- 如請求項36所述之方法,其中使用包含稀釋硫酸或稀釋磺酸之蝕刻劑來移除該氧化物。
- 如請求項37所述之方法,其中該稀釋硫酸或該稀釋磺酸具有包含1比20的硫酸或磺酸與水之比率。
- 如請求項32所述之方法,其中在不用黏著劑將該基板直接接合至另一微電子元件前,執行該蝕刻。
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US201862703727P | 2018-07-26 | 2018-07-26 | |
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US16/511,394 US20200035641A1 (en) | 2018-07-26 | 2019-07-15 | Post cmp processing for hybrid bonding |
US16/511,394 | 2019-07-15 |
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