CN112470272A - 针对混合接合的后cmp处理 - Google Patents
针对混合接合的后cmp处理 Download PDFInfo
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- CN112470272A CN112470272A CN201980049187.5A CN201980049187A CN112470272A CN 112470272 A CN112470272 A CN 112470272A CN 201980049187 A CN201980049187 A CN 201980049187A CN 112470272 A CN112470272 A CN 112470272A
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- Toxicology (AREA)
Abstract
器件和技术包括用于形成穿过经堆叠和接合的结构的开口的工艺步骤。在接合层的平面化(通过化学机械抛光(CMP)等)之后并且在接合之前,开口通过预蚀刻穿过经制备的裸片的一个或多个层而形成。例如,在将裸片接合以形成组件之前,开口被蚀刻穿过待被接合的裸片的一个或多个层。
Description
相关申请的交叉引用
本申请根据35 U.S.C.§119(e)(1),要求于2019年7月15日提交的美国非临时申请号16/511,394、以及于2018年7月26日提交的美国临时申请号62/703,727的权益,其内容通过引用以其整体并入本文。
技术领域
以下描述涉及集成电路(“IC”)。更具体地,以下描述涉及制造IC裸片(die)和晶片。
背景技术
微电子元件通常包括通常被称为半导体晶片的半导体材料(诸如,硅或砷化镓)的薄平板。晶片可以被形成为包括在晶片表面上和/或部分地嵌入晶片内的多个集成芯片或裸片。与晶片分开的裸片通常被提供为单独的、经预封装的单元。在一些封装设计中,裸片被安装到衬底或芯片载体,衬底或芯片载体进而被安装在电路板(诸如印刷电路板(PCB))上。例如,许多裸片以适合表面安装的封装来提供。
经封装的半导体裸片也可以按照“堆叠”布置来提供,其中一个封装被提供在例如电路板或其他载体上,而另一封装被安装在第一封装的顶部上。这些布置可以允许数个不同的裸片或器件被安装在电路板上的单个占用区(footprint)内,并且可以通过在封装之间提供短的互连件来进一步促进高速操作。通常,该互连距离可以仅略大于裸片本身的厚度。为了待在裸片封装的堆叠内实现的互连,针对机械和电连接的互连结构可以被提供在每个裸片封装(最顶部的封装除外)的两侧(例如,面)上。
附加地,作为各种微电子封装方案的一部分,裸片或晶片可以以三维布置来堆叠。这可以包括将一个或多个裸片、器件和/或晶片的层堆叠在较大的基部裸片、器件、晶片、衬底等上,从而以垂直或水平布置以及两者的各种组合来堆叠多个裸片或晶片。
裸片或晶片可以使用各种接合技术,以堆叠布置来接合,接合技术包括直接电介质接合、非粘合技术(诸如,)或混合接合技术(诸如,),两者均可从Invensas Bonding Technologies,Inc(前身为Ziptronix,Inc)、Xperi公司(例如参见美国专利号6,864,585和7,485,968,其内容以其整体被并入本文)获得。接合裸片或晶片的相应配合表面通常包括嵌入式传导性互连结构等。在一些示例中,接合表面被布置和对准,使得来自相应表面的传导性互连结构在接合期间被联接。经联接的互连结构在堆叠的裸片或晶片之间形成(用于信号、功率等的)连续的传导性互连。
实现堆叠的裸片和晶片布置可能存在多种挑战。当使用直接接合或混合接合技术将堆叠的裸片接合时,通常期望待接合的裸片的表面极其平坦、光滑且清洁。例如,通常,表面应在表面形貌上具有非常低的变化(即,纳米级变化),使得表面可以被紧密地配合来形成持久的接合。
接合表面处的传导性互连结构可以略微凹入,恰好在接合表面的绝缘材料的下方。在接合表面下方的凹入量可以由器件或应用的尺寸公差、规范或物理限制来确定。混合表面可以被制备来使用化学机械抛光(CMP)工艺等而与另一裸片、晶片或其他衬底接合。
附加地,在一些应用中,期望在接合表面上或接合表面旁边,或接合表面处的腔内形成引线接合焊盘、测试焊盘以及其他结构,其在接合之后,将通常从堆叠和接合器件的外侧而被接入。开口或腔可以被用于创建针对传感器应用的接入口、(例如,用于引线接合、测试、电连接等的)物理和电接入、低阻抗、低损耗的连接、空气桥等。特别是当所期望的腔将具有小节距(pitch)和/或显著的深度时,形成通过堆叠和接合裸片、晶片和衬底,用以容纳这些结构、连接、接入以及用于其他目的的腔可能是有问题的。
附图说明
参考附图来阐述具体实施方式。在附图中,附图标记的(多个)最左边数字标识该附图标记首次出现的附图。在不同附图中使用相同的附图标记指示相似或相同的项。
为了进行讨论,图中所示的设备和***被示出为具有多个部件。如本文所描述的,设备和/或***的各种实现方式可以包括更少的部件,并且仍在本公开的范围内。备选地,设备和/或***的其他实现方式可以包括附加部件或所描述的部件的各种组合,并且仍在本公开的范围内。
图1和图2示出了根据一个实施例的用于制备接合表面的示例过程的示例图形流程图。
图3示出了根据一个实施例的从堆叠和接合器件形成的示例组件,该堆叠和接合器件具有混合接合焊盘、以及***焊盘。
图4和图5图示了根据一个实施例的用于形成图3的组件的器件中的一个器件的示例过程的图形流程图。
图5A至图5C图示根据一个实施例的在图4和图5处所描述的示例过程的可选步骤。
图6示出了根据一个实施例的从堆叠和接合器件形成的示例组件,该堆叠和接合器件在裸片周界(perimeter)内侧具有混合接合焊盘和***焊盘。
图7和图8图示了根据一个实施例的图形流程图,该图形流程图示出了用于形成图6的组件的器件中的一个器件的示例过程。
图9和图10图示了根据一个实施例的图形流程图,该图形流程图示出了用于形成图6的组件的器件中的另一器件的示例过程。
图11和图12图示了根据一个实施例的图形流程图,该图形流程图示出了用于形成从堆叠和接合器件形成的示例组件示例过程,该堆叠和接合器件具有在裸片周界内侧的混合接合焊盘和***焊盘。
图13图示了根据一个实施例的图形流程图,该图形流程图示出了用于形成从堆叠和接合器件形成的示例组件的示例过程,该堆叠和接合器件具有在裸片周界内侧的混合接合焊盘和***焊盘。
图14和图15图示了根据一个实施例的图形流程图,该图形流程图示出了用于利用密封环或接触式混合接合表面来形成腔的示例过程。
图16和图17图示了根据一个实施例的图形流程图,该图形流程图示出了在分割(singulation)之前对晶片进行道蚀刻(street ectching)的示例过程。
图18至图23示出了根据各种实施例的从堆叠和接合器件形成的组件的示例,该堆叠和接合器件具有混合接合焊盘和***焊盘。
图24至图26示出了根据各种实施例的从堆叠和接合器件形成的组件的示例,该堆叠和接合器件具有内部腔和密封环。
图27示出了根据一个实施例的从堆叠和接合器件形成的组件的示例,该堆叠和接合器件具有混合接合焊盘和密封环、以及在裸片周界外侧的至少一个***焊盘。
图28示出了根据一个实施例的从多个堆叠和接合器件形成的组件的示例,该多个堆叠和接合器件具有混合接合焊盘和密封环。
图29至图32示出了根据各种实施例的示例堆叠和接合微电子组件,其具有穿过微电子组件层的蚀刻开口。
图33是图示了根据一个实施例的用于制备裸片以用于接合的示例过程的流程图。
发明内容
公开了表示性的技术和器件,包括用于形成穿过堆叠和接合结构的孔、腔、开口、凹部等(以下被称为“开口”)的工艺步骤。如上所讨论的,特别关注的是紧密接合结构,该紧密接合结构在没有粘合剂的情况下,使用直接接合和混合接合技术形成。在各种实施例中,在接合层的平坦化(通过化学机械抛光(CMP)等)之后并且在接合之前,开口通过预蚀刻穿过经制备的晶片或裸片的一个或多个层而形成。例如,在接合裸片以形成组件之前,开口被蚀刻穿过待接合的裸片的一个或多个层。
在各种实现方式中,微电子组件包括:具有接合表面的第一衬底,该接合表面具有无机电介质材料或绝缘体的平面化形貌;以及第一多个电传导性特征,被嵌入在电介质层中,其中一个表面在第一衬底的接合表面处暴露;以及具有接合表面的第二衬底,该接合表面具有无机电介质材料或绝缘体的平面化形貌、且被接合到第一衬底的接合表面。第二衬底包括第二多个电传导性特征,被嵌入在电介质层中,其中一个表面在第二衬底的接合表面处暴露,第二多个电传导性特征被接合到第一多个电传导性特征。第一多个电传导性特征和第二多个电传导性特征例如使用混合接合技术等被直接接合,而不使用焊料或其他添加的接合材料。术语“传导性特征”在本文将用来具体指代这些直接接合的传导性特征。
与直接接合的电传导性特征分开的一个或多个电传导性接触焊盘被设置在第二衬底的绝缘层内、并且在第二衬底的接合表面下方。一个或多个电传导性接触焊盘可以被设置在第一多个电传导性特征和第二多个电传导性特征的周界的外侧或内侧,或者在一个或多个指定区域中。电传导性接触焊盘可以包括不同于电传导性特征的任何传导性结构,其可以用作引线接合、端子、测试焊盘、球栅等的传导性互连件。
在一个裸片或晶片的“传导性特征”具有在第二直接接合的裸片或晶片上相匹配或配合的传导性特征的情况下,出于裸片对裸片、晶片对晶片或者裸片对晶片的直接接合的目的,“接触焊盘”是不匹配的。例如,一个裸片或晶片的接触焊盘通常不具有第二接合裸片或晶片上的待直接接合到的相配合的接触焊盘。此外,接触焊盘通常在裸片或晶片中、与电传导性特征不同的(例如,“较低”)层上,并且可以被设置或掩埋在裸片或晶片的接合表面的下方。
在一个实现方式中,微电子组件还包括一个或多个次级开口,该一个或多个次级开口在第二衬底的绝缘层中、与一个或多个电传导性接触焊盘对准。一个或多个次级开口从第二衬底的接合表面延伸到一个或多个电传导性接触焊盘,从而提供了到一个或多个电传导性接触焊盘的接入。
在另一实现方式中,微电子组件还包括一个或多个初级开口,该一个或多个初级开口在第一衬底的绝缘层中,一个或多个初级开口与一个或多个次级开口、以及与电传导性接触焊盘对准。一个或多个初级开口延伸到一个或多个次级开口,从而提供到一个或多个电传导性接触焊盘的接入。
在另一实现方式中,微电子组件还包括一个或多个三级开口,该一个或多个三级开口在第一衬底的基层中,一个或多个三级开口与第一衬底的绝缘层中的一个或多个初级开口、以及与电传导性接触焊盘对准。一个或多个三级开口从第一衬底的外侧表面延伸到一个或多个初级开口,从而提供从第一衬底的外侧表面之外到一个或多个电传导性接触焊盘的接入。
在一个实施例中,微电子组件包括一个或多个电传导性结构,一个或多个电传导性结构被设置在一个或多个次级开口、一个或多个初级开口以及一个或多个三级开口中的一项或多项内,并且被电耦合到一个或多个电传导性接触焊盘。
在另一实现方式中,微电子组件包括:具有接合表面的第一衬底,该接合表面具有平面化形貌,第一衬底在第一衬底的接合表面处具有第一多个电传导性特征;以及具有接合表面的第二衬底,该接合表面具有平面化形貌,被接合到第一衬底的接合表面。第二多个电传导性特征被设置在第二衬底的接合表面处、并且被接合到第一多个电传导性特征,同时与第一多个电传导性特征以第一程度而未对准。一个或多个电传导性接触焊盘被设置在第二衬底的绝缘层内、并且在第二衬底的接合表面下方。一个或多个电传导性接触焊盘被设置在第一多个电传导性特征和第二多个电传导性特征的周界外侧、或在一个或多个指定区域中。第二衬底的绝缘层中的一个或多个次级开口与一个或多个电传导性接触焊盘对准,并且一个或多个次级开口从第二衬底的接合表面延伸到一个或多个电传导性接触焊盘。第一衬底的绝缘层中的一个或多个初级开口与一个或多个次级开口以第一程度而未对准,并且一个或多个初级开口延伸到一个或多个次级开口,且提供到一个或多个电传导性接触焊盘的接入。
在附加的实现方式中,微电子组件包括:第一衬底,具有混合接合表面,混合接合表面包括具有在其中的一个或多个金属特征的绝缘体材料、以及平面化形貌;以及第二衬底,具有混合接合表面,混合接合表面包括具有一个或多个金属特征被嵌入在其中的绝缘体材料、具有平面化形貌并且被接合到第一衬底的混合接合表面。第二衬底的一个或多个金属特征被接合到第一衬底的一个或多个金属特征。腔被设置在第一衬底与第二衬底之间的接合联接处,该接合联接处,第一衬底的混合接合表面与第二衬底的混合接合表面接触。腔至少由第一衬底的混合接合层中的凹部形成。连续密封件由第一衬底的一个或多个金属特征、以及第二衬底的一个或多个金属特征形成,并且被设置在接合联接处的腔的周界周围。
参考电气和电子部件以及各种载体讨论了各种实现方式和装置。尽管提到了特定的部件(即,裸片、晶片、集成电路(IC)芯片裸片、衬底等),但这并不意味着是限制性的,并且是为了便于讨论和例示方便。参考晶片、裸片、衬底等讨论的技术和器件可应用于任何类型或数量的电子部件、电路(例如,集成电路(IC)、混合电路、ASICS、存储器器件、处理器等)、部件组、封装的部件、结构(例如,晶片、面板、板、PCB等)等,其可以彼此耦合并且与外部电路、***、载体等的接口耦合。这些不同的部件、电路、组、封装、结构等中的每一项可以被统称为“微电子部件”。为简单起见,除非另有指定,否则与另一部件接合的部件在本文中将被称为“裸片”。
该发明内容并不旨在给出完整的描述。以下使用多个示例来更详细地解释实现方式。尽管此处和下文讨论了各种实现方式和示例,但是通过将单独实现方式和示例的特征和元素组合,进一步的实现方式和示例是可能的。
具体实施方式
概述
图案化的金属和无机电介质材料(诸如,氧化硅)层通常作为混合接合或表面层而被提供在裸片、晶片或其他衬底(以下称为“裸片”)上。电介质层通常是高度平面的(通常到纳米级粗糙度),而金属层(例如,嵌入的传导性特征)在氧化物表面处或恰好凹入在氧化物表面的下方。在氧化物下方的凹入量通常由尺寸公差、规范或物理限制来确定。混合表面通常使用化学机械抛光(CMP)步骤来制备,以用于与另一裸片、晶片或其他衬底接合。
本文所公开的器件和技术允许在CMP步骤之后进一步蚀刻氧化物(或其他绝缘层),以形成在接合层中的、或穿过接合层的开口、腔或凹部。开口或凹部允许特征或结构形成并被接入,诸如引线接合焊盘、测试焊盘、裸片腔等。形成这样的腔可能意味着需要在CMP步骤之后但在接合之前,将附加的开口蚀刻到混合接合表面层中。这样的腔可以被用于创建针对传感器应用(例如,DNA分析)的接入口、(例如,用于测试、引线接合、电连接等的)物理和电接入、低阻抗、低损耗的连接、空气桥等。
本文所述的技术对于在接合之前,在单独裸片或晶片中形成较浅的腔、凹部或开口是有用的,由此避免在接合之后,需要在两个裸片或晶片中蚀刻较深的单个腔。与在接合之后将可能利用氧化物蚀刻的工艺相比,该工艺还可以使得接合焊盘表面更清洁并且节距性能更好。附加地,该工艺还允许在顶部和底部晶片或裸片中形成具有不同尺寸的腔。例如,沟槽开口可以在底部裸片中形成,并且点开口可以在顶部裸片中形成,反之亦然。备选地,在底部裸片中所形成的开口可以比在顶部裸片中所形成的开口更大,反之亦然(参见图29至图32)。
如将理解的,该腔蚀刻技术也可以改进针对微机电***(MEMS)或其他传感器应用的金属密封环或电接触。本文所述的技术还通过在裸片分割之前的道蚀刻的工艺来改进接合。这可以通过减少碎屑来改进切割,并且可以改进本领域的晶体管的可靠性。
图1至图33图示了用于形成和制备各种微电子部件(例如,诸如裸片102)的表示性器件和过程,以用于接合,诸如用于在无粘合剂的情况下的直接接合。过程包括:在微电子部件上提供接合表面(例如诸如,接合表面108),或者在某些示例中提供两个接合表面(未示出);提供被嵌入到接合表面中的传导性互连特征或结构;修复或减轻由于处理或缺陷而导致的接合表面中的腐蚀、凹入等;在接合表面中预蚀刻一个或多个开口;通过在接合表面处直接接合微电子部件来形成微电子组件等。
过程被描述的顺序不旨在被解释为限制性的,并且过程中所描述的任意数目的过程框可以以任何顺序组合来实现过程或备选过程。附加地,在不脱离本文描述的主题的精神和范围的情况下,可以从任何过程中删除单独框。此外,可以在不脱离本文描述的主题的范围的情况下,以任何合适的硬件、软件、固件或其组合来实现过程。在备选实现方式中,其他技术可以以各种组合而被包括在过程中,并且仍然在本公开的范围内。
参考图1和图2,以及相应地过程100和200,表示性的“裸片”102可以使用各种技术而被形成,以包括基衬底104和绝缘或电介质层106。基衬底104可以包括硅、锗、玻璃、石英、电介质表面、直接或间接间隙半导体材料或层或另一合适的材料、以及绝缘电介质中的多个金属布线层,其通常被称为“后道工序”(BEOL)层。绝缘层106被沉积或形成在衬底104之上,并且可以包括无机电介质材料层,诸如,氧化物、氮化物、氧氮化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃陶瓷等。例如,绝缘层106可以是BEOL的最后一层,或者是特别针对混合接合而沉积的附加层。
裸片102的接合表面108可以包括传导性特征110,例如诸如互连结构,传导性特征110被嵌入绝缘层106中并且被布置为使得来自相对裸片102的相应接合表面108的传导性特征110可以根据需要,在接合期间进行配合或联接。联接的传导性特征110可以在堆叠的裸片102之间形成连续的传导性互连(用于信号、功率等)。
镶嵌过程(或类似过程)可以被用于形成绝缘层106中的嵌入式传导性特征110。传导性特征110可以包括金属(例如,铜等)或其他传导性材料或材料的组合,并且包括结构、迹线、焊盘、图案等。传导性特征110可以被包括在绝缘层106中,以提供电和/或热路径,或者可以替代地被配置为通过使用附加的焊盘或所谓的虚拟焊盘、迹线、图案等,来平衡接合表面108的金属化。在传导性特征110被形成之后,裸片102中暴露的表面,包括绝缘层106和电传导性特征110,可以被平面化(例如,经由CMP),以形成平坦的接合表面108。
如图1和图2所示,在过程100和200的框A处,裸片102中一个或多个接合表面108,包括嵌入式互连结构110,可以被平面化(使用化学机械抛光(CMP)等)来制备用于接合的(多个)表面108。形成接合表面108包括对表面108进行加工(finishing)来满足电介质粗糙度规范和金属层(例如,铜等)凹入规范,从而制备用于直接接合的表面108。换言之,接合表面108被形成为尽可能平坦和光滑,具有非常小的表面形貌变化。诸如化学机械抛光(CMP)的各种常规过程可以被用来实现低表面粗糙度。该过程提供平坦的、光滑的表面108,导致裸片102之间的可靠接合。
在某些情况中,如在图1的过程100的框A中所示,电传导性特征110的暴露的表面可以相对于接合表面108有意地凹入例如深度“d1”,以特别是在加热退火(如果被执行)期间,允许材料膨胀。在其他情况下,如图2的过程200的框A所示,传导性特征110的暴露的表面可以被形成为超过凹部规范,并且可以在接合表面108上方突出到高度“d2”,以允许在稍后处理期间对传导性特征110进行氧化。例如,这可以通过对电介质层106的选择性蚀刻来实现。
在抛光或其他过程步骤(诸如在抛光步骤之后,形成接合层108中的开口)期间,接合层108处的传导性特征110可能改变(例如,变得被氧化)并变得在期望规范之外。这在图1和图2的过程100和200的框B中图示,其中氧化在112处被示出。
传导性特征110可以在如图1和图2的过程100和200的框C处被调整,以改进随后的接合和电连接。该调整可以通过对传导性特征110进行选择性湿法蚀刻(例如,利用化学蚀刻,该化学蚀刻选择性地溶解在传导性特征110上所形成的金属氧化物(例如,氧化铜)的)或通过修整(touch-up)CMP过程来实现等。在调整之后,传导性特征110相对于接合表面108的凹入在规范的公差内(例如,“d3”和“d4”)。
示例实施例
参考图3,示出了微电子组件300,微电子组件300包括至少两个直接接合的(例如,在没有粘合剂的情况下)裸片102和302。备选地,微电子部件302可以包括晶片或其他衬底等。然而,微电子部件302包括被设置在裸片102周界外侧的一个或多个接触焊盘306。
裸片102和302二者的嵌入式电传导性特征110(例如,混合接合焊盘等)延伸到裸片102和302的接合表面108并且被接合在一起,从而形成接合的互连结构304。在一个实施例中,第一裸片102可以如上所述在过程100或200处地形成。
由于裸片302的绝缘层106中的开口308,裸片302的接触焊盘306(即,暴露的非混合电传导性焊盘)通过裸片302的接合表面108而被暴露。如上所讨论的,焊盘306可以被用于关于裸片302的测试、引线接合、其他电连接等。在一些实施例中,例如,包括镍、金或其他金属的传导性涂层310可以被设置在接触焊盘306之上,以保护焊盘306免受氧化、腐蚀等。
在一个实现方式中,第二裸片302可以如过程400中所描述地形成,包括在将第二裸片302接合到第一裸片102之前,形成开口308。备选地,在具有结构300的一些实施例中,在第二裸片302接合到第一裸片102之后,开口308可以形成在第二裸片302中。
参考图4。过程400(对于文本流程图还参见图33,以补充图4和图5的图形流程图)在框A处,裸片302被形成并制备用于直接接合,包括:在基衬底104上形成绝缘层106,在绝缘层106中形成一个或多个传导性特征110,以及如上所述的,形成高度平面的接合层108。在一个实现方式中,过程400包括在绝缘层106内形成掩埋式接触焊盘306。
在框B处,过程400包括:在接合表面108之上形成图案化的抗蚀剂层402,其中抗蚀剂层402中图案化的间隙在掩埋式接触焊盘306之上对准。可选地,若需要,图案化的抗蚀剂层402可以包括在切割道之上的间隙。在框C处,过程400包括:通过抗蚀剂层402中的间隙来蚀刻绝缘层106,从而形成开口308以暴露掩埋式接触焊盘306。
参考图5,在框D处,如果期望保护焊盘306,则过程400包括可选地利用保护性金属层310(例如,镍、金、银、焊料等)来覆盖未经覆盖的接触焊盘306。保护性层310可以例如使用非电解镀制,或若需要使用另一技术(诸如浸入镀制等)来施加。
在框E处,过程400包括:从接合表面108移除抗蚀剂402。例如,抗蚀剂402可以通过如下而被移除:使用湿法剥离,随后进行氧等离子体灰化。在一些情况下,抗蚀剂402的移除步骤可以使得电传导性特征110的表面氧化(例如,形成氧化铜404)。如图5所示,取决于氧化物404的量,电传导性特征110的表面可以突出到接合表面108的上方。
在框F处,过程400包括从传导性特征110移除氧化物404。例如,氧化物404可以是1至100nm厚。备选地,在某些情况下,氧化可能更厚。在任何情况下,控制材料的移除速率,包括移除氧化物404的速率、以及移除传导性结构110的金属的一些金属(例如,铜等)以符合凹部规范的速率可以是重要的。例如,移除正确量的材料可以避免必须重新制造裸片302,包括重新形成绝缘层106和/或传导性结构110。不幸的是,使用常用技术中的许多技术可能容易地过度蚀刻材料。
在各种实施例中,受控的、选择性的蚀刻技术被用于移除氧化物404,这可以包括利用稀释配方(诸如,1:20比例的硫酸或磺酸与水)来蚀刻氧化物404。备选地,利用浆料的轻型CMP可以被用于选择性地移除氧化物404,该浆料被配制用于抛光阻挡层(诸如在镶嵌过程期间,在铜沉积之前被沉积到绝缘层106的腔中的阻挡层)。然而,纳米级材料的移除使用化学蚀刻可以更容易地控制。针对传导性特征110的指定凹部可以作为利用受控的材料移除的氧化物404移除步骤的一部分来实现。
参考图5A至图5C,作为对过程400的备选步骤,或者附加于框D至F中的过程步骤,一个或多个可选层可以沉积在暴露的接触焊盘306(和保护性金属层310)之上,这可以包括在裸片302的接合表面108之上沉积(多个)层。例如,在某些情况下,由于对于耦合到电路、或暴露的接合焊盘的传导性特征110的双金属效应和光伏效应,可能经历在一些电传导性特征110上对蚀刻的电化学增强。这些效应可能导致对接触焊盘306的腐蚀。
在这些情况下,(参考图5A,在框G处),大致10至200nm的氧化物和/或阻挡金属的层502可以沉积在接合表面108和接触焊盘306(包括保护性金属层310)之上。如在框H处所示,CMP(或类似方法)可以被用于将电传导性特征110重新暴露在接合表面108上。层502保留在接触焊盘306上。在框I处,第一裸片或晶片102被直接接合到第二裸片302而不需要粘合剂。
参考图5B,在框J处,在第二裸片302被接合到第一裸片或晶片102之后,第一裸片或晶片102的顶部基层104可以被薄化。在框K处,图案化的抗蚀剂层402被施加到裸片102的顶表面,其中间隙在抗蚀剂中期望移除基层104的位置处(例如,如所期望的,在开口602、以及其他位置之上)。在框L处,开口在晶片或裸片102的基层104中蚀刻,以接入接触焊盘306。裸片102的基层104中的开口可以被形成为与裸片102和裸片302中的一者或两者的绝缘层106中的开口相同的尺寸,或者裸片102的基层104中的开口可以大于或小于裸片102和/或裸片302中的配合开口。
参考图5C,在框M处,利用被创建在晶片或裸片102的基层104中的开口,接触焊盘306之上的薄层502可以利用短暂的毯式(blanket)干法蚀刻或类似技术而被移除。然后,如所示出,光抗蚀剂402可以在框N处被移除。例如,抗蚀剂402可以使用湿法剥离(wet strip)而被移除。在框N处,所得的微电子组件500被示出。
参考图6,微电子组件600被示出,微电子组件600包括至少两个直接接合(例如,没有粘合剂)的裸片102和302。备选地,微电子组件102和302可以包括两个裸片、两个晶片、一个裸片和一个晶片或其他衬底等。然而,微电子部件302包括被设置在裸片102周界的内侧的一个或多个接触焊盘306。
两个裸片102和302的嵌入式传导性特征110(例如,混合接合焊盘等)延伸到裸片102和302的接合表面108、并且被接合在一起,从而形成接合的互连结构304。在一个实施例中,第一裸片102可以如过程700所描述地来形成。
参考图7以及过程700,在框A处,裸片102被形成并且被制备用于直接接合,包括:在基衬底104上形成绝缘层106、在绝缘层106中形成一个或多个电传导性特征110、以及形成如上所述的高度平面的接合层108(例如,使用CMP)。在各种实现方式中,框A可以在晶片上执行,并且过程700的步骤可以在分割(若需要)之前执行。
在框B处,过程700包括:在接合表面108之上形成图案化的抗蚀剂层402,其中一旦裸片102和302被对准并接合,抗蚀剂层402中图案化的间隙就在绝缘层106中与掩埋式接触焊盘306在裸片302中的位置相对应的一部分之上对准。可选地,裸片102中的开口可以被形成为与裸片302中的开口相同,或者其可以大于或小于裸片302中的配合开口。可选地,若需要,图案化的抗蚀剂层402可以包括在切割道之上的间隙。在框C处,过程700包括:通过抗蚀剂层402中的间隙来蚀刻绝缘层106(以及若需要,基衬底104的一些),从而形成绝缘层106中的开口702。
参考图8,在框D处,过程700包括从接合表面108移除抗蚀剂402。例如,抗蚀剂402可以通过如下而被移除:使用湿法剥离、随后进行氧等离子体灰化。在一些情况下,抗蚀剂402移除步骤可以使得传导性特征110的表面氧化(例如,从而形成氧化铜404)。如图8所示,取决于氧化物404的量,传导性特征110的表面可以突出到接合表面108的上方。
在框E处,过程700包括:使用利用浆料的CMP过程、和/或使用如上所述的湿法蚀刻过程,从传导性特征110移除氧化物404,同时控制传导性特征110上的材料移除速率,浆料被配制用于抛光阻挡层等。例如,选择性蚀刻技术被用来移除氧化物404,这可以包括利用稀释配方(诸如,1:20比例的硫酸或磺酸与水)来蚀刻氧化物404。传导性特征110的指定凹部可以被实现为利用受控的材料移除来进行氧化物404移除步骤的一部分。
在一些情况下,例如由于双金属效应和光伏效应,可能经历在一些传导性特征110上对蚀刻的电化学增强。在这些情况下,10nm至200nm的氧化物和/或阻挡金属可以被沉积在接合表面108和接触焊盘306之上。CMP(或类似)可以被用于将传导性特征110重新暴露在接合表面108上。
在一个实现方式中,第二裸片302可以如过程900中所描述地形成,包括:在将第二裸片302接合到第一裸片102之前,在裸片302的绝缘层106中形成开口308。
参考图9的过程900,在框A处,裸片302被形成并且被制备用于直接接合,包括:在基衬底104上形成绝缘层106、在绝缘层106中形成一个或多个传导性特征110,以及形成如上所述的高度平面的接合层108。在一个实现方式中,过程900包括:形成在绝缘层106内的掩埋式接触焊盘306。在各种实现方式中,框A可以在晶片上执行,并且过程900的步骤可以在分割(若需要)之前执行。
在框B处,过程900包括:在接合表面108之上形成图案化的抗蚀剂层402,其中抗蚀剂层402中图案化的间隙在掩埋式接触焊盘306之上对准。可选地,若需要,图案化的抗蚀剂层402可以包括在切割道之上的间隙。在框C处,过程900包括:通过抗蚀剂层402中的间隙来蚀刻绝缘层106,从而形成开口308以暴露掩埋式接触焊盘306。
参考图10,在框D处,若需要保护焊盘306,则过程900包括可选地利用保护性金属层310(例如,镍、金、银、焊料等)来镀制未经覆盖的接触焊盘306。保护性层310可以例如使用非电解镀制、或者若需要另一技术(诸如,浸入镀制等)来施加。
在框E处,过程900包括:从接合表面108移除抗蚀剂402。例如,抗蚀剂402可以通入如下而被移除:使用湿法剥离、随后进行氧等离子体灰化。在一些情况下,抗蚀剂402移除步骤可以使得传导性特征110的表面氧化(例如,从而形成氧化铜404)。如图10所示,取决于氧化物404的量,传导性特征110的表面可以突出到接合表面108的上方。
在框F处,过程900包括如上所述的使用CMP过程和/或使用湿法蚀刻过程,从传导性特征110移除氧化物404,同时控制传导性特征110上材料的移除速率。例如,选择性蚀刻技术被用于移除氧化物404,这可以包括利用稀释配方(诸如,1:20比例的硫酸(或磺酸)与水)或利用浆料的轻型CMP等来蚀刻氧化物404,浆料被配制用于抛光阻挡层。针对传导性特征110的指定凹部可以被实现为利用受控材料移除来进行氧化物404移除步骤的一部分。
在一些情况下,例如由于双金属效应和光伏效应,可能经历在一些传导性特征110上对蚀刻的电化学增强。在这些情况下,大致10nm至200nm的氧化物和/或阻挡金属可以被沉积在接合表面108之上、以及在接触焊盘306(未示出)之上。CMP(或类似)可以被用于将传导性特征110重新暴露在接合表面108上。在第二裸片302被接合到第一裸片102之后,接触焊盘306可以通过被创建在第一裸片102中的开口来接入,并且焊盘306可以利用干法蚀刻而解覆盖(uncover)。
返回参考图6,将所制备的裸片102和302在每一者的接合表面108处直接接合产生了微电子组件600。如所示出的,裸片302中的开口308与裸片102中的开口702组合,以形成在接触焊盘306之上的腔602。在一些实施例中,第一裸片102的基衬底104(例如,其可以包括硅)可以在腔602和接触焊盘306之上蚀刻,以提供从微电子组件600外侧到接触焊盘306的接入(若需要)。在这样的实施例中,当第一裸片102被接合到第二裸片302时,仅蚀刻穿过基层104优于蚀刻穿过裸片102的基层104和绝缘层106。在绝缘层106已被移除的情况下,蚀刻穿过单个层104更容易,这改进了制造过程。此外,与蚀刻穿过裸片102的基层104和绝缘层106两者时相比,这可以导致在焊盘306之上的更精细的节距开口。附加地,若需要,这允许在接合在一起的两个裸片102和302中的每一项内的不同大小和形状的开口。
参考图11,用于形成微电子组件1200的过程1100被示出,微电子组件1200包括至少两个直接接合(例如,没有粘合剂)的裸片102和302。备选地,微电子部件302可以包括晶片或其他衬底等。然而,微电子部件302包括一个或多个接触焊盘306,该一个或多个接触焊盘306被设置在裸片102周界的内侧。
裸片102和302二者的嵌入式传导性特征110(例如,混合接合焊盘等)延伸到裸片102和302的接合表面108、并且被接合在一起,从而形成接合的互连结构304。在一个实施例中,第一裸片102可以如上所描述地在过程700处形成,并且第二裸片302可以如上所描述地在过程900处形成。因此,过程1100以微电子组件600或类似开始,其中第一裸片102可以具有一占用区,该占用区与第二裸片302相比更小、更大或实质相同大小。在一些情况中,第一裸片102和第二裸片302可以被实质对准,或者第一裸片102和第二裸片302可以稍微未对准,但是在混合接合公差内。
参考图11,在框A处,示出了示例微电子组件,诸如先前讨论的微电子组件600。在框B处,过程1100包括:将第一裸片102的顶部基晶片104如期望地薄化。在框C处,过程1100包括:在第一裸片102的基层104之上形成图案化的抗蚀剂层1102,其中抗蚀剂层1102中图案化的间隙在基层104对应于如下位置的部分之上对准:期望移除基层104各部分的位置,包括例如在腔602、以及裸片302中的掩埋式接触焊盘306之上、在裸片102的非有源区域之上、以及如期望的裸片102的其他区域之上。
参考图12,在框D处,过程1100包括蚀刻裸片102的基层104的材料(例如,硅等),以显露下方的区域,包括第二裸片302中的接触焊盘306(或腔602中的(多个)其他结构)。如图所示,有源基材料(例如,硅)岛1202可以在裸片102的有源区域中被保留裸片102顶表面上。在框E处,过程1100包括:从基层104上移除抗蚀剂1102。例如,抗蚀剂1102可以通过如下而被移除:使用湿法剥离、随后进行氧等离子体灰化。这产生了如所示出的微电子元件1200。在框F处,过程1100可以包括可选步骤,在可选步骤中,基材料岛1202可以被电绝缘和/或EMI屏蔽等。在图像传感器、激光器、发光二极管(LED)等的情况下,抗反射涂层1204等可以被施加到岛1202。
参考图13,用于形成微电子组件1302的过程1300被示出,微电子组件1302包括至少两个直接接合(例如,没有粘合剂)的裸片102和302。备选地,微电子部件302可以包括晶片或其他衬底等。然而,微电子部件302包括一个或多个接触焊盘306,一个或多个接触焊盘306被设置在裸片102周界的内侧。
裸片102和302二者的嵌入式传导性特征110(例如,混合接合焊盘等)延伸到裸片102和302的接合表面108、并且被接合在一起,从而形成接合的互连结构304。在一个实施例中,第一裸片102可以如上所描述地在过程700处形成,并且第二裸片302可以如上所描述地在过程900处形成。因此,过程1300以微电子组件600或类似开始,其中第一裸片102可以具有以占用区,该占用区与第二裸片302相比更小、更大或实质相同大小。在一些情况下,第一裸片102和第二裸片302可以被实质对准,或者第一裸片102和第二裸片302可以稍微未对准,但是在混合接合公差内。
在框A处,示例微电子组件被示出,诸如先前讨论的微电子组件600。在框B处,过程1300包括:在第一裸片102的基层104之上形成图案化的抗蚀剂层1102,其中抗蚀剂层1102中图案化的间隙在基层104对应于如下位置的部分之上对准:针对腔602的、以及针对裸片302中的掩埋式接触焊盘306的位置。附加地,如框B所示,抗蚀剂可以被沉积在其他位置处,诸如在裸片302的接合层108的预定部分等处。抗蚀剂被放置在附加位置处,以防止在这些位置处蚀刻材料。
在框C处,过程1300包括:蚀刻裸片102的基层104的材料(例如,硅等),以显露第二裸片302中的接触焊盘306。在框D处,过程1300包括:从基层104移除抗蚀剂1102。抗蚀剂1102可以例如通过如下而被移除:使用湿法剥离、随后进行氧等离子体灰化。这产生了如所示出的微电子元件1302。
附加实施例
参考图14,用于形成微电子组件1500的过程1400被示出。在各种实施例中,组件1500从所制备的裸片102形成,裸片102具有金属密封环1402,金属密封环1402如期望地被设置在裸片102内(例如,嵌入在绝缘层106内,并且在某些情况下延伸到基衬底104中)。在一些示例中,所加工的组件1500的气密性可以基于密封环1402的尺寸。
裸片102如过程100或200中所描述地来制备,例如,使用镶嵌工艺(或类似)来形成密封环1402。组件1500还包括一个或多个腔1404,一个或多个腔可以终止于绝缘层106内侧、终止于绝缘层106与基层104的界面处、或者延伸穿过绝缘层106并且也可以至少部分地延伸穿过裸片102的基层104。因此,组件1500非常适合于具有腔的应用,诸如MEMS、传感器等。组件1500可以被形成并制备用于直接接合到另一裸片、晶片、衬底等或者另一组件,诸如本文所描述的另一组件1500。
在框A处,过程1400包括:例如使用CMP过程,如期望地将第一裸片102的混合接合表面108平面化。在框B处,过程1400包括:在第一裸片102的接合表面108之上形成图案化的抗蚀剂层402,其中抗蚀剂层402中图案化的间隙在绝缘层104中对应于如下位置的部分之上对准:针对待形成腔1404的位置。例如,腔1404可以被形成在密封环1402的周界的内侧。
在框C处,过程1400包括:(部分或全部)对绝缘层106的材料(例如,氧化物、硅等)进行蚀刻,并且可选地部分到裸片102的基层104中至期望深度,以形成一个或多个腔1404。
参考图15,在框D处,过程1400包括:从接合表面108移除抗蚀剂402。例如,抗蚀剂402可以通过如下而被移除:使用湿法剥离、随后进行氧等离子体灰化。在一些情况下,抗蚀剂402移除步骤可能导致密封环1402的表面氧化(例如,从而形成氧化铜404)。如图15所示,取决于氧化物404的量,密封环1402的表面可以突出到接合表面108的上方。
在框E处,过程1400包括使用如上所述的CMP过程和/或湿法蚀刻过程而从密封环1402移除氧化物404,同时控制密封环1402上材料的移除速率。例如,选择性蚀刻技术被用于移除氧化物404,这可以包括利用稀释配方(诸如,1:20比例的硫酸与水),利用浆料的修整CMP等来蚀刻氧化物404,浆料被配制为抛光阻挡层。密封环1402的指定凹部(如果适用)可以被实现为利用受控的材料移除来进行氧化物404移除步骤的一部分。
在一些情况中,例如由于双金属效应和光伏效应,可能经历在一些密封环1402上的对蚀刻的电化学增强。在这些情况下,大致10至200nm的氧化物和/或阻挡金属可以被沉积在接合表面108之上。例如,利用阻挡层浆料的CMP(或类似)可以被用于接触抛光并且将密封环1402重新暴露在接合表面108上。由于绝缘层106的边缘与密封环1402相接,必须注意避免使得绝缘层106的边缘制圆(例如,侵蚀)。过程1400的结果是如所示出的微电子元件1500,微电子元件1500准备好以用于直接粘合。
参考图16和图17,用于在裸片102分割之前的道蚀刻的过程1600被示出。在各种实施例中,晶片1602可以如过程100或200中所描述地来形成并制备,例如使用镶嵌工艺(或类似)来形成一个或多个传导性特征110(或密封环1402等)。在框A处,过程1600包括:例如使用CMP过程,将混合接合表面108如期望地平面化。在框B处,过程1600包括:在晶片1602的裸片102的接合表面108之上形成图案化的抗蚀剂层402,其中抗蚀剂层402中图案化的间隙在绝缘层106中的如下部分之上对准:与用于芯片102分割的切割道1604相对应的部分。例如,切割道1604被设置在晶片1602所形成的裸片102之间。
在框C处,过程1600包括:将裸片102的绝缘层104和基层104的材料(例如,氧化物、硅等)蚀刻到期望深度,以形成切割道1604通道或凹部1606。
参考图17,在框D处,过程1600包括:从接合表面108移除抗蚀剂402。例如,抗蚀剂402可以通过如下而被移除:使用湿法剥离、随后通过氧等离子体灰化。在一些情况下,抗蚀剂402移除步骤可以导致传导性特征110(例如,或密封环1402)的表面氧化(例如,从而形成氧化铜404)。如图17所示,取决于氧化物404的量,传导性特征110的表面可以突出到接合表面108的上方。
在框E处,过程1600包括:使用如上所描述的CMP过程和/或湿法蚀刻过程,从传导性特征110移除氧化物404,同时控制传导性特征110上材料的移除速率。例如,选择性蚀刻技术可以被用于移除氧化物404,这可以包括利用稀释配方(诸如,1:20比例的硫酸和水),或通过利用浆料的轻型CMP等来蚀刻氧化物404,浆料被配制为抛光阻挡层。传导性特征110的指定凹部(如果适用)可以被实现为利用受控的材料移除来进行氧化物404移除步骤的一部分。
在一些情况下,例如由于双金属效应和光伏效应,可能经历在一些传导性特征110上对蚀刻的电化学增强。在这些情况下,大致10nm至200nm的氧化物和/或阻挡金属可以被沉积在接合表面108之上。例如,利用阻挡层浆料的CMP(或类似)可以被用于接触抛光并重新暴露传导性特征110于接合表面108上。由于绝缘层106的边缘相接于传导性特征110,必须注意避免使绝缘层106的边缘制圆(例如,侵蚀)。
在框F处,作为一选项,若需要,保护性涂层1702可以被施加到接合表面、以及在切割道凹部1606内。保护性涂层可以在到单独裸片102的分割期间保护接合表面108,该分割发生在切割道凹部1606内。
在各种实施例中,在长期存储导致金属特征(诸如,传导性特征110、密封环1402等)一定程度的氧化之后,具有混合接合表面108的晶片(诸如晶片1602)、裸片(诸如裸片102和302)以及其他衬底等可以被接触抛光。接触抛光可以包括使用如上所述的CMP过程和/或湿法蚀刻过程,同时控制金属特征上的材料移除速率。例如,选择性蚀刻技术被用于移除氧化物,这可以包括利用稀释配方(诸如,1:20比例的硫酸和水)、利用浆料的接触抛光等来蚀刻氧化物,浆料被配制用于抛光阻挡层。金属特征的指定凹部(如果适用)可以作为利用受控的材料移除来进行氧化物移除步骤的一部分而被恢复。
在一些情况中,例如由于双金属效应和光伏效应,可能经历在一些金属特征上的对蚀刻的电化学增强。在这些情况下,大致10nm至200nm的氧化物和/或阻挡金属可以被沉积在接合表面108之上。例如,利用阻挡层浆料的CMP(或类似)可以被用于接触抛光并重新暴露金属特征于接合表面108上。由于绝缘层106的边缘相接于金属特征时,必须注意避免使绝缘层106的边缘边缘制圆(例如,侵蚀)。在接触抛光之后,晶片、裸片、衬底等被制备以用于直接接合。
附加示例组件
参考图18至图32,在各种实施例中,各种微电子组件可以基于组件300、600、1200、1302、1500等或与之相关来形成。换言之,各种微电子组件包括两个或更多个直接接合裸片102和/或302、晶片1602、衬底、或类似、以其各种组合的组件。
参考图18,在框A处,微电子组件1800被示出,微电子组件1800包括具有一个或多个接触焊盘306的组件600,一个或多个接触焊盘306被设置在裸片102的周界内侧。组件1800包括蚀刻穿过裸片102的基层104的开口,以显露第二裸片302和腔602中的接触焊盘306,如图12的框E所示。
如图18所示,在一些情况下,第一裸片102和第二裸片302(以及相应的传导性特征110)可以被实质对准,或者第一裸片102和第二裸片302可以稍微未对准、但是在混合接合公差之内。第一裸片102和第二裸片302中的开口702和308也可以稍微未对准,但是仍然形成腔602并且仍然提供到接触焊盘306的足够接入。
可选地,如框B所示,一个或多个传导性互连结构1802可以被电耦合到接触焊盘306,以提供从组件1800的顶部到接触焊盘306的电接入。例如,在一些情况下,传导性互连结构1802可以突出到裸片102的基层104的顶部的上方。
在一个实施例中,如图19所示,组件1800的第一裸片102可以具有比第二裸片302小的占用区。在另一实施例中,如图19所示,不是所有的腔602可以包括传导性互连结构1802。到接触焊盘306的接入可以是从腔602内侧,或类似。
在一个实施例中,如图20所示,微电子组件2000可以包括组件300,其中组件2000的第一裸片102具有比第二裸片302小的占用区,并且其中第二裸片302的非混合接触焊盘306被设置在第一裸片102周界的外侧。在一个备选实现方式中,组件200包括被电耦合到接触焊盘306的一个或多个传导性互连结构1802,以提供从组件2000的顶部到接触焊盘306的电接入。
在一个实施例中,如图21所示,微电子组件2100可以包括组件1200,其中组件2000的第一裸片102具有比第二裸片302更小的、更大的、或实质相同大小的占用区,并且其中第二裸片302的非混合***接触焊盘306被设置在第一裸片102的周界的内侧。此外,第一裸片102包括岛1202,岛1202通过在裸片102的非有源区域中蚀刻掉裸片102的顶部基层104而形成。例如,有源基材料(例如,硅)岛1202可以在裸片102的有源区域中被保留在裸片102的顶表面上。在一些实施例中,基材料岛1202可以被电绝缘和/或EMI屏蔽等。在图像传感器、激光器、发光二极管(LED)等的情况下,抗反射涂层可以被施加到岛1202。
在一个备选实施例中,如图22所示,组件2100包括在第一裸片102的暴露的绝缘层106上的至少一个金属层2202。在各种示例中,金属层2202可以提供EMI保护、散热或如期望的其他功能。
在另一备选实施例中,如图23所示,组件2100可以包括在一个或多个腔602中的沉积金属2302,沉积金属2302被电耦合到接触焊盘306,以用于到焊盘306的互连。例如,在一些情况下,为了方便进行期望的互连,端子2304(诸如焊球等)可以被耦合到沉积金属2302。
参考图24至图26,具有腔1404和密封环1402的直接接合组件2400被示出。在各种实现方式中,组件2400由直接接合而没有粘合剂(例如,混合接合)的至少一对组件1500形成。在如图24所示的一个实施例中,组件1500中的每一个组件的腔1404被蚀刻穿过绝缘层106并且部分地穿过基层104。在各种备选实施例中,与另一组件1500'相比,腔1404可以被更多或更少地蚀刻到组件的一个组件1500中。参见以下针对一些示例蚀刻深度选项。
在一个示例中,如图25所示,腔1404被蚀刻到第一组件1500中,而不被蚀刻到第二组件1500'中。在图25的附图中示出的示例蚀刻深度穿过绝缘层106并且部分地到基层104中。备选地,蚀刻深度可以仅部分地穿过绝缘层106,或穿过绝缘层106但不进入基层104中。在备选实施例中,腔1404可以被蚀刻到第二组件1500'中但不被蚀刻到第一组件1500中(例如,参见以上针对示例蚀刻深度选项)。此外,如图26所示,组件2400可以包括被安装在腔1404内侧的一个或多个部件2602(例如,部件、结构、电路、元件等)。由于组件2400包括密封环1402,所以腔1404可以被气密地密封,从而提供用于各种传感器、MEMS等的理想环境。
参考图27至图28,在另一实施例中,组件2700包括组件2400,其中第二组件1500'具有比第一组件1500的占用区大的占用区。在一个示例中,第二组件1500'包括在第一组件155的周界的外侧的***接合焊盘2702,***接合焊盘2702可以被用于引线接合2704或类似的电连接。组件的腔1404可以包括一个或多个部件2602,并且由于存在密封环1402,腔1404可以被气密地密封。而且,组件2700可以包括一个或多个传导性特征110,用于在组件2700内的电互连、以及到外侧部件的电互连,例如使用穿透硅过孔(例如,through-siliconvia,TSV)2706等。
如图28所示,多个组件2700可以被堆叠来形成组件2800。备选地,如图所示,多个组件2700中的至少一个或多个组件可以不包括在组件1500和/或1500'中的一者上的基层104。如图所示,组件可以包括密封环1402以及传导性特征110(这些被布置为在具有或不具有过孔2706的情况下,将组件2700电耦合在一起)。
参考图29至图32,示出了微电子组件2900,微电子组件2900包括具有一个或多个接触焊盘306的组件500,一个或多个接触焊盘306被设置在裸片102周界的内侧。例如,在图29和图31处,示出了微电子组件2900,其中接触焊盘306被设置在组件2900的两个有源区域(2902和2904)之间。因此,接触焊盘306可以被设置在预选定区域处,该预选定区域不一定位于裸片102和302的***处。例如,接触焊盘306可以被设置在裸片102和302的有源区域的周界内。组件2900包括开口,该开口蚀刻穿过裸片102的基层104和绝缘层106、以及裸片302的绝缘层106,以显露第二裸片302中的腔602和接触焊盘306。
图30图示了组件2900或其类似的俯视图,其示出了接触焊盘306可以是传导性条带或其他形状结构的形式。例如,堆叠的动态随机存取存储器(DRAM)组件通常具有在裸片302的中央条带(或类似位置)中的TSV。该装置也可以与其他组件一起使用。
如图31所示,在第一裸片102的基层104和绝缘层106、以及第二裸片302的绝缘层106中的蚀刻开口不需要被完全对准,开口形成腔602以用于到接触焊盘306的接入。附加地,如图32所示,第一裸片102的基层104和绝缘层106、以及第二裸片302的绝缘层106中的蚀刻开口可以具有不同的大小、形状、占用区等。例如,如图32所示,第一裸片102的基层104中的开口3202可以包括第一形状(例如,对于该示例,矩形,但是可以包括任何几何形状或不规则形状),其暴露了第一裸片102和/或第二裸片302的(多个)绝缘层106。附加地,第一裸片102和第二裸片302的绝缘层106中的开口3204和3206可以具有相同或不同的形状(例如,在该示例中,分别为椭圆形和矩形,但可以包括任何几何形状或不规则形状),其暴露第二裸片302的接触焊盘306。
在各种实施例中,与本文描述的过程步骤相比,一些过程步骤可以被修改或消除。
本文所述的技术、部件和器件不限于图1至图28的例示,并且在不脱离本公开的范围的情况下,本文所述的技术、部件和器件可以被应用于其他设计、类型、装置和构造(包括具有其他电部件)。在一些情况下,附加或备选的部件、技术、序列或过程可以被用来实现本文所述的技术。此外,部件和/或技术可以按各种组合来布置和/或组合,同时产生相似或大致相同的结果。
结论
尽管已以特定于结构特征和/或方法学动作的语言描述了本公开的实现方式,但是应当理解,实现方式不必限于所描述的特定特征或动作。相反,特定特征和动作作为实现示例器件和技术的表示性形式而公开。
Claims (39)
1.一种微电子组件,包括:
具有接合表面的第一衬底,所述第一衬底的所述接合表面具有平面化形貌;
第一多个电传导性特征,在所述第一衬底的所述接合表面处;
具有接合表面的第二衬底,所述第二衬底的所述接合表面具有平面化形貌、并且被接合到所述第一衬底的所述接合表面;
第二多个电传导性特征,在所述第二衬底的所述接合表面处、并且被接合到所述第一多个电传导性特征;以及
一个或多个电传导性接触焊盘,被设置在所述第二衬底的绝缘层内、并且在所述第二衬底的所述接合表面下方,所述一个或多个电传导性接触焊盘被设置在与所述第一多个电传导性特征、以及所述第二多个电传导性特征不同的区域中。
2.根据权利要求1所述的微电子组件,还包括一个或多个次级开口,所述一个或多个次级开口在所述第二衬底的所述绝缘层中,所述一个或多个次级开口与所述一个或多个电传导性接触焊盘对准,所述一个或多个次级开口从所述第二衬底的所述接合表面延伸到所述一个或多个电传导性接触焊盘,从而提供到所述一个或多个电传导性接触焊盘的接入。
3.根据权利要求2所述的微电子组件,还包括一个或多个初级开口,所述一个或多个初级开口在所述第一衬底的绝缘层中,所述一个或多个初级开口与所述一个或多个次级开口、以及与所述电传导性接触焊盘对准,所述一个或多个初级开口延伸到所述一个或多个次级开口,从而提供到所述一个或多个电传导性接触焊盘的接入。
4.根据权利要求3所述的微电子组件,其中所述一个或多个初级开口具有一占用区,所述占用区具有与所述一个或多个次级开口不同的尺寸和/或形状。
5.根据权利要求3所述的微电子组件,还包括一个或多个三级开口,所述一个或多个三级开口在所述第一衬底的基层中,所述一个或多个三级开口与所述第一衬底的所述绝缘层中的所述一个或多个初级开口、以及与所述电传导性接触焊盘对准,所述一个或多个三级开口从所述第一衬底的外侧表面延伸到所述一个或多个初级开口,从而提供从所述第一衬底的所述外侧表面之外到所述一个或多个电传导性接触焊盘的接入。
6.根据权利要求5所述的微电子组件,还包括一个或多个电传导性结构,所述一个或多个电传导性结构被设置在以下一项或多项内:所述一个或多个次级开口、所述一个或多个初级开口以及所述一个或多个三级开口,并且所述一个或多个电传导性结构被电耦合到所述一个或多个电传导性接触焊盘。
7.根据权利要求6所述的微电子组件,还包括端子部件,所述端子部件被耦合到所述电传导性结构中的一个或多个电传导性结构,并且所述端子部件被配置为提供从所述第一衬底的所述外侧表面之外到所述一个或多个电传导性接触焊盘的电接入。
8.根据权利要求6所述的微电子组件,其中所述电传导性结构中的一个或多个电传导性结构突出超过所述第一衬底的所述外侧表面。
9.根据权利要求5所述的微电子组件,其中所述一个或多个三级开口具有一占用区,所述占用区具有与所述一个或多个初级开口和/或所述一个或多个次级开口不同的尺寸和/或形状。
10.根据权利要求1所述的微电子组件,还包括一个或多个电传导性互连件,所述一个或多个电传导性互连件被电耦合到所述电传导性接触焊盘中的一个或多个电传导性接触焊盘。
11.根据权利要求1所述的微电子组件,还包括至少一个金属层,所述至少一个金属层被设置在所述第一衬底的暴露的外侧表面上,被配置用于电磁干扰(EMI)保护和/或用于散热。
12.根据权利要求1所述的微电子组件,还包括保护性金属涂层,所述保护性金属涂层被设置在所述一个或多个电传导性接触焊盘的暴露的表面上。
13.根据权利要求1所述的微电子组件,其中所述第一衬底的占用区比所述第二衬底的占用区小。
14.根据权利要求1所述的微电子组件,其中所述一个或多个电传导性接触焊盘被设置在所述第一衬底的周界内。
15.根据权利要求1所述的微电子组件,其中所述一个或多个电传导性接触焊盘被设置在所述第一衬底的周界的外侧。
16.根据权利要求1所述的微电子组件,其中所述一个或多个电传导性接触焊盘被设置在所述微电子组件的两个或更多有源区域之间,和/或所述一个或多个电传导性接触焊盘被设置在所述微电子组件的一个或多个有源区域内。
17.根据权利要求1所述的微电子组件,其中所述第二多个电传导性特征与所述第一多个电传导性特征以第一程度未对准。
18.根据权利要求1所述的微电子组件,其中所述第一衬底包括分开的有源区的多个岛。
19.根据权利要求1所述的微电子组件,其中所述第一衬底的所述接合表面使用无粘合剂的室温共价接合技术,被接合到所述第二衬底的所述接合表面。
20.一种微电子组件,包括:
具有接合表面的第一衬底,所述第一衬底的所述接合表面具有平面化形貌;
第一多个电传导性特征,在所述第一衬底的所述接合表面处;
具有接合表面的第二衬底,所述第二衬底的所述接合表面具有平面化形貌、并且被接合到所述第一衬底的所述接合表面;
第二多个电传导性特征,在所述第二衬底的所述接合表面处,所述第二多个电传导性特征被接合到所述第一多个电传导性特征,同时与所述第一多个电传导性特征以第一程度未对准;
一个或多个电传导性接触焊盘,被设置在所述第二衬底的绝缘层内、并且在所述第二衬底的所述接合表面下方,所述一个或多个电传导性接触焊盘被设置在以下项的内侧或外侧:所述第二多个电传导性特征以及所述第一多个电传导性特征的周界;
一个或多个次级开口,所述一个或多个次级开口在所述第二衬底的所述绝缘层中,所述一个或多个次级开口与所述一个或多个电传导性接触焊盘对准,所述一个或多个次级开口从所述第二衬底的所述接合表面延伸到所述一个或多个电传导性接触焊盘;以及
一个或多个初级开口,所述一个或多个初级开口在所述第一衬底的绝缘层中,所述一个或多个初级开口与所述一个或多个次级开口以所述第一程度未对准,所述一个或多个初级开口延伸到所述一个或多个次级开口,并且提供到所述一个或多个电传导性接触焊盘的接入。
21.根据权利要求20所述的微电子组件,还包括一个或多个三级开口,所述一个或多个三级开口在所述第一衬底的基层中,所述一个或多个三级开口与所述第一衬底的所述绝缘层中的一个或多个初级开口对准,所述一个或多个三级开口从所述第一衬底的外侧表面延伸到所述一个或多个初级开口,从而提供从所述第一衬底的所述外侧表面之外到所述一个或多个电传导性接触焊盘的接入。
22.根据权利要求21所述的微电子组件,还包括一个或多个电传导性结构,所述一个或多个电传导性结构被设置在以下一项或多项内:所述一个或多个次级开口、所述一个或多个初级开口以及所述一个或多个三级开口,并且所述一个或多个电传导性结构被电耦合到所述一个或多个电传导性接触焊盘。
23.根据权利要求20所述的微电子组件,其中所述第一衬底的占用区比所述第二衬底的占用区小。
24.一种微电子组件,包括:
第一衬底,具有包括绝缘体材料的混合接合表面,所述绝缘体材料具有在其中的一个或多个金属特征,所述混合接合表面具有平面化形貌;
第二衬底,具有包括绝缘体材料的混合接合表面,该绝缘体材料具有被嵌入在其中的一个或多个金属特征,所述第二衬底的所述混合接合表面具有平面化形貌、并且被接合到所述第一衬底的所述混合接合表面,其中所述第二衬底的所述一个或多个金属特征被接合到所述第一衬底的所述一个或多个金属特征;
腔,被设置在所述第一衬底与所述第二衬底之间的接合联接处,在所述第一衬底与所述第二衬底之间的所述接合联接处,所述第一衬底的所述混合接合表面和所述第二衬底的所述混合接合表面接触,所述腔至少由在所述第一衬底的所述混合接合层中的凹部形成;以及
连续密封件,通过所述第一衬底的所述一个或多个金属特征被接合到所述第二衬底的所述一个或多个金属特征而形成,所述连续密封件被设置在所述接合联接处,围绕所述腔的周界。
25.根据权利要求24所述的微电子组件,还包括被设置在所述腔内的以下一项或多项:微电子部件、电路或传感器。
26.根据权利要求24所述的微电子组件,还包括:第三衬底,具有包括绝缘体材料的混合接合表面,该绝缘体材料具有被嵌入在其中的一个或多个金属特征,所述第三衬底的所述混合接合表面具有平面化形貌、并且被接合到所述第一衬底,其中所述第三衬底的所述一个或多个金属特征被接合到所述第一衬底的所述金属特征中的一个或多个金属特征。
27.根据权利要求26所述的微电子组件,其中所述腔是第一腔,并且其中所述第三衬底包括第二腔,所述第二腔被设置在所述第一衬底与所述第三衬底之间的接合联接处,在所述第一衬底与所述第三衬底之间的所述接合联接处,所述第三衬底的所述混合接合表面与所述第一衬底接触,所述第二腔至少由所述第三衬底的所述混合接合层中的凹部形成。
28.根据权利要求24所述的微电子组件,其中所述腔由所述第一衬底的所述混合接合层中的所述凹部、以及所述第二衬底的所述混合接合层中的另一凹部形成。
29.根据权利要求24所述的微电子组件,其中所述第一衬底的所述一个或多个金属特征与所述第二衬底的所述一个或多个金属特征以第一程度彼此偏移。
30.根据权利要求24所述的微电子组件,其中所述第二衬底的占用区比所述第一衬底的占用区大,并且其中所述第二衬底包括一个或多个电传导性接触焊盘,所述一个或多个电传导性接触焊盘被设置在所述第一衬底的周界外侧的所述第二衬底的所述混合接合表面处,所述一个或多个电传导性接触焊盘被配置为将所述第二衬底电互连到不同于所述第一衬底的元件。
31.根据权利要求24所述的微电子组件,其中所述第一衬底的所述一个或多个金属特征从所述第一衬底的所述接合表面延伸到超过所述第一衬底的所述绝缘体材料、并且延伸到所述第一衬底的基层中,和/或所述第二衬底的所述一个或多个金属特征从所述第二衬底的所述接合表面延伸到超过所述第二衬底的所述绝缘体材料、并且延伸到所述第二衬底的基层中。
32.一种方法,包括:
提供具有混合接合表面的衬底,所述混合接合表面包括具有一个或多个金属特征的绝缘体材料,所述混合接合表面具有平面化形貌,所述衬底包括一个或多个电传导性接触焊盘,所述一个或多个电传导性接触焊盘被设置在所述衬底的所述绝缘体材料内、并且在所述混合接合表面下方,所述一个或多个电传导性接触焊盘被设置在所述一个或多个金属特征的周界的外侧;
将所述混合接合表面抛光;以及
通过所述混合接合表面在所述绝缘体材料中蚀刻一个或多个开口,以暴露所述一个或多个电传导性接触焊盘。
33.根据权利要求32所述的方法,还包括:在与所述衬底的切割道相对应的位置处,在所述衬底中蚀刻凹部,以预备用于将所述衬底分割为多个裸片。
34.根据权利要求32所述的方法,还包括在所述蚀刻之后,对所述一个或多个金属特征的暴露的表面进行接触抛光。
35.根据权利要求32所述的方法,还包括:
在所述混合接合表面之上形成图案化的抗蚀剂层;
蚀刻所述绝缘体材料的未由所述抗蚀剂层覆盖的区;以及
从所述混合接合表面移除所述抗蚀剂层。
36.根据权利要求35所述的方法,还包括:在蚀刻所述绝缘体材料的未由所述抗蚀剂层覆盖的所述区之后,从所述一个或多个金属特征的暴露的表面移除氧化物。
37.根据权利要求36所述的方法,其中包括稀硫酸或稀磺酸的蚀刻剂被用于移除所述氧化物。
38.根据权利要求37所述的方法,其中所述稀硫酸或稀磺酸具有包括1比20的硫酸或磺酸对水的比率。
39.根据权利要求32所述的方法,其中所述蚀刻在以下之前执行:在无粘合剂的情况下,所述衬底被直接接合到另一微电子元件。
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PCT/US2019/042050 WO2020023249A1 (en) | 2018-07-26 | 2019-07-16 | Post cmp processing for hybrid bonding |
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