TW201941375A - 封裝、疊層封裝結構及製造疊層封裝結構的方法 - Google Patents

封裝、疊層封裝結構及製造疊層封裝結構的方法 Download PDF

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TW201941375A
TW201941375A TW107147317A TW107147317A TW201941375A TW 201941375 A TW201941375 A TW 201941375A TW 107147317 A TW107147317 A TW 107147317A TW 107147317 A TW107147317 A TW 107147317A TW 201941375 A TW201941375 A TW 201941375A
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package
die
conductive structures
conductive
cross
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TW107147317A
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TWI769359B (zh
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邱勝煥
陳俊仁
陳承先
劉國洲
張國輝
林忠儀
鄭錫圭
賴怡仁
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台灣積體電路製造股份有限公司
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Abstract

一種封裝包括晶粒、多個第一導電結構、多個第二導電結構、包封體及重佈線結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述第一導電結構及所述第二導電結構環繞所述晶粒。所述第一導電結構包括圓形柱且所述第二導電結構包括橢圓形柱或圓臺。所述包封體包封所述晶粒、所述第一導電結構及所述第二導電結構。所述重佈線結構位於所述晶粒的所述主動表面及所述包封體上。所述重佈線結構電性連接到所述晶粒、所述第一導電結構及所述第二導電結構。

Description

封裝、疊層封裝結構及製造疊層封裝結構的方法
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度的持續提高，半導體行業已經歷快速增長。在很大程度上，集成密度的此種提高來自於最小特徵大小（minimum feature size）的重複減小，此使得更多較小的元件能夠集成到給定區域中。這些較小的電子元件也需要與先前的封裝相比利用較小區域的較小的封裝。當前，集成扇出型封裝因其緊湊性而正變得日漸流行。如何確保集成扇出型封裝的可靠性已成為此領域中的挑戰。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開在各種實例中可重複使用標號及/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所討論的各個實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。除附圖中所繪示的排列方向以外，所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同排列方向。設備可被另外排列方向（旋轉90度或處於其他排列方向），且本文所使用的空間相對性用語可同樣相應地作出解釋。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional；3D）封裝或三維積體電路（three-dimensional integrated circuit；3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊，以使得能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率並降低成本。
圖1A到圖1L是根據本公開的一些實施例的封裝10及疊層封裝（package-on-package；PoP）結構1000的製造流程的示意性剖面圖。參照圖1A，提供載板C，在載板C上堆疊有剝離層DB及介電層100。在一些實施例中，剝離層DB形成在載板C的上表面上，且剝離層DB位於載板C與介電層100之間。舉例來說，載板C可為玻璃基板，且剝離層DB可為形成在所述玻璃基板上的光熱轉換（light-to-heat conversion；LTHC）釋放層。然而，本公開並非僅限於此，且其他合適的材料也可適用於載板C及剝離層DB。在一些實施例中，介電層100的材料包括聚醯亞胺（polyimide；PI）、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（benzocyclobutene，BCB）、聚苯並噁唑（polybenzooxazole，PBO）或任何其他合適的聚合物系介電材料。可例如通過例如旋塗（spin-on coating）、化學氣相沉積（chemical vapor deposition；CVD）、等離子體增強型化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）等合適的製作技術來形成介電層100。在一些實施例中，介電層100可具有黏附性質以黏附於隨後形成的元件。
參照圖1B，在介電層100上形成多個導電結構200及晶粒300。在一些實施例中，拾取晶粒300且將晶粒300放置到介電層100上。晶粒300例如包括半導體基板310、多個導電接墊320、鈍化層330、後鈍化層340、多個導電通孔350及保護層360。在一些實施例中，導電接墊320設置在半導體基板310上。鈍化層330形成在半導體基板310上且具有局部地暴露出導電接墊320的接觸開口。半導體基板310可為矽基板，所述矽基板包括形成在所述矽基板中的主動元件（例如，電晶體等）及被動元件（例如，電阻器、電容器、電感器等）。導電接墊320可為鋁接墊、銅接墊或其他合適的金屬接墊。鈍化層330可為氧化矽層、氮化矽層、氮氧化矽層、或由其他合適的介電材料形成的介電層。此外，後鈍化層340形成在鈍化層330上。後鈍化層340覆蓋鈍化層330且具有多個接觸開口。導電接墊320被後鈍化層340的接觸開口局部地暴露出。後鈍化層340可為聚醯亞胺層、聚苯並噁唑層或由其他合適的聚合物形成的介電層。另外，導電通孔350形成在導電接墊320上。在一些實施例中，導電通孔350鍍覆在導電接墊320上。保護層360形成在後鈍化層340上以覆蓋導電通孔350。
如圖1B所示，晶粒300具有後表面300a及與後表面300a相對的前表面300b。在一些實施例中，晶粒300的後表面300a通過晶粒貼合膜（die attach film；DAF；未示出）貼合（或黏附）到介電層100。另一方面，晶粒300的前表面300b面向上且被暴露出。儘管在圖1B中示出一個晶粒300，然而在本公開中並不限制於此。在一些替代實施例中，可拾取多於一個晶粒300且將晶粒300放置到介電層100上。
導電結構200被形成為環繞晶粒300。在一些實施例中，形成導電結構200的方法包括以下步驟。首先，在介電層100上形成晶種材料層（未示出）。在一些實施例中，晶種材料層包括通過濺鍍製程形成的鈦/銅複合物層。隨後，在晶種材料層上形成具有開口的光阻（未示出）。光阻的開口暴露出隨後形成的導電結構200的預期位置。然後，執行鍍覆製程以在被光阻的開口暴露出的晶種材料層上形成金屬材料層（例如，銅層）。然後移除光阻及下伏晶種材料層以形成導電結構200。然而，本公開並非僅限於此。在一些替代實施例中，可通過拾取及放置（pick and place）預先製作的導電結構到介電層100上來形成導電結構200。在一些實施例中，導電結構200的高度可為100 μm到200 μm。
在一些實施例中，導電結構200的幾何形狀及排列在確保隨後形成的封裝10的可靠性方面發揮重要作用。以下將結合圖2A到圖2D詳細闡述導電結構200的配置。
圖2A到圖2D是圖1B的導電結構200的各種排列的示意性俯視圖。參照圖1B及圖2A，在一些實施例中，導電結構200可由多個第一導電結構200a及多個第二導電結構200b構成。在一些實施例中，第一導電結構200a包括圓形柱且第二導電結構200b包括橢圓形柱。如圖2A所示，第一導電結構200a的俯視圖表現為圓形形狀而第二導電結構200b的俯視圖表現為橢圓形形狀。換句話說，第一導電結構200a的與晶粒300的後表面300a平行的剖面為圓形，而第二導電結構200b的與晶粒300的後表面300a平行的剖面為橢圓形。如圖2A所示，橢圓形（第二導電結構200b的剖面）具有長軸200b1及短軸200b2。在一些實施例中，長軸200b1對短軸200b2的比率大於1且小於8。
參照圖2A，第二導電結構200b設置成比第一導電結構200a更靠近晶粒300。舉例來說，第二導電結構200b可被設置成以放射狀（radial）方式包圍晶粒300，且第一導電結構200a可被設置成環繞第二導電結構200b。在一些實施例中，第二導電結構200b中的一些被排列成相對於晶粒300的側壁的延伸方向傾斜。舉例來說，晶粒300可為具有彼此連接的四條邊S1到S4的平行四邊形。邊S1及邊S3沿第一方向D1延伸，而邊S2及邊S4沿第二方向D2延伸。第一方向D1垂直於第二方向D2。在一些實施例中，橢圓形（第二導電結構200b的剖面）的長軸200b1與第一方向D1形成0°到90°的夾角θa 。在一些實施例中，橢圓形（第二導電結構200b的剖面）的長軸200b1與第二方向D2形成0°到90°的夾角θb 。換句話說，第二導電結構200b的剖面的長軸200b1與從晶粒300的中心沿放射狀向外朝隨後形成的封裝10的邊緣延伸的虛擬線對齊。
參照圖2B，提供導電結構200的替代配置。如圖2B所示，第一導電結構200a（圓形柱）排列成多個第一導電結構陣列A200a ，且第二導電結構200b（橢圓形柱）排列成多個第二導電結構陣列A200b 。在一些實施例中，第二導電結構陣列A200b 比鄰晶粒300的邊S1到S4設置，而第一導電結構陣列A200a 比鄰晶粒300的四個角落設置。舉例來說，如圖2B所示，每一第二導電結構陣列A200b 夾置在兩個相鄰的第一導電結構陣列A200a 之間。在一些實施例中，比鄰邊S1及邊S3（沿第一方向D1延伸）排列的第二導電結構200b（橢圓形柱）的剖面的長軸200b1與第二方向D2平行。相似地，比鄰邊S2及邊S4（沿第二方向D2延伸）排列的第二導電結構200b（橢圓形柱）的剖面的長軸200b1與第一方向D1平行。換句話說，在一些實施例中，第二導電結構200b不是以放射狀方式排列在晶粒300周圍。然而，本公開中並不限制於前述排列。在一些替代實施例中，除了第二導電結構陣列A200b 中的第二導電結構200b相對於晶粒300的側壁的延伸方向傾斜以外，可利用與圖2B所示配置相似的方式來排列第一導電結構200a及第二導電結構200b。換句話說，第二導電結構陣列A200b 中的第二導電結構200b可利用放射狀方式排列在晶粒300周圍。
參照圖2C，提供導電結構200的替代配置。如圖2C所示，除了所有導電結構200均為橢圓形柱以外，導電結構200的配置相似於圖2A所示的配置。舉例來說，導電結構200中的一些被排列成相對於晶粒300的側壁的延伸方向傾斜。在一些實施例中，橢圓形（導電結構200的剖面）的長軸200b1與第一方向D1形成0°到90°的夾角θa 。在一些實施例中，橢圓形（導電結構200的剖面）的長軸200b1與第二方向D2形成0°到90°的夾角θb 。換句話說，導電結構200的剖面的長軸200b1與從晶粒300的中心沿放射狀向外朝隨後形成的封裝10的邊緣延伸的虛擬線對齊。
參照圖2D，提供導電結構200的替代配置。如圖2D所示，設置在晶粒300的兩個相對的邊（即，邊S1及邊S3）上的導電結構200沿同一方向排列。另一方面，設置在晶粒300的另外兩個相對的邊（即，邊S2及邊S4）上的導電結構200沿另一方向排列。舉例來說，在邊S1及邊S3旁邊排列的導電結構200的剖面的長軸200b1與第二方向D2平行。相似地，在邊S2及邊S4旁邊排列的導電結構200的剖面的長軸200b1與第一方向D1平行。換句話說，導電結構200不是以放射狀方式排列在晶粒300周圍。導電結構200被排列成具有與第一方向D1平行或垂直的長軸200b1。
在一些實施例中，導電結構200並非僅限於具有筆直側壁的導電柱。舉例來說，在一些替代實施例中，導電結構200可包括具有錐形（tapered）側壁的導電支柱。以下將結合圖3論述具有錐形側壁的導電結構200。
圖3是圖1B的製造步驟的替代實施例的示意性剖面圖。參照圖3，在一些實施例中，導電結構200’包括圓臺（conical frustum）。在一些實施例中，每一導電結構200’（圓臺）具有頂表面T200’ 及底表面B200’ 。底表面B200’ 貼合到介電層100。另一方面，頂表面T200’ 面向上且被暴露出。在一些實施例中，頂表面T200’ 及底表面B200’ 為圓形，且頂表面T200’ 的直徑d1小於底表面B200’ 的直徑d2。舉例來說，頂表面T200’ 的直徑d1對底表面B200’ 的直徑d2的比率可大於0.5且小於1。換句話說，底表面B200’ 的面積大於頂表面T200’ 的面積。在一些實施例中，導電結構200’可由圓形柱及圓臺構成。舉例來說，導電結構200’可利用與圖2A或圖2B所示配置相似的方式來排列。換句話說，圓臺可被排列成比圓形柱更靠近晶粒300。作為另一選擇，圓臺可比鄰晶粒300的邊S1到S4排列，而圓形柱可比鄰晶粒300的四個角落排列。在一些實施例中，導電結構200’可由橢圓形柱、圓形柱及圓臺構成。在一些替代實施例中，導電結構200’可為橢圓形柱與圓臺的組合。在一些替代實施例中，所有導電結構200’可均為圓臺。
再次參照圖1B，在一些實施例中，可在放置晶粒300之前形成導電結構200。然而，本公開並非僅限於此。在一些替代實施例中，可在介電層100上形成導電結構200之前放置晶粒300。如圖1B所示，晶粒300的頂表面低於導電結構200的頂表面。然而，本公開並非僅限於此。在一些替代實施例中，晶粒300的頂表面可與導電結構200的頂表面實質上共面。
參照圖1C，在介電層100上形成包封材料400以包封導電結構200及晶粒300。導電結構200及晶粒300的保護層360被包封材料400包封。換句話說，導電結構200及晶粒300的保護層360不會被顯露出而是被包封材料400很好地保護住。在一些實施例中，包封材料400是模製化合物、模製底部填充膠（molding underfill）、樹脂（例如環氧樹脂）等。可通過模製製程（例如壓縮模製製程（compression molding process））來形成包封材料400。在一些實施例中，將包封材料400從圖1B所示結構上方施加到靠近晶粒300的位置。然後，在包封材料400上放置頂部模具（top mold；未示出）。隨後，對頂部模具施力以使包封材料400從靠近晶粒300的位置朝導電結構200所在之處流動，以包封晶粒300及導電結構200。在一些實施例中，由於包封材料400從晶粒300所在之處沿放射狀向外朝導電結構200流動，因此導電結構200會經受從包封材料400的流動所產生的扭力（torque force）。如果導電結構的幾何形狀或排列無法抵抗扭力，則導電結構可能受到包封材料推擠而塌陷倒下。塌陷的導電結構無法發揮將封裝結構的前側及背側上的元件電性連接的功能，從而在裝置中造成連接失敗。然而，如以上結合圖2A到圖2D及圖3所論述，導電結構200的至少一部分包括橢圓形柱或圓臺。在一些實施例中，橢圓形柱的幾何形狀及圓臺的幾何形狀使這些結構能夠具有更強的對抗扭力的抗力。在一些實施例中，通過將橢圓形柱的剖面的長軸與扭力的行進方向對齊，對抗扭力的抗力可被進一步增強。因此，通過將橢圓形柱及/或圓臺用作導電結構200以及通過將導電結構200設置成具有特定排列方向，可確保隨後形成的封裝10的可靠性。
參照圖1C及圖1D，研磨包封材料400及晶粒300的保護層360直到暴露出導電通孔350的頂表面為止。在對包封材料400進行研磨之後，在介電層100上形成包封體400a，以包封晶粒300及導電結構200。在一些實施例中，通過機械研磨製程及/或化學機械拋光（chemical mechanical polishing；CMP）製程來研磨包封材料400。在一些實施例中，在包封材料400的研磨製程期間，對保護層360進行研磨以顯露出導電通孔350。在一些實施例中，導電通孔350的一些部分及導電結構200的一些部分也會受到輕微的研磨。在研磨之後，晶粒300具有主動表面300c及與主動表面300c相對的後表面300a。導電通孔350被暴露的部分位於晶粒300的主動表面300c上。
包封體400a包封晶粒300的側壁，且包封體400a被導電結構200穿透。換句話說，晶粒300及導電結構200嵌置在包封體400a中。應注意的是，導電結構200的頂表面、保護層360的頂表面及導電通孔350的頂表面與包封體400a的頂表面實質上共面。
參照圖1E，在導電結構200的頂表面、包封體400a的頂表面、導電通孔350的頂表面及保護層360的頂表面上形成重佈線結構500。重佈線結構500與晶粒300的導電通孔350及導電結構200電性連接。換句話說，重佈線結構500形成在晶粒300的主動表面300c上。在一些實施例中，重佈線結構500包括交替堆疊的多個層間介電層500A與多個重佈線導電層500b。重佈線導電層500b與晶粒300的導電通孔350及嵌置在包封體400a中的導電結構200電性連接。在一些實施例中，導電通孔350的頂表面及導電結構200的頂表面接觸重佈線結構500的最底部的重佈線導電層500b。在一些實施例中，導電通孔350的頂表面及導電結構200的頂表面被最底部層間介電層500a局部地覆蓋。如圖1E所示，最頂部的重佈線導電層500b包括多個接墊。在一些實施例中，上述接墊包括用於球安裝（ball mount）的多個球下金屬（under-ball metallurgy；UBM）圖案500b1及/或用於安裝被動元件的至少一個連接接墊500b2。層間介電層500a及重佈線導電層500b的數目在本公開中不受限制。在一些實施例中，球下金屬圖案500b1及連接接墊500b2的配置可基於電路設計來決定。
參照圖1F，在形成重佈線結構500之後，在球下金屬圖案500b1上放置多個導電端子600，且在連接接墊500b2上安裝多個被動元件700。在一些實施例中，導電端子600包括焊料球。另一方面，被動元件700例如是電容器、電阻器、電感器、天線、類似元件、或其組合。在一些實施例中，可通過植球（ball placement）製程在球下金屬圖案500b1上放置導電端子600，且可通過焊接製程及/或回焊製程在連接接墊500b2上安裝被動元件700。
參照圖1F及圖1G，在重佈線結構500上安裝導電端子600及被動元件700之後，將形成在包封體400a的底表面上的介電層100從剝離層DB剝離，以使介電層100從載板C分離。在一些實施例中，可通過紫外（ultraviolet；UV）雷射照射剝離層DB（例如光熱轉換釋放層），以使黏附在包封體400a的底表面上的介電層100可從載板C脫落。
參照圖1G及圖1H，將圖1G所示結構顛倒，且將所述結構放置到膠帶TP上。然後，對包封體400a及晶粒300的後表面300a上的介電層100進行圖案化，以形成具有多個橢圓形開口OP的介電層102。橢圓形開口OP至少局部地暴露出導電結構200。在一些實施例中，橢圓形開口OP的數目對應於導電結構200的數目。然而，本公開並非僅限於此。在一些替代實施例中，橢圓形開口OP的數目可多於導電結構200的數目。舉例來說，可形成額外的橢圓形開口OP以暴露出晶粒300的後表面300a以便用於將來形成擬連接端子（dummy joint terminal）。在一些實施例中，通過雷射鑽孔（laser drilling）製程形成介電層102的橢圓形開口OP。
參照圖1I，在介電層102上放置模版ST。圖4是圖1I的模版ST及介電層102的橢圓形開口OP的示意性俯視圖。以下將結合圖1I及圖4闡述模版ST與介電層102的相對配置。參照圖1I及圖4，模版ST具有多個橢圓形開孔AP。在一些實施例中，模版ST的橢圓形開孔AP的形狀對應於介電層102的橢圓形開口OP的形狀。舉例來說，從俯視圖看，橢圓形開孔AP及橢圓形開口OP二者均可具有橢圓形形狀。在一些實施例中，橢圓形開孔AP的輪廓與橢圓形開口OP的輪廓共形。在一些實施例中，模版ST的橢圓形開孔AP小於或等於介電層102的橢圓形開口OP的大小。舉例來說，橢圓形開口OP可具有100 μm到200 μm的直徑（長軸），而橢圓形開孔AP可具有70 μm到200 μm的直徑（長軸）。在一些實施例中，將模版ST放置在介電層102上，以使橢圓形開孔AP與橢圓形開口OP同軸（coaxial）。如圖4所示，橢圓形開口OP及橢圓形開孔AP暴露出每一導電結構200的至少一部分。在一些實施例中，模版ST的厚度介於50 μm到150 μm的範圍內。
參照圖1J，在導電結構200被暴露的部分上塗布導電膏800。舉例來說，通過分配器（dispenser；未示出）在模版ST上塗布導電膏800。隨後，可採用刮刀（squeegee；未示出）將導電膏800刮抹到模版的橢圓形開孔AP及介電層102的橢圓形開口OP中。換句話說，將導電膏800填充到介電層102的橢圓形開口OP及模版ST的橢圓形開孔AP中。在一些實施例中，橢圓形開口OP及橢圓形開孔AP的橢圓性將填充在其中的導電膏800塑形成橢圓形柱/橢圓形塊（tablet）的形狀。在一些實施例中，導電膏800可包括銅膏或其他合適的膏。
參照圖1J及圖1K，接著移除模版ST，且將導電膏800固化以在橢圓形開口OP中形成多個連接端子802。在一些實施例中，導電膏800的固化製程可包括回焊製程。如圖1K所示，連接端子802包括橢球（ellipsoid）。在一些實施例中，連接端子802從介電層102的表面突出以用於將來的電性連接。在此階段，實質上完成了封裝10。
在一些實施例中，連接端子802的幾何形狀及排列在確保隨後形成的疊層封裝結構1000的可靠性方面發揮重要作用。以下將結合圖5A及圖5B詳細闡述連接端子802的配置。
圖5A及圖5B是圖1K的連接端子802的各種排列的示意性俯視圖。參照圖1K及圖5A，每一連接端子802的俯視圖表現為橢圓形形狀。換句話說，連接端子802的與晶粒300的後表面300a平行的剖面是橢圓形。如圖5A所示，橢圓形（連接端子802的剖面）具有長軸802a1及短軸802a2。在一些實施例中，剖面的短軸802a2對剖面的長軸802a1的比率介於0.2與0.9之間或1.1與3之間。
參照圖5A，設置在晶粒300的兩個相對的邊（即，邊S1及邊S3）上的連接端子802沿同一方向排列。另一方面，設置在晶粒300的另外兩個相對的邊（即，邊S2及邊S4）上的連接端子802沿另一方向排列。舉例來說，在邊S1及邊S3旁邊排列的連接端子802的剖面的長軸802a1與第二方向D2平行。相似地，在邊S2及邊S4旁邊排列的連接端子802的剖面的長軸802a1與第一方向D1平行。換句話說，連接端子802被排列成具有與第一方向D1平行或垂直的長軸802a1。
參照圖5B，提供連接端子802的替代配置。如圖5B所示，連接端子802中的一些被排列成相對於晶粒300的側壁的延伸方向傾斜。在一些實施例中，橢圓形（連接端子802的剖面）的長軸802a1與第一方向D1形成0°到90°的夾角。在一些實施例中，橢圓形（連接端子802的剖面）的長軸802a1與第二方向D2形成0°到90°的夾角。如圖5B所示，連接端子802排列成多個第一連接端子陣列A1、多個第二連接端子陣列A2及多個第三連接端子陣列A3。在一些實施例中，第三連接端子陣列A3設置在比鄰晶粒300的邊S1及邊S3的區的上方，且第二連接端子陣列A2設置在比鄰晶粒300的邊S2及邊S4的區的上方。另一方面，第一連接端子陣列A1可設置在比鄰晶粒300的四個角落的區的上方。舉例來說，如圖5B所示，每一第二連接端子陣列A2夾置在兩個相鄰的第一連接端子陣列A1之間。相似地，每一第三連接端子陣列A3夾置在兩個相鄰的第一連接端子陣列A1之間。
在一些實施例中，第一方向D1與第一連接端子陣列A1中的每一連接端子802的剖面的長軸802a1形成第一夾角θ1 。另一方面，第一方向D1與第二連接端子陣列A2中的每一連接端子802的剖面的長軸802a1形成第二夾角θ2 。如圖5B所示，在一些實施例中，由於第一連接端子陣列A1中的連接端子802被排列成相對於第一方向D1比第二連接端子陣列A2中的連接端子802更傾斜，因此第一夾角θ1 大於第二夾角θ2 。舉例來說，第一夾角θ1 可介於0°與80°之間且第二夾角θ2 可介於0°與45°之間。在一些實施例中，第二方向D2與第一連接端子陣列A1中的每一連接端子802的剖面的長軸802a1形成第三夾角θ3 。另一方面，第二方向D2與第三連接端子陣列A3中的每一連接端子802的剖面的長軸802a1形成第四夾角θ4 。如圖5B所示，在一些實施例中，由於第一連接端子陣列A1中的連接端子802被排列成相對於第二方向D2比第三連接端子陣列A3中的連接端子802更傾斜，因此第三夾角θ3 大於第四夾角θ4 。舉例來說，第三夾角θ3 可介於0°與80°之間且第四夾角θ4 可介於0°與45°之間。在一些實施例中，連接端子802的剖面的長軸802a1與從晶粒300的中心沿放射狀向外朝封裝10的邊緣延伸的虛擬線對齊。
在一些實施例中，連接端子802的排列方向可對應於導電結構200的排列方向。在一些實施例中，在連接端子802為橢球且導電結構200為橢圓形柱的情況下，連接端子802的剖面的長軸802a1可與對應的導電結構200的剖面的長軸200b1平行或對齊。舉例來說，圖5A所示的連接端子802的配置相似於圖2D所示的導電結構200的配置，且圖5B所示的連接端子802的配置相似於圖2C所示的導電結構200的配置。
儘管圖5A及圖5B示出了連接端子802不形成在晶粒300的正上方，然而本公開並非僅限於此。如上所述，在圖1H的步驟期間，可形成額外的橢圓形開口OP以暴露出晶粒300的後表面300a。在一些替代實施例中，可在晶粒300上的這些額外的橢圓形開口OP中形成多個擬連接端子（未示出）。擬連接端子可進一步增強封裝10及隨後形成在連接端子802及擬連接端子上的其他元件之間的結合，從而增強這兩者之間的機械強度。
此外，儘管圖1A到圖1K所示步驟涉及使用集成扇出型（Integrated Fan-out；InFO）封裝作為示例性說明，然而本公開並非僅限於此。在一些替代實施例中，圖1H到圖1K、圖4、圖5A到圖5B所示的連接端子802的形成方法及配置可被用於其他類型的封裝結構。舉例來說，基板上晶圓上晶片（Chip on Wafer on Substrate，CoWoS）封裝也可利用圖1H到圖1K、圖4、圖5A到圖5B所示步驟來形成連接端子。
參照圖1L，在封裝10上堆疊子封裝20，以得到疊層封裝（package-on-package；PoP）結構1000。在一些實施例中，封裝10可被稱為第一封裝，且子封裝20可被稱為第二封裝。如上所述，封裝10可包括集成扇出型封裝、基板上晶圓上晶片封裝或其他類型的封裝。在一些實施例中，子封裝20為例如記憶體裝置或其他積體電路封裝。在一些實施例中，子封裝20通過連接端子802與封裝10電性連接。在一些實施例中，在封裝10上堆疊子封裝20之後，還執行回焊製程。在堆疊製程及/或回焊製程期間，可能產生應力從而造成冷接合（cold joint）缺陷，因而有損於疊層封裝結構的可靠性。在一些實施例中，應力從疊層封裝結構的中心沿放射狀向外朝疊層封裝結構的邊緣發射。如圖1H到圖1K、圖4、圖5A到圖5B所示，連接端子802被形成為具有各種排列方向的橢球。在一些實施例中，橢球的幾何形狀及排列方向使連接端子802能夠釋放在堆疊製程及/或回焊製程期間產生的應力。因此，通過將具有特定排列方向的橢球用作連接端子802，會確保疊層封裝結構1000的可靠性。應注意的是，儘管在圖1L中示出一個子封裝20，然而子封裝20的數目並非僅限於此。在一些替代實施例中，可同時在封裝上堆疊多於一個子封裝以形成疊層封裝結構。
根據本公開的一些實施例，一種封裝包括晶粒、多個第一導電結構、多個第二導電結構、包封體及重佈線結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述第一導電結構及所述第二導電結構環繞所述晶粒。所述第一導電結構包括圓形柱且所述第二導電結構包括橢圓形柱或圓臺（conical frustum）。所述包封體包封所述晶粒、所述第一導電結構及所述第二導電結構。所述重佈線結構位於所述晶粒的主動表面及所述包封體上。所述重佈線結構與所述晶粒、所述第一導電結構及所述第二導電結構電性連接。
根據本公開的一些實施例，一種疊層封裝（package-on-package，PoP）結構包括第一封裝及第二封裝。所述第一封裝包括晶粒、多個導電結構、包封體、重佈線結構、介電層及多個連接端子。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述導電結構環繞所述晶粒且包括橢圓形柱。所述包封體包封所述晶粒及所述導電結構。所述重佈線結構位於所述晶粒的主動表面、所述導電結構及所述包封體上。所述介電層位於所述包封體及所述晶粒的後表面上。所述介電層暴露出所述導電結構。所述連接端子設置在所述導電結構上且包括橢球。所述第二封裝位於所述第一封裝上。所述第二封裝通過所述連接端子與所述第一封裝電性連接。
根據本公開的一些實施例，一種製造疊層封裝（package-on-package，PoP）結構的方法包括至少以下步驟。形成第一封裝。形成第一封裝的方法包括至少以下步驟。提供載板，其中所述載板上形成有介電層。在所述介電層上形成晶粒及多個導電結構。所述晶粒具有主動表面及與所述主動表面相對的後表面。所述導電結構環繞所述晶粒。所述導電結構包括橢圓形柱。使用包封體包封所述晶粒及所述導電結構。在所述晶粒的主動表面、所述導電結構及所述包封體上形成重佈線結構。將所述載板從所述介電層分離。在所述介電層中形成多個橢圓形開口以暴露出所述導電結構。在所述介電層的橢圓形開口中形成多個連接端子。所述連接端子包括橢球。然後，在所述第一封裝上堆疊第二封裝。所述第二封裝通過所述連接端子與所述第一封裝電性連接。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10‧‧‧封裝
20‧‧‧子封裝
100、102‧‧‧介電層
200、200’‧‧‧導電結構
200a‧‧‧第一導電結構
200b‧‧‧第二導電結構
200b1、802a1‧‧‧長軸
200b2、802a2‧‧‧短軸
300‧‧‧晶粒
300a‧‧‧後表面
300b‧‧‧前表面
300c‧‧‧主動表面
310‧‧‧半導體基板
320‧‧‧導電接墊
330‧‧‧鈍化層
340‧‧‧後鈍化層
350‧‧‧導電通孔
360‧‧‧保護層
400‧‧‧包封材料
400a‧‧‧包封體
500‧‧‧重佈線結構
500a‧‧‧層間介電層
500b‧‧‧重佈線導電層
500b1‧‧‧球下金屬圖案
500b2‧‧‧連接接墊
600‧‧‧導電端子
700‧‧‧被動元件
800‧‧‧導電膏
802‧‧‧連接端子
1000‧‧‧疊層封裝結構
A1‧‧‧第一連接端子陣列
A2‧‧‧第二連接端子陣列
A3‧‧‧第三連接端子陣列
A200a‧‧‧第一導電結構陣列
A200b‧‧‧第二導電結構陣列
AP‧‧‧橢圓形開孔
B200 ’‧‧‧底表面
C‧‧‧載板
D1‧‧‧第一方向
d1、d2‧‧‧直徑
D2‧‧‧第二方向
DB‧‧‧剝離層
OP‧‧‧橢圓形開口
S1、S2、S3、S4‧‧‧邊
ST‧‧‧模版
T200 ’‧‧‧頂表面
TP‧‧‧膠帶
θ1‧‧‧第一夾角
θ2‧‧‧第二夾角
θ3‧‧‧第三夾角
θ4‧‧‧第四夾角
θa、θb‧‧‧夾角
圖1A到圖1L是根據本公開的一些實施例的封裝及疊層封裝（package-on-package；PoP）結構的製造流程的示意性剖面圖。
圖2A到圖2D是圖1B的導電結構的各種排列的示意性俯視圖。
圖3是圖1B的製造步驟的替代實施例的示意性剖面圖。
圖4是圖1I的模版及介電層的橢圓形開口的示意性俯視圖。
圖5A及圖5B是圖1K的連接端子的各種排列的示意性俯視圖。

Claims (20)

  1. 一種封裝，包括： 晶粒，具有主動表面及與所述主動表面相對的後表面； 環繞所述晶粒的多個第一導電結構及多個第二導電結構，其中所述第一導電結構包括圓形柱且所述多個第二導電結構包括橢圓形柱或圓臺； 包封體，包封所述晶粒、所述多個第一導電結構及所述多個第二導電結構；以及 重佈線結構，位於所述晶粒的所述主動表面及所述包封體上，其中所述重佈線結構與所述晶粒、所述多個第一導電結構及所述多個第二導電結構電性連接。
  2. 如申請專利範圍第1項所述的封裝，其中每一所述橢圓形柱具有與所述晶粒的所述後表面平行的剖面，且所述剖面的長軸對所述剖面的短軸的比率大於1且小於8。
  3. 如申請專利範圍第1項所述的封裝，其中所述圓臺的頂表面的直徑對所述圓臺的底表面的直徑的比率大於0.5且小於1。
  4. 如申請專利範圍第1項所述的封裝，其中所述多個第二導電結構設置成比所述多個第一導電結構更靠近所述晶粒。
  5. 如申請專利範圍第4項所述的封裝，其中所述晶粒的兩個相對的邊沿第一方向排列，且所述晶粒的另外兩個相對的邊沿與所述第一方向垂直的第二方向排列，每一所述橢圓形柱具有與所述晶粒的所述後表面平行的剖面，且所述剖面的長軸與所述第一方向形成0°到90°的夾角。
  6. 如申請專利範圍第1項所述的封裝，其中所述圓形柱排列成多個第一導電結構陣列，所述橢圓形柱排列成多個第二導電結構陣列，所述多個第二導電結構陣列與所述晶粒的四個邊比鄰設置且設置在所述多個第一導電結構陣列之間。
  7. 如申請專利範圍第6項所述的封裝，其中所述晶粒的兩個相對的第一邊沿第一方向排列，且所述晶粒的兩個相對的第二邊沿與所述第一方向垂直的第二方向排列，每一所述橢圓形柱的剖面平行於所述晶粒的所述後表面且具有長軸，在所述第一邊旁邊排列的所述橢圓形柱的所述剖面的所述長軸平行於所述第二方向，且在所述第二邊旁邊排列的所述橢圓形柱的所述剖面的所述長軸平行於所述第一方向。
  8. 一種疊層封裝結構，包括： 第一封裝，包括： 晶粒，具有主動表面及與所述主動表面相對的後表面； 環繞所述晶粒的多個導電結構，其中所述多個導電結構包括橢圓形柱； 包封體，包封所述晶粒及所述多個導電結構； 重佈線結構，位於所述晶粒的所述主動表面、所述多個導電結構及所述包封體上； 介電層，位於所述包封體及所述晶粒的所述後表面上，其中所述介電層暴露出所述多個導電結構；以及 多個連接端子，設置在所述多個導電結構上，其中所述多個連接端子包括橢球；以及 第二封裝，位於所述第一封裝上，其中所述第二封裝通過所述多個連接端子與所述第一封裝電性連接。
  9. 如申請專利範圍第8項所述的疊層封裝結構，其中所述晶粒的兩個相對的邊沿第一方向排列，且所述晶粒的另外兩個相對的邊沿與所述第一方向垂直的第二方向排列，每一所述橢圓形柱具有與所述晶粒的所述後表面平行的剖面，且所述剖面的長軸與所述第一方向形成0°到90°的夾角。
  10. 如申請專利範圍第8項所述的疊層封裝結構，其中每一所述橢圓形柱具有與所述晶粒的所述後表面平行的剖面，且所述剖面的長軸對所述剖面的短軸的比率大於1且小於8。
  11. 如申請專利範圍第8項所述的疊層封裝結構，其中每一所述多個連接端子具有與所述晶粒的所述後表面平行的剖面，且所述剖面的短軸對所述剖面的長軸的比率介於0.3與0.9之間或1.1與3之間。
  12. 如申請專利範圍第8項所述的疊層封裝結構，其中所述晶粒的兩個相對的第一邊沿第一方向排列且所述晶粒的兩個相對的第二邊沿與所述第一方向垂直的第二方向排列，每一所述多個連接端子具有與所述晶粒的所述後表面平行的剖面，所述剖面具有長軸，且所述長軸與所述第一方向形成0°到90°的夾角。
  13. 如申請專利範圍第12項所述的疊層封裝結構，其中所述多個連接端子排列成多個第一連接端子陣列、多個第二連接端子陣列及多個第三連接端子陣列，所述多個第三連接端子陣列設置在所述晶粒的所述第一邊旁邊，所述多個第二連接端子陣列設置在所述晶粒的所述第二邊旁邊，且所述多個第二連接端子陣列及所述多個第三連接端子陣列位於所述多個第一連接端子陣列之間。
  14. 如申請專利範圍第13項所述的疊層封裝結構，其中所述第一方向與所述多個第一連接端子陣列中的每一連接端子的所述剖面的所述長軸之間的第一夾角大於所述第一方向與所述多個第二連接端子陣列中的每一連接端子的所述剖面的所述長軸之間的第二夾角，所述第二方向與所述多個第一連接端子陣列中的每一連接端子的所述剖面的所述長軸之間的第三夾角大於所述第二方向與所述多個第三連接端子陣列中的每一連接端子的所述剖面的所述長軸之間的第四夾角。
  15. 如申請專利範圍第14項所述的疊層封裝結構，其中所述第一夾角介於0°與80°之間，且所述第二夾角介於0°與45°之間。
  16. 如申請專利範圍第14項所述的疊層封裝結構，其中所述第三夾角介於0°與80°之間，且所述第四夾角介於0°與45°之間。
  17. 如申請專利範圍第8項所述的疊層封裝結構，其中所述多個連接端子的排列方向對應於所述多個導電結構的排列方向。
  18. 一種製造疊層封裝結構的方法，包括： 形成第一封裝，包括： 提供載板，其中所述載板上形成有介電層； 在所述介電層上形成晶粒及多個導電結構，其中所述晶粒具有主動表面及與所述主動表面相對的後表面，所述多個導電結構環繞所述晶粒，且所述多個導電結構包括橢圓形柱； 使用包封體包封所述晶粒及所述多個導電結構； 在所述晶粒的所述主動表面、所述多個導電結構及所述包封體上形成重佈線結構； 將所述載板從所述介電層分離； 在所述介電層中形成多個橢圓形開口以暴露出所述多個導電結構；以及 在所述介電層的所述多個橢圓形開口中形成多個連接端子，其中所述多個連接端子包括橢球；以及 在所述第一封裝上堆疊第二封裝，其中所述第二封裝通過所述多個連接端子與所述第一封裝電性連接。
  19. 如申請專利範圍第18項所述的方法，其中所述形成所述第一封裝的步驟還包括在所述重佈線結構上形成多個導電端子。
  20. 如申請專利範圍第18項所述的方法，其中所述形成所述多個連接端子的步驟包括： 在所述介電層上提供具有多個橢圓形開孔的模版，其中所述多個橢圓形開孔的形狀對應於所述介電層的所述多個橢圓形開口的形狀，且所述多個橢圓形開孔小於所述多個橢圓形開口； 將導電膏填充到所述多個橢圓形開孔及所述多個橢圓形開口中； 從所述介電層移除所述模版；以及 將所述導電膏固化以在所述多個橢圓形開口中形成所述多個連接端子。
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