TW201815046A

TW201815046A - Power supply control unit and isolation type switching power supply device

Info

Publication number: TW201815046A
Application number: TW106131364A
Authority: TW
Inventors: 原英夫; 赤松陽平
Original assignee: 羅姆股份有限公司
Priority date: 2016-09-16
Filing date: 2017-09-13
Publication date: 2018-04-16
Also published as: TWI677177B

Abstract

The power supply control unit includes an on trigger signal generating unit arranged to generate an on trigger signal for turning on the switching element on the basis of a feedback signal of flyback voltage, a first timer arranged to measure a predetermined minimum OFF time, a second timer arranged to measure time based on an ON time, a minimum OFF time setting unit arranged to compare the predetermined minimum OFF time measured by the first timer with the time measured by the second timer so as to set a longer time as a minimum OFF time, and an on timing determining unit arranged to determine timing for turning on the switching element on the basis of the set minimum OFF time and the on trigger signal.

Description

電源控制裝置、及絕緣型開關電源裝置Power control device, and insulated switching power supply device

本發明係關於一種電源控制裝置。The present invention relates to a power control device.

先前，開發有各種將經輸入之直流電壓轉換為所需之直流電壓的反馳方式之絕緣型開關電源裝置。就該絕緣型開關電源裝置而言，藉由對串聯連接於變壓器之一次繞組之開關元件進行開關驅動，而於變壓器之二次側獲得輸出電壓。於使開關元件接通時對變壓器充入激磁能，當使開關元件斷開時，激磁能經由配置於變壓器之二次側之二極體及平滑電容器而放電。絕緣型開關電源裝置之一例係例如揭示於日本專利特開2012-125084號公報。又，作為開關電源裝置之控制方式，先前以來採用線性控制方式(例如電壓模式控制方式、電流模式控制方式)、或非線性控制方式(例如接通時間固定方式、斷開時間固定方式、遲滯窗口方式)。此處，如上所述之反馳方式之絕緣型開關電源裝置中存在如下者，即，以使開關元件斷開之斷開時間不會變得過短的方式設定特定之最小斷開時間，並以斷開時間不會短於最小斷開時間之方式進行限制。於上述情形時，在輸出電壓急遽地下降之暫態響應時，為使輸出電壓上升而將斷開時間設為最小斷開時間地控制開關，但根據使開關元件接通而向變壓器充入激磁能之狀況，有因斷開時間較短而無法充分地於二次側將激磁能放電之情況。因此，有暫態響應之速度降低之問題。又，當斷開時間被設為最小斷開時間時，激磁能之放電時間較短，故而於下一次使開關元件接通之時間點流向一次側之一次側電流變大。因此，亦有接通時產生之一次側電流之峰值上升之變化量變大的問題。又，由於斷開時間被設為最小斷開時間，故而亦有開關頻率之變動變大之問題。鑒於上述狀況，使暫態響應高速化、抑制一次側電流之峰值之上升、及降低開關頻率之變動成為第1課題。進而，如上所述之反馳方式之絕緣型開關電源裝置中存在如下者，即，具有檢測一次側電流之過電流並進行保護之功能(OCP(Over Current Protection，過電流保護))。於此種絕緣型開關電源裝置中，進行如下控制：當偵測到一次側電流達到過電流保護位準(OCP位準)時，強制性地使開關元件斷開，當此後經過上述最小斷開時間時使開關元件再次接通。於使開關元件斷開之期間，所產生之二次側電流減少，但若為如上所述之控制，則僅於稱為最小斷開時間之較短之期間設為斷開，故而二次側電流並未那麼減少，於下一次接通時開始流通之一次側電流變大，若一次側電流上升則會立即達到過電流保護位準，開關元件被再次斷開。因此，有如下問題：使開關元件接通而進行之於一次側之充電變得不充分，絕緣型開關電源裝置之輸出電壓之上升變慢。若鑒於上述狀況，則可於過電流保護時加快輸出電壓之上升成為第2課題。進而，於如上所述之絕緣型開關電源中存在如下者，即，將反饋反馳電壓(＝將由輸出電壓與二次側二極體之正向電壓之和所獲得之電壓以變壓器之圈數比轉換為一次側而得之電壓)之信號於開關元件斷開時輸出並用於控制。此時，自開始反饋信號之輸出後，於上述最小斷開時間之稍前之時序進行輸出之保持。此處，關於反馳電壓，二次側二極體之正向電壓量成為誤差量，二次側電流變少而正向電壓變小之情況時間上越靠後，誤差越小。然而，上述最小斷開時間之稍前之時序係時間上靠前者，故而反饋信號之精度有可能不充分。若鑒於上述狀況，則可將精度良好之狀態下之反饋反馳電壓之信號用於控制成為第3課題。進而，於如上所述之反馳方式之絕緣型開關電源裝置中，有因變壓器之漏電感而導致於開關元件斷開時施加至開關元件之電壓產生振鈴之情況。為了防止該振鈴超過開關元件之耐壓而造成開關元件被破壞，多數情況下設置緩衝電路以抑制振鈴。然而，上述緩衝電路對使用者而言為設計困難之電路，有當設計失敗時開關元件被破壞之虞。若鑒於上述狀況，則即便未使用緩衝電路，亦可抑制於開關元件斷開時施加至開關元件之電壓產生之振鈴成為第4課題。Previously, various types of insulated switching power supply devices have been developed which are in a reverse mode in which an input DC voltage is converted into a required DC voltage. In the insulated switching power supply device, an output voltage is obtained on the secondary side of the transformer by switching the switching elements connected in series to the primary winding of the transformer. When the switching element is turned on, the transformer is charged with excitation energy. When the switching element is turned off, the excitation energy is discharged via the diode disposed on the secondary side of the transformer and the smoothing capacitor. An example of the insulated switching power supply device is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2012-125084. Moreover, as a control method of the switching power supply device, a linear control method (for example, a voltage mode control method, a current mode control method) or a nonlinear control method (for example, an on-time fixed method, an off-time fixed method, a hysteresis window) has been used. the way). Here, in the insulated switching power supply device of the flyback method as described above, there is a case where the specific minimum off time is set such that the off-time of turning off the switching element does not become too short, and The limit is made in such a way that the disconnection time is not shorter than the minimum disconnection time. In the above case, when the output voltage rises sharply, the switch is controlled to set the off time to the minimum off time in order to increase the output voltage, but the switch is energized according to the switching element being turned on. In the case of energy, there is a case where the excitation time cannot be sufficiently discharged on the secondary side due to the short disconnection time. Therefore, there is a problem that the speed of the transient response is lowered. Further, when the off time is set to the minimum off time, the discharge time of the excitation energy is short, so that the current flowing to the primary side on the primary side becomes larger at the time point when the switching element is turned on next time. Therefore, there is also a problem that the amount of change in the peak value of the primary current generated at the time of turning on becomes large. Further, since the off time is set to the minimum off time, there is also a problem that the variation of the switching frequency becomes large. In view of the above situation, it is a first problem to increase the transient response speed, suppress the rise of the peak value of the primary current, and reduce the fluctuation of the switching frequency. Further, in the insulated switching power supply device of the above-described reverse mode, there is a function (OCP (Over Current Protection)) for detecting an overcurrent of the primary current and protecting it. In the insulated switching power supply device, the following control is performed: when the primary current is detected to reach the overcurrent protection level (OCP level), the switching element is forcibly turned off, and then the minimum disconnection is performed after that. The switching element is turned on again at the time. During the period in which the switching element is turned off, the secondary current generated is reduced. However, if the control is as described above, it is turned off only during the short period called the minimum off time, so the secondary side The current does not decrease so much, and the current on the primary side that starts to flow at the next turn-on becomes larger. If the current on the primary side rises, the overcurrent protection level is immediately reached, and the switching element is turned off again. Therefore, there is a problem in that charging of the primary side by turning on the switching element is insufficient, and an increase in the output voltage of the insulated switching power supply device is slow. In view of the above situation, it is a second problem to increase the output voltage during overcurrent protection. Further, in the above-described insulated switching power supply, there is a feedback flyback voltage (= the voltage obtained by the sum of the output voltage and the forward voltage of the secondary side diode is the number of turns of the transformer) The signal of the voltage converted to the primary side is output and used for control when the switching element is turned off. At this time, after the output of the feedback signal is started, the output is held at a timing slightly before the minimum off time. Here, regarding the flyback voltage, the amount of forward voltage of the secondary side diode becomes an error amount, and the secondary side current decreases and the forward voltage becomes smaller. The time is later, the error is smaller. However, the timing before the minimum disconnection time is earlier than the previous one, and thus the accuracy of the feedback signal may be insufficient. In view of the above situation, it is possible to control the signal of the feedback flyback voltage in a state of high precision for the third problem. Further, in the insulated switching power supply device of the flyback method as described above, there is a case where the voltage applied to the switching element is ringing when the switching element is turned off due to the leakage inductance of the transformer. In order to prevent the ringing from being broken by the withstand voltage of the switching element, the snubber circuit is often provided to suppress ringing. However, the above-mentioned snubber circuit is a circuit that is difficult for the user to design, and the switching element is destroyed when the design fails. In view of the above, even if the snubber circuit is not used, it is possible to suppress the ringing of the voltage applied to the switching element when the switching element is turned off, which is the fourth problem.

本發明之一態樣之電源控制裝置係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其計測基於接通時間之時間；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；及接通時序決定部，其基於上述所設定之最小斷開時間及上述接通觸發信號而決定使上述開關元件接通之時序。本發明之另一態樣之電源控制裝置係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：接通時間設定部，其基於上述開關元件之開關時之工作週期而設定接通時間；接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其對基於由上述接通時間設定部所設定之接通時間之時間進行計測；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；及接通時序決定部，其基於上述所設定之最小斷開時間及上述接通觸發信號而決定使上述開關元件接通之時序。本發明之又一態樣之電源控制裝置係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備： OCP部(過電流保護部)，其偵測一次側電流之過電流；斷開控制部，其於偵測到上述過電流時，使上述開關元件斷開；第1計時器，其於自藉由上述斷開控制部斷開起經延遲之時序，計測特定之最小斷開時間；接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；及接通時序決定部，其基於上述計測出之最小斷開時間與上述接通觸發信號而決定使上述開關元件接通之時序。本發明之又一態樣之電源控制裝置係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：反饋信號輸出部，其產生、輸出反饋反馳電壓之反饋信號；接通觸發信號產生部，其基於上述反饋信號輸出部之輸出而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其對接通時間之第1特定比率之時間進行計測；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；接通時序決定部，其基於上述所設定之最小斷開時間及上述接通觸發信號決定使上述開關元件接通之時序；及時序控制部，其控制上述反饋信號輸出部之輸出時序；且上述時序控制部係以如下方式進行控制：自上述開關元件成為斷開後，至經過將上述特定之最小斷開時間之第2特定比率的時間、與上述接通時間之第1特定比率之時間之進而第3特定比率的時間加以比較後較長之時間之時序為止，輸出上述反饋信號，並於該時序保持輸出。本發明之又一態樣之絕緣型開關電源裝置具備：變壓器，其包含在一端連接有輸入電壓之施加端之一次繞組、及二次繞組；主開關元件，其於上述一次繞組之另一端連接有電流流入端；副開關元件，其於上述主開關元件之上述電流流入端連接有電流流入端；及電壓施加部，其以按照上述主開關元件與上述副開關元件均成為接通之狀態、上述主開關元件成為斷開且上述副開關元件成為接通之狀態、上述主開關元件與上述副開關元件均成為斷開之狀態之順序轉變之方式，對上述副開關元件之控制端施加電壓。本發明之又一態樣之電源控制裝置係使用於絕緣型開關電源裝置者，該絕緣型開關電源裝置具備包含一端連接輸入電壓之施加端之一次繞組、及二次繞組之變壓器；且上述電源控制裝置具備：主開關元件，其電流流入端連接於上述一次繞組之另一端；副開關元件，其電流流入端連接於上述主開關元件之上述電流流入端；及電壓施加部，其以上述副開關元件較上述主開關元件更遲地成為斷開之方式，對上述副開關元件之控制端施加電壓。The power supply control device according to an aspect of the present invention is applied to a reverse switching type insulated switching power supply device having a transformer including a primary winding and a secondary winding, and a switching element, and Connecting the input end of the input voltage to one end of the primary winding, and connecting the switching element to the other end of the primary winding; and the power control device includes: an on trigger signal generating unit that generates a feedback signal based on the feedback reverse voltage a turn-on trigger signal for turning on the switching element; a first timer for measuring a specific minimum off time; a second timer for measuring a time based on an on time; and a minimum off time setting unit for comparing The specific minimum off time measured by the first timer and the time measured by the second timer are set to be the minimum off time; and the on timing determining unit is based on the set minimum The timing of turning on the switching element is determined by the on time and the above-described turn-on trigger signal. Another aspect of the present invention is directed to a power supply control device for use in a reverse switching type of an isolated switching power supply device having a transformer including a primary winding and a secondary winding, and a switching element. And connecting the input end of the input voltage to one end of the primary winding, and connecting the switching element to the other end of the primary winding; and the power control device includes: an on-time setting unit based on a duty cycle of switching of the switching element And setting an on-time; turning on a trigger signal generating unit that generates an on-trigger signal for turning on the switching element based on a feedback signal of the feedback flyback voltage; and a first timer that measures a specific minimum off time; The second timer measures the time based on the on-time set by the on-time setting unit, and the minimum off-time setting unit compares the specific minimum off-time measured by the first timer. And the time measured by the second timer, the longer one is set as the minimum off time; and the on timing determination unit Which is based on the setting of the minimum off time and the on-timing of the trigger signal is determined so that the switching element is turned on it. Another aspect of the present invention is directed to a power supply control device for use in a reverse switching type of an isolated switching power supply device having a transformer including a primary winding and a secondary winding, and a switching element. And connecting the input end of the input voltage to one end of the primary winding, and connecting the switching element to the other end of the primary winding; and the power control device includes: an OCP unit (overcurrent protection unit), which detects the primary current a current interrupting control unit that turns off the switching element when the overcurrent is detected; and a first timer that measures a specific delay from a time when the disconnection control unit is turned off a minimum off time; a turn-on trigger signal generating unit that generates an on-trigger signal for turning on the switching element based on a feedback signal of the feedback flyback voltage; and an on-timing determining unit that determines the minimum off-time based on the measurement The turn-on time and the above-described turn-on trigger signal determine the timing at which the switching element is turned on. Another aspect of the present invention is directed to a power supply control device for use in a reverse switching type of an isolated switching power supply device having a transformer including a primary winding and a secondary winding, and a switching element. And connecting the input end of the input voltage to one end of the primary winding, and connecting the switching element to the other end of the primary winding; and the power control device includes: a feedback signal output unit that generates and outputs a feedback signal of the feedback reverse voltage; a turn-on trigger signal generating unit that generates an on-trigger signal for turning on the switching element based on an output of the feedback signal output unit; a first timer that measures a specific minimum off time; and a second timer that Measuring the time of the first specific ratio of the on-time; the minimum off-time setting unit compares the specific minimum off-time measured by the first timer with the time measured by the second timer The longer one is set as the minimum off time; the on timing determination unit is based on the set minimum off time and above a turn-on trigger signal determines a timing at which the switching element is turned on; and a timing control unit that controls an output timing of the feedback signal output unit; and the timing control unit controls the switching element to be turned off after the switching element is turned off The time until the second specific ratio of the time of the specific minimum disconnection time and the time of the first specific ratio of the on-time is further compared with the time of the third specific ratio, and the time is longer. The above feedback signal is output and the output is maintained at this timing. An insulated switching power supply device according to still another aspect of the present invention includes: a transformer including a primary winding having an input end of an input voltage connected to one end thereof, and a secondary winding; and a main switching element connected to the other end of the primary winding a current inflow end; a sub-switching element having a current inflow end connected to the current inflow end of the main switching element; and a voltage applying unit in a state in which the main switching element and the sub-switching element are both turned on, The main switching element is turned off and the sub-switching element is turned on, and the main switching element and the sub-switching element are sequentially turned off, and a voltage is applied to the control terminal of the sub-switching element. A power control device according to still another aspect of the present invention is for use in an insulated switching power supply device comprising: a primary winding having one end connected to an application end of an input voltage, and a transformer of a secondary winding; and the power supply The control device includes: a main switching element having a current inflow end connected to the other end of the primary winding; a sub-switching element having a current inflow end connected to the current inflow end of the main switching element; and a voltage applying unit having the above-mentioned pair The switching element is turned off later than the main switching element, and a voltage is applied to the control terminal of the sub-switching element.

＜絕緣型開關電源裝置之整體構成＞以下，參照圖式對本發明之一實施形態進行說明。圖1係表示本發明之一實施形態之絕緣型開關電源裝置10之整體構成之圖。絕緣型開關電源裝置10係自輸入電壓Vin產生輸出電壓Vout之反馳方式之DC/DC(Direct Current-Direct Current，直流-直流)轉換器。又，絕緣型開關電源裝置10係進行如下所述之適應型接通時間控制作為控制方式。絕緣型開關電源裝置10具備電源控制IC(Integrated Circuit，積體電路)1、外置於電源控制IC1之各種分立零件(變壓器Tr1、二極體D2、平滑電容器C2、電阻R11、及電阻R12)。電源控制IC1(電源控制裝置)係總體地控制絕緣型開關電源裝置10之整體動作之主體(半導體裝置)。電源控制IC1為確立與外部之電性連接而具有電源端子T1、反饋端子T2、開關輸出端子T3、接地端子T4、及REF端子T5。將直流電壓之輸入電壓Vin被施加至電源端子T1，且施加於變壓器Tr1所具有之一次繞組L1之一端。一次繞組L1之另一端係經由外置之電阻R11而連接於反饋端子T2，並且連接於開關輸出端子T3。變壓器Tr1所具有之二次繞組L2之一端連接於二極體D2之陽極。於二極體D2之陰極與二次繞組L2之另一端之間，連接平滑電容器C2。於電容器C2之一端與二極體D2之陰極之連接點產生輸出電壓Vout。於接地端子T4連接接地電位之施加端。於REF端子T5連接外置之電阻R12之一端。圖2係表示電源控制IC1之內部構成之方塊圖。電源控制IC1構成為具有差分電路11、比較器13、邏輯部14、驅動器15、計時器部16、濾波器17、漣波產生部18、OCP部(過電流保護部)19、及開關元件M1，且將該等各構成要素集成化於1個晶片。包含N通道MOSFET(metal-oxide-semiconductorfield-effecttransistor，金屬氧化物半導體場效應電晶體)之開關元件M1之汲極經由開關輸出端子T3連接於一次繞組L1之一端。開關元件M1之源極經由接地端子T4連接於接地電位之施加端。當開關元件M1成為接通時，電流流向變壓器Tr1之一次繞組L1，對變壓器Tr1充入激磁能。此時，二極體D2為斷開。其次，當開關元件M1成為斷開時，已充入之激磁能自變壓器Tr1之二次繞組L2通過二極體D2而放電，由平滑電容器C2進行平滑後產生輸出電壓Vout。此時，電流流向二極體D2。於開關元件M1斷開時，一次繞組L1中產生下述(1)式所示之反馳電壓VOR。 VOR＝Np/Ns×(Vout＋Vf) (1) 其中，Np：一次繞組L1之圈數、Ns：二次繞組L2之圈數、Vf：二極體D2之正向電壓此時，開關元件M1之汲極電壓即開關電壓Vsw係以下述(2)式表示。 Vsw＝Vin＋VOR (2) 差分電路11連接於被施加輸入電壓Vin之電源端子T1、與一端被施加開關電壓Vsw之電阻R11之另一端連接的反饋端子T2、及連接有電阻R12之一端之REF端子T5。藉此，藉由差分電路11，利用電阻R11將開關電壓Vsw與輸入電壓Vin之差量進行電壓、電流轉換，藉由轉換後之電流及電阻R12而於REF端子T5產生REF端子電壓VTref。即，REF端子電壓VTref係作為反饋反馳電壓VOR之反饋信號產生。差分電路11相當於反饋信號輸出部。差分電路11進行如下動作：於開關元件M11斷開時，將REF端子電壓VTref直接輸出作為輸出VTref2；及保持某時序之輸出VTref2。差分電路11係將輸出VTref2輸出至比較器13。比較器13比較輸出VTref2與由漣波產生部18產生之例如三角波狀之基準電壓Vref，將作為比較結果之FET(Field Effect Transistor，場效應晶體管)接通觸發信號Tgon輸出至邏輯部14。比較器13相當於接通觸發信號產生部。邏輯部14產生第1PWM信號pwm1及第2PWM信號pwm2。第1PWM信號pwm1與第2PWM信號pwm2係脈衝狀之信號，且接通工作週期基本上相同。濾波器17藉由將第1PWM信號pwm1過濾而提取接通工作週期資訊。濾波器17相當於工作週期資訊獲取部。計時器部16及邏輯部14基於來自濾波器17之接通工作週期資訊，設定使開關元件M1接通之期間即接通時間。為於如成為所設定之接通時間之時序將開關元件M1自接通切換為斷開，邏輯部14將第2PWM信號pwm2設為Low(低)位準。又，計時器部16及邏輯部14基於來自濾波器17之接通工作週期資訊，設定作為使開關元件M1斷開之期間之斷開時間之最小值即最小斷開時間。為於基於所設定之最小斷開時間及來自比較器13之FET接通觸發信號Tgon之時序將開關元件M1自斷開切換為接通，邏輯部14將第2PWM信號pwm2設為High(高)位準。驅動器15基於由邏輯部14產生之第2PWM信號pwm2產生閘極電壓GT並將其施加至開關元件M1之閘極。藉此，開關元件M1被進行接通/斷開控制。又，計時器部16產生指示差分電路11中所包含之開關(未圖示)之接通/斷開時序之開關時序信號SWT並輸出至差分電路11。差分電路11於開關時序信號SWT指示接通之情形時，將REF端子電壓Vtref直接輸出作為輸出VTref2，於指示斷開之情形時，保持自接通切換為斷開之時序之輸出VTref2。＜關於接通時間/斷開時間設定控制＞其次，對利用本實施形態之電源控制IC1之設定接通時間/斷開時間之控制進行說明。圖3係表示計時器部16及邏輯部14之具體之一構成例之圖。計時器部16具有最小斷開時間計時器161、1/2接通時間計時器162、最小接通時間計時器163、接通時間計時器164、及反相器165。邏輯部14具有第1閂鎖電路141、第2閂鎖電路142、及(AND)電路143～145、以及或(OR)電路146。第1閂鎖電路141輸出第1PWM信號pwm1。第2閂鎖電路142將第2PWM信號pwm2輸出至驅動器15。第1閂鎖電路141與第2閂鎖電路142係藉由輸入至設定端子之信號被同時設定，且藉由輸入至重設端子之信號而基本上同時地(除利用OCP部19之過電流檢測時以外)重設，故而第1PWM信號pwm1與第2PWM信號pwm2同步且接通工作週期相同。於藉由設定第1閂鎖電路141使得第1PWM信號pwm1自Low上升為High時，即於藉由第2PWM信號pwm2使得開關元件M1成為接通時，反相器165之輸出成為Low，藉此，最小接通時間計時器163及接通時間計時器164被重設。最小接通時間計時器163於被重設時開始特定之最小接通時間(固定值)之計測。此處，特定之最小接通時間係決定輸出電壓Vout之過升壓之程度之參數。接通時間計時器164於被重設時，開始接通時間之計測，該接通時間係藉由基於第1PWM信號pwm1由濾波器17產生之濾波器輸出電壓V1而設定。此處，圖4係表示濾波器17之一構成例之圖。濾波器17具有電阻R17、電容器C17、分壓用之電阻R171及R172。於電阻R17之一端，連接有被施加第1PWM信號pwm1之輸入端子T171。電阻R17之另一端連接於電容器C17之一端，並且連接於產生濾波器輸出電壓V1之第1輸出端子T172。電容器C17之另一端連接於接地電位之施加端。即，低通濾波器包含電阻R17及電容器C17，使第1PWM信號pwm1通過低通濾波器後之信號成為濾波器輸出電壓V1。因此，濾波器輸出電壓V1表示第1PWM信號pwm1之接通工作週期資訊。又，圖5係表示接通時間計時器164之一構成例之圖。接通時間計時器164係具有定電流電路Ic、電容器C164及比較器CP164之所謂燈計數器。於電源電壓Vcc與接地電位之間，串聯連接有定電流電路Ic及電容器C164，其連接點連接於比較器CP164之非反相輸入端子(+)。對比較器CP164之反相輸入端子(-)施加濾波器輸出電壓V1。比較器CP164之輸出成為接通時間計時器164之輸出。當接通時間計時器164被重設時，蓄積於電容器C164之電荷被放電。繼而，利用由定電流電路Ic控制為固定之電流對電容器C164進行充電。藉由電容器C164之充電，比較器CP164之非反相輸入端子之電壓V164達到作為基準電壓之濾波器輸出電壓V1之前之時間t以下述(3)式表示。 t＝C×V1/I (3) 其中，C：電容器C164之電容、I：定電流值重設時，比較器CP164之輸出為Low，當經過上述時間t而比較器CP164之非反相輸入端子之電壓V164達到濾波器輸出電壓V1時，比較器CP164之輸出成為High。再者，最小接通時間計時器163可包含與圖5所示之構成相同之燈計數器。此時，比較器之基準電壓、定電流電路之定電流值、及電容器之電容係以上述時間t成為特定之最小接通時間之方式被適當設定。最小接通時間計時器163之輸出與接通時間計時器164之輸出被輸入至AND電路145。於藉由AND電路145而最小接通時間計時器163與接通時間計時器165之各輸出均成為High時，AND電路145之輸出成為High。即，於計測出由最小接通時間計時器163計測之特定之最小接通時間與由接通時間計時器164計測之接通時間中之較長者之時序，AND電路145之輸出成為High。因此，於接通時間短於特定之最小接通時間之情形時，會被限制為特定之最小接通時間。AND電路145相當於斷開時序決定部。 AND電路145之輸出被輸入至第1閂鎖電路141之重設端子，並且被輸入至OR電路146。對於OR電路146，亦輸入OCP部19之輸出。OR電路146之輸出被輸入至第2閂鎖電路142。未檢測出過電流之通常時，OCP部19之輸出成為Low，故而於AND電路145之輸出成為High之時序，第1閂鎖電路141與第2閂鎖電路142均被重設。斷開控制部包含OR電路146及第2閂鎖電路142。藉此，第1PWM信號pwm1與第2PWM信號pwm2均切換為低(Low)位準，藉由第2PWM信號pwm2使開關元件M1斷開，且規定接通時間。當第1PWM信號pwm1成為低(Low)位準時，最小斷開時間計時器161與1/2接通時間計時器162均被重設。最小斷開時間計時器161於被重設時開始特定之最小斷開時間(固定值)之計測。於開關元件M1斷開時，藉由差分電路11直接輸出REF端子電壓VTref，並保持輸出，但由於剛將開關元件M1斷開後開關電壓Vsw產生振鈴，故而必須確保振鈴穩定之前之時間，決定上述特定之最小斷開時間。最小斷開時間計時器可包含與圖5所示之構成相同之燈計數器。此時，比較器之基準電壓、定電流電路之定電流值、電容器之電容係以上述時間t成為特定之最小斷開時間之方式適當設定。又，1/2接通時間計時器162於被重設時，開始接通時間之50%之時間之計測。此處，於開關元件M1為接通時流向一次繞組L1之一次側電流Ip上升，當開關元件M1被設為斷開時，流向二次繞組L2之二次側電流Is產生將圈數比乘以一次側電流之峰值而得之峰值。而且，二次側電流隨著時間之經過而緩慢地減少。圖6係表示使開關元件M1斷開時之二次側電流Is之減少的情況之一例之圖。如圖6般，二次側電流Is自斷開之時間點之峰值Ispk緩慢地減少，於經過放電時間toff2時成為零。放電時間toff2之50%(1/2toff2)之時間為止之放電之放電量較平均之放電量(面積S1)多出面積S2之放電量之程度，故而可實現有效率之放電。相反，若超過放電時間toff2之50%，則效率會變差。因此，只要將放電時間(即斷開時間)延長至放電時間toff2之50%便可，但實際之放電時間toff2係依存於變壓器Tr1及負載狀況，故而難以推測。由此，於本實施形態中，作為類似於放電時間toff2之50%之標準，設為將斷開時間延長至接通時間之50%為止。具體而言，於圖4所示之濾波器17之構成中，藉由電阻值相等之電阻R171、R172將濾波器輸出電壓V1分壓並自第2輸出端子T173作為濾波器輸出電壓V2輸出。藉此，濾波器輸出電壓V2成為濾波器輸出電壓V1之50%。而且，與圖5所示之燈計數器之構成同樣地構成1/2接通時間計時器162，且施加濾波器輸出電壓V2作為比較器之基準電壓。藉此，1/2接通時間計時器162自被重設而輸出成為Low後，於計測到接通時間之50%之時間點使輸出為High。對於AND電路144，輸入最小斷開時間計時器161與1/2接通時間計時器162之各輸出。AND電路144之輸出係於最小斷開時間計時器161與1/2接通時間計時器162之各輸出均成為High時被設為High。即，特定之最小斷開時間與接通時間之50%中之較長者被選擇並設定為最小斷開時間。AND電路144相當於最小斷開時間設定部。而且，對於AND電路143，輸入FET接通觸發信號Tgon及AND電路144之輸出。藉此，於FET接通觸發信號Tgon、及AND電路144之輸出均成為High時，AND電路143之輸出被設為High。即，若FET接通觸發信號Tgon成為High之時序為經過上述所設定之最小斷開時間後，則選擇該時序，若經過上述所設定之最小斷開時間之時序較FET接通觸發信號Tgon成為High之時序更靠後，則選擇經過最小斷開時間之時序。即，斷開時間被以不短於最小斷開時間之方式進行限制。AND電路143相當於接通時序決定部。 AND電路143之輸出被輸入至第1閂鎖電路141與第2閂鎖電路142之各設定端子。由此，於AND電路143之輸出被設為High之時序，第1閂鎖電路141與第2閂鎖電路142均被設定，第1PWM信號pwm1與第2PWM信號pwm2均切換為High。藉此，開關元件M1成為接通，且被規定斷開時間。於因負載變動而導致輸出電壓Vout下降之情形時，以將上述所設定之最小斷開時間設為斷開時間之方式將閘極開關元件M1接通。此時，第1PWM信號pwm1之接通工作週期變大，藉由濾波器輸出電壓V1設定之接通時間變長。如此，藉由進行使用第1PWM信號pwm1之接通工作週期之資訊設定接通時間的適應性接通時間控制，可改善針對負載變動之應答特性。此處，圖7係表示因負載變動而導致輸出電壓Vout下降之暫態響應時之各PWM信號及各計時器輸出之一例的時序圖。再者，於圖7中，除此以外，亦表示接通時間計時器164中之比較器CP164之非反相輸入端子之電壓V164(圖5)、AND電路145、144之各輸出、及FET接通觸發信號Tgon。於時序t1，第1PWM信號pwm1與第2PWM信號pwm2均被設為High，開關元件M1被設為接通。於是，最小接通時間計時器163與接通時間計時器164均被重設，各計時器之輸出成為Low。當接通時間計時器164被重設時，電壓V164因電容器C164之放電而成為零。之後，藉由利用定電流電路Ic對電容器C164之充電，電壓V164以特定之速度上升。繼而，當藉由最小接通時間計時器163計測特定之最小接通時間時，最小接通時間計時器163之輸出被設為High(時序t2)。其後，當電壓V164達到濾波器輸出電壓V1後，藉由接通時間計時器164計測接通時間時，接通時間計時器164之輸出被設為High(時序3)。於該時序，AND電路145之輸出成為High，故而第1閂鎖電路141與第2閂鎖電路142均被重設，第1PWM信號pwm1與第2PWM信號pwm2均被設為Low，開關元件M1被設為斷開。此時，最小斷開時間計時器161與1/2接通時間計時器162均被重設，各計時器之輸出成為Low。其後，當藉由最小斷開時間計時器161計測特定之最小斷開時間時，最小斷開時間計時器161之輸出被設為High(時序t4)。其後，當藉由1/2接通時間計時器162計測接通時間之50%之時間時，1/2接通時間計時器162之輸出被設為High(時序t5)。此處，FET接通觸發信號Tgon成為High之時序先於時序t5，故而於時序t5，AND電路143之輸出成為High。藉此，第1閂鎖電路141與第2閂鎖電路142均被設定，第1PWM信號pwm1與第2PWM信號pwm2均被設為High，開關元件M1被設為接通。如此，將較特定之最小斷開時間更長之接通時間之50%之時間設定為最小斷開時間，故而與將特定之最小斷開時間設為斷開時間之情形相比，可確保放電時間，且可使暫態響應高速化。再者，上述50%之特定比率係一例，例如只要設定為20%～80%之比率，則可發揮一定之效果。又，接通時間計時器164基於表示第1PWM信號pwm1之接通工作週期資訊之濾波器輸出電壓V1及電壓V164而決定接通時間。即，作為接通時間設定部之接通時間計時器164基於開關元件M1之開關時之工作週期而設定接通時間。而且，1/2接通時間計時器162對藉由接通時間計時器164設定之接通時間之50%之時間進行計測。又，此處，使用圖8A及圖8B說明與假設僅使用最小斷開時間計時器設定最小斷開時間之實施形態之比較。圖8A係表示用於僅使用最小斷開時間計時器之比較之實施形態之各波形例的時序圖。於圖8A中，自上段起表示PWM信號、最小斷開時間計時器之輸出、一次側電流Ip、及二次側電流Is之各波形例。於圖8A中，表示PWM信號成為High而開關元件成為接通之時序t11之後，因負載變動而導致輸出電壓Vout下降之情形。於開關元件接通之期間，一次側電流Ip增加。於PWM信號成為Low而開關元件成為斷開之時序t12，最小斷開時間計時器被重設而開始計測特定之最小斷開時間。於時序t12，一次側電流Ip成為零，二次側電流Is對應於1側電流Ip之峰值而產生，之後減少。於時序t13結束計測最小斷開時間，最小斷開時間計時器之輸出成為High。此處，因輸出電壓Vout之下降導致FET接通觸發信號Tgon於時序t13之前成為High，故而於時序t13，PWM信號被設為High，開關元件成為接通。此處，二次側電流Is成為零，一次側電流Ip係相應於二次側電流Is之值而產生，之後增加。繼而，於時序t14，PWM信號被設為Low，開關元件成為斷開。此時，一次側電流Ip成為零。圖8B係與比較例之圖8A對應之本實施形態之時序圖。於圖8B中，自上段起表示第1PWM信號pwm1(及第2PWM信號pwm2)、最小斷開時間計時器161之輸出、1/2接通時間計時器162之輸出、一次側電流Ip、及二次側電流Is之各波形例。於圖8B中，於第1PWM信號pwm1被設為Low而開關元件M1成為斷開之時序t12'，最小斷開時間計時器161與1/2接通時間計時器162均被重設，各計時器開始時間計測。此處，一次側電流Ip成為零，二次側電流Is產生並於之後減少。於圖8B中，於最小斷開時間計時器161結束計測特定之最小斷開時間之時序t13'之後，1/2接通時間計時器162於時序t14'結束計測接通時間之50%。此處，因輸出電壓Vout之下降導致FET接通觸發信號Tgon於時序t14'之前成為High，故而於時序t14'，第1PWM信號pwm1被設為High，開關元件M1成為接通。此處，二次側電流Is成為零，一次側電流Ip相應於二次側電流Is之值而產生，之後增加。而且，於時序t15'，第1PWM信號pwm1被設為Low，開關元件M1成為斷開。此時，一次側電流Ip成為零。於圖8B中，與圖8A相比，於在計測較特定之最小斷開時間長之接通時間之50%之時序規定斷開時間，故而藉由確保二次側之放電時間而使二次側電流Is減少至更低之值。藉此，可使開關元件M1成為接通時所產生之一次側電流Ip之值變低，故而與圖8A中之一次側電流之自峰值Ippk1向峰值Ippk2之上升變化量相比，可抑制圖8B中之一次側電流之自峰值Ippk1'向峰值Ippk2'之上升變化量。又，可知就圖8B而言，與圖8A相比，可抑制開關週期(開關頻率)之變動。再者，與特定之最小斷開時間加以比較之時間並不限定於接通時間之固定值即特定比率(例如50%)之時間，亦可根據負載狀況而將上述特定比率控制為可變。＜關於過電流保護時之動作＞其次，使用圖9A及圖9B對本實施形態之絕緣型開關電源裝置10之過電流保護時之動作進行說明。圖9A係表示用以與本實施形態加以比較之比較例之絕緣型開關電源裝置的過電流保護時之動作之一例之時序圖。於圖9A中，於PWM信號成為High且開關元件成為接通之時序t21，一次側電流Ip開始流通並於之後上升。繼而，於偵測到一次側電流Ip產生過電流，且一次側電流Ip達到特定之OCP位準之時序t22，PWM信號被設為Low，開關元件成為斷開。此時，一次側電流Ip成為零，二次側電流Is產生並於之後減少。於時序t22，最小斷開時間計時器被重設，開始計測特定之最小斷開時間。繼而，當於時序t23結束計測最小斷開時間時，PWM信號被設為High，開關元件成為接通。此時，二次側電流Is成為零，一次側電流Ip開始流通並於之後上升。繼而，於偵測到一次側電流Ip達到OCP位準之時序t24，PWM信號被設為Low，開關元件成為斷開。此時，一次側電流Ip成為零，二次側電流Is開始流通。與此相對，於本實施形態中，作為過電流保護時之動作之一例，成為圖9B所示之時序圖。此處，如圖2所示，OCP部19係藉由偵測將開關元件M1之接通電阻值乘以一次側電流Ip之電流值所獲得之電壓值即開關電壓Vsw達到特定之參考電壓，偵測過電流。於圖9B中，於第1PWM信號pwm1及第2PWM信號pwm2成為High而開關元件成為接通之時序t21'，一次側電流Ip開始流通並於之後增加。繼而，當藉由OCP部19於時序t22'偵測一次側電流Ip之過電流時，OCP部19將High之輸出信號輸出至OR電路146(圖3)。藉此，OR電路146之輸出成為High，第2閂鎖電路142被重設，第2PWM信號pwm2被設為Low，開關元件M1成為斷開。此時，一次側電流Ip成為零，二次側電流Is開始流通並於之後減少。然而，於時序t22'，AND電路145之輸出為Low，一次側電流Ip達到OCP位準，故而第2PWM信號pwm2成為Low，但第1閂鎖電路141未被重設，第1PWM信號pwm1維持High。其後，於AND電路145之輸出成為High之時序t23'，第1閂鎖電路141被重設，第1PWM信號pwm1成為Low。此時，最小斷開時間計時器161與1/2接通時間計時器162均被重設，開始時間計測。繼而，於最小斷開時間計時器161結束計測特定之最小斷開時間之時序t24'之後，於時序t25'，1/2接通時間計時器162結束計測接通時間之50%之時間。又，此時，因過電流狀態而導致輸出電壓Vout較低，故而FET接通觸發信號Tgon已成為High。因此，於時序25'，第1閂鎖電路141與第2閂鎖電路142均被設定，第1PWM信號pwm1與第2PWM信號pwm2均被設為High。藉此，開關元件M1成為接通。此時，二次側電流Is成為零，一次側電流Ip開始流通並於之後增加。繼而，於藉由OCP部19而偵測到一次側電流Ip達到OCP位準之時序t26'，第2PWM信號pwm2被設為Low，開關元件M1成為斷開。此時，一次側電流Ip成為零，二次側電流Is開始流通並於之後減少。如此，於本實施形態中，於偵測到過電流之時序t22'使開關元件M1斷開，但於之後之時序t23'延遲地將第1PWM信號pwm1設為Low並重設最小斷開時間計時器161及1/2接通時間計時器162，故而僅於時序t22'～t23'之期間T1，二次側之放電時間延長。進而，於本實施形態中，藉由利用1/2接通時間計時器162計測較特定之最小斷開時間長之期間T2而規定斷開期間，故而放電時間進一步延長。藉此，相較比較例之圖9A所示之一次側電流Ip的開始流通之值之上升變化量ΔIp，可抑制本實施形態之圖9B所示的一次側電流Ip之開始流通之值之上升變化量ΔIp'。於圖9A中，上升變化量ΔIp變大，一次側電流Ip會立即達到OCP位準(時序t24)，故而一次側之充電時間變短，輸出電壓之上升變遲。與此相對，於圖9B中，藉由抑制上升變化量ΔIp'，使一次側電流Ip達到OCP位準之前之時間(時序t25'～t26')變長，藉此，可確保一次側之充電時間，並可加快輸出電壓Vout之上升。＜關於差分電路之輸出時序控制＞其次，對本實施形態之絕緣型開關電源裝置10中之差分電路11之輸出時序控制進行說明。如上所述，差分電路11於開關元件M1斷開時直接輸出REF端子電壓VTref，並保持輸出。於圖10中表示控制利用差分電路11之輸出時序之構成。圖10所示之計時器部16相當於時序控制部。圖10所示之計時器部16具有最小斷開時間計時器1611、1/2接通時間計時器1621、反相器166、AND電路167、屏蔽期間計時器168、及閂鎖電路169。再者，圖10所示之計時器部16係與上述圖3所示之計時器部16相同者，即，於圖3之計時器部16中省略圖10所示之構成，但實際上進而具有該構成。最小斷開時間計時器1611對最小斷開時間計時器161所計測之特定之最小斷開時間之95%的時間進行計測。1/2接通時間計時器1621與圖5所示之燈計數器同樣地構成，且施加濾波器17所輸出之輸出電壓V3作為比較器之基準電壓。輸出電壓V3係上述輸出電壓V2(圖4)之95%之電壓。藉此，1/2接通時間計時器1621對接通時間之50%之進而95%之時間進行計測。再者，關於最小斷開時間計時器1611及1/2接通時間計時器1621之稱為95%之比率係一例，只要為小於100%之比率則亦可使用其他比率(例如70%以上之比率)。對於反相器166，輸入第1閂鎖電路141輸出之第1PWM信號pwm1。最小斷開時間計時器1611、1/2接通時間計時器1621、及反相器166之各輸出被輸入至AND電路167。AND電路167之輸出被輸入至閂鎖電路169之重設端子。屏蔽期間計時器168係計測特定之屏蔽期間(例如240 nsec)。屏蔽期間計時器168之輸出被輸入至閂鎖電路169之設定端子。閂鎖電路169之輸出被設為開關時序信號SWT而輸入至差分電路11。若對此種構成之動作進行說明，則當第1PWM信號pwm1(及第2PWM信號pwm2)成為Low，開關元件M1成為斷開時，屏蔽期間計時器168被重設而開始時間計測，輸出成為Low，反相器166之輸出成為High。此時，最小斷開時間計時器1611與1/2接通時間計時器1621均被重設，開始時間計測，各計時器之輸出成為Low。再者，當各時間計測結束時，各計時器之輸出成為High。屏蔽期間計時器168於計測特定之屏蔽期間時，將輸出設為High。於是，閂鎖電路169被設定，且將開關時序信號SWT設為High。藉此，差分電路11中所包含之開關(未圖示)成為接通，差分電路11開始將REF端子電壓VTref直接輸出作為輸出VTref2之動作。其後，於藉由最小斷開時間計時器1611計測特定之最小斷開時間之95%之時序與藉由1/2接通時間計時器1621計測接通時間之50%之進而95%之時序中的較遲之時序，AND電路167成為High。於是，閂鎖電路169被重設，且將開關時序信號SWT設為Low。藉此，差分電路11中所包含之開關被設為斷開，差分電路11保持自接通至斷開之切換時序之輸出VTref2。此處，將使開關元件M1斷開時之開關電壓Vsw之波形例示於圖11。如圖11所示，於剛使開關元件M1斷開後，因變壓器Tr1之一次繞組L1所具有之漏電感，導致開關電壓Vsw產生振鈴。因此，藉由利用屏蔽期間計時器168僅對屏蔽期間Tmsk進行屏蔽，使產生振鈴期間不進行將REF端子電壓VTref直接輸出之動作。當經過屏蔽期間Tmsk時，開始將REF端子電壓VTref直接輸出之動作。其後，於經過特定之最小斷開時間之95%之時間Tmin_off與接通時間之50%之進而95%之時間T1/2on中之較長者時，進行輸出之保持(於圖11之例中T1/2on較長)。於Tmin_off較長之情形時，於經過特定之最小斷開時間之時序以後，開關元件M1被設為接通，於T1/2on較長之情形時，於經過接通時間之50%之時序以後，開關元件M1被設為接通。因此，進行輸出之保持之時序先於開關元件M1成為接通之時序，故而可於二次側電流Is流通時進行輸出之保持。即，可抑制開關元件M1成為接通之時序與保持輸出之時序重疊而導致輸出產生異常之情況。又，REF端子電壓VTref係反饋反馳電壓VOR之信號，反馳電壓VOR以上述(1)式表示。(1)式中之二極體D2之正向電壓Vf量成為誤差量，故而二次側電流Is越接近零，Vf越變小，誤差越變小。即，時間上越往後，作為保持輸出之時序越適當。於T1/2on較Tmin_off長之情形時，可將保持輸出之時序設為時間上更往後。＜與開關元件相關之變化例＞其次，對以上所說明之本實施形態之絕緣型開關電源裝置的變化例進行敍述。將變化例之絕緣型開關電源裝置10'之構成示於圖12。圖12所示之絕緣型開關電源裝置10'具備電源控制IC1'。電源控制IC1'構成為具有主開關元件M11、副開關元件M12、電阻R12、及比較器CP。再者，於電源控制IC1'中，關於除圖12所示之構成以外之構成部係與上述實施形態(圖2)相同。包含N通道MOSFET之主開關元件M11係藉由被開關驅動而有助於利用絕緣型開關電源裝置10'之輸出電壓Vout之產生的開關元件。主開關元件M11之汲極(電流流入端)連接於開關輸出端子T3，源極(電流流出端)連接於接地端子T41。副開關元件M12包含N通道MOSFET。副開關元件M12之汲極(電流流入端)經由電阻R12連接於主開關元件M11之汲極與開關輸出端子T3之連接點。副開關元件M12之源極(電流流出端)連接於接地端子T42。於主開關元件M11之閘極(控制端)，連接有未圖示之驅動器之輸出端。於比較器CP之非反相輸入端子(+)，連接有開關元件M11之閘極。對於比較器CP之反相輸入端子(-)，施加特定之閾值電壓Vth1作為基準電壓。比較器CP之輸出端連接於副開關元件M12之閘極(控制端)。比較器CP相當於電壓施加部。此處，參照圖13說明使用有主開關元件M11與副開關元件M12之構成之動作。圖13係表示使主開關元件M11斷開時之各波形之一例之時序圖。於圖13中，自上段起表示主開關元件M11之閘極電壓Vg11、副開關元件M12之閘極電壓Vg12、流經主開關元件M11之電流(汲極電流)I11、二次側電流Is、開關電壓Vsw、及流經副開關元件M12之電流(汲極電流)I12。於主開關元件M11接通(副開關元件M12斷開)時，於時序t31，為了藉由未圖示之驅動器將主開關元件M11斷開而開始自主開關元件M11之閘極電容奪取電荷。於是，主開關元件M11之閘極電壓Vg11減少。繼而，於自閘極電壓Vg11達到鏡電壓Vm後，低於鏡電壓Vm之時序t32，電流I11開始減少，開關電壓Vsw開始上升。繼而，當閘極電壓Vg11達到閾值電壓Vth1時，比較器CP之輸出成為Low(時序t33)。藉此，開始自副開關元件M12之閘極電容奪取電荷，閘極電壓Vg12開始減少。繼而，當閘極電壓Vg11達到主開關元件M11之閾值電壓Vth11時，電流I11成為零(時序t34)。於自時序t32起至閘極電壓Vg12達到副開關元件Vg12之閾值電壓Vth12之時序t35為止的期間，電流I12流經接通之副開關元件M12。於時序t35，副開關元件M12成為斷開，電流I12不再流通。因此，於自時序t32至主開關元件M11之電流I11成為零之時序t34為止的期間，主開關元件M11、副開關元件M12均為接通。繼而，自時序t34至時序t35為止之期間，主開關元件M11為斷開，副開關元件M12為接通。繼而，於時序t35之後，主開關元件M11、副開關元件M12均成為斷開。此處，變壓器Tr1之一次繞組L1具有漏電感，於開關元件接通時，電流亦流向該漏電感而蓄積能量，由於未與其他繞組結合，故而不會進行電力轉移。藉此，於假設未設置副開關元件M12之情形時，在使主開關元件M11斷開時，開關電壓Vsw產生較大且時間較長之振鈴。因此，於本實施形態中，設置副開關元件M12，並於使主開關元件M11斷開時使電流I12流向副開關元件M12，藉此，可抑制開關電壓Vsw中產生之振鈴。於圖13中表示可使於假設未設置副開關元件M12之情形時開關電壓Vsw所產生之振鈴(虛線)之峰值下降至本實施形態中實線所示之開關電壓Vsw之峰值。先前，有為了抑制振鈴而使用緩衝電路之情況，但緩衝電路對使用者而言為設計困難之電路，有當設計失敗時開關元件被破壞之虞。根據本實施形態，即便未使用此種緩衝電路亦可抑制振鈴。如上所述，比較器CP之閾值電壓Vth1係設定於主開關元件M11之鏡電壓Vm與主開關元件M11自身之閾值電壓Vth11之間，對其理由進行說明。首先，流向主開關元件M11之電流I11自閘極電壓Vg11低於鏡電壓Vm時減少，並於閘極電壓Vg11達到閾值電壓Vth11時成為零。於閾值電壓Vth1被設定為鏡電壓Vm以上之情形時，於閘極電壓Vg11成為閾值電壓Vth1～鏡電壓Vm之期間，於副開關元件M12中幾乎未流通有電流，故而該期間不發揮功能。另一方面，於將閾值電壓Vth1設定為閾值電壓Vth11以下之情形時，閘極電壓Vg12達到閾值電壓Vth12之時序會變遲，電流I12會過剩地流向副開關元件M12。因此，閾值電壓Vth1較佳為低於鏡電壓Vm，且進而設定於鏡電壓Vm與閾值電壓Vth11之間。又，設置電阻R12之目的在於限制電流I12。有於主開關元件M11接通時副開關元件M12成為接通之期間(時序t32～t34)，但於該期間，作為自開關輸出端子T3流向接地端子T41、T42之間之電流，電流流向電阻較低之主開關元件M11側，藉由電阻R12使電流幾乎不流向副開關元件M12。其原因在於，若假設使電流I12流通過多，則於使主開關元件M11斷開時，開關電壓Vsw之上升之電壓異常變低。又，於本實施形態中，主開關元件M11與副開關元件M12較佳為利用相同之步驟製造，主開關元件M11較副開關元件M12尺寸大(例如1000︰1)。由於利用相同之步驟製造，故而主開關元件M11與副開關元件M12成為相同之偏差，且具有相同之特性。因此，自閘極電壓開始下降至成為零為止(或達到開關元件之閾值電壓為止)之時間就主開關元件M11與副開關元件M12而言大致相同，得以保證於主開關元件M11之電流I11成為零時，副開關元件M12接通。又，若主開關元件M11之尺寸較大，則於常規之接通狀態下流通之電流較大，產生諧振現象之寄生電容器之電容亦變大，藉由副開關元件M12抑制振鈴之效果變大。再者，亦可代替如上述般使用比較器CP之構成，而設為使用有使施加至主開關元件M11之閘極之電壓延遲地施加至副開關元件M12之閘極的濾波器等之延遲電路之構成。例如只要於主開關元件M11之電流I11成為零之前經過延遲時間，且於主開關元件M11之電流為零時，副開關元件M12保持接通，則可抑制振鈴。＜其他＞以上，對本發明之實施形態進行了說明，但只要為本發明之主旨之範圍內，則實施形態可進行各種變化。例如電源控制IC亦可不具備開關元件，而是將開關元件設置於其外部。又，本發明之絕緣型開關電源裝置較佳為用於例如太陽能反相器、FA反相器、蓄電系統等工業設備反相器等。本申請基於日本專利特願2016-181320(2016.9.16)、日本專利特願2016-181322(2016.9.16)、日本專利特願2016-181323(2016.9.16)、日本專利特願2016-181325(2016.9.16)、及日本專利特願2016-235245(2016.12.2)。<Overall Configuration of Insulated Switching Power Supply Unit> An embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a view showing the overall configuration of an isolated switching power supply device 10 according to an embodiment of the present invention. The isolated switching power supply device 10 is a DC/DC (Direct Current-Direct Current) in which the output voltage Vout is generated from the input voltage Vin. DC-DC converter. also, The insulated switching power supply device 10 performs an adaptive on-time control as described below as a control method. The insulated switching power supply device 10 includes a power supply control IC (Integrated Circuit, Integrated circuit)1 Externally placed in the various discrete parts of the power control IC1 (transformer Tr1 Diode D2 Smoothing capacitor C2 Resistor R11, And the resistor R12). The power supply control IC 1 (power supply control device) mainly controls the main body (semiconductor device) of the overall operation of the isolated switching power supply device 10. The power supply control IC1 has a power supply terminal T1 for establishing an electrical connection with the outside. Feedback terminal T2 Switch output terminal T3, Ground terminal T4, And REF terminal T5. The input voltage Vin of the DC voltage is applied to the power terminal T1, And applied to one end of the primary winding L1 of the transformer Tr1. The other end of the primary winding L1 is connected to the feedback terminal T2 via an external resistor R11. And connected to the switch output terminal T3. One end of the secondary winding L2 of the transformer Tr1 is connected to the anode of the diode D2. Between the cathode of the diode D2 and the other end of the secondary winding L2, Connect the smoothing capacitor C2. An output voltage Vout is generated at a connection point between one end of the capacitor C2 and the cathode of the diode D2. The ground terminal T4 is connected to the application end of the ground potential. One end of the external resistor R12 is connected to the REF terminal T5. Fig. 2 is a block diagram showing the internal structure of the power supply control IC 1. The power supply control IC 1 is configured to have a differential circuit 11, Comparator 13, Logic part 14, Driver 15, Timer unit 16, Filter 17, Chop generating unit 18, OCP (overcurrent protection) 19 And switching element M1, These components are integrated into one wafer. Includes a N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) The drain of the switching element M1 of the metal oxide semiconductor field effect transistor is connected to one end of the primary winding L1 via the switching output terminal T3. The source of the switching element M1 is connected to the application end of the ground potential via the ground terminal T4. When the switching element M1 is turned on, The current flows to the primary winding L1 of the transformer Tr1, The transformer Tr1 is charged with excitation energy. at this time, The diode D2 is disconnected. Secondly, When the switching element M1 is turned off, The charged excitation energy is discharged from the secondary winding L2 of the transformer Tr1 through the diode D2. The output voltage Vout is generated by smoothing by the smoothing capacitor C2. at this time, Current flows to diode D2. When the switching element M1 is turned off, The flyback voltage VOR shown by the following formula (1) is generated in the primary winding L1. VOR=Np/Ns×(Vout+Vf) (1) where, Np: The number of turns of the primary winding L1, Ns: The number of turns of the secondary winding L2, Vf: Forward voltage of diode D2 At this time, The gate voltage of the switching element M1, that is, the switching voltage Vsw is expressed by the following formula (2). Vsw=Vin+VOR (2) The differential circuit 11 is connected to the power supply terminal T1 to which the input voltage Vin is applied. a feedback terminal T2 connected to the other end of the resistor R11 to which the switching voltage Vsw is applied at one end And a REF terminal T5 connected to one end of the resistor R12. With this, By the differential circuit 11, The voltage difference between the switching voltage Vsw and the input voltage Vin is performed by the resistor R11. Current conversion, The REF terminal voltage VTref is generated at the REF terminal T5 by the converted current and the resistor R12. which is, The REF terminal voltage VTref is generated as a feedback signal of the feedback flyback voltage VOR. The difference circuit 11 corresponds to a feedback signal output unit. The difference circuit 11 performs the following actions: When the switching element M11 is turned off, Directly output REF terminal voltage VTref as output VTref2; And maintain the output of a certain timing VTref2. The differential circuit 11 outputs the output VTref2 to the comparator 13. The comparator 13 compares the output VTref2 with a reference voltage Vref such as a triangular wave generated by the chopper generating portion 18, The FET (Field Effect Transistor, which will be the result of the comparison) The field effect transistor) turns on the trigger signal Tgon to the logic unit 14. The comparator 13 corresponds to an on-trigger signal generating unit. The logic unit 14 generates a first PWM signal pwm1 and a second PWM signal pwm2. The first PWM signal pwm1 and the second PWM signal pwm2 are pulsed signals, And the on duty cycle is basically the same. The filter 17 extracts the ON duty cycle information by filtering the first PWM signal pwm1. The filter 17 corresponds to a duty cycle information acquisition unit. The timer unit 16 and the logic unit 14 are based on the on duty cycle information from the filter 17, The period in which the switching element M1 is turned on is set as the on-time. In order to switch the switching element M1 from on to off, such as the timing of the set on-time, The logic unit 14 sets the second PWM signal pwm2 to the Low level. also, The timer unit 16 and the logic unit 14 are based on the on duty cycle information from the filter 17, The minimum off time which is the minimum value of the off time during the period in which the switching element M1 is turned off is set. In order to switch the switching element M1 from off to on based on the set minimum off time and the timing of the FET turn-on trigger signal Tgon from the comparator 13. The logic unit 14 sets the second PWM signal pwm2 to the High level. The driver 15 generates a gate voltage GT based on the second PWM signal pwm2 generated by the logic portion 14 and applies it to the gate of the switching element M1. With this, The switching element M1 is subjected to on/off control. also, The timer unit 16 generates a switching timing signal SWT indicating the on/off timing of a switch (not shown) included in the differential circuit 11, and outputs it to the differential circuit 11. When the switching timing signal SWT indicates that the switching is performed, the differential circuit 11 Directly output the REF terminal voltage Vtref as the output VTref2, When indicating a disconnection, The output VTref2 is maintained at the timing of switching from on to off. <About the on/off time setting control> Next, The control of setting the on-time/off-time of the power supply control IC 1 of the present embodiment will be described. FIG. 3 is a view showing a specific configuration example of the timer unit 16 and the logic unit 14. The timer unit 16 has a minimum off time timer 161, 1/2 on-time timer 162, Minimum on time timer 163, On time timer 164, And an inverter 165. The logic unit 14 has a first latch circuit 141, The second latch circuit 142, And (AND) circuits 143 to 145, And OR circuit 146. The first latch circuit 141 outputs the first PWM signal pwm1. The second latch circuit 142 outputs the second PWM signal pwm2 to the driver 15. The first latch circuit 141 and the second latch circuit 142 are simultaneously set by signals input to the setting terminals. And resetting substantially simultaneously (except when overcurrent detection by the OCP unit 19) by the signal input to the reset terminal, Therefore, the first PWM signal pwm1 is synchronized with the second PWM signal pwm2 and the ON duty cycle is the same. When the first latch circuit 141 is set to raise the first PWM signal pwm1 from Low to High, That is, when the switching element M1 is turned on by the second PWM signal pwm2, The output of the inverter 165 becomes Low, With this, The minimum on time timer 163 and the on time timer 164 are reset. The minimum on-time timer 163 starts the measurement of the specific minimum on-time (fixed value) when reset. Here, The specific minimum on-time is a parameter that determines the degree of over-boost of the output voltage Vout. When the on time timer 164 is reset, Start measurement of the connection time, This on-time is set by the filter output voltage V1 generated by the filter 17 based on the first PWM signal pwm1. Here, Fig. 4 is a view showing an example of the configuration of the filter 17. The filter 17 has a resistor R17, Capacitor C17, Resistors R171 and R172 for voltage division. At one end of the resistor R17, An input terminal T171 to which the first PWM signal pwm1 is applied is connected. The other end of the resistor R17 is connected to one end of the capacitor C17. And connected to the first output terminal T172 that generates the filter output voltage V1. The other end of the capacitor C17 is connected to the application end of the ground potential. which is, The low pass filter includes a resistor R17 and a capacitor C17. The signal obtained by passing the first PWM signal pwm1 through the low pass filter becomes the filter output voltage V1. therefore, The filter output voltage V1 represents the ON duty information of the first PWM signal pwm1. also, FIG. 5 is a view showing an example of the configuration of the on-time timer 164. The on-time timer 164 has a constant current circuit Ic, A so-called lamp counter of capacitor C164 and comparator CP164. Between the power supply voltage Vcc and the ground potential, A constant current circuit Ic and a capacitor C164 are connected in series, Its connection point is connected to the non-inverting input terminal (+) of the comparator CP164. A filter output voltage V1 is applied to the inverting input terminal (-) of the comparator CP164. The output of comparator CP 164 becomes the output of on time timer 164. When the on time timer 164 is reset, The charge accumulated in the capacitor C164 is discharged. Then, The capacitor C164 is charged by a current controlled to be fixed by the constant current circuit Ic. By charging the capacitor C164, The time t before the voltage V164 of the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 as the reference voltage is expressed by the following formula (3). t=C×V1/I (3) where, C: Capacitor C164 capacitance, I: When the constant current value is reset, The output of the comparator CP164 is Low, When the voltage V164 of the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 after the above time t, The output of the comparator CP164 becomes High. Furthermore, The minimum on time timer 163 may include the same lamp counter as that shown in FIG. at this time, Comparator voltage, The constant current value of the constant current circuit, The capacitance of the capacitor is appropriately set so that the time t becomes a specific minimum on-time. The output of the minimum on-time timer 163 and the output of the on-time timer 164 are input to the AND circuit 145. When the outputs of the minimum on-time counter 163 and the on-time counter 165 are both High by the AND circuit 145, The output of the AND circuit 145 becomes High. which is, The timing of the longer of the particular minimum on time measured by the minimum on time timer 163 and the on time measured by the on time timer 164 is measured, The output of the AND circuit 145 becomes High. therefore, When the on-time is shorter than the specified minimum on-time, Will be limited to a specific minimum on time. The AND circuit 145 corresponds to an off-timing determining unit. The output of the AND circuit 145 is input to the reset terminal of the first latch circuit 141, And it is input to the OR circuit 146. For the OR circuit 146, The output of the OCP section 19 is also input. The output of the OR circuit 146 is input to the second latch circuit 142. When the overcurrent is not detected, The output of the OCP unit 19 becomes Low, Therefore, the output of the AND circuit 145 becomes the timing of High, Both the first latch circuit 141 and the second latch circuit 142 are reset. The disconnection control unit includes an OR circuit 146 and a second latch circuit 142. With this, The first PWM signal pwm1 and the second PWM signal pwm2 are both switched to a low (Low) level. The switching element M1 is turned off by the second PWM signal pwm2. And the connection time is specified. When the first PWM signal pwm1 is at the Low level, Both the minimum off time timer 161 and the 1/2 on time timer 162 are reset. The minimum off time timer 161 starts the measurement of the specific minimum off time (fixed value) when reset. When the switching element M1 is turned off, Directly outputting the REF terminal voltage VTref by the differential circuit 11, And keep the output, However, since the switching voltage Vsw is ringing immediately after the switching element M1 is turned off, Therefore, it must be ensured that the time before the ringing is stabilized, Determine the specific minimum disconnection time above. The minimum off time timer may include the same lamp counter as that shown in FIG. at this time, Comparator voltage, The constant current value of the constant current circuit, The capacitance of the capacitor is appropriately set so that the time t becomes a specific minimum off time. also, When the 1/2 on-time timer 162 is reset, The measurement of the time when the connection time is 50% started. Here, When the switching element M1 is turned on, the current Ip flowing to the primary winding L1 rises, When the switching element M1 is set to off, The secondary side current Is flowing to the secondary winding L2 generates a peak obtained by multiplying the turns ratio by the peak value of the primary side current. and, The secondary current slowly decreases over time. FIG. 6 is a view showing an example of a case where the secondary side current Is is reduced when the switching element M1 is turned off. As shown in Figure 6, The peak value Ispk of the secondary side current Is from the time point of disconnection is slowly decreased, It becomes zero when the discharge time toff2 passes. The discharge amount of the discharge up to 50% (1/2toff2) of the discharge time toff2 is greater than the average discharge amount (area S1) by the discharge amount of the area S2. Therefore, efficient discharge can be achieved. in contrast, If it exceeds 50% of the discharge time toff2, Then the efficiency will be worse. therefore, As long as the discharge time (ie, the off time) is extended to 50% of the discharge time toff2, However, the actual discharge time toff2 depends on the transformer Tr1 and the load condition. Therefore, it is difficult to speculate. thus, In this embodiment, As a standard similar to 50% of the discharge time toff2, Set to extend the off time to 50% of the on time. in particular, In the configuration of the filter 17 shown in FIG. 4, Resistor R171 with equal resistance value, R172 divides the filter output voltage V1 and outputs it from the second output terminal T173 as the filter output voltage V2. With this, The filter output voltage V2 becomes 50% of the filter output voltage V1. and, The 1/2 on-time timer 162 is configured in the same manner as the configuration of the lamp counter shown in FIG. And the filter output voltage V2 is applied as the reference voltage of the comparator. With this, After the 1/2 on-time timer 162 is reset and the output is Low, The output is made High at a time point when 50% of the on-time is measured. For the AND circuit 144, The outputs of the minimum off time timer 161 and the 1/2 on time timer 162 are input. The output of the AND circuit 144 is set to High when the outputs of the minimum off time timer 161 and the 1/2 on time timer 162 are both High. which is, The longer of the specified minimum off time and 50% of the on time is selected and set to the minimum off time. The AND circuit 144 corresponds to a minimum off time setting unit. and, For the AND circuit 143, The input FET turns on the trigger signal Tgon and the output of the AND circuit 144. With this, The FET turns on the trigger signal Tgon, And when the output of the AND circuit 144 becomes High, The output of the AND circuit 143 is set to High. which is, If the timing at which the FET turn-on trigger signal Tgon becomes High is after the minimum off time set as described above, Then select the timing, If the timing of the minimum off time set by the above is later than the timing at which the FET turn-on trigger signal Tgon becomes High, Then select the timing after the minimum disconnection time. which is, The disconnection time is limited in a manner that is not shorter than the minimum disconnection time. The AND circuit 143 corresponds to an on-time determination unit. The output of the AND circuit 143 is input to each of the setting terminals of the first latch circuit 141 and the second latch circuit 142. thus, The output of the AND circuit 143 is set to the timing of High, Both the first latch circuit 141 and the second latch circuit 142 are set. Both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to High. With this, The switching element M1 is turned on. And is prescribed the disconnection time. When the output voltage Vout drops due to load fluctuations, The gate switching element M1 is turned on to set the minimum off time set as described above to the off time. at this time, The switching period of the first PWM signal pwm1 becomes larger, The on-time set by the filter output voltage V1 becomes long. in this way, By setting the adaptive on-time control of the on-time by using the information of the on-duty cycle of the first PWM signal pwm1, It can improve the response characteristics for load changes. Here, Fig. 7 is a timing chart showing an example of each PWM signal and each timer output in a transient response in which the output voltage Vout is lowered due to a load fluctuation. Furthermore, In Figure 7, Other than that, Also shown is the voltage V164 of the non-inverting input terminal of the comparator CP164 in the on-time timer 164 (Fig. 5), AND circuit 145, 144 of each output, And the FET turns on the trigger signal Tgon. At time t1, The first PWM signal pwm1 and the second PWM signal pwm2 are both set to High. The switching element M1 is set to be turned on. then, Both the minimum on time timer 163 and the on time timer 164 are reset. The output of each timer becomes Low. When the on time timer 164 is reset, Voltage V164 is zero due to discharge of capacitor C164. after that, By charging the capacitor C164 with the constant current circuit Ic, Voltage V164 rises at a particular rate. Then, When the minimum minimum on time is measured by the minimum on time timer 163, The output of the minimum on-time timer 163 is set to High (timing t2). Thereafter, When the voltage V164 reaches the filter output voltage V1, When the on time is measured by the on time timer 164, The output of the on-time timer 164 is set to High (timing 3). At this timing, The output of the AND circuit 145 becomes High, Therefore, both the first latch circuit 141 and the second latch circuit 142 are reset. The first PWM signal pwm1 and the second PWM signal pwm2 are both set to Low. The switching element M1 is set to be off. at this time, Both the minimum off time timer 161 and the 1/2 on time timer 162 are reset. The output of each timer becomes Low. Thereafter, When the minimum minimum off time is measured by the minimum off time timer 161, The output of the minimum off time timer 161 is set to High (timing t4). Thereafter, When the time of 50% of the on time is measured by the 1/2 on-time timer 162, The output of the 1/2 on-time timer 162 is set to High (timing t5). Here, The timing at which the FET turn-on trigger signal Tgon becomes High precedes the timing t5. Therefore, at time t5, The output of the AND circuit 143 becomes High. With this, Both the first latch circuit 141 and the second latch circuit 142 are set. The first PWM signal pwm1 and the second PWM signal pwm2 are both set to High. The switching element M1 is set to be turned on. in this way, Set the time to 50% of the on-time that is longer than the specified minimum disconnection time to the minimum off time. Therefore, compared with the case where the specific minimum disconnection time is set to the off time, Can ensure discharge time, Moreover, the transient response can be speeded up. Furthermore, The above specific ratio of 50% is an example. For example, if the ratio is set to 20% to 80%, It can exert a certain effect. also, The on-time timer 164 determines the on-time based on the filter output voltage V1 and the voltage V164 indicating the on-duty cycle information of the first PWM signal pwm1. which is, The on-time timer 164 as the on-time setting unit sets the on-time based on the duty cycle at the time of switching of the switching element M1. and, The 1/2 on-time timer 162 measures the time of 50% of the on-time set by the on-time timer 164. also, Here, A comparison of an embodiment in which a minimum off time is set using only a minimum off time timer will be described using FIGS. 8A and 8B. Fig. 8A is a timing chart showing an example of waveforms for an embodiment using only a comparison of the minimum off-time timer. In Figure 8A, From the last paragraph, it indicates the PWM signal, The output of the minimum off time timer, Primary side current Ip, And waveform examples of the secondary side current Is. In Figure 8A, After the timing t11 at which the PWM signal becomes High and the switching element is turned on, The output voltage Vout drops due to load fluctuations. During the period when the switching element is turned on, The primary side current Ip increases. At a timing t12 when the PWM signal becomes Low and the switching element is turned off, The minimum off time timer is reset to begin measuring a particular minimum off time. At time t12, The primary side current Ip becomes zero, The secondary side current Is is generated corresponding to the peak value of the 1-side current Ip, Then reduce. The minimum disconnection time is measured at the end of time t13, The output of the minimum off time timer becomes High. Here, The FET turn-on trigger signal Tgon becomes High before the timing t13 due to the drop in the output voltage Vout. Therefore, at time t13, The PWM signal is set to High, The switching element is turned on. Here, The secondary side current Is becomes zero, The primary side current Ip is generated corresponding to the value of the secondary side current Is, Then increase. Then, At time t14, The PWM signal is set to Low, The switching element is turned off. at this time, The primary side current Ip becomes zero. Fig. 8B is a timing chart of the embodiment corresponding to Fig. 8A of the comparative example. In Figure 8B, The first PWM signal pwm1 (and the second PWM signal pwm2) are indicated from the upper stage, The output of the minimum off time timer 161, 1/2 on time timer 162 output, Primary side current Ip, And waveform examples of the secondary side current Is. In Figure 8B, When the first PWM signal pwm1 is set to Low and the switching element M1 is turned off, the timing t12' is turned off. Both the minimum off time timer 161 and the 1/2 on time timer 162 are reset. Each timer starts time measurement. Here, The primary side current Ip becomes zero, The secondary side current Is is generated and decreases thereafter. In Figure 8B, After the minimum disconnection time timer 161 ends the timing t13' of measuring the specific minimum disconnection time, The 1/2 on-time timer 162 ends 50% of the measurement on-time at the timing t14'. Here, The FET turn-on trigger signal Tgon becomes High before the timing t14' due to the drop in the output voltage Vout. Therefore, at time t14', The first PWM signal pwm1 is set to High, The switching element M1 is turned on. Here, The secondary side current Is becomes zero, The primary side current Ip is generated corresponding to the value of the secondary side current Is, Then increase. and, At time t15', The first PWM signal pwm1 is set to Low, The switching element M1 is turned off. at this time, The primary side current Ip becomes zero. In Figure 8B, Compared with Figure 8A, The off time is specified at a timing that measures 50% of the on-time that is longer than the specified minimum disconnection time, Therefore, the secondary side current Is is reduced to a lower value by ensuring the discharge time of the secondary side. With this, The value of the primary side current Ip generated when the switching element M1 is turned on can be lowered. Therefore, compared with the amount of change in the primary side current from the peak Ippk1 to the peak Ippk2 in FIG. 8A, The amount of change in the rise of the primary side current from the peak Ippk1' to the peak Ippk2' in Fig. 8B can be suppressed. also, It can be seen that as far as Figure 8B is concerned, Compared with Figure 8A, The variation of the switching period (switching frequency) can be suppressed. Furthermore, The time to compare with the specific minimum off time is not limited to the fixed value of the on time, that is, the specific ratio (for example, 50%). The above specific ratio can also be controlled to be variable depending on the load condition. <Action on overcurrent protection> Second, The operation at the time of overcurrent protection of the isolated switching power supply device 10 of the present embodiment will be described with reference to FIGS. 9A and 9B. Fig. 9A is a timing chart showing an example of an operation at the time of overcurrent protection of the isolated switching power supply device of the comparative example which is compared with the present embodiment. In Figure 9A, At a timing t21 when the PWM signal is High and the switching element is turned on, The primary side current Ip starts to circulate and rises thereafter. Then, After detecting the primary current Ip, an overcurrent is generated. And the primary side current Ip reaches the timing T22 of the specific OCP level, The PWM signal is set to Low, The switching element is turned off. at this time, The primary side current Ip becomes zero, The secondary side current Is is generated and decreases thereafter. At time t22, The minimum disconnect time timer is reset. Start measuring the specific minimum disconnection time. Then, When the minimum disconnection time is measured at the end of the timing t23, The PWM signal is set to High, The switching element is turned on. at this time, The secondary side current Is becomes zero, The primary side current Ip starts to circulate and rises thereafter. Then, At the timing t24 at which the primary current Ip reaches the OCP level, The PWM signal is set to Low, The switching element is turned off. at this time, The primary side current Ip becomes zero, The secondary side current Is begins to circulate. in comparison, In this embodiment, As an example of the action during overcurrent protection, The timing chart shown in Fig. 9B is obtained. Here, as shown in picture 2, The OCP unit 19 achieves a specific reference voltage by detecting a voltage value obtained by multiplying the on-resistance value of the switching element M1 by the current value of the primary side current Ip, that is, the switching voltage Vsw. Detected over current. In Figure 9B, When the first PWM signal pwm1 and the second PWM signal pwm2 are High and the switching element is turned on, the timing t21' is turned on. The primary side current Ip starts to flow and increases thereafter. Then, When the overcurrent of the primary side current Ip is detected by the OCP unit 19 at the timing t22', The OCP section 19 outputs the output signal of High to the OR circuit 146 (Fig. 3). With this, The output of the OR circuit 146 becomes High, The second latch circuit 142 is reset, The second PWM signal pwm2 is set to Low, The switching element M1 is turned off. at this time, The primary side current Ip becomes zero, The secondary side current Is begins to circulate and decreases thereafter. however, At time t22', The output of the AND circuit 145 is Low, The primary current Ip reaches the OCP level. Therefore, the second PWM signal pwm2 becomes Low, However, the first latch circuit 141 is not reset. The first PWM signal pwm1 is maintained at High. Thereafter, The output of the AND circuit 145 becomes the timing t23' of High, The first latch circuit 141 is reset, The first PWM signal pwm1 becomes Low. at this time, Both the minimum off time timer 161 and the 1/2 on time timer 162 are reset. Start time measurement. Then, After the minimum disconnection time timer 161 ends the timing t24' of measuring the specific minimum disconnection time, At time t25', The 1/2 on-time timer 162 ends the time to measure 50% of the on-time. also, at this time, The output voltage Vout is low due to the overcurrent condition. Therefore, the FET turn-on trigger signal Tgon has become High. therefore, At time 25', Both the first latch circuit 141 and the second latch circuit 142 are set. Both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High. With this, The switching element M1 is turned on. at this time, The secondary side current Is becomes zero, The primary side current Ip starts to flow and increases thereafter. Then, The timing t26' at which the primary side current Ip reaches the OCP level is detected by the OCP unit 19, The second PWM signal pwm2 is set to Low, The switching element M1 is turned off. at this time, The primary side current Ip becomes zero, The secondary side current Is begins to circulate and decreases thereafter. in this way, In this embodiment, The switching element M1 is turned off at the timing t22' at which the overcurrent is detected. However, the subsequent timing t23' delays the first PWM signal pwm1 to Low and resets the minimum off time timer 161 and the 1/2 on time timer 162, Therefore, only during the period T1 of the timing t22'~t23', The discharge time on the secondary side is prolonged. and then, In this embodiment, The off period is specified by measuring the period T2 that is longer than the specific minimum off time by the 1/2 on-time timer 162, Therefore, the discharge time is further extended. With this, The amount of change in change ΔIp of the value of the initial flow of the primary side current Ip shown in FIG. 9A of the comparative example, The amount of change ΔIp' in the value of the initial flow of the primary side current Ip shown in FIG. 9B of the present embodiment can be suppressed. In Figure 9A, The amount of change in rise ΔIp becomes larger, The primary current Ip immediately reaches the OCP level (timing t24). Therefore, the charging time on the primary side becomes shorter. The rise in the output voltage becomes late. in comparison, In Figure 9B, By suppressing the amount of change ΔIp', The time until the primary side current Ip reaches the OCP level (timing t25' to t26') becomes long, With this, It can ensure the charging time of the primary side, And can accelerate the rise of the output voltage Vout. <About Output Timing Control of Differential Circuit> Second, The output timing control of the differential circuit 11 in the isolated switching power supply device 10 of the present embodiment will be described. As mentioned above, The differential circuit 11 directly outputs the REF terminal voltage VTref when the switching element M1 is turned off, And keep the output. The configuration of controlling the output timing of the differential circuit 11 is shown in FIG. The timer unit 16 shown in Fig. 10 corresponds to a timing control unit. The timer section 16 shown in FIG. 10 has a minimum off-time timer 1611. 1/2 on-time timer 1621 Inverter 166, AND circuit 167, Masking period timer 168, And a latch circuit 169. Furthermore, The timer unit 16 shown in FIG. 10 is the same as the timer unit 16 shown in FIG. 3 described above. which is, The configuration shown in FIG. 10 is omitted in the timer unit 16 of FIG. However, it actually has this configuration. The minimum off time timer 1611 measures the time of 95% of the specified minimum disconnection time measured by the minimum off time timer 161. The 1/2 on-time timer 1621 is configured in the same manner as the lamp counter shown in FIG. The output voltage V3 output from the filter 17 is applied as a reference voltage of the comparator. The output voltage V3 is a voltage of 95% of the above-mentioned output voltage V2 (Fig. 4). With this, The 1/2 on-time timer 1621 measures the time of 50% and then 95% of the on-time. Furthermore, The ratio of the minimum off time timer 1611 and the 1/2 on time timer 1621 referred to as 95% is an example. Other ratios (e.g., ratios of more than 70%) may also be used as long as the ratio is less than 100%. For inverter 166, The first PWM signal pwm1 output from the first latch circuit 141 is input. Minimum disconnection time timer 1611 1/2 on-time timer 1621 The respective outputs of the inverter 166 are input to the AND circuit 167. The output of the AND circuit 167 is input to the reset terminal of the latch circuit 169. The mask period timer 168 measures a particular mask period (eg, 240 nsec). The output of the mask period timer 168 is input to the set terminal of the latch circuit 169. The output of the latch circuit 169 is input to the differential circuit 11 as the switching timing signal SWT. If the action of this kind of composition is explained, Then, when the first PWM signal pwm1 (and the second PWM signal pwm2) become Low, When the switching element M1 is turned off, The mask period timer 168 is reset to start time measurement. The output becomes Low, The output of the inverter 166 becomes High. at this time, The minimum off time timer 1611 and the 1/2 on time timer 1621 are both reset. Start time measurement, The output of each timer becomes Low. Furthermore, When the time measurement ends, The output of each timer becomes High. The mask period timer 168 is used to measure a specific mask period. Set the output to High. then, The latch circuit 169 is set, And the switch timing signal SWT is set to High. With this, The switch (not shown) included in the difference circuit 11 is turned on. The difference circuit 11 starts the operation of directly outputting the REF terminal voltage VTref as the output VTref2. Thereafter, The timing of measuring 95% of the specific minimum off time by the minimum off time timer 1611 and the time ratio of 50% and then 95% of the on time by the 1/2 on time timer 1621 Late timing, The AND circuit 167 becomes High. then, The latch circuit 169 is reset, And the switch timing signal SWT is set to Low. With this, The switch included in the differential circuit 11 is set to be off, The differential circuit 11 maintains the output VTref2 of the switching timing from on to off. Here, A waveform of the switching voltage Vsw when the switching element M1 is turned off is exemplified in FIG. As shown in Figure 11, After the switch element M1 is disconnected, Due to the leakage inductance of the primary winding L1 of the transformer Tr1, This causes the switching voltage Vsw to ring. therefore, By masking the mask period Tmsk by using the mask period timer 168, The operation of directly outputting the REF terminal voltage VTref is not performed during the ringing period. When the mask period Tmsk is passed, Start the action of directly outputting the REF terminal voltage VTref. Thereafter, When the Tmin_off of 95% of the specified minimum disconnection time and the longer of the 50% of the on time and then 95% of the time T1/2on, The output is maintained (T1/2on is longer in the example of Fig. 11). When Tmin_off is long, After a certain minimum break time sequence, The switching element M1 is set to be turned on. When T1/2on is longer, After the time of 50% of the connection time, The switching element M1 is set to be turned on. therefore, The timing of maintaining the output is prior to the timing at which the switching element M1 is turned on. Therefore, the output can be maintained while the secondary side current Is is flowing. which is, It is possible to suppress the timing at which the switching element M1 is turned on and the timing at which the output is held overlap, and the output may be abnormal. also, The REF terminal voltage VTref is a signal for feeding back the reverse voltage VOR, The flyback voltage VOR is expressed by the above formula (1). The amount of forward voltage Vf of the diode D2 in the formula (1) becomes an error amount, Therefore, the secondary current Is is closer to zero, Vf becomes smaller, The error becomes smaller. which is, The later the time, The more appropriate the timing as the output is maintained. When T1/2on is longer than Tmin_off, The timing of keeping the output can be set to be later in time. <Modifications relating to switching elements> Secondly, A modification of the insulated switching power supply device of the present embodiment described above will be described. The configuration of the insulated switching power supply device 10' according to the modification is shown in Fig. 12. The insulated switching power supply device 10' shown in Fig. 12 is provided with a power supply control IC 1'. The power supply control IC 1 ′ is configured to have a main switching element M11, Sub-switching element M12, Resistor R12, And comparator CP. Furthermore, In the power control IC1', The components other than the configuration shown in Fig. 12 are the same as those of the above embodiment (Fig. 2). The main switching element M11 including the N-channel MOSFET is driven by the switch to facilitate the use of the switching element of the output voltage Vout of the isolated switching power supply device 10'. The drain (current inflow end) of the main switching element M11 is connected to the switch output terminal T3, The source (current outflow end) is connected to the ground terminal T41. The sub-switching element M12 includes an N-channel MOSFET. The drain (current inflow end) of the sub-switching element M12 is connected to the junction of the drain of the main switching element M11 and the switching output terminal T3 via the resistor R12. The source (current outflow end) of the sub-switching element M12 is connected to the ground terminal T42. At the gate (control terminal) of the main switching element M11, An output of a driver (not shown) is connected. In the non-inverting input terminal (+) of the comparator CP, A gate of the switching element M11 is connected. For the inverting input terminal (-) of the comparator CP, A specific threshold voltage Vth1 is applied as a reference voltage. The output of the comparator CP is connected to the gate (control terminal) of the sub-switching element M12. The comparator CP corresponds to a voltage applying unit. Here, The operation using the configuration of the main switching element M11 and the sub switching element M12 will be described with reference to FIG. Fig. 13 is a timing chart showing an example of waveforms when the main switching element M11 is turned off. In Figure 13, The gate voltage Vg11 of the main switching element M11 is indicated from the upper stage, The gate voltage Vg12 of the sub-switching element M12, Current flowing through the main switching element M11 (drain current) I11, Secondary side current Is, Switching voltage Vsw, And a current (drain current) I12 flowing through the sub-switching element M12. When the main switching element M11 is turned on (the sub-switching element M12 is turned off), At time t31, In order to turn off the main switching element M11 by a driver (not shown), the gate capacitance of the autonomous switching element M11 is started to take charge. then, The gate voltage Vg11 of the main switching element M11 is reduced. Then, After the gate voltage Vg11 reaches the mirror voltage Vm, Below the mirror voltage Vm, the timing t32, Current I11 begins to decrease, The switching voltage Vsw starts to rise. Then, When the gate voltage Vg11 reaches the threshold voltage Vth1, The output of the comparator CP becomes Low (timing t33). With this, Starting to take charge from the gate capacitance of the sub-switching element M12, The gate voltage Vg12 begins to decrease. Then, When the gate voltage Vg11 reaches the threshold voltage Vth11 of the main switching element M11, The current I11 becomes zero (timing t34). During the period from the timing t32 until the gate voltage Vg12 reaches the timing t35 of the threshold voltage Vth12 of the sub-switching element Vg12, The current I12 flows through the turned-on sub-switching element M12. At time t35, The sub-switching element M12 is turned off, Current I12 is no longer circulating. therefore, During the period from the timing t32 to the timing t34 at which the current I11 of the main switching element M11 becomes zero, Main switching element M11, The sub-switching elements M12 are all turned on. Then, During the period from time t34 to time t35, The main switching element M11 is turned off, The sub-switching element M12 is turned on. Then, After the time t35, Main switching element M11, The sub-switching elements M12 are all turned off. Here, The primary winding L1 of the transformer Tr1 has a leakage inductance, When the switching element is turned on, The current also flows to the leakage inductance to accumulate energy. Since it is not combined with other windings, Therefore, no power transfer will occur. With this, Assuming that the sub-switching element M12 is not provided, When the main switching element M11 is turned off, The switching voltage Vsw produces a large and long ringing. therefore, In this embodiment, Setting the sub-switching element M12, And causing the current I12 to flow to the sub-switching element M12 when the main switching element M11 is turned off, With this, The ringing generated in the switching voltage Vsw can be suppressed. As shown in Fig. 13, the peak value of the ringing (dashed line) generated by the switching voltage Vsw when the sub-switching element M12 is not provided is lowered to the peak value of the switching voltage Vsw indicated by the solid line in the present embodiment. previously, There is a case where a snubber circuit is used to suppress ringing, However, the snubber circuit is a circuit that is difficult for the user to design. There are flaws in the switching element when the design fails. According to this embodiment, Ringing can be suppressed even without using such a snubber circuit. As mentioned above, The threshold voltage Vth1 of the comparator CP is set between the mirror voltage Vm of the main switching element M11 and the threshold voltage Vth11 of the main switching element M11 itself. Explain the reasons for it. First of all, The current I11 flowing to the main switching element M11 decreases when the gate voltage Vg11 is lower than the mirror voltage Vm. And it becomes zero when the gate voltage Vg11 reaches the threshold voltage Vth11. When the threshold voltage Vth1 is set to be equal to or higher than the mirror voltage Vm, While the gate voltage Vg11 is at the threshold voltage Vth1 to the mirror voltage Vm, There is almost no current flowing through the sub-switching element M12. Therefore, it does not function during this period. on the other hand, When the threshold voltage Vth1 is set to be equal to or lower than the threshold voltage Vth11, The timing at which the gate voltage Vg12 reaches the threshold voltage Vth12 becomes late. The current I12 flows excessively to the sub-switching element M12. therefore, The threshold voltage Vth1 is preferably lower than the mirror voltage Vm, Further, it is set between the mirror voltage Vm and the threshold voltage Vth11. also, The purpose of setting resistor R12 is to limit current I12. When the main switching element M11 is turned on, the sub-switching element M12 is turned on (timing t32 to t34). But during this period, As the self-switching output terminal T3 flows to the ground terminal T41, The current between T42, The current flows to the side of the main switching element M11 having a lower resistance, The current hardly flows to the sub-switching element M12 by the resistor R12. The reason is that If it is assumed that the current I12 is circulated too much, Then, when the main switching element M11 is turned off, The voltage at which the switching voltage Vsw rises is abnormally low. also, In this embodiment, The main switching element M11 and the sub-switching element M12 are preferably manufactured by the same steps. The main switching element M11 is larger in size than the sub-switching element M12 (for example, 1000..1). Since it is manufactured using the same steps, Therefore, the main switching element M11 and the sub-switching element M12 have the same deviation. And have the same characteristics. therefore, The time from when the gate voltage starts to fall until it reaches zero (or reaches the threshold voltage of the switching element) is substantially the same for the main switching element M11 and the sub-switching element M12. It is ensured that when the current I11 of the main switching element M11 becomes zero, The sub-switching element M12 is turned on. also, If the size of the main switching element M11 is large, The current flowing in the normal on state is larger, The capacitance of the parasitic capacitor that generates the resonance phenomenon also becomes large, The effect of suppressing ringing by the sub-switching element M12 becomes large. Furthermore, Instead of using the composition of the comparator CP as described above, Further, a configuration is adopted in which a delay circuit that applies a voltage applied to the gate of the sub-switching element M12 with a delay applied to the gate of the main switching element M11 is used. For example, as long as the delay time elapses before the current I11 of the main switching element M11 becomes zero, And when the current of the main switching element M11 is zero, The sub-switching element M12 remains on, It can suppress ringing. <Others> Above, The embodiment of the present invention has been described. But as long as it is within the scope of the gist of the invention, The embodiment can be variously changed. For example, the power control IC may not have a switching element. Instead, the switching element is placed outside. also, The insulated switching power supply device of the present invention is preferably used for, for example, a solar inverter, FA inverter, Industrial equipment inverters such as power storage systems. This application is based on Japanese Patent Special Purpose 2016-181320 (2016. 9. 16), Japanese Patent Special Wish 2016-181322 (2016. 9. 16), Japanese Patent Special Wish 2016-181323 (2016. 9. 16), Japanese Patent Special Wish 2016-181325 (2016. 9. 16), and Japanese Patent Special Wish 2016-235245 (2016. 12. 2).

1‧‧‧電源控制IC1‧‧‧Power Control IC

1'‧‧‧電源控制IC1'‧‧‧Power Control IC

10‧‧‧絕緣型開關電源裝置10‧‧‧Insulated Switching Power Supply Unit

10'‧‧‧絕緣型開關電源裝置10'‧‧‧Insulated Switching Power Supply Unit

11‧‧‧差分電路11‧‧‧Differential circuit

13‧‧‧比較器13‧‧‧ comparator

14‧‧‧邏輯部14‧‧‧Logic Department

15‧‧‧驅動器15‧‧‧ drive

16‧‧‧計時器部16‧‧‧Timekeeping Department

17‧‧‧濾波器17‧‧‧ Filter

18‧‧‧漣波產生部18‧‧‧涟波产生部

19‧‧‧OCP部(過電流保護部)19‧‧‧OCP Department (Overcurrent Protection Department)

141‧‧‧第1閂鎖電路141‧‧‧1st latch circuit

142‧‧‧第2閂鎖電路142‧‧‧2nd latch circuit

143～145‧‧‧AND電路143～145‧‧‧AND circuit

146‧‧‧OR電路146‧‧‧OR circuit

161‧‧‧最小斷開時間計時器161‧‧‧Minimum disconnection timer

162‧‧‧1/2接通時間計時器162‧‧‧1/2 on time timer

163‧‧‧最小接通時間計時器163‧‧‧Minimum on time timer

164‧‧‧接通時間計時器164‧‧‧Connected time timer

165‧‧‧反相器165‧‧‧Inverter

166‧‧‧反相器166‧‧‧Inverter

167‧‧‧AND電路167‧‧‧AND circuit

168‧‧‧屏蔽期間計時器168‧‧‧Shielding period timer

169‧‧‧閂鎖電路169‧‧‧Latch circuit

1611‧‧‧最小斷開時間計時器1611‧‧‧Minimum disconnection timer

1621‧‧‧1/2接通時間計時器1621‧‧‧1/2 on time timer

C2‧‧‧平滑電容器C2‧‧‧Smoothing capacitor

C17‧‧‧電容器C17‧‧‧ capacitor

C164‧‧‧電容器C164‧‧‧ capacitor

CP‧‧‧比較器CP‧‧‧ comparator

CP164‧‧‧比較器CP164‧‧‧ comparator

D2‧‧‧二極體D2‧‧‧ diode

GT‧‧‧閘極電壓GT‧‧‧ gate voltage

I11‧‧‧電流(汲極電流)I11‧‧‧ Current (bump current)

I12‧‧‧電流(汲極電流)I12‧‧‧ Current (bump current)

Ic‧‧‧定電流電路Ic‧‧‧ constant current circuit

Ip‧‧‧一次側電流Ip‧‧‧ primary current

Ippk1‧‧‧峰值Peak of Ippk1‧‧

Ippk1'‧‧‧峰值Peak of Ippk1'‧‧‧

Ippk2‧‧‧峰值Peak of Ippk2‧‧

Ippk2'‧‧‧峰值Ippk2'‧‧‧ peak

Is‧‧‧二次側電流Is‧‧‧secondary current

Ispk‧‧‧峰值Ispk‧‧‧ peak

L1‧‧‧一次繞組L1‧‧‧First winding

L2‧‧‧二次繞組L2‧‧‧ secondary winding

M1‧‧‧開關元件M1‧‧‧ switching components

M11‧‧‧主開關元件M11‧‧‧ main switching element

M12‧‧‧副開關元件M12‧‧‧Sub Switch Components

PWM‧‧‧信號PWM‧‧‧ signal

pwm1‧‧‧第1PWM信號Pwm1‧‧‧1st PWM signal

pwm2‧‧‧第2PWM信號Pwm2‧‧‧2nd PWM signal

R11‧‧‧電阻R11‧‧‧ resistance

R12‧‧‧電阻R12‧‧‧ resistance

R17‧‧‧電阻R17‧‧‧resistance

R171‧‧‧電阻R171‧‧‧resistance

R172‧‧‧電阻R172‧‧‧resistance

S1‧‧‧面積S1‧‧‧ area

S2‧‧‧面積S2‧‧‧ area

SWT‧‧‧開關時序信號SWT‧‧‧Switch timing signal

t1‧‧‧時序T1‧‧‧ timing

T1‧‧‧電源端子T1‧‧‧ power terminal

t2‧‧‧時序T2‧‧‧ timing

T2‧‧‧反饋端子T2‧‧‧ feedback terminal

t3‧‧‧時序T3‧‧‧ Timing

T3‧‧‧開關輸出端子T3‧‧‧Switch output terminal

t4‧‧‧時序T4‧‧‧ Timing

T4‧‧‧接地端子T4‧‧‧ grounding terminal

t5‧‧‧時序T5‧‧‧ timing

T5‧‧‧REF端子T5‧‧‧REF terminal

t11‧‧‧時序T11‧‧‧ Timing

t11'‧‧‧時序T11'‧‧‧ Timing

t12‧‧‧時序T12‧‧‧ Timing

t12'‧‧‧時序T12'‧‧‧ Timing

t13‧‧‧時序T13‧‧‧ timing

t13'‧‧‧時序T13'‧‧‧ Timing

t14‧‧‧時序T14‧‧‧ Timing

t14'‧‧‧時序T14'‧‧‧ Timing

t15'‧‧‧時序T15'‧‧‧ Timing

t21‧‧‧時序T21‧‧‧ Timing

t21'‧‧‧時序T21'‧‧‧ Timing

t22‧‧‧時序T22‧‧‧ Timing

t22'‧‧‧時序T22'‧‧‧ Timing

t23‧‧‧時序T23‧‧‧ Timing

t23'‧‧‧時序T23'‧‧‧ Timing

t24‧‧‧時序T24‧‧‧ Timing

t24'‧‧‧時序T24'‧‧‧ Timing

t25‧‧‧時序T25‧‧‧ Timing

t25'‧‧‧時序T25'‧‧‧ Timing

t26'‧‧‧時序T26'‧‧‧ Timing

t31‧‧‧時序T31‧‧‧ Timing

t32‧‧‧時序T32‧‧‧ Timing

t33‧‧‧時序T33‧‧‧ Timing

t34‧‧‧時序T34‧‧‧ Timing

t35‧‧‧時序T35‧‧‧ Timing

T41‧‧‧接地端子T41‧‧‧ Grounding terminal

T42‧‧‧接地端子T42‧‧‧ Grounding terminal

T171‧‧‧輸入端子T171‧‧‧ input terminal

T172‧‧‧第1輸出端子T172‧‧‧1st output terminal

T173‧‧‧第2輸出端子T173‧‧‧2nd output terminal

T1/2on‧‧‧時間T1/2on‧‧‧ time

Tgon‧‧‧FET接通觸發信號Tgon‧‧‧FET turn-on trigger signal

Tmin_off‧‧‧時間Tmin_off‧‧‧Time

Tmsk‧‧‧屏蔽期間Tmsk‧‧‧Shielding period

toff2‧‧‧放電時間Toff2‧‧‧discharge time

Tr1‧‧‧變壓器Tr1‧‧‧Transformer

V1‧‧‧濾波器輸出電壓V1‧‧‧Filter output voltage

V2‧‧‧濾波器輸出電壓V2‧‧‧Filter output voltage

V3‧‧‧輸出電壓V3‧‧‧ output voltage

V164‧‧‧(非反相輸入端子之)電壓V164‧‧‧ (non-inverting input terminal) voltage

Vcc‧‧‧電源電壓Vcc‧‧‧Power supply voltage

Vg11‧‧‧閘極電壓Vg11‧‧‧ gate voltage

Vg12‧‧‧閘極電壓Vg12‧‧‧ gate voltage

Vin‧‧‧輸入電壓Vin‧‧‧Input voltage

Vm‧‧‧鏡電壓Vm‧‧‧ mirror voltage

Vout‧‧‧輸出電壓Vout‧‧‧ output voltage

Vref‧‧‧基準電壓Vref‧‧‧ reference voltage

Vsw‧‧‧開關電壓Vsw‧‧‧Switching voltage

Vth1‧‧‧閾值電壓Vth1‧‧‧ threshold voltage

Vth11‧‧‧閾值電壓Vth11‧‧‧ threshold voltage

Vth12‧‧‧閾值電壓Vth12‧‧‧ threshold voltage

VTref‧‧‧REF端子電壓VTref‧‧‧REF terminal voltage

VTref2‧‧‧輸出VTref2‧‧‧ output

ΔIp‧‧‧上升變化量ΔIp‧‧‧ rising change

ΔIp'‧‧‧上升變化量ΔIp'‧‧‧ rising change

圖1係本發明之一實施形態之絕緣型開關電源裝置的整體構成圖。圖2係表示本發明之一實施形態之電源控制IC之內部構成的方塊圖。圖3係表示計時器部及邏輯部之具體之一構成例之圖。圖4係表示濾波器之一構成例之圖。圖5係表示接通時間計時器之一構成例之圖。圖6係表示使開關元件斷開時之二次側電流之減少的情況之一例之圖。圖7係表示因負載變動而導致輸出電壓下降之暫態響應時之各PWM信號及各計時器輸出之一例的時序圖。圖8A係表示僅使用最小斷開時間計時器之比較例之各波形例之時序圖。圖8B係與比較例之圖8A對應之本發明之實施形態的時序圖。圖9A係表示比較例之絕緣型開關電源裝置中之過電流保護時的動作之一例之時序圖。圖9B係表示本發明之實施形態之絕緣型開關電源裝置中之過電流保護時的動作之一例之時序圖。圖10係表示控制差分電路之輸出時序之構成之圖。圖11係表示使開關元件斷開時之開關電壓之波形例之圖。圖12係本發明之變化例之絕緣型開關電源裝置之整體構成圖。圖13係表示於本發明之變化例之絕緣型開關電源裝置中，使主開關元件斷開時之各波形之一例之時序圖。Fig. 1 is a view showing the overall configuration of an insulated switching power supply device according to an embodiment of the present invention. Fig. 2 is a block diagram showing the internal configuration of a power supply control IC according to an embodiment of the present invention. 3 is a view showing a specific configuration example of a timer unit and a logic unit. Fig. 4 is a view showing an example of the configuration of a filter. Fig. 5 is a view showing an example of the configuration of an on-time timer. Fig. 6 is a view showing an example of a case where the secondary current is reduced when the switching element is turned off. Fig. 7 is a timing chart showing an example of each PWM signal and each timer output in the transient response in which the output voltage is lowered due to a load fluctuation. Fig. 8A is a timing chart showing an example of waveforms of a comparative example using only a minimum off-time timer. Fig. 8B is a timing chart showing an embodiment of the present invention corresponding to Fig. 8A of the comparative example. Fig. 9A is a timing chart showing an example of an operation at the time of overcurrent protection in the insulated switching power supply device of the comparative example. Fig. 9B is a timing chart showing an example of an operation at the time of overcurrent protection in the insulated switching power supply device according to the embodiment of the present invention. Fig. 10 is a view showing the configuration of the output timing of the control differential circuit. Fig. 11 is a view showing an example of a waveform of a switching voltage when the switching element is turned off. Fig. 12 is a view showing the overall configuration of an insulated switching power supply device according to a variation of the present invention. Fig. 13 is a timing chart showing an example of waveforms when the main switching element is turned off in the insulated switching power supply device according to the modification of the present invention.

Claims

一種電源控制裝置，其係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其計測基於接通時間之時間；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；及接通時序決定部，其基於上述設定之最小斷開時間及上述接通觸發信號而決定使上述開關元件接通之時序。A power supply control device for use in an inversion-type switching power supply device of a reverse mode, the insulated switching power supply device of the reverse mode having a transformer including a primary winding and a secondary winding, and a switching element, and the primary winding One end is connected to the application end of the input voltage, and the other end of the primary winding is connected to the switching element; and the power control device includes: an on trigger signal generating unit that generates the switching element based on a feedback signal of the feedback flyback voltage a turn-on trigger signal; a first timer that measures a specific minimum off time; a second timer that measures a time based on an on time; and a minimum off time setting unit that compares the first time The specific minimum off time measured by the device and the time measured by the second timer are set to be the minimum off time; and the on timing determining unit is based on the set minimum off time and the connection The timing at which the switching element is turned on is determined by a trigger signal.

如請求項1之電源控制裝置，其中上述第2計時器計測上述接通時間之特定比率之時間。The power control device of claim 1, wherein the second timer measures a time of a specific ratio of the on-times.

如請求項1之電源控制裝置，其中上述特定比率為20%～80%。The power control device of claim 1, wherein the specific ratio is 20% to 80%.

如請求項3之電源控制裝置，其中上述特定比率為50%。The power control device of claim 3, wherein the specific ratio is 50%.

如請求項1之電源控制裝置，其進而具備：工作週期資訊獲取部，其基於與上述開關元件之PWM驅動對應之PWM信號而獲取工作週期資訊；第3計時器，其基於上述獲取之工作週期資訊計測接通時間；及斷開時序決定部，其基於由上述第3計時器計測之上述接通時間，決定使上述開關元件斷開之時序；且上述第2計時器基於上述工作週期資訊而計測時間。The power control device of claim 1, further comprising: a duty cycle information acquisition unit that acquires duty cycle information based on a PWM signal corresponding to PWM driving of the switching element; and a third timer that is based on the acquired duty cycle And an off-timing determining unit that determines a timing at which the switching element is turned off based on the on-time measured by the third timer; and the second timer is based on the duty cycle information Measuring time.

如請求項5之電源控制裝置，其中上述工作週期資訊獲取部係被輸入上述PWM信號之低通濾波器，獲取上述工作週期資訊作為上述低通濾波器之輸出電壓。The power supply control device of claim 5, wherein the duty cycle information acquisition unit is configured to input a low pass filter of the PWM signal to obtain the duty cycle information as an output voltage of the low pass filter.

如請求項6之電源控制裝置，其中上述第2計時器及上述第3計時器各自具有電容器、向上述電容器充入電荷之定電流電路、及被輸入上述電容器之電壓與基準電壓之比較器，上述低通濾波器之輸出電壓成為上述第3計時器之上述基準電壓，上述低通濾波器之輸出電壓之特定比率之電壓成為上述第2計時器之上述基準電壓。The power supply control device according to claim 6, wherein each of the second timer and the third timer has a capacitor, a constant current circuit that charges the capacitor, and a comparator that inputs a voltage between the capacitor and a reference voltage, The output voltage of the low-pass filter is the reference voltage of the third timer, and the voltage of a specific ratio of the output voltage of the low-pass filter is the reference voltage of the second timer.

如請求項1之電源控制裝置，其中上述最小斷開時間設定部係AND電路。The power control device of claim 1, wherein the minimum off-time setting unit is an AND circuit.

如請求項1之電源控制裝置，其中上述接通時序決定部係AND電路。The power supply control device of claim 1, wherein the on-time determining unit is an AND circuit.

一種絕緣型開關電源裝置，其特徵在於具有如請求項1之電源控制裝置、開關元件、及變壓器。An insulated switching power supply device characterized by having the power supply control device, the switching element, and the transformer of claim 1.

一種電源控制裝置，其係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：接通時間設定部，其基於上述開關元件之開關時之工作週期而設定接通時間；接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其對基於由上述接通時間設定部設定之接通時間之時間進行計測；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；及接通時序決定部，其基於上述設定之最小斷開時間及上述接通觸發信號而決定使上述開關元件接通之時序。A power supply control device for use in an inversion-type switching power supply device of a reverse mode, the insulated switching power supply device of the reverse mode having a transformer including a primary winding and a secondary winding, and a switching element, and the primary winding One end is connected to the application end of the input voltage, and the other end of the primary winding is connected to the switching element; and the power control device includes: an on-time setting unit that sets an on-time based on a duty cycle of switching of the switching element a turn-on trigger signal generating unit that generates an on-trigger signal for turning on the switching element based on a feedback signal of the feedback flyback voltage; a first timer that measures a specific minimum off time; and a second timer, The measurement is based on the time of the on-time set by the on-time setting unit, and the minimum off-time setting unit compares the specific minimum off-time measured by the first timer with the second time The time for measuring the device, the longer one is set as the minimum off time; and the on timing determination unit is based on the above The predetermined minimum off time and the on-timing of the trigger signal is determined so that the switching element is turned on it.

一種絕緣型開關電源裝置，其特徵在於具有如請求項11之電源控制裝置、開關元件、及變壓器。An insulated switching power supply device characterized by having the power supply control device, the switching element, and the transformer of claim 11.

一種電源控制裝置，其係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備： OCP部(過電流保護部)，其偵測一次側電流之過電流；斷開控制部，其於偵測到上述過電流時，使上述開關元件斷開；第1計時器，其於自藉由上述斷開控制部斷開起經延遲之時序，計測特定之最小斷開時間；接通觸發信號產生部，其基於反饋反馳電壓之反饋信號而產生使上述開關元件接通之接通觸發信號；及接通時序決定部，其基於上述計測出之最小斷開時間與上述接通觸發信號而決定使上述開關元件接通之時序。A power supply control device for use in an inversion-type switching power supply device of a reverse mode, the insulated switching power supply device of the reverse mode having a transformer including a primary winding and a secondary winding, and a switching element, and the primary winding One end is connected to the application end of the input voltage, and the switching element is connected to the other end of the primary winding; and the power control device includes: an OCP unit (overcurrent protection unit) that detects an overcurrent of the primary side current; a portion that turns off the switching element when the overcurrent is detected; and a first timer that measures a specific minimum off time at a timing delayed by the disconnection of the off control unit; a turn-on trigger signal generating unit that generates an turn-on trigger signal for turning on the switching element based on a feedback signal of the feedback flyback voltage; and an on-time determining unit that is based on the measured minimum off time and the connection The timing at which the switching element is turned on is determined by a trigger signal.

如請求項13之電源控制裝置，其進而具備：第2計時器，其於與上述第1計時器相同之時序開始計測接通時間之特定比率之時間；及最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；且上述接通時序決定部基於上述設定之最小斷開時間與上述接通觸發信號而決定使上述開關元件接通之時序。The power supply control device of claim 13, further comprising: a second timer that starts measuring a specific ratio of the on-time at the same timing as the first timer; and a minimum off-time setting unit The specific minimum off time measured by the first timer and the time measured by the second timer are set to be the minimum off time; and the on timing determining unit is based on the set minimum disconnection The timing at which the switching element is turned on is determined by the time and the above-described turn-on trigger signal.

如請求項14之電源控制裝置，其中上述特定比率為20%～80%。The power control device of claim 14, wherein the specific ratio is 20% to 80%.

如請求項15之電源控制裝置，其中上述特定比率為50%。The power control device of claim 15, wherein the specific ratio is 50%.

如請求項14之電源控制裝置，其中上述最小斷開時間設定部係AND電路。The power control device of claim 14, wherein the minimum off time setting unit is an AND circuit.

如請求項13之電源控制裝置，其中上述接通時序決定部係AND電路。The power supply control device of claim 13, wherein the on-time determining unit is an AND circuit.

如請求項13之電源控制裝置，其進而具備：第3計時器，其計測接通時間；第1閂鎖電路，其被輸入上述第3計時器之輸出； OR電路，其被輸入上述OCP部之輸出與上述第3計時器之輸出；及第2閂鎖電路，其被輸入上述OR電路之輸出；且上述斷開控制部包含上述OR電路及上述第2閂鎖電路；自上述第2閂鎖電路輸出之第2PWM信號被輸入至驅動上述開關元件之驅動器，自上述第1閂鎖電路輸出之第1PWM信號被輸入至上述第1計時器，上述接通時序決定部之輸出被輸入至上述第1閂鎖電路及上述第2閂鎖電路。The power supply control device of claim 13, further comprising: a third timer that measures an on-time; a first latch circuit that receives an output of the third timer; and an OR circuit that is input to the OCP unit And an output of the third timer; and a second latch circuit input to the output of the OR circuit; and the off control unit includes the OR circuit and the second latch circuit; The second PWM signal output from the lock circuit is input to the driver that drives the switching element, and the first PWM signal output from the first latch circuit is input to the first timer, and the output of the turn-on timing determining unit is input to the above The first latch circuit and the second latch circuit.

一種絕緣型開關電源裝置，其特徵在於具有如請求項13之電源控制裝置、開關元件、及變壓器。An insulated switching power supply device characterized by having the power supply control device, the switching element, and the transformer of claim 13.

一種電源控制裝置，其係使用於反馳方式之絕緣型開關電源裝置者，該反馳方式之絕緣型開關電源裝置具有包含一次繞組及二次繞組之變壓器、及開關元件，且於上述一次繞組之一端連接輸入電壓之施加端，於上述一次繞組之另一端連接上述開關元件；且上述電源控制裝置具備：反饋信號輸出部，其產生、輸出反饋反馳電壓之反饋信號；接通觸發信號產生部，其基於上述反饋信號輸出部之輸出而產生使上述開關元件接通之接通觸發信號；第1計時器，其計測特定之最小斷開時間；第2計時器，其對接通時間之第1特定比率之時間進行計測；最小斷開時間設定部，其比較由上述第1計時器計測之上述特定之最小斷開時間與由上述第2計時器計測之時間，將較長者設定為最小斷開時間；接通時序決定部，其基於上述設定之最小斷開時間及上述接通觸發信號而決定使上述開關元件接通之時序；及時序控制部，其控制上述反饋信號輸出部之輸出時序；且上述時序控制部係以如下方式進行控制：自上述開關元件成為斷開起，直到經過將上述特定之最小斷開時間之第2特定比率的時間、與上述接通時間之第1特定比率之時間之進而第3特定比率的時間加以比較而為較長之時間之時序為止，輸出上述反饋信號，且於該時序保持輸出。A power supply control device for use in an inversion-type switching power supply device of a reverse mode, the insulated switching power supply device of the reverse mode having a transformer including a primary winding and a secondary winding, and a switching element, and the primary winding One end is connected to the application end of the input voltage, and the other end of the primary winding is connected to the switching element; and the power control device includes: a feedback signal output unit that generates and outputs a feedback signal for feedback of the reverse voltage; a second trigger generating a turn-on trigger signal for turning on the switching element based on an output of the feedback signal output unit; a first timer for measuring a specific minimum off time; and a second timer for a turn-on time The first specific ratio is measured; the minimum off time setting unit compares the specific minimum off time measured by the first timer with the time measured by the second timer, and sets the longer one to the minimum a turn-off time; an on-time determination unit that is based on the set minimum off time and the above-mentioned turn-on trigger signal And determining a timing at which the switching element is turned on; and a timing control unit that controls an output timing of the feedback signal output unit; and the timing control unit controls the switching element to be turned off from the switching element until after Comparing the time of the second specific ratio of the specific minimum disconnection time with the time of the third specific ratio of the first specific ratio of the on-time, and the time of the third specific ratio, and outputting the above-mentioned time The feedback signal is held at this timing.

如請求項21之電源控制裝置，其中上述第2特定比率與上述第3特定比率小於100%。The power control device of claim 21, wherein the second specific ratio and the third specific ratio are less than 100%.

如請求項21之電源控制裝置，其中上述第1特定比率為20%～80%。The power control device of claim 21, wherein the first specific ratio is 20% to 80%.

如請求項23之電源控制裝置，其中上述第1特定比率為50%。The power control device of claim 23, wherein the first specific ratio is 50%.

如請求項21之電源控制裝置，其中上述時序控制部具有：第3計時器，其對上述特定之最小斷開時間之第2特定比率的時間進行計測；第4計時器，其對上述接通時間之第1特定比率之時間的進而第3特定比率之時間進行計測 AND電路，其被輸入上述第3計時器與上述第4計時器之各輸出；及閂鎖電路，其被輸入上述AND電路之輸出。The power supply control device of claim 21, wherein the timing control unit includes: a third timer that measures a time of a second specific ratio of the specific minimum off time; and a fourth timer that turns on the The measurement AND circuit is input to each of the third timer and the fourth timer, and the latch circuit is input to the AND circuit. The output.

如請求項25之電源控制裝置，其中上述第3計時器與上述第4計時器係藉由與上述開關元件之PWM驅動對應之PWM信號予以重設。The power control device of claim 25, wherein the third timer and the fourth timer are reset by a PWM signal corresponding to PWM driving of the switching element.

如請求項26之電源控制裝置，其中上述時序控制部具有反相器，該反相器被輸入上述PWM信號，且其輸出被輸入至上述AND電路。A power supply control device according to claim 26, wherein said timing control portion has an inverter, said inverter is input with said PWM signal, and an output thereof is input to said AND circuit.

如請求項21之電源控制裝置，其中上述時序控制部係控制自上述開關元件成為斷開起經過特定之屏蔽期間之時序開始上述反饋信號之輸出。The power supply control device of claim 21, wherein the timing control unit controls the output of the feedback signal from a timing at which the switching element is turned off and after a specific mask period.

一種絕緣型開關電源裝置，其特徵在於具有如請求項21之電源控制裝置、開關元件、及變壓器。An insulated switching power supply device characterized by having the power supply control device, the switching element, and the transformer of claim 21.

一種絕緣型開關電源裝置，其具備：變壓器，其包含一端連接輸入電壓之施加端之一次繞組、及二次繞組；主開關元件，其電流流入端連接於上述一次繞組之另一端；副開關元件，其電流流入端連接於上述主開關元件之上述電流流入端；及電壓施加部，其對上述副開關元件之控制端施加電壓，而依序轉變為上述主開關元件與上述副開關元件均成為接通之狀態、上述主開關元件成為斷開且上述副開關元件成為接通之狀態、上述主開關元件與上述副開關元件均成為斷開之狀態。An insulated switching power supply device comprising: a transformer comprising a primary winding having one end connected to an application end of an input voltage, and a secondary winding; a main switching element having a current inflow end connected to the other end of the primary winding; a current inflow end connected to the current inflow end of the main switching element, and a voltage applying unit that applies a voltage to the control terminal of the sub switching element, and sequentially changes to the main switching element and the sub switching element. In a state in which the main switching element is turned off and the sub-switching element is turned on, the main switching element and the sub-switching element are both turned off.

如請求項30之絕緣型開關電源裝置，其中上述電壓施加部為比較器，於上述比較器之一輸入端，連接上述主開關元件之控制端，對上述比較器之另一輸入端施加閾值電壓作為基準電壓，上述比較器之輸出端連接於上述副開關元件之控制端。The insulated switching power supply device of claim 30, wherein the voltage applying portion is a comparator, and at one input end of the comparator, a control terminal of the main switching element is connected, and a threshold voltage is applied to the other input end of the comparator. As a reference voltage, an output end of the comparator is connected to a control terminal of the sub-switching element.

如請求項31之絕緣型開關電源裝置，其中將上述閾值電壓設定為低於上述主開關元件之鏡電壓之值。An insulated switching power supply device according to claim 31, wherein said threshold voltage is set to be lower than a value of a mirror voltage of said main switching element.

如請求項32之絕緣型開關電源裝置，其中將上述閾值電壓設定於上述鏡電壓與上述主開關元件自身之閾值電壓之間。The insulated switching power supply device of claim 32, wherein the threshold voltage is set between the mirror voltage and a threshold voltage of the main switching element itself.

如請求項30之絕緣型開關電源裝置，其中上述電壓施加部係使對上述主開關元件之控制端施加之電壓延遲而施加於上述副開關元件之控制端的濾波器。The insulated switching power supply device according to claim 30, wherein the voltage applying unit applies a filter applied to the control terminal of the sub-switching element by delaying a voltage applied to a control terminal of the main switching element.

如請求項30之絕緣型開關電源裝置，其中上述副開關元件之電流流入端經由電阻元件連接於上述主開關元件之電流流入端。An insulated switching power supply device according to claim 30, wherein a current inflow end of said sub-switching element is connected to a current inflow terminal of said main switching element via a resistive element.

如請求項30之絕緣型開關電源裝置，其中上述主開關元件與上述副開關元件係以相同之步驟製造者。An insulated switching power supply device according to claim 30, wherein said main switching element and said sub-switching element are manufactured in the same steps.

如請求項30之絕緣型開關電源裝置，其中上述主開關元件之尺寸大於上述副開關元件。An insulated switching power supply device according to claim 30, wherein said main switching element has a size larger than said sub-switching element.

一種電源控制裝置，其係使用於絕緣型開關電源裝置者，該絕緣型開關電源裝置具備包含一端連接輸入電壓之施加端之一次繞組、及二次繞組之變壓器；且該電源控制裝置具備：主開關元件，其電流流入端連接於上述一次繞組之另一端；副開關元件，其電流流入端連接於上述主開關元件之上述電流流入端；及電壓施加部，其以上述副開關元件較上述主開關元件更遲地成為斷開之方式，對上述副開關元件之控制端施加電壓。A power supply control device for use in an insulated switching power supply device comprising: a primary winding having one end connected to an application end of an input voltage, and a secondary winding transformer; and the power control device includes: a switching element having a current inflow end connected to the other end of the primary winding; a sub-switching element having a current inflow end connected to the current inflow end of the main switching element; and a voltage applying unit having the sub-switching element being the main The switching element is turned off later, and a voltage is applied to the control terminal of the sub-switching element.

如請求項38之電源控制裝置，其進而具備電阻元件，該電阻元件連接於上述主開關元件之電流流入端與上述副開關元件之電流流入端之間。The power supply control device of claim 38, further comprising a resistive element connected between the current inflow end of the main switching element and the current inflow end of the sub-switch element.