TW201709328A - 系統級封裝及其製造方法 - Google Patents

系統級封裝及其製造方法 Download PDF

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Publication number
TW201709328A
TW201709328A TW104138898A TW104138898A TW201709328A TW 201709328 A TW201709328 A TW 201709328A TW 104138898 A TW104138898 A TW 104138898A TW 104138898 A TW104138898 A TW 104138898A TW 201709328 A TW201709328 A TW 201709328A
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Taiwan
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semiconductor wafer
lead frame
package
fan
metal pattern
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TW104138898A
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English (en)
Inventor
李俊奎
權容台
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Ｎｅｐｅｓ股份有限公司
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Publication of TW201709328A publication Critical patent/TW201709328A/zh

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Abstract

在此揭露的系統級封裝及其製造方法。系統級封裝包括：包括複數個接合墊的一第一半導體晶片、佈置為環繞該第一半導體晶片且設有複數個訊號引線的一引線框、設置在該第一半導體晶片的一上側並藉由引線接合連接到該引線框的一第二半導體晶片，以及佈置在該第一半導體晶片與該引線框的一下側的一扇出金屬圖案，該扇出金屬圖案電性連接該些接合墊與該些訊號引線，並且設置有複數個金屬墊。

Description

系統級封裝及其製造方法 參照相關申請
本申請主張韓國專利申請案No.2015-047466的權益，該專利申請案為2015年4月03日在韓國智財局提申，其揭露的內容在此引用作為參考。
本揭露的實施例是關於系統級封裝及其製造方法，更具體地說，為引線接合型的系統級封裝及其製造方法，其中該引線接合型的系統級封裝的扇出(fan out)金屬圖案經由一個簡單的製程形成。
近年來，關於半導體元件，由於加工技術的微細化與功能的多樣化，晶片的尺寸被微小化並增加了輸入/輸出端子的數目，使得電極墊的間距越來越小。另外，由於各種功能的加速融合，系統級的封裝技術逐漸增多，其是複數個元件被整合在單一封裝中。系統級封裝技術已變為一個三維堆疊技術，其可保持較短的訊號長度，以最小化操作之間的雜訊並改善訊號的速度。另一方面，由於改良這些技術、高生產效率以及製造成本降低等等的需求，用以控制產品價格的上升幅度， 已導入藉由堆疊複數個半導體晶片所構成的堆疊型封裝，例如多晶片封裝(MCP)，其中複數個晶片被堆疊在單一的半導體封裝裡，以及系統級封裝(SiP)，其中堆疊的異構(heterogeneous)晶片在單個系統中進行操作。
然而，在使用半導體晶片的半導體封裝製程中，在半導體晶片中以小間隙形成的接合墊可能需要廣泛地擴展，以被安裝到大尺寸的外部連接端子(例如為焊球與凸塊)。
為了滿足這些需求，已導入能有效地擴大接合墊(包括在半導體晶片中的)的配置的半導體封裝的扇出。同時，在半導體封裝中的扇出結構，是指其中連接到接合墊的路徑重建圖案被重新配置以被擴張的比半導體晶片本身更寬的結構，且扇入(fan in)結構是指接合墊被重新排列在半導體晶片的尺寸範圍內的結構。
相關前案文獻
美國專利申請案No.2009/261,462 A1.
因此，本揭露的一個樣態是提供在半導體晶片下具有扇放金屬圖案的系統級封裝(其中，透過堆疊複數個晶片，系統級封裝作為一個單獨的系統)，以及系統級封裝的製造方法，其能透過簡化的製程降低製造成本。
本揭露的另外的樣態將在隨後的說明中逐步列舉闡述，並且將逐步從說明中顯而易見，或可透過本揭露的實踐而得知。
根據本揭露的一樣態，系統級封裝包括一第一半 導體晶片、一引線框、一第二半導體晶片，以及一扇出金屬圖案。該第一半導體晶片可包括複數個接合墊。該引線框可被佈置為圍繞該第一半導體晶片，並且該引線框可包括複數個訊號引線。該第二半導體晶片可被佈置在該第一半導體晶片的一上側，且可藉由引線接合連接到該引線框。該扇出金屬圖案可被佈置在該第一半導體晶片與該引線框的一下側，以電性連接的該些接合墊與該些訊號引線，並且該扇出金屬圖案可包括複數個金屬墊。
系統級封裝更包括設置在該第一半導體晶片與該引線框的一下側的一絕緣層。
該絕緣層的一部分可被蝕刻以暴露該接合墊與該引線框，且該扇出金屬圖案可設置在該絕緣層的一下側以連接該些接合墊與該些訊號引線。
系統級封裝更包括設置在該第一半導體晶片與該第二半導體晶片之間的一接合層。
該接合層可包括一環氧樹脂。
系統級封裝更包括設置在該些金屬墊的一下側的一導電連接終端，以電性連接到該扇出金屬圖案。
該導電連接終端可為一焊球或一焊料凸塊。
系統級封裝更包括裝配為覆蓋該第一半導體晶片、該第二半導體晶片以及該引線框的一密封層。
該密封層可包括一環氧樹脂。
該第一半導體晶片或該第二半導體晶片可包括一記憶體晶片或配置為控制該記憶體晶片的一邏輯晶片。
該記憶體晶片可以是一動態隨機存取記憶體(DRAM)、一靜態隨機存取記憶體(SRAM)、一快閃記憶體、一相變隨機存取記憶體(PRAM)、一電阻式隨機存取記憶體(ReRAM)、一鐵電隨機存取記憶體(FeRAM)或一磁阻式隨機存取記憶體(MRAM)。
根據本揭露的另一樣態，一種製造系統級封裝的方法包括：在一基底上，形成包括複數個接合墊的一第一半導體晶片、以及形成為環繞該第一半導體晶片且設有複數個訊號引線的一第二半導體晶片，接合一第二半導體晶片到該第一半導體晶片的一上側，在該第二半導體晶片與該引線框之間進行引線接合，從該第一半導體晶片與該引線框分離該基底，以及形成一扇出金屬圖案，其被配置為電性連接該些接合墊與該些訊號引線，並且，其在該第一半導體晶片與該引線框的一下側設置有複數個金屬墊。
一接合層可形成在該第一半導體晶片與該第二半導體晶片之間。
該方法更包括：在形成該扇出金屬圖案之前，形成一第一絕緣層且藉由蝕刻該第一絕緣層的一部分暴露該些接合墊與該些訊號引線。
該方法更包括：在形成該扇出金屬圖案之後，形成構造為覆蓋該扇出金屬圖案的一第二絕緣層，藉由蝕刻該第二絕緣層的一部分暴露該些金屬墊，並且在該些暴露的金屬墊的一下側形成一導電連接終端，該導電連接終端被配置為電性連接到該扇出金屬圖案。
該方法更包括：該第一半導體晶片與該引線框由該基底分離之前，形成構造為覆蓋該第一半導體晶片、該第二半導體晶片以及該引線框的一密封層。
10‧‧‧基底
100‧‧‧系統級封裝
110‧‧‧第一半導體晶片
111‧‧‧接合墊
120‧‧‧引線框
121‧‧‧訊號引線
130‧‧‧第二半導體晶片
131‧‧‧導線
140‧‧‧扇出金屬圖案
150‧‧‧絕緣層
151‧‧‧第一絕緣層
152‧‧‧第二絕緣層
160‧‧‧導電連接終端
170‧‧‧密封層
180‧‧‧接合層
從下列實施例的說明，本揭露的這些與/或其它樣態將變得更顯而易見與更容易理解，並結合附圖說明：圖1繪示根據本揭露第一實施例的引線接合型的系統級封裝的透視圖；以及圖2至圖9繪示在圖1中的引線接合型的系統級封裝的製造方法的剖面圖。
現在將詳細地說明本揭露的實施例，其為繪示在附圖中的例子。本揭露的實施例是為了對本領域技術人員更全面地說明本揭露，以及下列的實施例可在本揭露的樣態的範圍中進行改動，但不限定於下列的實施例。相反地，這些實施例用以加強本揭露，並且對本領域技術人員完整地說明本揭露的樣態。在圖式中，部件的繪示，與說明不相關的部分可以省略，以闡明本揭露，並且，繪示的組件的尺寸可被誇大。
圖1繪示根據本揭露的第一實施例中的引線接合型的系統級封裝的透視圖。
參照圖1，根據一實施例的引線接合型的系統級封裝100可包括：第一半導體晶片110、引線框120、第二半導體晶片130、扇出金屬圖案140、絕緣層150、導電連接終端160以及密封層170。
根據一實施例的系統級封裝體可以是引線接合型的系統級封裝。與其他系統級封裝相比，引線接合型的系統級封裝可具有改良的S參數(S21)，並因此可具有最低的功率損耗，例如，在封裝型的系統級封裝的封裝(package type system in package,POP SiP)以及面對面型的系統級封裝(face to face type system in package,F2F SiP)。
第一半導體110可包括複數個接合墊111。
引線框120可圍繞第一半導體晶片110而被佈置。引線框120可包括複數個訊號引線121。
第二半導體晶片130可設置在第一半導體晶片110的上側。第二半導體晶片130可藉由導線131被引線接合到引線框120。
儘管未繪示，第三半導體晶片與第四半導體晶片可以另外堆疊在第二半導體晶片130上。在第二半導體晶片130上的半導體晶片可藉由引線接合來連接。
更包括接合引線180，設置在第一半導體晶片110與第二半導體晶片130之間。也就是說，第一半導體晶片110與第二半導體晶片130可通過接合層180被相互接合。
例如，接合層180可包括環氧樹脂。
例如，在薄膜型的接合引線180可接合第一半導體晶片110與第二半導體晶片130，以及二擇一地，可藉由在樹脂型中施加接合層180到第一半導體晶片110，第二半導體晶片130被接合到第一半導體晶片110。
第一半導體晶片110或第二半導體晶片130可包 括記憶體晶片與控制記憶體晶片的邏輯晶片。例如，記憶體晶片可包括動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、相變隨機存取記憶體(PRAM)、電阻式隨機存取記憶體(ReRAM)、鐵電隨機存取記憶體(FeRAM)或磁阻式隨機存取記憶體(MRAM)。
例如，第一半導體晶片110或第二半導體晶片130可包括不同型的晶片。
扇出金屬圖案140可被佈置在第一半導體晶片110的下側，且引線框電性連接接合墊與訊號引線121。扇出金屬圖案140可包括複數個金屬墊。
扇出金屬圖案140可包括導電材料，例如金屬。例如，扇出金屬圖案140可包括銅、鋁以及其合金。
扇出金屬圖案140可重新由第一半導體晶片110佈線，並且可電性連接到導電連接終端160。因此，第一半導體晶片110的輸入/輸出端可被小型化，並可增加輸入/輸出端的數量。第一半導體晶片110可電性連接到扇出金屬圖案140，使得在系統級封裝100具有扇出結構。
絕緣層150可配置在第一半導體晶片110與引線框120下。例如，絕緣層150可包括有機或無機絕緣材料。例如，絕緣層150可包括環氧樹脂。
絕緣層150可包括第一絕緣層151與第二絕緣層152。第一絕緣層151可配置在第一半導體晶片110與引線框120下，且第二絕緣層152可配置在第一絕緣層151下。
第一絕緣層151可被佈置在第一半導體晶片110 與引線框120之間，以在其間為絕緣。
第一絕緣層151的一部分可被蝕刻，因此，接合墊111與訊號引線121可被暴露。扇出金屬圖案140可配置在第一絕緣層151下，以電性連接接合墊111與訊號引線121。
第二絕緣層152可被佈置在扇出金屬圖案140上。第二絕緣層152的一部分可被蝕刻，因此，扇出金屬圖案140的金屬墊可被暴露。
導電連接終端160可配置在金屬墊下，為扇出金屬圖案140的暴露部分，並且被電性連接到扇出金屬圖案140。因此，導電連接終端160可被安裝或被連接到外部裝置，以便由系統級封裝傳送電訊號到外界。
導電連接終端160可包括導電材料，例如，金屬。例如，扇出金屬圖案140可包括銅、鋁以及其合金。
導電連接終端160可以是焊球或焊料凸塊。
密封層170可覆蓋第一半導體晶片110、第二半導體晶片130以及引線框120。即，密封層170可密封第一半導體晶片110、第二半導體晶片130以及引線框120，使得第一半導體晶片110、第二半導體晶片130以及引線框120不會暴露。
例如，密封層170可包括有機或無機絕緣材料。例如，密封層170可包括環氧樹脂。
圖2至圖9是剖面圖，繪示出在圖1中的引線接合型的系統級封裝的製造方法。
將參照圖1至圖9，說明下文中引線接合型的系統 級封裝的製造方法。
在一基底10，可形成包括接合墊的第一半導體晶片110與形成引線框120，引線框120被設置為圍繞第一半導體晶片110，且引線框120包括複數個訊號引線121。
基底10可被用來固定第一半導體晶片110與引線框120。在第二半導體晶片130被堆疊在第一半導體晶片110與引線框120上、第二半導體晶片130連接到第一半導體晶片110且藉由引線接合連接第二半導體晶片110與引線框120等動作之後，接著在其上進行密封製程後，基底10可被移除。
第一半導體晶片110與引線框120可藉由粘合劑材料被接合到基底10。例如，在引線框120被接合到基底10之後，第一半導體晶片110可被接合到基底10。
第一半導體晶片110可包括複數個接合墊111。引線框120配置為圍繞第一半導體晶片110。引線框120可包括複數個訊號引線121。
基底10可以是剛體型的材料。例如，模具形成材料或聚亞醯胺膠帶可作為基底10。
第一半導體晶片110可被設置，使得形成電路的第一表面朝向下側。也就是說，第一半導體晶片110可被設置為相對於基底10的上表面。因此，第一半導體晶片110可被設置，使得未形成電路的第二表面朝向上側。
按順序，第二半導體晶片130可被堆疊在第一半導體晶片110上。例如，第二半導體晶片130可在第一半導體晶片110上被接合。
第一半導體晶片110或第二半導體晶片130可包括記憶體晶片與配置成控制記憶體晶片的邏輯晶片。例如，記憶體晶片可包括動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、相變隨機存取記憶體(PRAM)，電阻式隨機存取記憶體(ReRAM)、鐵電隨機存取記憶體(FeRAM)或磁阻式隨機存取記憶體(MRAM)。
例如，第一半導體晶片110或第二半導體晶片130可包括不同型的晶片。
可包括設置在第一半導體晶片110與第二半導體晶片130之間的接合線180。也就是說，第一半導體晶片110與第二半導體晶片130可通過接合層180被相互接合。
例如，接合層180可包括環氧樹脂。
例如，薄膜型的接合層180可接合第一半導體晶片110與第二半導體晶片130，以及二選一地，藉由在樹脂型施加接合層180到第一半導體晶片110，第二半導體晶片130可被接合到第一半導體晶片110。
第二半導體晶片130可被佈置在第一半導體上。第二半導體晶片130可通過導線131被引線接合到引線框120。
在引線框120與第二半導體晶片130通過引線接合而彼此連接之後，密封層170可被形成在第一半導體晶片110、第二半導體晶片130以及引線框120上。
密封層170可覆蓋第一半導體晶片110、第二半導體晶片130以及引線框120。即，密封層170可密封第一半導體晶片110、第二半導體晶片130以及引線框120，使得第一 半導體晶片110、第二半導體晶片130以及引線框120可不被暴露。
例如，密封層170可包括絕緣材料。例如，密封層170可包括環氧樹脂。
在施加絕緣材料到第二半導體晶片130、第一半導體晶片110以及引線框120之後(其中有引線接合)，也可以在其上進行熱固化與光固化，因此，可形成密封層170。
在形成密封層170後，基底10可從第一半導體晶片110與引線框120中分離。
雖然基底10藉由黏著劑材料被接合到第一半導體晶片110與引線框120，基底10可容易從第一半導體晶片110與引線框120分離。
第一半導體晶片110、引線框120以及第二半導體晶片130這三者藉由密封層170被固定，三者從基底10分離，第一半導體晶片110、引線框120以及第二半導體晶片130可反轉為上下顛倒，且接著在下一個製程中繼續使用。
下文將描述元件之間的排列，而假定元件之間的排列是在半導體晶片不反轉的狀態下的排列。
第一絕緣層151可形成在第一半導體晶片110與引線框120(兩者從基底10分離)之下。
第一絕緣層151可包括有機或無機絕緣材料。例如，第一絕緣層151可包括環氧樹脂。
第一絕緣層151可藉由施加絕緣材料到第一半導體晶片110與引線框120的下部而形成。第一絕緣層151的一 部分可被蝕刻以對應於接合墊111與訊號引線121設置的區域。第一絕緣層151可為乾式或濕式蝕刻。
因此，第一絕緣層151的部分可被蝕刻，使得接合墊111與訊號引線121可被暴露。
藉由沉積金屬材料到第一絕緣層151以形成金屬層。
金屬材料可包括導電材料，例如，金屬。例如，金屬材料可包括銅、鋁以及其合金。
扇出金屬圖案140可藉由蝕刻金屬層來形成。扇出金屬圖案140可電性連接接合墊111與訊號引線121，兩者位在第一半導體晶片110與引線框120下，並且可包括複數個金屬墊。例如，金屬層可容易地透過光阻製程進行蝕刻，使形成扇出金屬圖案140。
扇出金屬圖案140可重新由第一半導體晶片110佈線，並且可以電性連接到導電連接終端160。因此，第一半導體晶片110的輸入/輸出終端可被小型化，且增加輸入/輸出終端的數量。第一半導體晶片110可電性連接到扇出金屬圖案140，使得系統級封裝100具有扇出結構。
因此，第一絕緣層151可被佈置在第一半導體晶片、引線框120以及扇出金屬圖案140之間，以便從扇出金屬圖案140絕緣第一半導體晶片110與引線框120。
第二絕緣層152可形成在扇出金屬圖案140之下。
第二絕緣層152可包括有機或無機絕緣材料。例如，第二絕緣層152可包括環氧樹脂。
第二絕緣層152可藉由施加絕緣材料到扇出金屬圖案140的下部而形成。第二絕緣層152的一部分可被蝕刻以對應於導電連接終端160被連接的區域。第二絕緣層152可為乾式或濕式蝕刻。
因此，第二絕緣層152的一部分可被蝕刻，以暴露金屬墊。
導電連接終端160可配置在金屬墊下。
導電連接終端160可配置在金屬墊下，其是扇出金屬圖案140的暴露部分，並且被電性連接到扇出金屬圖案140。因此，導電連接終端160可被安裝或連接到外部裝置，以便在傳送來自系統級封裝的電性訊號到外部。
導電連接終端160可包括導電材料，例如，金屬。例如，導電連接終端160可包括銅、鋁以及其合金。
例如，導電連接終端160可為焊球或焊料凸塊。
從上面的說明可明顯看出，根據提出的系統級封裝，透過包括在半導體晶片下的扇出金屬圖案的引線接合型的系統級封裝(WB SiP)，與形成在半導體晶片上的窄間隙的接合墊可以更廣泛地展開。
根據提出的製造系統級封裝的方法，藉由提供製造引線型的系統級封裝(WB SiP)的方法，與另一種系統級封裝相比，製程的數目可減少，並且製程成本可降低，例如，封裝型系統級封裝的封裝(POP SiP)與面對面型系統級封裝(F2F SiP)。
雖然本揭露的幾個實施例已被繪示與說明，本領 域技術人員應理解可對這些實施例作出不脫離本揭露的原理與精神的狀況下的改動，且本發明的範疇定義在申請專利範圍及其等同物之中。
100‧‧‧系統級封裝
110‧‧‧第一半導體晶片
111‧‧‧接合墊
120‧‧‧引線框
121‧‧‧訊號引線
130‧‧‧第二半導體晶片
131‧‧‧導線
140‧‧‧扇出金屬圖案
150‧‧‧絕緣層
151‧‧‧第一絕緣層
152‧‧‧第二絕緣層
160‧‧‧導電連接終端
170‧‧‧密封層
180‧‧‧接合層

Claims (15)

  1. 一種系統級封裝，包括：一第一半導體晶片，其包括複數個接合墊；一引線框，佈置為環繞該第一半導體晶片，且設置有複數個訊號引線；一第二半導體晶片，設置在該第一半導體晶片的一上側並藉由引線接合連接到該引線框；以及一扇出金屬圖案，佈置在該第一半導體晶片與該引線框的一下側，以電性連接該些接合墊與該些訊號引線，且該扇出金屬圖案設置有複數個金屬墊。
  2. 如申請專利範圍第1項的系統級封裝，更包括：一絕緣層，佈置在該第一半導體晶片與該引線框的一下側。
  3. 如申請專利範圍第2項的系統級封裝，其中，該絕緣層的一部分被蝕刻，以暴露該些接合墊與該些引線框，以及該扇出金屬圖案被佈置在該絕緣層的一下側以連接該些接合墊與該些訊號引線。
  4. 如申請專利範圍第1項的系統級封裝，更包括：一接合層，佈置在該第一半導體晶片與該第二半導體晶片之間。
  5. 如申請專利範圍第4項的系統級封裝，其中，該接合層包含一環氧樹脂。
  6. 如申請專利範圍第1項的系統級封裝，更包括：一導電連接終端，設置在該些金屬墊的一下側以電性連接到該扇出金屬圖案。
  7. 如申請專利範圍第6項的系統級封裝，其中，該導電連接終端為一焊球或一焊料凸塊。
  8. 如申請專利範圍第1項的系統級封裝，更包括：一密封層，構造為覆蓋該第一半導體晶片、該第二半導體晶片以及該引線框。
  9. 如申請專利範圍第8項的系統級封裝，其中，該密封層包含一環氧樹脂。
  10. 如申請專利範圍第1項的系統級封裝，其中，該第一半導體晶片或該第二半導體晶片包括一記憶體晶片或配置為控制該記憶體晶片的一邏輯晶片。
  11. 一種製造系統級封裝的方法，包括：在一基底上，形成包括複數個接合墊的一第一半導體晶片，以及形成設置為環繞該第一半導體晶片且包括複數個訊號引線的一引線框；附著一第二半導體晶片到該第一半導體晶片的一上側；在該第二半導體晶片與該引線框之間進行引線接合；由該第一半導體晶片與該引線框分離該基底；以及在該第一半導體晶片與該引線框的一下側形成一扇出金屬圖案，該扇出金屬圖案被配置為電性連接該些接合墊與該些訊號引線，且該扇出金屬圖案具有複數個金屬墊。
  12. 如申請專利範圍第11項的方法，其中，在該第一半導體晶片與該第二半導體晶片之間形成一接合層。
  13. 如申請專利範圍第11項的方法，更包括：在形成該扇出金屬圖案之前，形成一第一絕緣層；以及 藉由蝕刻該第一絕緣層的一部分以暴露該些接合墊與該些訊號引線。
  14. 如申請專利範圍第13項的方法，更包括：在形成該扇出金屬圖案之後，形成結構為覆蓋該扇出金屬圖案的一第二絕緣層；藉由蝕刻該第二絕緣層的一部分以暴露該些金屬墊；以及形成一導電連接終端，在該些暴露的金屬墊的一下側，該導電連接終端被電性連接到該扇出金屬圖案。
  15. 如申請專利範圍第11項的方法，更包括：從該基底分離該第一半導體晶片與該引線框之前，形成一密封層，該密封層的構造為覆蓋該第一半導體晶片、該第二半導體晶片以及該引線框。
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