TW201705409A - 半導體裝置以及囊封半導體晶粒的方法 - Google Patents

半導體裝置以及囊封半導體晶粒的方法 Download PDF

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TW201705409A
TW201705409A TW105116081A TW105116081A TW201705409A TW 201705409 A TW201705409 A TW 201705409A TW 105116081 A TW105116081 A TW 105116081A TW 105116081 A TW105116081 A TW 105116081A TW 201705409 A TW201705409 A TW 201705409A
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trench
semiconductor wafer
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沙亞莫希 奇努薩米
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Abstract

具有半導體晶圓的半導體裝置。所述半導體晶圓包括多個半導體晶粒。絕緣層形成在所述半導體晶粒的主動表面上方。溝渠形成在所述半導體晶粒之間的所述半導體晶圓的非主動區域中。所述溝渠部分地延伸穿過所述半導體晶圓。提供具有黏合層的載體。所述半導體晶粒被同時設置在所述黏合層以及所述載體上方以作為單一個單元。背部研磨運作被實行以移除半導體晶圓的一部分並且曝露所述溝渠。在所述背部研磨運作期間，所述黏合層在原位固持所述半導體晶粒。囊封物被沉積於所述半導體晶粒上方以及所述溝渠中。所述載體以及所述黏合層被移除。經囊封之所述半導體晶粒被清洗並且單粒化為個別的半導體裝置。所述半導體裝置的電性效能以及功能被測試。

Description

半導體裝置以及囊封半導體晶粒的方法
本發明一般而言有關於半導體裝置，更具體地是有關於半導體裝置和囊封半導體晶粒的方法。
半導體裝置在現代電子產品中是常見的。半導體裝置在電性構件的數量和密度方面有所變化。離散式半導體裝置大致上含有一種類型的電性構件，例如，發光二極體(LED)、小型訊號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(MOSFET)。整合式半導體裝置通常含有數百到數百萬個電性構件。整合式半導體裝置的範例包括微控製器、微處理器和各種訊號處理電路。
半導體裝置執行廣泛的功能，諸如訊號處理、高速運算、傳送和接收電磁訊號、控制電子裝置、將太陽光轉換為電能以及產生用於電視顯示的視覺影像。半導體裝置被發現於娛樂、通信、電力轉換、網路、計算機以及消費性產品的領域中。半導體裝置亦被發現於軍事應用、航空、汽車、工業控制器以及辦公設備中。
半導體裝置利用了半導體材料的電性特性。半導體材料的結構允許材料的導電性藉由電場或基極電流的施加或經由摻雜的製程所操 縱。摻雜引入雜質進入半導體材料，以操縱和控制的半導體裝置的傳導性。
半導體裝置含有主動和被動電性結構。主動結構(包括雙極性和場效電晶體)控制電流的流動。藉由改變摻雜的位準和電場或基極電流的施加，電晶體會促進或限制電流的流動。被動結構(包括電阻器、電容器和電感器)在電壓和電流之間產生執行各種電性功能所需的關係。被動和主動結構被電性連接以形成電路，而使半導體裝置能夠執行高速的運作和其他有用的功能。
半導體裝置大致上使用兩種複雜的製造製程來製造(亦即，前端製造以及後端製造)，其每一者皆可能涉及數百個步驟。前端製造涉及在半導體晶圓的表面上形成複數個晶粒。每一個半導體晶粒通常是相同的並且含有藉由電性連接主動和被動構件所形成的電路。後端製造涉及從完成的晶圓單粒化個別的半導體晶粒以及將晶粒封裝以提供結構支撐、電性互連以及環境隔離。本文中所使用的「半導體晶粒(semiconductor die)」一詞兼具單數與複數兩種形式，據此，其可能係表示單一半導體裝置與多個半導體裝置。
半導體製造的一個目標是生產較小的半導體裝置。較小的裝置通常消耗較少的功率、具有較高的效能以及可更有效率地生產。此外，較小的半導體裝置具有較小的佔用面積，這對於較小的最終產品是理想的。較小的半導體晶粒尺寸可藉由改善前端製程而導致具有較小、較高密度的主動和被動構件的半導體晶粒來達成。後端製程可藉由改善電性互連和封裝材料而導致具有較小佔用面積的半導體裝置封裝。
假如半導體晶粒的一部分是曝露至外部元件，則半導體晶粒 會受到損壞或劣化。舉例而言，半導體晶粒會在處理期間或由於曝露於光的情況下被損壞或劣化。因此，半導體晶粒通常是封閉在囊封物內以提供晶粒的電性隔離、結構支撐以及環境保護。囊封半導體晶粒可藉由將半導體晶圓單粒化為個別的半導體晶粒、個別地安裝半導體晶粒至載體以及隨後沉積囊封物在半導體上方來執行。然而，安裝個別的半導體晶粒增加製造時間，從而減少生產量。個別的(亦即，經單粒化的)半導體晶粒亦是脆弱的並且會在附接至載體期間被損壞。再者，將個別的半導體晶粒安裝至載體會增加半導體晶粒之間的距離以及囊封物在半導體晶粒周圍的數量，從而導致最終封裝尺寸的增加。
一種需要存在以封裝半導體晶粒同時增加生產量並且減少封裝尺寸。因此，在一實施例中，本發明揭示製造半導體裝置的方法，其包括以下步驟：提供半導體晶圓，半導體晶圓包括多個半導體晶粒；形成溝渠於半導體晶粒之間並且部分地穿過半導體晶圓；設置半導體晶粒於載體上方；移除半導體晶圓的第一部分；以及沉積囊封物於半導體晶粒上方以及溝渠中。
在另一實施例中，本發明揭示製造半導體裝置的方法，其包括以下步驟：提供半導體晶圓，半導體晶圓包括多個半導體晶粒；形成溝渠於半導體晶粒之間；將半導體晶粒設置在載體上方；以及沉積囊封物於溝渠中。
在另一實施例中，本發明揭示製造半導體裝置的方法，其包括以下步驟：提供多個半導體晶粒；形成溝渠於半導體晶粒之間；以及沉 積囊封物於溝渠中。
在另一實施例中，本發明是包括載體的半導體裝置。半導體晶圓被設置在載體上方並且包括由溝渠所隔開的多個半導體晶粒。
100‧‧‧半導體晶圓
102‧‧‧基底基板材料
104‧‧‧半導體晶粒
106‧‧‧切割道
108‧‧‧表面
110‧‧‧主動表面
112‧‧‧傳導層
114‧‧‧絕緣層
116‧‧‧溝渠
118‧‧‧切割工具
119‧‧‧表面
120‧‧‧載體
122‧‧‧黏合層
124‧‧‧研磨器
126‧‧‧研磨器
128‧‧‧背側表面
130‧‧‧背側表面
132‧‧‧囊封物
134‧‧‧表面
圖1a至1m例示囊封半導體晶粒的方法；以及圖2例示經囊封的半導體晶粒。
本發明在以下參照圖示的說明中以一或多個實施例來說明，其中相似的數字代表相同或相似的元件。儘管以實現本發明目的之最佳模式來說明本發明，然該領域中習知此技術者將瞭解的是，本揭示意圖涵蓋替代物、修改以及等效物，如同可以包含於藉以下的揭露事項與附圖所支持的所附申請專利範圍及其等效物所定義的本發明精神與範疇之內。
半導體裝置大致上使用兩種複雜的製程來製造：前端製造以及後端製造。前端製造涉及在半導體晶圓的表面上形成複數個晶粒。在晶圓上的每一個晶粒皆包括主動與被動電性構件，其等被電性連接以形成功能性電路。主動電性構件(諸如，電晶體和二極體)具有控制電流流動之能力。被動電性構件(諸如，電容器、電感器以及電阻器)在電壓和電流之間建立執行電路功能所需的關係。
被動和主動構件係藉由一連串包含摻雜、沉積、光學微影術、蝕刻及平坦化之製程步驟而形成於半導體晶圓之表面上方。摻雜藉由諸如離子植入或熱擴散的技術將雜質掺入半導體材料之中。摻雜製程藉由動態地改變半導體材料的傳導性改變在主動裝置中半導體材料之導電性， 以回應於電場或基極電流(base current)。電晶體含有具有不同類型及程度的摻雜的區域，該些區域係以使得電晶體在電場或基極電流的施加時能夠提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電性特性的材料層來加以形成。該些層可藉由多種沉積技術來形成，該技術部分地是由被沉積的材料類型來決定的。舉例而言，薄膜沉積可涉及到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解電鍍以及無電電鍍製程。每一個層大致上是被圖案化，以形成部分的主動構件、被動構件或是在構件間的電連接。
後端製造係指切割或單粒化完成的晶圓成為個別的晶粒並且封裝半導體晶粒以提供結構支撐、電性互連以及環境隔離。為了單粒化半導體晶粒，晶圓係沿著晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。晶圓係利用雷射切割工具或鋸刀而被單粒化。在單粒化之後，個別的半導體晶粒係被安裝到封裝基板，封裝基板包括用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒上方的接觸墊接著連接至封裝內的接觸墊。電性連接可以利用傳導層、凸塊、柱形凸塊(stud bump)、導電膏、或是引線接合來製成。囊封物或是其它模製材料沉積在封裝上方，以提供實體支撐以及電性隔離。完成的封裝接著被***電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a例示具有基底基板材料102(諸如，矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或其它的塊體半導體材料)的半導體晶圓100以用於結構支撐。多個半導體晶粒或構件104形成在晶圓100上而由如上所述的非主動、晶粒間的晶圓區域或切割道106所隔開。切 割道106提供切割區域以將半導體晶圓100單粒化成個別的半導體晶粒104。
圖1b例示半導體晶圓100的一部分的截面圖。每一個半導體晶粒104皆具有背部或非主動表面108以及含有類比或數位電路的主動表面110，類比或數位電路被實作為根據電性設計以及晶粒的功能而形成在晶粒內並且電性互連的主動裝置、被動裝置、傳導層以及介電層。舉例而言，電路可包括形成在主動表面110的一或多個電晶體、二極體以及其他電路元件，以實施類比電路或數位電路(諸如，數位訊號處理器(DSP)、ASIC、MEMS、記憶體或其他訊號處理電路)。半導體晶粒104亦可含有整合式被動裝置(IPD)(諸如，電感器、電容器以及電阻器)以用於射頻(RF)訊號處理。
電性傳導層112利用PVD、CVD、電解電鍍、無電電鍍製程或其他合適的金屬沉積製程而形成在主動表面110上方。傳導層112包括以下所組成的一或多個層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈀(Pd)、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其他合適的電性傳導材料或它們的組合。傳導層112作用為電性連接至主動表面110上的電路的接觸墊。接觸墊112有助於在半導體晶粒104內的主動電路與外部裝置(例如，印刷電路板(PCB))之間的電性互連。
絕緣層或鈍化層114利用PVD、CVD、網版印刷、旋轉塗覆、噴霧塗覆、燒結或熱氧化而形成在主動表面110上方以及接觸墊112周圍。絕緣層114含有由以下所組成的一或多個層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、氧化鉿(HfO2)，苯並環丁烯(BCB)、聚亞醯胺(PI)、聚苯噁唑(PBO)、聚 合物、阻焊劑、或具有類似的絕緣和結構特性的其它材料。絕緣層114覆蓋主動表面110並且為其提供保護。絕緣層114圍繞接觸墊112並且提供電性隔離。接觸墊112的部分是從絕緣層114曝露以允許後續至半導體晶粒104的電性連接。
在圖1c中，多個溝渠或開口116是利用切割工具118而被形成在晶圓100中。在一實施例中，深式反應離子蝕刻(DRIE)是被使用以形成溝渠116。溝渠116亦可利用雷射直接燒蝕(LDA)、機械鑽孔、電漿蝕刻或其他合適的製程而形成。溝渠116是被形成在切割道106中的半導體晶粒104之間。溝渠116是被形成以在半導體晶粒104周圍的週邊區域中圍繞半導體晶粒104。溝渠116是被形成以穿過絕緣層114以及基底基板材料102。溝渠116僅部分地延伸穿過半導體晶圓100，以使得基底基板材料102的部分餘留在溝渠116的底部表面119以及半導體晶圓100的表面108之間。半導體晶粒104藉由餘留在切割道106上(亦即，在表面119以及表面108之間)的基底基板材料102的部分而保持彼此連接。
圖1d例示用於結構支撐而含有犧牲基底基板材料(例如，矽、聚合物、氧化鈹、玻璃、或其他合適的低成本、剛性材料)的載體或暫時性基板120的部分的截面圖。黏合層122是被形成在載體120上方以作為暫時性接合膜、蝕刻停止層、熱脫膜層或UV脫膜層。在一實施例中，黏合層122是被附接至載體120的表面的雙面膠帶。替代而言，黏合層122可利用旋轉塗覆、層壓、銲膏印刷或其他合適的施加製程而被形成在載體120的表面上。
半導體晶圓100被設置在黏合層122和載體120上方，而溝 渠116和半導體晶粒104的主動表面110朝向載體。半導體晶粒104藉由餘留在半導體晶粒104之間的切割道106的部分而連接或保持在一起。餘留在半導體晶粒104之間的切割道106的部分允許晶圓100的半導體晶粒104被安裝作為單一個單元。設置半導體晶粒104在載體120上方作為單一個單元允許半導體晶粒104在單一個步驟中被同時地安裝。
圖1e例示被設置在黏合層122和載體120上的半導體晶粒104。在將半導體晶圓100安裝至載體120之後，表面108利用研磨器124而接受背部研磨運作。背部研磨運作從表面108移除基底基板材料102的部分並且曝露溝渠116。背部研磨運作移除切割道106覆蓋溝渠116的部分並且薄化或減少半導體晶粒104的厚度。從背側表面108移除基底基板材料102使半導體晶粒104有新的背側表面130。替代而言，可使用LDA、蝕刻、拋光、化學機械研磨(CMP)或其他合適的去除製程以薄化半導體晶粒104並且露出溝渠116。背部研磨運作單粒化半導體晶粒104，亦即，在背部研磨之後半導體晶粒104不再藉由基底基板材料102彼此連接。在背部研磨期間以及在單粒化之後(亦即，在背部研磨之後)，半導體晶粒104藉由黏合層122而被固持在原位。
圖1f例示背部研磨運作之後的半導體晶粒104。半導體晶粒104之間的空間是藉由溝渠116而產生，以使得經單粒化的半導體晶粒104之間的寬度W1是相等於溝渠116的寬度。
圖1g-1j例示單粒化半導體晶粒104的替代性方法。從圖1d繼續，圖1g例示被設置在黏合層122和載體120上方的晶圓100，而溝渠116和半導體晶粒104的主動表面110朝向載體。半導體晶粒104藉由餘留 在溝渠116的表面119以及晶圓100的表面108之間的切割道106的部分而連接。餘留在半導體晶粒104之間的切割道106的部分允許半導體晶粒104被同時安裝在載體120上方作為單一個單元。
在圖1h中，半導體晶圓100的表面108接受背部研磨運作以移除基底基板材料102的部分。研磨器126從表面108移除基底基板材料102並且產生新的背側表面128。背部研磨運作並未曝露溝渠116。在背部研磨運作之後，半導體晶粒104藉由在切割道106中基底基板材料102的部分而保持連接。在一實施例中，在背部研磨之後仍餘留30-40微米的基底基板材料102在溝渠116的表面119以及晶圓100的新的背側表面128之間。
圖1i例示背部研磨運作之後的晶圓100。在背部研磨運作期間，餘留在溝渠116的表面119以及晶圓100的表面128之間的基底基板材料102的部分支撐並且強化半導體晶粒104。連接半導體晶粒104的基底基板材料102的部分減少位於半導體晶粒104上的研磨應力。減少半導體晶粒104上的研磨應力降低半導體晶粒104在背部研磨運作期間被損壞的可能性，而增加了功能性半導體晶粒104的可靠性和生產量。
連接半導體晶粒104的切割道106的部分亦允許溝渠116在研磨操作期間保持被覆蓋。留下溝渠116未曝露防止碎屑(例如，基底基板材料102的顆粒)落入溝渠116中。防止研磨碎屑進入溝渠116則排除對溝渠116進行後研磨清洗的需要。排除後研磨清洗製程減少了製造時間和成本。
在圖1j中，切割道106的剩餘部分是利用電漿蝕刻、DRIE或其他合適的蝕刻過程序而被移除。從切割道106移除基底基板材料102 的最後部分曝露溝渠116並且單粒化半導體晶粒104。用於曝露溝渠116的蝕刻運作亦可移除背側表面128的部分以進一步薄化半導體晶粒104。在背部研磨和蝕刻製程兩者期間以及在單粒化之後(亦即，在蝕刻之後)，黏合層122固持半導體晶粒104在原位。半導體晶粒104之間的空間是藉由溝渠116而產生，以使得經單粒化的半導體晶粒104之間的寬度W1是相等於溝渠116的寬度。
從圖1f繼續，圖1k例示被沉積在半導體晶粒104、黏合層122和載體120上方的囊封物或模製化合物132。囊封物132利用網版印刷、噴霧塗覆、銲膏印刷(paste printing)、壓縮模製、轉移模製、液態囊封模製、真空積層、旋轉塗覆或其他合適的施加方法而被沉積在半導體晶粒104上方和周圍。囊封物132覆蓋半導體晶粒104的四個側表面和背側表面130。囊封物132包括聚合物複合材料(諸如，具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或具有合適填充物的聚合物)。囊封物132是不導電的並且在環境上保護半導體裝置免受外部元件和污染物影響。囊封物132是被沉積在由溝渠116所產生的空間中的半導體晶粒104之間。溝渠116允許囊封物132在半導體晶粒104的側表面上方和周圍流動。囊封物132可在沉積或稍後在製造製程中被立即地固化。
在圖1l中，載體120和黏合層122是藉由化學蝕刻、機械式剝除(mechanical peel-off)、CMP、機械式研磨(mechanical grinding)、熱烘(thermal bake)、UV光、雷射掃描(laser scanning)或濕式剝除(wet stripping)而被移除。移除載體120和黏合層122曝露絕緣層114、接觸墊112和囊封物132的表面134。囊封物132的表面134是與絕緣層114的表面和接觸墊 112共平面。半導體晶粒104是藉由囊封物132而被固持在一起。囊封物132在後續製造期間提供結構支撐並且保護半導體晶粒104。
在移除載體120和黏合層122之後，經囊封的半導體晶粒104接受除膠渣(desmearing)或清洗製程以移除來自絕緣層114、接觸墊112和囊封物134的表面132的任何顆粒或殘留物。清洗製程可包括旋轉清洗乾燥(spin rinse drying(SRD))製程、電漿清洗製程、乾式清洗製程、濕式清洗製程或它們的組合。
在圖1m中，切割保護膠(dicing tape)或支撐載體136被施加在經囊封的半導體晶粒104上方。經囊封的半導體晶粒104是接著利用鋸片或雷射切割工具138而被單粒化為個別的半導體裝置或封裝140。切割工具138切割穿過被設置在半導體晶粒104之間的囊封物132。切割保護膠136在單粒化期間支撐半導體晶粒104。在單粒化之後，囊封物132餘留在半導體晶粒104的四個側表面上方。
在半導體裝置140內的主動和被動構件接受電性效能和電路功能的測試。測試可包括對於構件類型的特定電路功能、引線完整性、電阻、連慣性(continuity)、可靠度、接面深度、靜電放電(ESD)、RF效能、驅動電流、閾值電流、漏電流和操作參數。檢驗和測試使得通過的半導體裝置140可被指定為已知良品(known good)。已知良品裝置接著利用例如壓紋帶(embossed tape)和卷軸而被捲裝。被捲裝的半導體裝置140是接著被送出以進一步處理或併入於其他電子裝置和系統。
圖2例示單粒化之後的半導體裝置140。接觸墊112被電性連接至半導體晶粒104的主動表面110上的電路並且有助於外部裝置(例 如，PCB)和半導體裝置間的後續連接。絕緣層114為了保護和電性隔離而被設置在主動表面110上方和接觸墊112周圍。囊封物132被設置在背側表面130和半導體晶粒104的四個側表面上方。囊封物132提供機械保護、電性隔離和保護而免於由於曝露於來自光或來自其他輻射的光子所造成的劣化。囊封物132在環境上保護半導體晶粒104免受外部元件和污染物影響。
由於半導體晶粒104被設置在載體120上方作為單一個晶圓或單元，半導體裝置140的生產量因而增加。設置半導體晶粒104在載體120上方作為單一個單元簡化了製造並且排除了個別地將半導體晶粒104安裝至載體的需要。同時安裝半導體晶粒104降低了製造時間，從而提高生產量和降低成本。在半導體晶粒仍然為晶圓形式時(亦即，當半導體晶粒仍然藉由基底基板材料102而連接時)安裝半導體晶粒104強化和提高在安裝期間半導體晶粒104的穩固性。經連接的半導體晶粒是更受支撐的並且因而更不容易在附接至載體120期間被損壞。在背部研磨運作期間，黏合層122固持半導體晶粒104在原位。在沉積囊封物132期間，黏合層122亦保持半導體晶粒104之間的對位和間距。
利用預先成形的溝渠116來安裝經連接的半導體晶粒104增加半導體晶粒104對載體120的對位準確度和間距一致性。由於在半導體晶粒104之間有一致的間距，囊封物132可更均勻地分佈在半導體晶粒104上方和周圍。在半導體晶粒104之間一致的間距和均勻數量的囊封物允許在單粒化半導體裝置140期間提高準確度。準確的單位化產出均一的半導體裝置140並且減少在單粒化期間損壞半導體晶粒104的可能性。
經囊封的半導體晶粒104以小的佔用面積製造堅固的半導 體裝置140。由於在半導體晶粒104之間有基底基板材料102的緣故，當半導體晶粒104被安裝至載體120時半導體晶粒104是被更好地支撐並且受到更小的應力。在單粒化半導體晶粒104之後，囊封物132被沉積在半導體晶粒104上方和周圍，以在後續處理和製造期間保護和支撐半導體晶粒104。因此，由於在製造製程期間和之後半導體晶粒104更不易受到損壞的緣故，增加了良好的半導體裝置140的整體功能和數量。
儘管已經詳細地闡述了本發明一或更多之實施例，然熟知該項技術者將會察知的是，在不違反在以下申請專利範圍中所提的本發明之範疇，可以從事這些實施例的修改與變更。
104‧‧‧半導體晶粒
110‧‧‧主動表面
112‧‧‧傳導層
114‧‧‧絕緣層
130‧‧‧背側表面
132‧‧‧囊封物
134‧‧‧表面
140‧‧‧半導體裝置

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供半導體晶圓，所述半導體晶圓包括多個半導體晶粒；形成溝渠於所述半導體晶粒之間並且部分地穿過所述半導體晶圓；將所述半導體晶圓設置在載體上方，而所述溝渠朝向所述載體；在將所述半導體晶圓設置在所述載體上方之後，移除在所述溝渠上方的所述半導體晶圓的第一部分以單粒化所述半導體晶粒；以及沉積囊封物於所述半導體晶粒上方以及所述溝渠中。
  2. 如申請專利範圍第1項所述的方法，進一步包括在移除所述半導體晶圓的所述第一部分之前，移除在所述溝渠上方的所述半導體晶圓的第二部分。
  3. 如申請專利範圍第2項所述的方法，進一步包括：藉由背部研磨移除所述半導體晶圓的所述第二部分；以及藉由蝕刻移除所述半導體晶圓的所述第一部分。
  4. 如申請專利範圍第1項所述的方法，其中移除所述半導體晶圓的所述第一部分曝露所述溝渠。
  5. 如申請專利範圍第1項所述的方法，進一步包括將黏合層設置在所述載體上方。
  6. 如申請專利範圍第1項所述的方法，進一步包括：移除所述載體；以及清洗所述半導體晶粒。
  7. 一種製造半導體裝置的方法，其包括： 提供半導體晶圓，所述半導體晶圓包括多個半導體晶粒；形成溝渠於所述半導體晶粒之間的所述半導體晶圓中。將所述半導體晶圓設置在載體上方；以及沉積囊封物於所述溝渠中。
  8. 如申請專利範圍第7項所述的方法，進一步包括移除所述半導體晶圓的一部分以曝露所述溝渠。
  9. 如申請專利範圍第7項所述的方法，進一步包括移除在所述溝渠上方的所述半導體晶圓的第一部分，同時留下在所述溝渠上方的所述半導體晶圓的第二部分。
  10. 如申請專利範圍第9項所述的方法，進一步包括藉由蝕刻移除所述半導體晶圓的所述第二部分。
  11. 一種半導體裝置，其包括：載體；以及半導體晶圓，其被設置在所述載體上方，其中所述半導體包括由溝渠所隔開的多個半導體晶粒，而所述溝渠朝向所述載體。
  12. 如申請專利範圍第11項所述的半導體裝置，進一步包括黏合層，所述黏合層被設置在所述載體上方。
  13. 如申請專利範圍第12項所述的半導體裝置，其中所述黏合層包括雙面膠帶。
  14. 如申請專利範圍第11項所述的半導體裝置，其中所述半導體晶粒的主動表面朝向所述載體。
  15. 如申請專利範圍第11項所述的半導體裝置，其中所述溝渠部分地 延伸穿過所述半導體晶圓。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI651786B (zh) * 2017-08-01 2019-02-21 台虹科技股份有限公司 晶粒封裝方法
TWI713849B (zh) * 2017-06-26 2020-12-21 大陸商矽力杰半導體技術（杭州）有限公司 半導體製程及半導體結構

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014111106A1 (de) * 2014-08-05 2016-02-11 Osram Opto Semiconductors Gmbh Elektronisches Bauelement, optoelektronisches Bauelement, Bauelementeanordnung und Verfahren zur Herstellung eines elektronisches Bauelements
US10529576B2 (en) 2017-08-17 2020-01-07 Semiconductor Components Industries, Llc Multi-faced molded semiconductor package and related methods
US11342189B2 (en) 2015-09-17 2022-05-24 Semiconductor Components Industries, Llc Semiconductor packages with die including cavities and related methods
US9837375B2 (en) * 2016-02-26 2017-12-05 Semtech Corporation Semiconductor device and method of forming insulating layers around semiconductor die
US10483434B2 (en) * 2017-01-03 2019-11-19 Innolux Corporation Display devices and methods for forming display devices
US10410922B2 (en) * 2017-02-23 2019-09-10 Nxp B.V. Semiconductor device with six-sided protected walls
CN107180891A (zh) * 2017-04-11 2017-09-19 中国电子科技集团公司第十研究所 一种红外探测器的划片方法
US11361970B2 (en) 2017-08-17 2022-06-14 Semiconductor Components Industries, Llc Silicon-on-insulator die support structures and related methods
US11393692B2 (en) 2017-08-17 2022-07-19 Semiconductor Components Industries, Llc Semiconductor package electrical contact structures and related methods
US11404277B2 (en) 2017-08-17 2022-08-02 Semiconductor Components Industries, Llc Die sidewall coatings and related methods
US11367619B2 (en) 2017-08-17 2022-06-21 Semiconductor Components Industries, Llc Semiconductor package electrical contacts and related methods
US11404276B2 (en) 2017-08-17 2022-08-02 Semiconductor Components Industries, Llc Semiconductor packages with thin die and related methods
US11348796B2 (en) 2017-08-17 2022-05-31 Semiconductor Components Industries, Llc Backmetal removal methods
US10209542B1 (en) 2017-12-15 2019-02-19 Didrew Technology (Bvi) Limited System and method of embedding driver IC (EmDIC) in LCD display substrate
WO2019135783A1 (en) 2018-01-04 2019-07-11 Didrew Technology (Bvi) Limited Frameless lcd display with embedded ic system and method of manufacturing thereof
WO2019156695A1 (en) 2018-02-09 2019-08-15 Didrew Technology (Bvi) Limited Method of manufacturing fan out package with carrier-less molded cavity
WO2019160570A1 (en) 2018-02-15 2019-08-22 Didrew Technolgy (Bvi) Limited System and method of fabricating tim-less hermetic flat top his/emi shield package
WO2019160566A1 (en) 2018-02-15 2019-08-22 Didrew Technology (Bvi) Limited Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener
US10283424B1 (en) * 2018-03-08 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and packaging method
US10957595B2 (en) * 2018-10-16 2021-03-23 Cerebras Systems Inc. Systems and methods for precision fabrication of an orifice within an integrated circuit
DE102018132447B4 (de) 2018-12-17 2022-10-13 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung
CN111370323A (zh) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司 半导体器件制作方法
WO2020214825A2 (en) * 2019-04-16 2020-10-22 Next Biometrics Group Asa Systems and methods for manufacturing flexible electronics
JP7334063B2 (ja) * 2019-05-24 2023-08-28 株式会社ディスコ モールドチップの製造方法
KR102243674B1 (ko) * 2019-10-28 2021-04-23 주식회사 루츠 세라믹칩 제조방법
US11145530B2 (en) 2019-11-08 2021-10-12 Cerebras Systems Inc. System and method for alignment of an integrated circuit
FR3103315B1 (fr) * 2019-11-19 2021-12-03 St Microelectronics Tours Sas Procédé de fabrication de puces électroniques
WO2022139674A1 (en) * 2020-12-23 2022-06-30 Heraeus Deutschland Gmbh & Co. Kg. Process for the manufacture of encapsulated semiconductor dies and/or of encapsulated semiconductor packages
US11688718B2 (en) * 2021-09-07 2023-06-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage during LAB
FR3131799A1 (fr) * 2022-01-10 2023-07-14 Stmicroelectronics (Crolles 2) Sas Procédé de fabrication de circuits intégrés à partir d’une plaquette en substrat semiconducteur

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6338980B1 (en) 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
JP3910843B2 (ja) * 2001-12-13 2007-04-25 東京エレクトロン株式会社 半導体素子分離方法及び半導体素子分離装置
JP4564351B2 (ja) * 2004-12-28 2010-10-20 パナソニック株式会社 半導体ウェーハの分割方法、研削装置および半導体ウェーハ分割システム
JP2009070880A (ja) * 2007-09-11 2009-04-02 Nec Electronics Corp 半導体装置の製造方法
US8497564B2 (en) * 2009-08-13 2013-07-30 Broadcom Corporation Method for fabricating a decoupling composite capacitor in a wafer and related structure
US9136144B2 (en) * 2009-11-13 2015-09-15 Stats Chippac, Ltd. Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
JP5580719B2 (ja) * 2009-12-24 2014-08-27 日東電工株式会社 ダイシングテープ一体型半導体裏面用フィルム
JP5474630B2 (ja) * 2010-03-30 2014-04-16 トッパン・フォームズ株式会社 電子部品およびその製造方法、部品実装基板
US8492203B2 (en) * 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
JP5659033B2 (ja) * 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
US9401289B2 (en) * 2012-06-04 2016-07-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of backgrinding and singulation of semiconductor wafer while reducing kerf shifting and protecting wafer surfaces
US8975162B2 (en) * 2012-12-20 2015-03-10 Applied Materials, Inc. Wafer dicing from wafer backside
US9799590B2 (en) * 2013-03-13 2017-10-24 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package
US9548248B2 (en) * 2014-08-07 2017-01-17 Infineon Technologies Ag Method of processing a substrate and a method of processing a wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI713849B (zh) * 2017-06-26 2020-12-21 大陸商矽力杰半導體技術（杭州）有限公司 半導體製程及半導體結構
TWI651786B (zh) * 2017-08-01 2019-02-21 台虹科技股份有限公司 晶粒封裝方法

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