TW201543688A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TW201543688A
TW201543688A TW103126711A TW103126711A TW201543688A TW 201543688 A TW201543688 A TW 201543688A TW 103126711 A TW103126711 A TW 103126711A TW 103126711 A TW103126711 A TW 103126711A TW 201543688 A TW201543688 A TW 201543688A
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Taiwan
Prior art keywords
forming
layer
intermediate layer
metal oxide
opening
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TW103126711A
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English (en)
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TWI550871B (zh
Inventor
Yu-Hung Lin
Sheng-Hsuan Lin
Chih-Wei Chang
You-Hua Chou
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201543688A publication Critical patent/TW201543688A/zh
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract

本發明揭露了一種形成具有摻雜金屬氧化物中間層的金屬-半導體接觸之方法：在半導體基底的頂表面上形成絕緣層，其中一目標區位於上述半導體基底的頂表面；蝕穿該絕緣層形成一開口，上述開口暴露目標區的一部分頂表面；在上述開口中形成一摻雜金屬氧化物中間層且與目標區的頂表面接觸；及以一金屬栓塞填充上述開口的剩餘部分，上述摻雜金屬氧化物中間層設置於金屬栓塞及半導體基底之間，由氧化錫、氧化鈦或氧化鋅其中之一形成且由氟進行摻雜。

Description

半導體裝置及其形成方法
半導體裝置被使用在許多種類的電子應用中，例如：個人電腦、行動電話、數位相機及其他電子儀器，半導體裝置的製造通常係藉由連續地沉積絕緣層或介電層、導電層及半導體層的材料在一半導體基底上，接著利用微影技術在各種材料層上形成圖案以在其上形成電路組件及元件。
半導體產業持續地改善不同的電子組件(例如：電晶體、二極體、電阻器、電容器…等)之整合密度，藉由持續降低最小元件尺寸，讓更多組件能夠在給定的面積中整合。為了增加主動元件的密度，主動元件形成在半導體基底上方，且彼此連接或連接晶粒中的其他元件或藉由重分布層(redistribution layers,RDLs)中的絕緣層之導電線路連接至外部元件，重分布層的互連係藉由形成於層間介電層(interlayer dielectric,ILD)中的導電栓塞或接觸與每個主動元件中個別的元件連接，上述層間介電層位於半導體表面及重分布層之間。鈍化層及後鈍化內連線提供重分布層及連接器，像是焊接球、間柱(stud)、凸塊等，之間的連接。重分布層及鈍化層通常係利用後段(back-end-of-line,BEOL)製程形成，後段製程在製造主動半導體元件之後，但在晶圓單粒化形成晶粒之前。
因此，根據實施例形成半導體裝置的方法包括： 在一半導體基底的一頂表面上形成一絕緣層，其中一目標區設置在該半導體基底的該頂表面；蝕穿該絕緣層形成一開口，上述開口暴露該目標區的一部分頂表面；在該開口中形成一摻雜金屬氧化物中間層，且與該目標區之該頂表面接觸；及以一金屬栓塞填充該開口的剩餘部分，上述摻雜金屬氧化物中間層設置於該金屬栓塞及該半導體基底之間。在一些實施例中，蝕穿開口的步驟包括：產生一蝕刻的副產物於開口的表面，蝕刻的副產物包括第一摻質，且其中形成摻雜金屬氧化物中間層的步驟包括：形成一金屬氧化物中間層於蝕刻副產物的上方，及蝕刻副產物中的第一摻質至少部分地摻雜至金屬氧化物中間層。 在另一些實施例中，形成摻雜金屬氧化物中間層的步驟包括：佈植第一摻質至金屬氧化物中間層中；由氧化錫、氧化鈦或氧化鋅其中之一形成金屬氧化物中間層；在形成絕緣層之前，形成一電晶體於半導體基底之上，其中目標區係電晶體的源極或汲極。在一些實施例中，金屬氧化物中間層由氟進行摻雜。
根據實施例，形成半導體裝置的方法包括：在一 半導體基底的頂表面上形成絕緣層，且至少有一主動元件形成於上述半導體基底中，其中至少一主動元件的目標區設置在半導體基底的頂表面；蝕穿絕緣層形成開口，上述開口暴露目標區的一部分頂表面；在開口中形成金屬氧化物中間層，且與目標區接觸；以第一摻質對金屬氧化物中間層進行摻雜；在開口中形成黏著層，且設置於金屬氧化物中間層之上；在開口中形 成金屬栓塞，且形成於黏著層之上，摻雜金屬氧化物中間層設置於金屬栓塞及半導體基底之間；及在絕緣層的頂表面上方形成重分布層(redistribution layer,RDL)，重分布層的金屬元件與金屬栓塞電性接觸。形成金屬氧化物中間層包括：由氧化錫、氧化鈦或氧化鋅其中之一形成金屬氧化物中間層。形成摻雜金屬氧化物中間層的步驟包括：佈植第一摻質至金屬氧化物中間層中；佈植第一摻質包括：佈植氟至金屬氧化物中間層中。在一些實施例中，在形成絕緣層之前，形成一電晶體於半導體基底上，其中目標區係電晶體的一源極或一汲極；目標區由不同於該第一摻質的一第二摻質進行摻雜且目標區大致上不含有矽化物。
根據實施例，半導體裝置包括：一絕緣層，設置 於半導體基底上方，有一開口延伸穿過絕緣層，基底的第一表面設置在開口的底部；接點的中間層，設置在開口中且具有第一部分與基底的第一表面接觸；及接點的金屬栓塞，設置在開口中，中間層分隔金屬栓塞和基底的第一表面；其中，中間層包括一摻雜氧化物。在一實施例中，中間層包括一摻雜金屬氧化物，其中經摻雜金屬氧化物的金屬氧化物為氧化錫、氧化鈦或氧化鋅其中之一，摻雜金屬氧化物經氟摻雜至濃度大約為0.1%至15%。上述半導體裝置更包括設置於中間層及金屬栓塞之間的黏著層，黏著層包括氮化鈦，且金屬栓塞包括鎢，金屬栓塞的最高表面與中間層的最高表面、黏著層的最高表面及絕緣層的最高表面係大致齊平的。在一些實施例中，重分布層(RDL)有至少一金屬元件與金屬栓塞電性連接。
102‧‧‧目標區
104‧‧‧基底
106‧‧‧絕緣層
202‧‧‧接觸開口
204‧‧‧罩幕
302‧‧‧副產物
402‧‧‧中間層
502‧‧‧摻質
602‧‧‧黏著層
702‧‧‧栓塞
802‧‧‧接觸
902‧‧‧閘極結構
904‧‧‧源極/汲極區
906‧‧‧閘極接觸
908‧‧‧介面層
910‧‧‧閘極介電層
1002‧‧‧重分布層
1004‧‧‧修整層
1006‧‧‧連接器
1008‧‧‧底層凸塊金屬化結構
1010‧‧‧後鈍化內連線
1012‧‧‧保護層
1014‧‧‧鈍化層
1016‧‧‧介電層
1018‧‧‧金屬元件
1100‧‧‧雙極接面電晶體裝置
1102‧‧‧井
1104‧‧‧集極
1106‧‧‧基極
1108‧‧‧射極
1120‧‧‧鰭式場效電晶體結構
1122‧‧‧鰭片
1124‧‧‧源極/汲極區
1126‧‧‧通道區
1128‧‧‧閘極接觸
1130‧‧‧閘極介電層
1200‧‧‧形成具有摻雜中間層的接觸之方法
1202~1220‧‧‧形成具有摻雜中間層的接觸之方法步驟
以下將配合所附圖式詳述本發明之實施例，除了 特別指明之外，相同的數字及符號在不同的圖示中通常指的係相同部分，圖示的繪製係用以說明實施例的相關方位，應注意的是，依據工業中的標準實行，以下許多元件並未按照比例繪製，事實上，可能任意的放大或縮小元件的尺寸以便清楚表現出本發明的特徵。
第1-8圖係實施例中形成具有摻雜中間層的金屬半導體接觸的製程中，各中間步驟之剖面圖；第9-10、11A-11B圖係實施例中具有摻雜中間層的金屬半導體接觸在不同主體中的剖面圖；第12圖係實施例中形成具有摻雜中間層的金屬半導體接觸的方法之流程圖。
以下公開許多不同的實施方法或是例子來實行本發明之不同特徵，以下描述具體的元件及其排列的例子以闡述本發明。當然這些僅是例子且不該以此限定本發明的範圍。例如，在描述中提及第一個元件形成一第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其他元件形成於第一個與第二個元件之間的實施例，其中第一個元件與第二個元件並未直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在…之下”、“在下方”、“低的”、“在…之上”、“上面的”及類似的用詞，這些關係詞係為了便於描述圖示中一個元件或特徵與另一個(一些)元件或特徵之間的關係，這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
主動元件形成於半導體基底上有時會由設置於介電層或半導體層(像是層間介電層(ILD)或是類似的材料)之中的金屬栓塞或接觸提供電性連接，依據金屬及半導體材料，金屬接觸接觸到半導體層的地方形成蕭基特接合(Schottky junction)或屏障(Schottky barrier)，而半導體晶體結構被金屬表面終止導致的費米能階釘扎(Fermi-level pinning)使得蕭基特屏障產生整流接觸。
本發明揭露一種形成具有摻雜中間層的金屬-半導體接觸之方法，本發明發現具有氟摻雜金屬氧化物外部中間層的接觸，能夠降低費米能階釘扎，也能減少通道穿過中間層-半導體屏障的電阻，降低的費米能階釘扎及穿隧電阻允許接觸接面有較少的電流電阻及電流下降。本發明也發現在一些實施例中，摻雜金屬氧化物中間層係利用蝕刻層間介電層產生的副產物或利用電漿摻雜進行的，其使得較不需退火及移動摻質至層間介電層及半導體層。此外，利用蝕刻步驟產生的副產物減少了在蝕刻後清洗層間介電層及半導體表面的需要，增加了主動元件在製造過程中的產能。
第1圖係實施例中基底104與絕緣層106的剖面圖， 基底104係半導體材料像是矽、砷化鎵、矽化鍺、碳化矽、磷化矽或其他半導體材料，例如在一些實施例中，基底104係晶圓、主動元件、絕緣底半導體層(semiconductor-on-insulator layer)、應變層、磊晶層或其類似物。目標區102設置於基底中，目標區102為基底104的一部分，係接著形成的金屬半導體接觸與基底104接觸的位置且提供電性連接，根據形成於基底104上的結構，目標區102的用途、材料及結構會有所不同，例如在一實施例中，橫向電晶體形成於基底104之上，目標結構為源極、汲極，或目標區係基底主體的一部分，例如：接觸提供一基底接地。在另一些實施例中，鰭式場效電晶體(FinFET)形成於基底104之上，且目標區102為凸起的鰭之源極或汲極，或雙極性接面電晶體形成於基底中，目標區102為射極、集極或基極。同樣地，二極體形成在基底104中，目標區102為二極體的陽極或陰極。應理解的是，於此揭露的實施例並非限定於一特定結構，且能應用至任何金屬-半導體(metal-to-semiconductor)接面，此外，在一些實施例中，基底104係晶片、晶粒晶圓或其他半導體結構。
絕緣層106形成於基底104之上且覆蓋目標區102， 在一些實施例中，絕緣層106為氧化物、氮化物、氮氧化物、碳化物或其他絕緣材料，依據絕緣層材料，絕緣層106的形成藉由製程像是化學氣相沉積(chemical vapor deposition)、電漿加強式化學氣相沉積(plasma enhanced CVD)、低壓化學氣相沉積(low pressure CVD)、原子層沉積(atomic layer deposition)、 旋塗玻璃製程、熱氧化作用或其他沉積方法或形成製程。在一些實施例中，絕緣層106係層間介電層以一厚度形成，延展或覆蓋在設置於基底104上的結構上面，例如，一個或多個平面電晶體形成在基底上，為層間介電層的絕緣層106延展且覆蓋在電晶體的閘極結構上面，替後續形成的層提供大致平坦的表面。
第2圖係實施例中，在絕緣層106中蝕刻接觸開口 202的剖面圖，罩幕204形成於絕緣層106之上且圖案化絕緣層106暴露的部分。在一實施例中，罩幕204為硬罩幕，像是氮化物或其類似物，經沉積及蝕刻形成蝕刻圖案，在另一實施例中，罩幕204為抗蝕層，例如：經圖案化、曝光及顯影形成圖案的光阻。
絕緣層106經蝕刻貫穿絕緣層106而產生開口202， 開口202蝕穿絕緣層106以暴露至少一部份的目標區102，絕緣層106利用，例如：濕或乾蝕刻、濕或乾電漿蝕刻製程、離子蝕刻或其他蝕刻製程進行蝕刻。用於蝕刻絕緣層的反應物由絕緣層106的成分決定，在一些實施例中，二氧化矽(SiO2)絕緣層106以氟基(fluorine based)蝕刻劑，像是氟化氫(HF)進行蝕刻；或氮化矽(Si3N4)層以氟基或磷基蝕刻劑，像是磷酸(H3PO4)進行蝕刻。
在一些實施例中，絕緣層為，例如二氧化矽，實 行氧化蝕刻製程，上述製程比起矽，其對二氧化矽具有高度選擇性的蝕刻，在這類製程中，使用三氟化氮(NF3)及氨(NH3)的前驅物並利用電漿或射頻來源，遠距地產生氟化銨(NH4F)及二 氟化銨(NH4F.HF)蝕刻劑，請參見第1式。
1)NF3+NH3 → NH4F+NH4F.HF
上述蝕刻劑接著被用於蝕刻二氧化矽絕緣層106，請參見第2-3式。
2)NH4F+SiO2 → (NH4)2SiF6(固體)+H2O
3)NH4F.HF+SiO2 → (NH4)2SiF6(固體)+H2O
氧化蝕刻製程允許低溫蝕刻，例如約在20℃至50℃間，遠距的電漿產生之蝕刻劑提供具活性的蝕刻劑，且不因電漿對基底104造成損害。
第3圖係實施例中蝕刻基底104後產生開口202之剖面圖，罩幕204(參見第2圖)從絕緣層106被移除，在一些實施例中，蝕刻製程留下一殘留物或副產物302，例如，如上述第2式及第3式，氧化蝕刻製程產生六氟矽酸銨((NH4)2SiF6)副產物。蝕刻副產物302，在一些實施例中，會藉由退火或由刷洗、沖洗、蝕刻或其他清潔製程清理。
本發明發現在開口202的底部及側壁留下蝕刻副產物使得副產物能夠利用在之後的製程步驟中，例如在一些實施例中，蝕刻副產物302被用來至少部分地摻雜至後續沉積的層，因此，可選擇蝕刻劑，讓其留下的蝕刻副產物302具有後續摻雜沉積層所需的摻質，這能夠避免用來移除蝕刻副產物302的清潔或退火步驟，進而增加製程速度及產能。
第4圖係實施例中形成中間層104的剖面圖，一金屬氧化物中間層402形成於絕緣層106上方及開口202中，中間層402至少配置在開口202的底部且與目標區102接觸，在一些 實施例中，中間層402與基底104的表面直接接觸於目標區102中。在另一些實施例中，額外的數層像是原始氧化層、蝕刻終止層、阻障層等被配置於基底及中間層402之間。在一些實施例中，實行清潔步驟以移除，例如：原始氧化層；或可藉由維持基底104的表面暴露於一真空或一不含氧氣或氧化劑的環境中，避免原始氧化層產生。
在一些實施例中，中間層402由金屬氧化物，像是 二氧化鈦(TiO2)、二氧化錫(SnO2)、氧化鋅(ZnO)或其他氧化物利用沉積技術，像是：原子層沉積(atomic layer deposition)、物理氣相沉積(physical vapor deposition)、化學氣相沉積(chemical vapor deposition)等形成。本發明發現二氧化鈦、二氧化錫、氧化鋅可由氟(F)進行摻雜且其提供了不可預期之效果，摻雜氟時，其降低基底半導體材料的費米能階釘扎的能帶間隙及減少中間層-基底接面的穿隧電阻。降低的費米能階釘扎藉由降低蕭基特屏障，提供中間層-基底接面更大的導電率，此外，經摻雜的中間層402提供了較小的穿隧電阻，允許更多的電子藉由穿隧而不藉由克服蕭基特屏障來通過上述接面，進而使得中間層-基底接面有更大的導電率。
在一實施例中，中間層402利用原子層沉積製程形 成，使中間層402的底部與目標區102接觸的部分厚度約為5Å至150Å，中間層402的厚度在開口202的側壁通常比在其底部小，而這樣的中間層底部厚度已知會產生能降低費米能階釘扎及穿隧電阻的摻雜濃度，因此，於中間層402及基底104之間產生了實質上的歐姆接觸，其不需矽化物或對基底104做其他修飾， 使得目標區102大致上不含有矽。原子層沉積製程沉積金屬層，接著金屬層被氧化，例如在一些實施例中，原子層沉積製程利用四二甲氨基鈦(TDMAT或C8H24N4Ti)、四氯化鈦(TiCl4)、鈦酸甲酯(Ti(OMe)4，Me為甲基基團)等，在溫度範圍約100℃至500℃作為鈦沉積的前驅物。二乙基鋅(DEZ或Zn(C2H5)2)或其類似物在溫度範圍約100℃至500℃作為鋅沉積的前驅物。或是二乙酸二丁基錫(DBTDA或(C4H9)2Sn(OOCCH3)2)、四氯化錫(SnCl4)、二氯化錫(SnCl2)或其類似物，在溫度範圍約50℃至500℃作為錫沉積的前驅物。在原子層沉積製程沉積金屬層後，該金屬層經氧化劑氧化，例如：氧(O2)、臭氧(O3)、水(H2O)或其他氧化劑，在一些實施例中，可重複原子層沉積製程建立中間層402至想要的厚度。
在另一些實施例中，中間層的形成係利用物理氣 相沉積或化學氣相沉積製程，例如：電漿加強式化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)、濺鍍、蒸氣氣相沉積(evaporative vapor deposition)等。在這類實施例中，金屬氧化物中間層402藉由沉積金屬接著氧化該金屬，或藉由沉積金屬氧化物而形成。
在一些實施例中，蝕刻副產物302(請參見第3圖) 不會藉由退火或清潔製程移除，而中間層402沉積於上述蝕刻副產物302上方，蝕刻副產物302與中間層402結合。例如，使用氧化蝕刻於絕緣層106中蝕刻開口202，六氟矽酸銨副產物302被留在開口202的表面，當金屬層形成於六氟矽酸銨副產物302上方時，六氟矽酸銨副產物302分解並與金屬層結合，六氟 矽酸銨副產物302的氟作為金屬層的摻質，並在氧化作用及接續的原子層沉積步驟持續存在於金屬層中，形成摻雜金屬氧化物中間層402。在一些實施例中，中間層402在相當低的溫度進行退火或是僅短暫地進行退火，驅使蝕刻副產物302的摻質與中間層402結合，且不大會摻雜至絕緣層106及基底104。本發明發現低溫或短暫地退火及趨入(drive in)能防止摻質移動至絕緣層106及基底104中。
第5圖係實施例中佈植摻質至中間層402的剖面圖， 中間層402由供給型(donor-type)摻質502進行摻雜，在一些實施例中，中間層402經由射頻電漿處理或電漿加強式化學氣相沉積摻雜，例如：氟或其類似物。例如在一實施例中，使用電漿製程其時間範圍約為5秒至500秒，其功率範圍約為50瓦特至2000瓦特，在約5sccm至500sccm的氣體流量的情況下，利用前驅物，例如：四氟化碳(CF4)或六氟乙烷(C2F6)，摻雜中間層402，在開口202的底部之金屬-半導體接觸區域，氟的摻雜濃度約為0.1%至15%。本發明發現以上述參數進行的摻雜反應使基底半導體材料的費米能階釘扎的能階及中間層-基底接面的穿隧電阻降低。此外，以電漿摻雜製程摻雜中間層402確保中間層402的摻雜大致上為均勻的，應注意的是，摻雜中間層402的側壁部分對中間層402及目標區102的接觸區域之特性沒有什麼影響，在一些實施例中，用來摻雜中間層402的摻質與用來摻雜目標區102或基底104的其他摻雜區域之摻質不同，更應注意的是，實施例中描述以氟摻雜中間層，但其他實施例可能包括一種或多種能降低費米能階釘扎及穿隧電阻的其他摻質， 且摻雜反應的參數也可能根據不同的摻質而有所調整。
第6圖係實施例中形成黏結層或黏著層602的剖面 圖，黏著層602藉由原子層沉積、化學氣相沉積、磊晶或其他沉積製程進行沉積，在一些實施例中，黏著層602由氮化鈦(TiN)或其他材料形成，其厚度約為10Å至40Å。
第7圖係實施例中以填充層形成栓塞702的剖面圖， 填充層沉積在開口202中且延展覆蓋在開口202上方(請參見第2圖至第6圖)使得開口202由導電材料所填充，上述導電材料可為金屬，例如：鎢(W)、銅(Cu)、金(Au)或其類似物，或為合金、多晶矽或其他導電材料。在一些實施例中，栓塞702藉由化學氣相沉積、物理氣相沉積、濺鍍或其他沉積製程沉積導電材料形成。在一些實施例中，晶種層形成於黏著層602上，而填充層藉電鍍、無電式電鍍或其他鍍覆製程形成，在此類實施例中，晶種層利用原子層沉積、化學氣相沉積等形成，且在沉積填充層時，晶種層會與填充層結合。
第8圖係實施例中接觸802平坦化的剖面圖，在一 些實施例中，部份的中間層402、黏著層602及栓塞702的平坦化係藉由，例如：化學機械平坦化(CMP)製程、蝕刻、機械性拋光、研磨製程或其他平坦化製程。在一些實施例中，絕緣層106也被平坦化以達到想要的厚度。所得到的接觸802之中間層402、黏著層602及栓塞702的頂表面大致為平坦的，或彼此間的頂表面為齊平的且與絕緣層106的頂表面也是齊平的。目標區102大致上不含有矽，此外，目標區102大致上也不含有用於摻雜中間層402之摻質。
第9圖係實施例中具有接觸802的平面電晶體主動 元件之剖面圖，在一些實施例中，絕緣層106為層間介電層，具有延伸通過絕緣層106的接觸802，且與基底104的源極/汲極區904接觸，平面電晶體也有閘極結構902，其具有，例如：介面層908、閘極介電質910及閘極接觸906。在一些實施例中，具有摻雜中間層的接觸802形成於閘極接觸906之上並且與閘極接觸906接觸。然而，在一些實施例中，閘極接觸906係由金屬合金或其他不會產生蕭基特接合接面的材料所形成。在一些實施例中，閘極結構902的接觸802沒有摻雜中間層，當結構有許多個半導體目標區904(像是源極及汲極)，多個接觸802可在單一製程中形成，在這類實施例中，每一個接觸802中的中間層402、黏著層602及栓塞702分別由單一層橫跨絕緣層106的多個開口而形成，而接著由化學機械平坦化等步驟平坦化該接觸而彼此分開(請參見，例如第8圖)。
第10圖係實施例中具有平面電晶體的組件，上述 平面電晶體具有接觸802，重分布層1002及一或多層的修整層(finishing layer)1004形成於層間介電層絕緣層106之上，重分布層1002有一或多個金屬元件1018配置於介電層1016中，金屬元件1018與接觸802接觸且提供接觸802與外部裝置之間的電性連接，在一些實施例中，修整層1004包括一或多層的鈍化層1014，鈍化層具有後鈍化內連線1010(post-passivation interconnects,PPIs)配置至於其上，且後鈍化內連線延伸通過鈍化層1014中的開口。一或多層的保護層1012配置於鈍化層1014之上，後鈍化內連線1010及底層凸塊金屬化結構1008及連 接器1006形成於保護層1012之上，且提供組件固定外部裝置及提供電性連接至外部裝置，像是晶粒、組件、中介層(interposer)、印刷電路板等，因此，接觸802與重分布層1002電性接觸且重分布層與連接器1006電性接觸。
第11A圖係實施例中具有接觸802的雙極接面電晶 體(bipolar junction transistor,BJT)裝置1100，雙極接面電晶體裝置具有形成於基底中的井1102，井1102形成射極1108、基極1106及集極1104，每一個井1102中至少有一接觸802形成，用以與井接觸及提供電性連接。
第11B圖係實施例中具有接觸802的鰭式場效電晶 體1120，鰭式場效電晶體有鰭片1122，鰭片具有源極/汲極區1124及通道區1126，閘極介電層1130及閘極接觸1128配置於鰭片1122的頂表面及側壁表面且環繞通道區，接觸802提供源極/汲極區1124電性連接，在一些實施例中，具有摻雜中間層的接觸802被作為閘極之接觸。
第12圖係實施例中方法1200之流程圖，其說明形 成具有摻雜中間層的接觸之結構。在步驟1202中絕緣層形成，絕緣層配置於具有一或多個目標區的基底上方；在步驟1204中絕緣層經罩幕及蝕刻，絕緣層經蝕刻形成一開口，上述開口暴露基底上的目標區，在一些實施例中，於步驟1206，任何蝕刻殘留物或副產物藉由清潔或退火製程去除；步驟1208中，中間層形成在絕緣層的開口中，在一些實施例中，於步驟1210，中間層經摻雜且摻雜中間層於步驟1212經退火處理，在一些實施例中，中間層，例如：藉由電漿佈植、藉由使用蝕刻殘留物或 副產物、藉由結合佈植及重複使用殘留物或其他技術，摻雜氟或其類似物。步驟1214中，黏著層形成於中間層之上，黏著層延展至絕緣層的開口中且與目標區接觸；步驟1216中，填充層填充絕緣層開口的剩餘部分形成栓塞；步驟1218中，栓塞、黏著層及中間層被平坦化；接著步驟1220中，形成內連線層及修整層，像是重分布層、鈍化層及相關的內連線，在一些實施例中，於步驟1220，一或多個連接器形成在修整層上方，使得基底連結至組件、載體、印刷電路板、晶粒等，就像，例如：三維積體電路、垂直堆疊封裝、覆晶排列等。此外，在一些實施例中，形成修整層後，基底會經單粒化、測試及封裝。
前述內文概述了許多實施例的特徵，使本技術領 域中具有通常知識者可以更佳的了解本發明的各個方面。本技術領域中具有通常知識者應該可理解，他們可以很容易的以本發明為基礎來設計或修飾其它製程及結構，並以此達到相同的目的及/或達到與本發明介紹的實施例相同的優點。本技術領域中具有通常知識者也應該了解這些相等的結構並不會背離本發明的發明精神與範圍。本發明可以作各種改變、置換、修改而不會背離本發明的發明精神與範圍。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1200‧‧‧形成具有摻雜中間層的接觸之方法
1202~1220‧‧‧形成具有摻雜中間層的接觸之方法步驟

Claims (10)

  1. 一種半導體裝置的形成方法，包括：在一半導體基底的一頂表面上形成一絕緣層，其中一目標區設置在該半導體基底的該頂表面；蝕穿該絕緣層形成一開口，上述開口暴露該目標區的一部分頂表面；在該開口中形成一摻雜金屬氧化物中間層，且與該目標區之該頂表面接觸；及以一金屬栓塞填充該開口的剩餘部分，上述摻雜金屬氧化物中間層設置於該金屬栓塞及該半導體基底之間。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中蝕穿該開口的步驟包括：產生一蝕刻的副產物於該開口的表面，該蝕刻的副產物包括一第一摻質，且其中形成該摻雜金屬氧化物中間層的步驟包括：形成一金屬氧化物中間層於該蝕刻副產物的上方，及其中蝕刻副產物中的該第一摻質至少部分地摻雜至該金屬氧化物中間層。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該摻雜金屬氧化物中間層的步驟包括：佈植一第一摻質至一金屬氧化物中間層中。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中形成該摻雜金屬氧化物中間層的步驟包括：由氧化錫、氧化鈦或氧化鋅其中之一形成該金屬氧化物中間層。
  5. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括：在形成該絕緣層之前，形成一電晶體於該半導體基底 之上，其中該目標區係該電晶體的一源極或一汲極。
  6. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該摻雜金屬氧化物中間層包括：形成一氟摻雜金屬氧化物中間層。
  7. 一種半導體裝置的形成方法，包括：在一半導體基底的一頂表面上形成一絕緣層，且至少有一主動元件形成於上述半導體基底中，其中該至少一主動元件的一目標區設置在該半導體基底的該頂表面；蝕穿該絕緣層形成一開口，上述開口暴露該目標區的一部分頂表面；在該開口中形成一金屬氧化物中間層，且與該目標區接觸；以一第一摻質對該金屬氧化物中間層進行摻雜；在該開口中形成一黏著層，且設置於該金屬氧化物中間層之上；在該開口中形成一金屬栓塞，且形成於該黏著層之上，該摻雜金屬氧化物中間層設置於該金屬栓塞及該半導體基底之間；及在該絕緣層的頂表面上方形成一重分布層(redistribution layer)，該重分布層的一金屬元件與該金屬栓塞電性接觸。
  8. 一種半導體裝置，包括：一絕緣層，設置於一半導體基底上方，及有一開口延伸穿過該絕緣層，該基底的一第一表面設置在該開口的一底部； 一接點的一中間層，設置在該開口中且具有一第一部分與該基底的第一表面接觸；及該接點的一金屬栓塞，設置在該開口中，該中間層分隔該金屬栓塞和該基底的第一表面；其中該中間層包括一摻雜氧化物。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該中間層包括一摻雜金屬氧化物；該摻雜金屬氧化物的金屬氧化物係氧化錫、氧化鈦或氧化鋅其中之一；該摻雜金屬氧化物係經氟摻雜；該摻雜金屬氧化物的摻雜濃度大約為0.1%至15%。
  10. 如申請專利範圍第8項所述之半導體裝置，更包括一重分布層(RDL)，該重分布層有至少一金屬元件與該金屬栓塞電性連接。
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