TW201535510A - Fine pattern forming method, semiconductor device manufacturing method, substrate processing device, and recording medium - Google Patents

Fine pattern forming method, semiconductor device manufacturing method, substrate processing device, and recording medium Download PDF

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TW201535510A
TW201535510A TW104101311A TW104101311A TW201535510A TW 201535510 A TW201535510 A TW 201535510A TW 104101311 A TW104101311 A TW 104101311A TW 104101311 A TW104101311 A TW 104101311A TW 201535510 A TW201535510 A TW 201535510A
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film
gas
etching
forming
substrate
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TW104101311A
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Satoshi Shimamoto
Jiro Yugami
Yoshiro Hirose
Toshiyuki Kikuchi
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Hitachi Int Electric Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

In order to provide a technique for highly selectively etching a first film mainly consisting of silicon with respect to a second film having a lower silicon content than the first film, a fine pattern forming method includes: the first film mainly consisting of silicon and the second film having a lower silicon content than the first film. In the etching step, the first film is removed until the etching gas reaches the film forming the channels formed of the same type of film as the second film.

Description

微細圖案的形成方法、半導體裝置的製造方法、基板處理裝置及記錄媒體 Method for forming fine pattern, method for manufacturing semiconductor device, substrate processing device, and recording medium

本發明是有關使用利用特定的處理氣體的蝕刻技術之微細圖案形成方法,半導體裝置的製造方法,基板處理裝置及記錄媒體。 The present invention relates to a fine pattern forming method using an etching technique using a specific processing gas, a method of manufacturing a semiconductor device, a substrate processing apparatus, and a recording medium.

在半導體裝置中,為了謀求更進一步的高集成化,而圖案的微細化跟著進展。為了實現微細圖案,而檢討了使用蝕刻工程的各種手法(例如參照專利文獻1)。在活用該等的手法之下,可形成具有極細的溝或柱的圖案。 In the semiconductor device, in order to achieve further high integration, the miniaturization of the pattern has progressed. In order to realize a fine pattern, various methods using an etching process have been examined (for example, refer to Patent Document 1). Under the use of these methods, a pattern having extremely fine grooves or columns can be formed.

近年來,以NAND快閃記憶體為代表的快閃記憶體,基於加工面、電氣特性面的雙方的點,難以繼續微細化。於是相較於以往在2D上的元件尺寸的微細化之位元集成度提升的研究,可緩和元件尺寸的微細化的3D構造的NAND快閃記憶體的開發正進展。 In recent years, flash memory represented by NAND flash memory is difficult to continue to be finer based on the points of both the processed surface and the electrical characteristic surface. In the past, the development of the NAND flash memory of the 3D structure which can reduce the size of the device is progressing, as compared with the conventional research on the improvement of the integration of the elements in the 2D.

在3D構造的裝置的製造中,以往的反應性離子蝕刻,難以對於多晶矽以外的膜(例如,矽氧化膜、矽 氮化膜、矽氧氮化膜、碳膜等)高選擇除去多晶矽(Poly-Si)膜。亦即,在多晶矽膜與SiO2膜的層疊構造穿過貫通溝後露出於側壁的多晶矽膜及SiO2膜的層之中,使用反應性離子蝕刻時,基於與SiO2膜等的選擇性的問題或需要各向同性蝕刻的點,只蝕刻多晶矽膜是非常困難。並且,也有與硬質遮罩膜(例如碳膜等)的選擇性的問題。 In the manufacture of a device having a 3D structure, conventional reactive ion etching is difficult to selectively remove polysilicon (Poly) for a film other than polysilicon (for example, a tantalum oxide film, a hafnium nitride film, a hafnium nitride film, a carbon film, or the like). -Si) film. In other words, when the laminated structure of the polycrystalline germanium film and the SiO 2 film passes through the through-groove and is exposed to the polycrystalline germanium film and the SiO 2 film of the sidewall, the selectivity with the SiO 2 film or the like is used when reactive ion etching is used. The problem or the point of isotropic etching is very difficult to etch only the polysilicon film. Further, there is a problem of selectivity with a hard mask film (for example, a carbon film).

又,以醋酸稀釋氟硝酸後的蝕刻液等的矽的溼蝕刻,因表面張力的問題,會有圖案倒塌等的問題。特別是當寬與溝的比(寬高比)為10以上時,此圖案倒塌會變顯著。 Further, the wet etching of the ruthenium or the like after the fluorinated nitric acid is diluted with acetic acid causes a problem such as collapse of the pattern due to the problem of surface tension. In particular, when the ratio of the width to the groove (the aspect ratio) is 10 or more, the pattern collapse becomes remarkable.

如此,以往的反應性離子蝕刻或溼蝕刻是在上述矽通道的側壁露出多晶矽膜及SiO2膜那樣的圖案形狀中,無法進行適當的蝕刻。此結果,會有發生具有3D構造的NAND快閃記憶體的半導體裝置的製造良品率降低的情況。 As described above, in the conventional reactive ion etching or wet etching, in the pattern shape in which the polycrystalline germanium film and the SiO 2 film are exposed on the sidewall of the meandering channel, appropriate etching cannot be performed. As a result, there is a case where the manufacturing yield of the semiconductor device in which the NAND flash memory having the 3D structure occurs is lowered.

〔先行技術文獻〕 [prior technical literature] 〔專利文獻〕 [Patent Document]

〔專利文獻1〕日本特開2011-44493 [Patent Document 1] Japanese Special Open 2011-44493

本發明的目的是在於提供一種使用對於含矽 率比第1膜更少的膜的第2膜高選擇蝕刻以矽為主成分的第1膜之技術的微細圖案的形成方法、半導體裝置的製造方法、基板處理裝置及記錄媒體。 The object of the present invention is to provide a use for bismuth A method of forming a fine pattern of a technique of a first film containing ruthenium as a main component, a method of forming a semiconductor device, a substrate processing apparatus, and a recording medium are selected from a second film having a lower rate than a film of the first film.

若根據本發明之一形態,則可提供一種微細圖案形成方法,其係具有:在包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜之層疊膜中設置複數的第一孔而形成第1微細圖案之工程;分別在前述複數的第一孔中形成通道之後,在前述各通道間設置第二孔而形成第2微細圖案之工程;及除去與前述第二孔鄰接的前述第1膜之工程。 According to one aspect of the present invention, there is provided a fine pattern forming method comprising: a first film comprising ruthenium as a main component; and a laminate film comprising a second film having a lower enthalpy ratio than the first film a process of forming a first fine pattern by providing a plurality of first holes; forming a second fine pattern between the respective channels after forming a channel in the plurality of first holes; and removing the The first film is adjacent to the second hole.

若根據上述的構成,則可提供一種對於以矽為主成分的第1膜,對於含矽率比前述第1膜更少的膜的第2膜,高選擇蝕刻的技術。 According to the above configuration, it is possible to provide a technique for selectively etching a second film having a film having a lower enthalpy ratio than the first film, for the first film containing ruthenium as a main component.

1‧‧‧Si基板 1‧‧‧Si substrate

2‧‧‧Si3N42‧‧‧Si 3 N 4 film

3‧‧‧SiO23‧‧‧SiO 2 film

4‧‧‧Poly-Si膜 4‧‧‧Poly-Si film

5‧‧‧碳硬質遮罩(CHM)膜 5‧‧‧Carbon hard mask (CHM) film

6‧‧‧SiO26‧‧‧SiO 2 film

7‧‧‧Si3N47‧‧‧Si 3 N 4 film

8‧‧‧SiO28‧‧‧SiO 2 film

9‧‧‧ONO膜 9‧‧‧ONO film

10‧‧‧Poly-Si膜 10‧‧‧Poly-Si film

11‧‧‧碳硬質遮罩(CHM)膜 11‧‧‧Carbon hard mask (CHM) film

12‧‧‧鎢(W)膜 12‧‧‧Tungsten (W) film

13‧‧‧貫通孔(第一孔) 13‧‧‧through hole (first hole)

14‧‧‧溝(第二孔) 14‧‧‧Ditch (second hole)

15‧‧‧(矽)除去部 15‧‧‧(矽)Removal Department

20‧‧‧基板處理裝置 20‧‧‧Substrate processing unit

30‧‧‧處理容器 30‧‧‧Processing container

31‧‧‧容器本體 31‧‧‧ container body

32‧‧‧蓋體 32‧‧‧ Cover

39‧‧‧基板搬送容器 39‧‧‧Substrate transfer container

50‧‧‧處理室 50‧‧‧Processing room

60‧‧‧晶圓(基板) 60‧‧‧ Wafer (substrate)

100‧‧‧EFEM 100‧‧‧EFEM

105‧‧‧淋浴頭 105‧‧‧ shower head

106(106a,106b)‧‧‧氣體供給管線 106 (106a, 106b) ‧ ‧ gas supply pipeline

107‧‧‧排氣口 107‧‧‧Exhaust port

104‧‧‧支撐銷 104‧‧‧Support pin

108‧‧‧搬送口 108‧‧‧Transportation port

110‧‧‧FOUP 110‧‧‧FOUP

112‧‧‧惰性氣體供給管 112‧‧‧Inert gas supply pipe

114‧‧‧管狀路 114‧‧‧Tube Road

115(115a,115b)‧‧‧氣體供給管 115 (115a, 115b) ‧ ‧ gas supply pipe

116(116a,116b)‧‧‧MFC 116 (116a, 116b) ‧‧MFC

117(117a,117b)‧‧‧氣體供給源 117 (117a, 117b) ‧ ‧ gas supply

120‧‧‧裝載埠 120‧‧‧Loading

121‧‧‧MFC 121‧‧‧MFC

122‧‧‧惰性氣體供給源 122‧‧‧Inert gas supply

124‧‧‧支撐軸 124‧‧‧Support shaft

130‧‧‧大氣搬送機器人 130‧‧‧Atmospheric transport robot

131‧‧‧鑷子 131‧‧‧镊子

140‧‧‧基板搬送室 140‧‧‧Substrate transfer room

142‧‧‧排氣管 142‧‧‧Exhaust pipe

200‧‧‧裝載鎖定腔室部 200‧‧‧Load lock chamber

210‧‧‧緩衝單元 210‧‧‧buffer unit

211‧‧‧晶舟 211‧‧‧ Boat

212‧‧‧索引裝配 212‧‧‧ index assembly

220‧‧‧緩衝單元 220‧‧‧buffer unit

221‧‧‧晶舟 221‧‧‧ Boat

222‧‧‧索引裝配 222‧‧‧ index assembly

250,260‧‧‧裝載鎖定腔室 250,260‧‧‧Load lock chamber

300‧‧‧傳送模組部 300‧‧‧Transport Module Department

310‧‧‧傳送模組 310‧‧‧Transmission module

311~314‧‧‧閘閥 311~314‧‧‧ gate valve

320‧‧‧真空搬送機器人 320‧‧‧Vacuum transport robot

321‧‧‧手指 321‧‧‧ fingers

400‧‧‧製程腔室部 400‧‧‧Processing chamber

410‧‧‧第1處理單元 410‧‧‧1st processing unit

411‧‧‧基座平台 411‧‧‧Base platform

413‧‧‧昇降銷 413‧‧‧lifting pin

414‧‧‧支撐部 414‧‧‧Support

430‧‧‧氣體緩衝室 430‧‧‧ gas buffer room

431‧‧‧壁 431‧‧‧ wall

432‧‧‧外側屏蔽 432‧‧‧Outside shielding

433‧‧‧氣體導入口 433‧‧‧ gas inlet

445‧‧‧處理室 445‧‧‧Processing room

446‧‧‧側壁 446‧‧‧ side wall

448‧‧‧底板 448‧‧‧floor

453‧‧‧O型環 453‧‧‧O-ring

454‧‧‧頂板 454‧‧‧ top board

454a‧‧‧蓋部 454a‧‧ ‧ cover

454b‧‧‧支撐部 454b‧‧‧Support

458‧‧‧擋環 458‧‧ ‧ retaining ring

459‧‧‧基座 459‧‧‧Base

461‧‧‧支柱 461‧‧‧ pillar

463‧‧‧加熱器 463‧‧‧heater

464‧‧‧基座冷卻劑流路 464‧‧‧Base coolant flow path

465‧‧‧排氣板 465‧‧‧Exhaust plate

467‧‧‧導軸 467‧‧‧Guide axis

469‧‧‧底板 469‧‧‧floor

471‧‧‧昇降板 471‧‧‧ lifting plate

472‧‧‧昇降軸 472‧‧‧ lifting shaft

473‧‧‧昇降驅動部 473‧‧‧ Lifting and Driving Department

474‧‧‧第1排氣室 474‧‧‧1st exhaust chamber

475‧‧‧排氣連通孔 475‧‧‧Exhaust communication hole

476‧‧‧第2排氣室 476‧‧‧2nd exhaust chamber

479‧‧‧壓力調整閥 479‧‧‧Pressure adjustment valve

480‧‧‧排氣管 480‧‧‧Exhaust pipe

481‧‧‧排氣泵 481‧‧‧Exhaust pump

482‧‧‧第1氣體供給單元(第1氣體供給部) 482‧‧‧1st gas supply unit (first gas supply unit)

482a‧‧‧氣體供給管 482a‧‧‧ gas supply pipe

482b‧‧‧第1氣體源 482b‧‧‧1st gas source

482c,482g‧‧‧質量流控制器 482c, 482g‧‧‧ mass flow controller

482d,482h‧‧‧開閉閥 482d, 482h‧‧‧Opening and closing valve

482e‧‧‧惰性氣體供給管 482e‧‧‧Inert gas supply pipe

482f‧‧‧惰性氣體源 482f‧‧‧Inert gas source

483‧‧‧第2氣體供給單元(第2氣體供給部) 483‧‧‧second gas supply unit (second gas supply unit)

483a‧‧‧氣體供給管 483a‧‧‧ gas supply pipe

483b‧‧‧第2氣體源 483b‧‧‧2nd gas source

483c‧‧‧質量流控制器 483c‧‧‧Quality Flow Controller

483d‧‧‧開閉閥 483d‧‧‧Opening and closing valve

484‧‧‧淋浴板 484‧‧‧ shower panel

484a‧‧‧板部 484a‧‧‧ Board

484b‧‧‧孔部 484b‧‧‧ Hole Department

485‧‧‧加熱器溫度控制部 485‧‧‧Heating Temperature Control Department

486‧‧‧冷卻劑流量控制部 486‧‧‧ coolant flow control department

487‧‧‧加熱器電力供給線 487‧‧‧heater power supply line

488‧‧‧溫度檢測部 488‧‧‧ Temperature Detection Department

489‧‧‧外部冷卻劑流路 489‧‧‧External coolant flow path

491‧‧‧冷卻劑供給單元 491‧‧‧ coolant supply unit

492‧‧‧冷卻劑溫度檢測部 492‧‧‧ coolant temperature detection department

510‧‧‧第2處理單元 510‧‧‧2nd processing unit

511‧‧‧基座平台 511‧‧‧Base platform

600‧‧‧控制器(控制部) 600‧‧‧Controller (Control Department)

600a‧‧‧CPU 600a‧‧‧CPU

600b‧‧‧RAM 600b‧‧‧RAM

600c‧‧‧記憶裝置 600c‧‧‧ memory device

600d‧‧‧I/O埠 600d‧‧‧I/O埠

600e‧‧‧內部匯流排 600e‧‧‧Internal bus

601‧‧‧輸出入裝置 601‧‧‧Input and output device

602‧‧‧外部記憶裝置 602‧‧‧External memory device

P‧‧‧真空泵 P‧‧‧vacuum pump

V‧‧‧APC閥 V‧‧‧APC valve

圖1是本發明的實施形態的基板處理裝置的概略橫剖面圖。 Fig. 1 is a schematic cross-sectional view showing a substrate processing apparatus according to an embodiment of the present invention.

圖2是本發明的實施形態的基板處理裝置的概略縱剖 面圖。 Fig. 2 is a schematic longitudinal sectional view of a substrate processing apparatus according to an embodiment of the present invention; Surface map.

圖3是本發明的實施形態的基板處理裝置所具有的第1處理單元的縱剖面圖。 3 is a longitudinal cross-sectional view showing a first processing unit included in the substrate processing apparatus according to the embodiment of the present invention.

圖4是第1處理單元所具有的基座的縱剖面圖。 4 is a longitudinal cross-sectional view of a susceptor included in the first processing unit.

圖5是表示本發明的實施形態的半導體裝置作成的一工程之微細圖案形成處理的流程圖。 Fig. 5 is a flowchart showing a fine pattern forming process of a process of the semiconductor device according to the embodiment of the present invention.

圖6是本發明的實施形態的控制器的構造圖。 Fig. 6 is a configuration diagram of a controller according to an embodiment of the present invention.

圖7是表示本發明的實施形態的第1微細圖案形成處理的第1階段的圖。 FIG. 7 is a view showing a first stage of the first fine pattern forming process in the embodiment of the present invention.

圖8是表示本發明的實施形態的第1微細圖案形成處理的第2階段的圖。 8 is a view showing a second stage of the first fine pattern forming process in the embodiment of the present invention.

圖9是表示本發明的實施形態的第2微細圖案形成處理的第1階段的圖。 FIG. 9 is a view showing a first stage of the second fine pattern forming process in the embodiment of the present invention.

圖10是表示本發明的實施形態的第2微細圖案形成處理的第2階段的圖。 FIG. 10 is a view showing a second stage of the second fine pattern forming process in the embodiment of the present invention.

圖11是表示本發明的實施形態的第3微細圖案形成處理的圖。 Fig. 11 is a view showing a third fine pattern forming process in the embodiment of the present invention.

圖12是表示本發明的實施形態的第4微細圖案形成處理的第1階段的圖。 FIG. 12 is a view showing a first stage of the fourth fine pattern forming process in the embodiment of the present invention.

圖13是表示本發明的實施形態的第4微細圖案形成處理的第2階段的圖。 Fig. 13 is a view showing a second stage of the fourth fine pattern forming process in the embodiment of the present invention.

圖14是表示本發明的實施形態的第1處理單元(第2處理單元)的處理流程的圖。 FIG. 14 is a view showing a processing flow of a first processing unit (second processing unit) according to the embodiment of the present invention.

圖15是表示在本發明的實施形態的基板處理裝置所 使用的蝕刻氣體的特性的圖。 Fig. 15 is a view showing a substrate processing apparatus according to an embodiment of the present invention; A graph of the characteristics of the etching gas used.

圖16是本發明的實施形態的基板處理裝置所具有的第3處理單元的縱剖面圖。 Fig. 16 is a longitudinal sectional view showing a third processing unit included in the substrate processing apparatus according to the embodiment of the present invention.

圖17是本發明的實施形態的基板處理裝置所具有的第3處理單元的縱剖面圖。 Fig. 17 is a longitudinal sectional view showing a third processing unit included in the substrate processing apparatus according to the embodiment of the present invention.

圖18是表示本發明的實施形態的第3處理單元的處理流程的圖。 Fig. 18 is a view showing a processing flow of a third processing unit according to the embodiment of the present invention.

發明者等發現為了解決上述課題,藉由進行使用至少含氟的蝕刻氣體的乾蝕刻,在一定的溫度領域中,至少對於氧化矽(SiO2)、氮化矽(Si3N4)、氮化鈦(TiN)、非晶形‧碳(a-C)等,可選擇性地除去以矽(Si)元素為主成分的Si膜。並且,發現藉由使用至少含氟的蝕刻氣體,可不使蝕刻氣體電漿化,維持高的選擇性來各向同性地除去以Si元素為主成分的Si膜。 The inventors have found that in order to solve the above problems, dry etching using an etching gas containing at least fluorine is used, at least for cerium oxide (SiO 2 ), cerium nitride (Si 3 N 4 ), and nitrogen in a constant temperature range. Titanium (TiN), amorphous ‧ carbon (aC), etc., can selectively remove Si films containing bismuth (Si) elements as a main component. Further, it has been found that by using at least a fluorine-containing etching gas, the etching gas can be plasma-free, and high selectivity can be maintained, and the Si film containing Si element as a main component can be isotropically removed.

在此,所謂以Si元素為主成分(以矽為主成分)的Si膜是例如Si元素為含90%以上的膜。另外,所謂「高選擇性」是意指使例如以矽為主成分的第1膜(例如矽膜)的蝕刻速率形成比含矽率少於第1膜的膜(例如矽氧化膜或矽氧氮化膜或矽氮化膜等)的第2膜更高。更佳是不蝕刻第2膜,蝕刻第1膜。 Here, the Si film containing Si as a main component (mainly ruthenium as a main component) is, for example, a film containing 90% or more of Si. In addition, "high selectivity" means that an etching rate of a first film (for example, a ruthenium film) containing ruthenium as a main component is formed to be smaller than a film having a ruthenium ratio lower than that of the first film (for example, a ruthenium oxide film or a ruthenium oxynitride). The second film of the film or the tantalum nitride film or the like is higher. More preferably, the first film is etched without etching the second film.

圖15是有關在本實施形態中所使用的蝕刻氣體之一的IF7(或IF5)氣體的蒸氣壓特性的圖。 Fig. 15 is a graph showing the vapor pressure characteristics of an IF 7 (or IF 5 ) gas which is one of the etching gases used in the present embodiment.

如圖15所示般,七氟化碘(IF7)(或五氟化碘(IF5))氣體是在後述的本實施形態的蝕刻處理條件C中,明顯成為氣體的條件。在如此的減壓下溫度為30℃~50℃的條件,IF7(或IF5)氣體是如上述般,可一面對於Si膜維持高的選擇性,一面對於Si膜各向同性蝕刻。 As shown in Fig. 15, the iodine heptafluoride (IF 7 ) (or iodine pentafluoride (IF 5 )) gas is a condition that becomes a gas in the etching treatment condition C of the present embodiment to be described later. Under the conditions of a temperature of 30 ° C to 50 ° C under such reduced pressure, the IF 7 (or IF 5 ) gas can be isotropically etched to the Si film while maintaining high selectivity to the Si film as described above.

在此,IF7氣體是可想像IF5氣體會從周知的製造過程產生作為副生成物。然而,在後述的蝕刻處理條件C那樣的減壓下,溫度為30℃~50℃(較理想是30℃~40℃)的條件,與IF7氣體的蝕刻一起,作為上述副生成物生成的IF5氣體也為氣體,因此可想像不會有附著於基板上的情形可容易淨化。 Here, the IF 7 gas is conceivable as an IF 5 gas which is produced as a by-product from a well-known manufacturing process. However, under the reduced pressure such as the etching treatment condition C to be described later, the temperature is 30 ° C to 50 ° C (preferably 30 ° C to 40 ° C), and is generated as the by-product together with the etching of the IF 7 gas. The IF 5 gas is also a gas, so it is conceivable that it can be easily purified without being attached to the substrate.

另外,為了除去作為副生成物的IF5氣體,如圖15所示般將基板溫度加熱至100℃以上為理想。因此,若考慮副生成物除去,則在從處理室排除蝕刻氣體的淨化工程中,使溫度上昇為理想。 Further, in order to remove the IF 5 gas as a by-product, it is preferable to heat the substrate temperature to 100 ° C or higher as shown in FIG. 15 . Therefore, in consideration of the removal of the by-product, the temperature is preferably increased in the purification process in which the etching gas is removed from the processing chamber.

1.基板處理裝置的構成 1. Composition of the substrate processing apparatus

以下,參照圖面來說明本發明的實施形態的基板處理裝置。在本實施形態中,基板處理裝置之一例是構成實施半導體裝置(IC:Integrated Circuit)的製造方法的處理工程之半導體製造裝置。並且,本實施形態的基板處理裝置是構成可在1個的處理室對1片的基板進行蝕刻處理之單片式裝置。圖1是本發明的實施形態的基板處理裝置的概略橫剖面圖。圖2是本發明的實施形態的基板處理裝置 的概略縱剖面圖。 Hereinafter, a substrate processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an example of the substrate processing apparatus is a semiconductor manufacturing apparatus that constitutes a process for performing a manufacturing method of a semiconductor device (IC: Integrated Circuit). Further, the substrate processing apparatus of the present embodiment is a one-chip device that can etch one substrate in one processing chamber. Fig. 1 is a schematic cross-sectional view showing a substrate processing apparatus according to an embodiment of the present invention. 2 is a substrate processing apparatus according to an embodiment of the present invention; A schematic longitudinal section of the diagram.

如圖1,圖2所示般,基板處理裝置20是具備:EFEM(Equipment Front End Module)100,裝載鎖定腔室部200,傳送模組部300,及含進行蝕刻處理的處理室的製程腔室部400。 As shown in FIG. 1 and FIG. 2, the substrate processing apparatus 20 includes an EFEM (Equipment Front End Module) 100, a load lock chamber unit 200, a transfer module unit 300, and a process chamber including a processing chamber for performing an etching process. Room 400.

另外,將圖1的x方向或y方向稱為橫方向,將圖2的z方向稱為縱方向。而且,在本實施形態中,xy面是與水平面平行,z方向是鉛直方向。 In addition, the x direction or the y direction of FIG. 1 is referred to as a horizontal direction, and the z direction of FIG. 2 is referred to as a vertical direction. Further, in the present embodiment, the xy plane is parallel to the horizontal plane, and the z direction is the vertical direction.

EFEM100是具備:載置FOUP(Front Opening Unified Pod)110的裝載埠120,及在裝載埠120上的FOUP110與裝載鎖定腔室250,260之間搬送作為基板的晶圓60之第1搬送部的大氣搬送機器人130。在此,有關基板(晶圓60)的詳細後述。 The EFEM 100 includes a loading cassette 120 on which a FOUP (Front Opening Unified Pod) 110 is placed, and a first conveying unit that transfers the first transfer unit of the wafer 60 as a substrate between the FOUP 110 on the loading cassette 120 and the load lock chambers 250 and 260. The atmospheric transfer robot 130. Here, the details of the substrate (wafer 60) will be described later.

在基板收容器的FOUP110中可收容晶圓60至25片。收容未處理基板的FOUP110是藉由裝置外部的搬送手段來載置於裝載埠120上,且收容處理完成基板的FOUP110是藉由裝置外部的搬送手段來從裝載埠120上搬出。 60 to 25 wafers can be accommodated in the FOUP 110 of the substrate container. The FOUP 110 accommodating the unprocessed substrate is placed on the loading cassette 120 by means of a conveying means outside the apparatus, and the FOUP 110 accommodating the processed substrate is carried out from the loading cassette 120 by means of a conveying means outside the apparatus.

大氣搬送機器人130是具有5個的鑷子131,同時可搬送5片的晶圓60。大氣搬送機器人130是可在圖1的xy面水平旋轉至箭號D1方向,且可在箭號D2方向(yy'方向)水平移動。而且,大氣搬送機器人130的鑷子131是可在圖2的箭號D4方向(zz'方向)昇降,且可在圖1的箭號D3方向(xx'方向)進退。 The atmospheric transfer robot 130 has five dice 131 and can transport five wafers 60 at the same time. The atmospheric transfer robot 130 is horizontally rotatable to the arrow D1 direction on the xy plane of FIG. 1 and horizontally movable in the arrow D2 direction (yy ' direction). Further, the dice 131 of the atmospheric transfer robot 130 can be moved up and down in the direction of the arrow D4 (the zz ' direction) of FIG. 2, and can advance and retreat in the direction of the arrow D3 (xx ' direction) of FIG.

裝載鎖定腔室部200是具備裝載鎖定腔室250,260。裝載鎖定腔室250是具備:保持從FOUP110搬送的晶圓60之緩衝單元210。緩衝單元210是具備晶舟211及其下部的索引裝配212。晶舟211及其下部的索引裝配212是可在圖1的箭號D5方向水平旋轉。藉由此旋轉,可將晶舟211的基板出入口朝向大氣搬送機器人130或真空搬送機器人320。索引裝配212是使晶舟211昇降的昇降機構。 The load lock chamber portion 200 is provided with load lock chambers 250, 260. The load lock chamber 250 is provided with a buffer unit 210 that holds the wafer 60 transferred from the FOUP 110. The buffer unit 210 is an index assembly 212 having a boat 211 and a lower portion thereof. The wafer boat 211 and its lower index assembly 212 are horizontally rotatable in the direction of arrow D5 of FIG. By this rotation, the substrate entrance and exit of the boat 211 can be directed to the atmospheric transfer robot 130 or the vacuum transfer robot 320. The index assembly 212 is a lifting mechanism that lifts and lowers the boat 211.

裝載鎖定腔室260,及裝載鎖定腔室260內所具備的緩衝單元220,晶舟221,索引裝配222是分別具備與裝載鎖定腔室250,緩衝單元210,晶舟211,索引裝配212同樣的構造及機能。 The load lock chamber 260 and the buffer unit 220 provided in the load lock chamber 260, the wafer boat 221, and the index assembly 222 are respectively provided in the same manner as the load lock chamber 250, the buffer unit 210, the boat 211, and the index assembly 212. Construction and function.

晶舟211是可使水平姿勢的晶圓60彼此在縱方向(z方向)取間隔的狀態下積載至5片為止。 The wafer boat 211 is configured such that the wafers 60 in the horizontal posture can be stacked in five sheets in the longitudinal direction (z direction).

裝載鎖定腔室250是具備真空排氣裝置(未圖示),可根據來自後述的控制器600的指令,將裝載鎖定腔室250內形成預定壓力的真空狀態(亦即低壓狀態)或大氣壓狀態。 The load lock chamber 250 is provided with a vacuum exhaust device (not shown), and can be in a vacuum state (that is, a low pressure state) or an atmospheric pressure state in which a predetermined pressure is formed in the load lock chamber 250 in accordance with an instruction from a controller 600 to be described later. .

傳送模組部300是具備作為真空搬送室使用的傳送模組310,前述的裝載鎖定腔室250(260)是經由閘閥311(312)來安裝於傳送模組310。在傳送模組310中設有作為第2搬送部使用的真空搬送機器人320。真空搬送機器人320是在裝載鎖定腔室250,260與處理單元410,510之間搬送晶圓60。傳送模組部300內是經常維 持於預定壓力的真空狀態。 The transport module unit 300 includes a transport module 310 that is used as a vacuum transport chamber. The load lock chamber 250 (260) is attached to the transport module 310 via a gate valve 311 (312). The transport module 310 is provided with a vacuum transfer robot 320 that is used as the second transport unit. The vacuum transfer robot 320 transports the wafer 60 between the load lock chambers 250, 260 and the processing units 410, 510. The transmission module unit 300 is a regular dimension Hold the vacuum under a predetermined pressure.

製程腔室部400是具備進行蝕刻處理的處理單元410(510)。處理單元410(510)是經由閘閥313(314)來安裝於傳送模組310。處理單元410,510內是經常被維持於預定壓力的真空狀態。 The process chamber portion 400 is provided with a processing unit 410 (510) that performs an etching process. The processing unit 410 (510) is mounted to the transport module 310 via a gate valve 313 (314). The processing unit 410, 510 is in a vacuum state that is often maintained at a predetermined pressure.

基板處理裝置20更具有:電性連接至基板處理裝置20的各構成,亦即藉由電氣訊號來連接的控制器600。控制器600是控制各構成的動作。控制器600的構成是後述。 The substrate processing apparatus 20 further has a configuration electrically connected to the substrate processing apparatus 20, that is, a controller 600 connected by an electrical signal. The controller 600 is an operation for controlling each configuration. The configuration of the controller 600 will be described later.

在以上那樣構成的基板處理裝置20中,晶圓60會從裝載埠120上的FOUP110往大氣壓狀態的裝載鎖定腔室250(260)搬送。此時,首先,如圖2所示般,大氣搬送機器人130會將鑷子131挿入至FOUP110,同時將5片的晶圓朝鑷子131上載置。此時,對準取出的晶圓60的高度方向的位置,使大氣搬送機器人130的鑷子131上下。 In the substrate processing apparatus 20 configured as described above, the wafer 60 is transferred from the FOUP 110 on the cassette 120 to the load lock chamber 250 (260) in the atmospheric pressure state. At this time, first, as shown in FIG. 2, the atmospheric transfer robot 130 inserts the dice 131 into the FOUP 110, and simultaneously deposits five wafers on the dice 131. At this time, the position of the taken-out wafer 60 in the height direction is aligned, and the dice 131 of the atmospheric transfer robot 130 is moved up and down.

將晶圓60往鑷子131載置而從FOUP110取出之後,大氣搬送機器人130會旋轉至箭號D1方向,在大氣壓狀態的緩衝單元210(220)內的晶舟211(221)載置晶圓60。此時,藉由晶舟211(221)的Z方向的動作,晶舟211(221)會從大氣搬送機器人130接收5片的晶圓60。接收5片的晶圓60之後,以位於晶舟211(221)的最下層之晶圓60的位置能夠對準傳送模組部300的高度位置之方式,使晶舟211(221)在Z方向昇降 動作。 After the wafer 60 is placed on the die 131 and taken out from the FOUP 110, the atmospheric transfer robot 130 rotates to the direction of the arrow D1, and the wafer 211 (221) in the buffer unit 210 (220) of the atmospheric pressure state mounts the wafer 60. . At this time, the wafer boat 211 (221) receives the five wafers 60 from the atmospheric transfer robot 130 by the operation of the boat 211 (221) in the Z direction. After receiving five wafers 60, the position of the wafer 60 at the lowermost layer of the boat 211 (221) can be aligned with the height position of the transport module portion 300, so that the boat 211 (221) is in the Z direction. Lifting action.

其次,將裝載鎖定腔室250(260)內形成預定壓力的真空狀態之後,真空搬送機器人320會將保持於裝載鎖定腔室250(260)內的晶舟211(221)之晶圓60的其中1片的晶圓60移載至處理單元410(510)內的基座平台411(511)上。此時,真空搬送機器人320是將保持於晶舟211(221)的1片的晶圓60搭載於手指321,從晶舟211(221)取出之後,旋轉至箭號D7方向,更在箭號D8方向延伸手指321,移載至處理單元410(510)內的基座平台411(511)上。 Next, after the vacuum state in which the predetermined pressure is formed in the load lock chamber 250 (260), the vacuum transfer robot 320 will hold the wafer 60 of the wafer boat 211 (221) held in the load lock chamber 250 (260). One wafer 60 is transferred to the susceptor stage 411 (511) in the processing unit 410 (510). At this time, the vacuum transfer robot 320 mounts one wafer 60 held by the boat 211 (221) on the finger 321 and takes it out of the boat 211 (221), and then rotates it to the direction of the arrow D7, and further in the arrow The finger 321 is extended in the D8 direction and transferred to the base platform 411 (511) in the processing unit 410 (510).

將晶圓60從手指321往基座平台411(511)移載時,藉由手指321與昇降銷413的協調動作,晶圓60會被移載至基座平台411(511)上。詳細是一旦載置晶圓60的手指321移動至基座平台411(511)上的預定的位置,則昇降銷413會上昇,支撐被載置於手指321的晶圓60,而使能夠從手指321離開。昇降銷413支撐晶圓60之後,手指321會退縮至箭號D8方向。然後,藉由昇降銷413下降,晶圓60會被載置於基座平台411(511)上。 When the wafer 60 is transferred from the finger 321 to the base platform 411 (511), the wafer 60 is transferred to the base platform 411 (511) by the coordinated operation of the finger 321 and the lift pin 413. Specifically, when the finger 321 on which the wafer 60 is placed is moved to a predetermined position on the susceptor table 411 (511), the lift pin 413 is raised to support the wafer 60 placed on the finger 321 to enable the finger 321 left. After the lift pin 413 supports the wafer 60, the finger 321 will retract to the direction of the arrow D8. Then, by the lift pins 413 descending, the wafer 60 is placed on the base platform 411 (511).

將處理終了的晶圓60從基座平台411(511)往裝載鎖定腔室250(260)內的晶舟211(221)搬送時,真空搬送機器人320及昇降銷413(513)是進行與在上述基座平台411(511)上移載晶圓60的動作相反的動作。 When the processed wafer 60 is transferred from the susceptor table 411 (511) to the boat 211 (221) in the loading lock chamber 250 (260), the vacuum transfer robot 320 and the lift pins 413 (513) are The operation of transferring the wafer 60 on the susceptor platform 411 (511) is reversed.

如以上說明般,在基板處理裝置20中,晶圓60會從裝載埠120上的FOUP110往大氣壓狀態的裝載鎖定腔室250(260)搬送。然後,裝載鎖定腔室250(260)內會被抽真空(真空置換),從裝載鎖定腔室250(260)經由傳送模組310往處理單元410(510)搬送晶圓60。 As described above, in the substrate processing apparatus 20, the wafer 60 is transferred from the FOUP 110 on the cassette 120 to the load lock chamber 250 (260) in the atmospheric pressure state. Then, the load lock chamber 250 (260) is evacuated (vacuum replacement), and the wafer 60 is transferred from the load lock chamber 250 (260) to the processing unit 410 (510) via the transfer module 310.

然後,在作為第1處理單元的處理單元410(510)進行第1處理(蝕刻處理),被進行第1處理的晶圓60會經由傳送模組310來搬送至裝載鎖定腔室250(260)。然後,裝載鎖定腔室250(260)內的晶圓60會回到裝載埠120上的FOUP110。在此,被搬送至處理單元410(510)之前(處理前)的晶圓60(基板)是例如形成預定的微細圖案的基板為理想。特別是在本實施形態中,例如在交替層疊至少2層以上以矽為主成分的第1膜(多晶矽膜)及比第1膜更少含矽率的膜的第2膜(SiO2膜)之層疊膜中形成貫通孔,且在形成於前述貫通孔的通道間形成預定的溝圖案之基板為理想。 Then, the first processing (etching process) is performed on the processing unit 410 (510) as the first processing unit, and the wafer 60 subjected to the first processing is transferred to the load lock chamber 250 (260) via the transfer module 310. . The wafer 60 within the load lock chamber 250 (260) will then return to the FOUP 110 on the load cassette 120. Here, the wafer 60 (substrate) before being transported to the processing unit 410 (510) (before processing) is preferably a substrate on which a predetermined fine pattern is formed, for example. In particular, in the present embodiment, for example, at least two or more layers of a first film (polysilicon film) containing ruthenium as a main component and a second film (SiO 2 film) having a film having a lower enthalpy ratio than the first film are alternately laminated. It is preferable that a through-hole is formed in the laminated film, and a predetermined groove pattern is formed between the channels formed in the through-hole.

或者,亦可進行處理單元410的第1處理及處理單元510的第2處理的連續處理。在此,作為第2處理單元的處理單元510是亦可進行與處理單元410不同的處理,例如亦可在處理單元510進行第2處理(成膜處理)。此情況,被搬送至處理單元410(510)之前(處理前)的晶圓60(基板)是形成預定的微細圖案的基板為理想,但亦可為Si基板。 Alternatively, the first processing of the processing unit 410 and the continuous processing of the second processing of the processing unit 510 may be performed. Here, the processing unit 510 as the second processing unit may perform processing different from the processing unit 410. For example, the processing unit 510 may perform the second processing (film formation processing). In this case, the wafer 60 (substrate) before being transported to the processing unit 410 (510) (before processing) is preferably a substrate on which a predetermined fine pattern is formed, but may be a Si substrate.

或者,亦可在處理單元410進行第1處理(蝕刻處理),被進行蝕刻對象物的除去的晶圓60會經由傳送模組310搬送至處理單元510。然後,在處理單元510進行第2處理(成膜處理),被進行第2處理的晶圓60會經由傳送模組310再搬送至處理單元410。然後,在處理單元410進行第3處理(蝕刻處理),被進行第3處理的晶圓60會經由傳送模組310搬送至裝載鎖定腔室250(260),然後,亦可以能夠回到裝載埠120上的FOUP110之方式搬送。在此,亦可第1處理為無電漿的蝕刻處理,第3處理為電漿蝕刻處理。此情況,被搬送至處理單元410(510)之前(處理前)的晶圓60(基板)是可為形成預定的微細圖案的基板,或Si基板。 Alternatively, the processing unit 410 may perform the first processing (etching process), and the wafer 60 on which the etching target is removed may be transferred to the processing unit 510 via the transfer module 310. Then, the processing unit 510 performs the second processing (film formation processing), and the wafer 60 subjected to the second processing is transferred to the processing unit 410 via the transfer module 310. Then, the processing unit 410 performs a third process (etching process), and the wafer 60 subjected to the third process is transferred to the load lock chamber 250 (260) via the transfer module 310, and then can be returned to the load port. The FOUP110 on the 120 is transported. Here, the first treatment may be an etching treatment without plasma, and the third treatment may be a plasma etching treatment. In this case, the wafer 60 (substrate) before being transported to the processing unit 410 (510) (before processing) is a substrate that can form a predetermined fine pattern, or a Si substrate.

如此,在基板處理裝置20中,可為僅處理單元410的單獨處理,或使用處理單元410及處理單元510的連續處理。 As such, in the substrate processing apparatus 20, only the processing of the processing unit 410 alone or the continuous processing of the processing unit 410 and the processing unit 510 may be used.

(第1處理單元) (first processing unit)

利用圖3及圖4來說明有關第1處理單元410。圖3是本實施形態的基板處理裝置所具有的第1處理單元的縱剖面圖。圖4是第1處理單元所具有的基座的縱剖面圖。 The first processing unit 410 will be described with reference to FIGS. 3 and 4. 3 is a longitudinal cross-sectional view showing a first processing unit included in the substrate processing apparatus of the embodiment. 4 is a longitudinal cross-sectional view of a susceptor included in the first processing unit.

第1處理單元410是對半導體基板或半導體元件實施蝕刻的處理單元。如圖3所示般,處理單元410是具備:氣體緩衝室430,及收容半導體基板等的晶圓60的處理室445。處理單元410是例如在作為架台的水平的底板 448的上方配置氣體緩衝室430,在底板448的下方配置處理室445。 The first processing unit 410 is a processing unit that etches a semiconductor substrate or a semiconductor element. As shown in FIG. 3, the processing unit 410 is a processing chamber 445 including a gas buffer chamber 430 and a wafer 60 for accommodating a semiconductor substrate or the like. The processing unit 410 is, for example, a horizontal floor as a gantry A gas buffer chamber 430 is disposed above the 448, and a processing chamber 445 is disposed below the bottom plate 448.

氣體緩衝室430是從氣體導入口433供給處理氣體。氣體緩衝室430的壁431是以高純度的石英玻璃或陶瓷來形成筒狀。壁431是以該筒的軸線能夠形成垂直的方式配置。在壁431的上端是設有頂板454。頂板454是被壁431及外側屏蔽432的上端所支撐。氣體緩衝室430的上端是藉由頂板454來氣密地密封。 The gas buffer chamber 430 supplies a processing gas from the gas introduction port 433. The wall 431 of the gas buffer chamber 430 is formed into a cylindrical shape by high-purity quartz glass or ceramic. The wall 431 is configured such that the axis of the barrel can be formed vertically. At the upper end of the wall 431 is a top plate 454. The top plate 454 is supported by the upper ends of the wall 431 and the outer shield 432. The upper end of the gas buffer chamber 430 is hermetically sealed by the top plate 454.

頂板454是由堵塞壁431的上端的蓋部454a及支撐蓋部454a的支撐部454b所構成。在蓋部454a的大致中央是設有氣體導入口433。在壁431的前端的凸緣部分(從壁431突出至外側的部分)與支撐部454b之間設有O型環453,構成可使氣體緩衝室430形成氣密。 The top plate 454 is composed of a lid portion 454a that blocks the upper end of the wall 431 and a support portion 454b that supports the lid portion 454a. A gas introduction port 433 is provided substantially at the center of the lid portion 454a. An O-ring 453 is provided between the flange portion of the front end of the wall 431 (portion protruding from the wall 431 to the outside) and the support portion 454b, and the gas buffer chamber 430 is formed to be airtight.

處理室445的側壁446是以高純度的石英玻璃或陶瓷來形成筒狀。側壁446是以其筒的軸線能夠形成垂直的方式配置。在側壁446的上端是配置氣體緩衝室430的壁431。在側壁446的下端是配置底板469。側壁446是以能夠將處理室445內保持於氣密的方式,氣密地設在底板469的上側。 The side wall 446 of the processing chamber 445 is formed into a cylindrical shape by high-purity quartz glass or ceramic. The side wall 446 is configured such that its axis can be formed perpendicular. At the upper end of the side wall 446 is a wall 431 in which the gas buffer chamber 430 is disposed. At the lower end of the side wall 446 is a bottom plate 469. The side wall 446 is airtightly provided on the upper side of the bottom plate 469 so as to be able to keep the inside of the processing chamber 445 airtight.

在處理室445的下方是設有作為藉由複數(例如4根)的支柱461來支撐的基板載置部之基座459。在基座459具備:基座平台411,及設於基座459的內部,作為加熱基座459上的晶圓60的基板加熱部之加熱器463,及後述的基座冷卻劑流路464。 Below the processing chamber 445, a susceptor 459 as a substrate mounting portion supported by a plurality of (for example, four) pillars 461 is provided. The susceptor 459 includes a pedestal stage 411, a heater 463 provided inside the susceptor 459 as a substrate heating portion of the wafer 60 on the susceptor 459, and a susceptor coolant flow path 464 to be described later.

在基座459的下方配設有排氣板465。排氣板465是經由導軸467來支撐於底板469。昇降板471是設成以導軸467作為導件來昇降自如地作動。昇降板471是至少支撐3根的昇降銷413。 An exhaust plate 465 is disposed below the base 459. The exhaust plate 465 is supported by the bottom plate 469 via a guide shaft 467. The lifting plate 471 is provided to be movable up and down with the guide shaft 467 as a guide. The lift plate 471 is a lift pin 413 that supports at least three.

如圖3所示般,昇降銷413是貫通基座459的基座平台411。而且,在昇降銷413的頂設有支撐晶圓60的支撐部414。支撐部414是延伸出於基座459的中心方向。可藉由昇降銷413的昇降來將晶圓60載置於基座平台411,或從基座平台411舉起。 As shown in FIG. 3, the lift pin 413 is a base platform 411 that penetrates the base 459. Further, a support portion 414 that supports the wafer 60 is provided on the top of the lift pin 413. The support portion 414 is extended from the center direction of the base 459. The wafer 60 can be placed on the susceptor platform 411 by lifting up and down of the lift pins 413, or lifted from the pedestal platform 411.

昇降板471是被連結至貫通底板469的昇降軸472。昇降軸472是被連結至昇降驅動部473。在昇降驅動部473使昇降軸472昇降之下,支撐部414會經由昇降板471及昇降銷413來昇降。 The lift plate 471 is a lift shaft 472 that is coupled to the through bottom plate 469. The lifting shaft 472 is coupled to the elevation drive unit 473. When the elevation drive unit 473 raises and lowers the elevation shaft 472, the support portion 414 moves up and down via the lift plate 471 and the lift pin 413.

在基座459與排氣板465之間設有擋環(baffle ring)458。以擋環458,基座459及排氣板465來包圍的方式形成第1排氣室474。在圓筒狀的擋環458的側面均一地設有多數個通氣孔(未圖示)。因此,第1排氣室474是藉由擋環458來與處理室445隔開,且藉由通氣孔來與處理室445連通。 A baffle ring 458 is provided between the base 459 and the exhaust plate 465. The first exhaust chamber 474 is formed to surround the retaining ring 458, the base 459, and the exhaust plate 465. A plurality of vent holes (not shown) are uniformly provided on the side surface of the cylindrical retaining ring 458. Therefore, the first exhaust chamber 474 is separated from the processing chamber 445 by the retaining ring 458, and communicates with the processing chamber 445 through the vent hole.

並且,以排氣板465及凹型的底板469來包圍的方式形成第2排氣室476。而且,在排氣板465的中心部設有排氣連通孔475。因此,藉由排氣連通孔475來連通第1排氣室474及第2排氣室476。 Further, the second exhaust chamber 476 is formed to surround the exhaust plate 465 and the concave bottom plate 469. Further, an exhaust gas communication hole 475 is provided at a central portion of the exhaust plate 465. Therefore, the first exhaust chamber 474 and the second exhaust chamber 476 are connected by the exhaust communication hole 475.

(第1排氣部) (first exhaust unit)

以能夠貫通底板469的方式,設有延伸於重力方向,亦即z方向的排氣管480。第2排氣室476是與排氣管480連通。在排氣管480中,從上游依序設有壓力調整閥479,排氣泵481。 An exhaust pipe 480 extending in the direction of gravity, that is, the z direction, is provided so as to be able to penetrate the bottom plate 469. The second exhaust chamber 476 is in communication with the exhaust pipe 480. In the exhaust pipe 480, a pressure regulating valve 479 and an exhaust pump 481 are provided in this order from the upstream.

藉由如此在基座459的下方且重力方向設置排氣管480,被供給至處理室445的氣體不會留在處理室445容易排氣。因此,在保養人員的維修實施時,可降低與氣體的接觸所造成的危險度。 By thus providing the exhaust pipe 480 below the susceptor 459 and in the direction of gravity, the gas supplied to the process chamber 445 is not left in the process chamber 445 and is easily exhausted. Therefore, the risk of contact with the gas can be reduced during the maintenance of the maintenance personnel.

以至少具有排氣管480,壓力調整閥479的方式,構成將處理室445內的氣體(環境)排出的第1排氣部。另外,亦可將排氣泵481含在第1排氣部中。 The first exhaust unit that discharges the gas (environment) in the processing chamber 445 is configured to have at least the exhaust pipe 480 and the pressure regulating valve 479. Further, the exhaust pump 481 may be included in the first exhaust unit.

(第1及第2氣體供給部) (first and second gas supply units)

在壁431上側的頂板454連接第1氣體供給單元482(第1氣體供給部)及第2氣體供給單元483(第2氣體供給部)。第1氣體供給單元482是具有:被連接至氣體導入口433的氣體供給管482a,及被連接至氣體供給管482a的惰性氣體供給管482e。在氣體供給管482a中,從上游依序設有第1氣體的氣體源之第1氣體源482b,質量流控制器482c,開閉閥482d。在惰性氣體供給管482e中,從上游依序設有惰性氣體的氣體源之惰性氣體源482f,質量流控制器482g,開閉閥482h。 The top plate 454 on the upper side of the wall 431 is connected to the first gas supply unit 482 (first gas supply unit) and the second gas supply unit 483 (second gas supply unit). The first gas supply unit 482 has a gas supply pipe 482a connected to the gas introduction port 433, and an inert gas supply pipe 482e connected to the gas supply pipe 482a. In the gas supply pipe 482a, the first gas source 482b of the gas source of the first gas, the mass flow controller 482c, and the opening and closing valve 482d are sequentially provided from the upstream. In the inert gas supply pipe 482e, an inert gas source 482f of a gas source of an inert gas, a mass flow controller 482g, and an opening and closing valve 482h are sequentially provided from the upstream.

藉由控制質量流控制器482c及開閉閥482d, 可控制第1氣體的流量。又,藉由控制質量流控制器482g及開閉閥482h,可控制惰性氣體的流量。惰性氣體是作為淨化(除去)氣體供給管482a內的殘留氣體的淨化氣體,更作為供給至氣體供給管482a的第1氣體的載流氣體使用。 By controlling the mass flow controller 482c and the opening and closing valve 482d, The flow rate of the first gas can be controlled. Further, by controlling the mass flow controller 482g and the opening and closing valve 482h, the flow rate of the inert gas can be controlled. The inert gas is used as a purge gas for purifying (removing) the residual gas in the gas supply pipe 482a, and is also used as a carrier gas of the first gas supplied to the gas supply pipe 482a.

第1氣體供給單元482是構成至少具有氣體供給管482a,質量流控制器482c及開閉閥482d。另外,亦可在第1氣體供給單元482中含淨化氣體供給管482e,質量流控制器482g,開閉閥482h。更亦可含第1氣體源482b,惰性氣體源482f。 The first gas supply unit 482 is configured to include at least a gas supply pipe 482a, a mass flow controller 482c, and an opening and closing valve 482d. Further, the first gas supply unit 482 may include a purge gas supply pipe 482e, a mass flow controller 482g, and an open/close valve 482h. Further, it may further include a first gas source 482b and an inert gas source 482f.

作為第1氣體的蝕刻氣體,在本實施形態是使用七氟化碘(IF7)氣體。另外,亦可例如使用氟氣體(F2)、三氟化氯(ClF3)、二氟化氙(XeF2)、三氟化溴(BrF3)、五氟化溴(BrF5)、五氟化碘(IF5)之中任一個含氟的氣體,作為第1氣體。 In the present embodiment, an iodine heptafluoride (IF 7 ) gas is used as the etching gas of the first gas. Further, for example, fluorine gas (F 2 ), chlorine trifluoride (ClF 3 ), xenon difluoride (XeF 2 ), bromine trifluoride (BrF 3 ), bromine pentafluoride (BrF 5 ), or five may be used. Any fluorine-containing gas among fluorinated iodine (IF 5 ) is used as the first gas.

作為從惰性氣體源482f供給的惰性氣體,例如可使用氮(N2)氣體等。 As the inert gas supplied from the inert gas source 482f, for example, a nitrogen (N 2 ) gas or the like can be used.

第2氣體供給單元483是在壁431上側的頂板454中,設成與氣體供給單元482鄰接。第2氣體供給單元483是具有連接至氣體導入口433的氣體供給管483a。在氣體供給管483a中,從上游依序設有第2氣體的氣體源的第2氣體源483b,質量流控制器483c,及開閉閥483d。 The second gas supply unit 483 is disposed adjacent to the gas supply unit 482 in the top plate 454 on the upper side of the wall 431. The second gas supply unit 483 has a gas supply pipe 483a connected to the gas introduction port 433. In the gas supply pipe 483a, a second gas source 483b of a gas source of the second gas, a mass flow controller 483c, and an opening and closing valve 483d are sequentially provided from the upstream.

藉由控制質量流控制器483c及開閉閥483d, 可控制第2氣體的流量。第2氣體供給單元483是構成至少具有氣體供給管483a,質量流控制器483c,及開閉閥483d。另外,亦可在第2氣體供給單元483中含第2氣體源483b。 By controlling the mass flow controller 483c and the opening and closing valve 483d, The flow rate of the second gas can be controlled. The second gas supply unit 483 is configured to include at least a gas supply pipe 483a, a mass flow controller 483c, and an opening and closing valve 483d. Further, the second gas source 483b may be included in the second gas supply unit 483.

第2氣體是例如使用氮(N2)等的惰性氣體。此惰性氣體是作為第1氣體的稀釋氣體,或作為處理室445內的殘留氣體的淨化氣體使用。 The second gas is, for example, an inert gas such as nitrogen (N 2 ). This inert gas is used as a diluent gas of the first gas or as a purge gas of the residual gas in the processing chamber 445.

另外,在本實施形態中是將來自第1氣體供給單元482及第2氣體供給單元483的氣體導入口設為共通的氣體導入口433,但並非限於此,亦可設置分別對應於第1氣體供給單元482及第2氣體供給單元483的氣體導入口。 In the present embodiment, the gas introduction ports 433 from the first gas supply unit 482 and the second gas supply unit 483 are common gas inlet ports 433. However, the present invention is not limited thereto, and may be provided corresponding to the first gas. The gas introduction port of the supply unit 482 and the second gas supply unit 483.

控制質量流控制器482c,483c等或壓力調整閥479,在調整氣體的供給量或來自處理室445的氣體排氣量之下,調整處理室445內的壓力或所導入的氣體的分壓。 The mass flow controllers 482c, 483c, etc. or the pressure regulating valve 479 are controlled to adjust the pressure in the processing chamber 445 or the partial pressure of the introduced gas under the adjustment gas supply amount or the gas exhaust amount from the processing chamber 445.

在氣體緩衝室430內設有多孔性的淋浴板484。淋浴板484是具有:板部484a,及複數設於該板部484a的孔部484b。從氣體導入口433導入的氣體是碰撞於淋浴板484的板部484a,通過孔部484b來供給至晶圓60的表面。如此,被導入至氣體緩衝室430內的氣體是藉由淋浴板484來均一地分散,供給至晶圓60上。 A porous shower plate 484 is provided in the gas buffer chamber 430. The shower plate 484 has a plate portion 484a and a plurality of hole portions 484b provided in the plate portion 484a. The gas introduced from the gas introduction port 433 is a plate portion 484a that collides with the shower plate 484, and is supplied to the surface of the wafer 60 through the hole portion 484b. Thus, the gas introduced into the gas buffer chamber 430 is uniformly dispersed by the shower plate 484 and supplied to the wafer 60.

(第1溫度控制部) (first temperature control unit)

圖4是第1處理單元410所具有的基座459的縱剖面圖。在基座平台411中內包有加熱器463及基座冷卻劑流路464。加熱器463及基座冷卻劑流路464是設在基座平台411內,控制被載置於基座459上的晶圓60的溫度。 FIG. 4 is a longitudinal cross-sectional view of the susceptor 459 included in the first processing unit 410. A heater 463 and a susceptor coolant flow path 464 are enclosed in the base platform 411. The heater 463 and the susceptor coolant flow path 464 are provided in the pedestal stage 411 to control the temperature of the wafer 60 placed on the susceptor 459.

加熱器463是經由加熱器電力供給線487來連接至加熱器溫度控制部485。在加熱器463的附近設有用以檢測出基座459或被載置於基座459上的晶圓60的溫度之溫度檢測部488。溫度檢測部488是被電性連接至控制器600。以溫度檢測部488來檢測出的溫度資料是被輸入至控制器600。控制器600是根據所被檢測出的溫度資料,控制往加熱器463供給的電力量,指示加熱器溫度控制部485,控制加熱器463,而使晶圓60能夠成為所望的溫度。 The heater 463 is connected to the heater temperature control unit 485 via the heater power supply line 487. A temperature detecting portion 488 for detecting the temperature of the susceptor 459 or the wafer 60 placed on the susceptor 459 is provided in the vicinity of the heater 463. The temperature detecting portion 488 is electrically connected to the controller 600. The temperature data detected by the temperature detecting unit 488 is input to the controller 600. The controller 600 controls the amount of electric power supplied to the heater 463 based on the detected temperature data, instructs the heater temperature control unit 485, and controls the heater 463 to bring the wafer 60 to a desired temperature.

基座冷卻劑流路464是被連接至外部基座冷卻劑流路489。詳細是基座冷卻劑流路464的冷卻劑導入口被連接至外部基座冷卻劑流路489a,基座冷卻劑流路464的冷卻劑排出口是被連接至外部基座冷卻劑流路489b。在基座冷卻劑流路464或外部基座冷卻劑流路489中,冷卻劑是流動於箭號D10方向。 The pedestal coolant flow path 464 is connected to the external pedestal coolant flow path 489. Specifically, the coolant introduction port of the susceptor coolant flow path 464 is connected to the external susceptor coolant flow path 489a, and the coolant discharge port of the susceptor coolant flow path 464 is connected to the external susceptor coolant flow path 489b. . In the susceptor coolant flow path 464 or the external susceptor coolant flow path 489, the coolant flows in the direction of the arrow D10.

外部基座冷卻劑流路489是連接冷卻劑供給單元491。冷卻劑供給單元491是根據來自冷卻劑流量控制部486的指示,將流動於外部基座冷卻劑流路489a的冷卻劑的溫度保持於預定值範圍,且控制其流量。 The external susceptor coolant flow path 489 is a connection coolant supply unit 491. The coolant supply unit 491 maintains the temperature of the coolant flowing through the external susceptor coolant flow path 489a within a predetermined value range in accordance with an instruction from the coolant flow rate control unit 486, and controls the flow rate thereof.

在冷卻劑供給單元491的上游的外部基座冷 卻劑流路489b中設有檢測出流動於基座冷卻劑流路464的冷卻劑的溫度之冷卻劑溫度檢測部492。冷卻劑溫度檢測部492及冷卻劑流量控制部486是與控制器600電性連接。在冷卻劑溫度檢測部492所被檢測出的溫度資料是被輸入至控制器600。控制器600是根據所被檢測出的溫度資料,以晶圓60能夠成為所望的溫度之方式,對於冷卻劑流量控制部486,指示控制流動於外部基座冷卻劑流路489a的冷卻劑流量。冷卻劑流量控制部486根據來自控制器600的指示,對於冷卻劑供給單元491,控制流動於外部基座冷卻劑流路489的冷卻劑的流量。 The external pedestal upstream of the coolant supply unit 491 is cold The coolant flow path 489b is provided with a coolant temperature detecting portion 492 that detects the temperature of the coolant flowing through the susceptor coolant flow path 464. The coolant temperature detecting unit 492 and the coolant flow rate control unit 486 are electrically connected to the controller 600. The temperature data detected by the coolant temperature detecting unit 492 is input to the controller 600. The controller 600 instructs the coolant flow rate control unit 486 to control the flow rate of the coolant flowing through the external susceptor coolant flow path 489a so that the wafer 60 can be at a desired temperature based on the detected temperature data. The coolant flow rate control unit 486 controls the flow rate of the coolant flowing to the external susceptor coolant flow path 489 with respect to the coolant supply unit 491 in accordance with an instruction from the controller 600.

第1溫度控制部是構成至少具有加熱器溫度控制部485及冷卻劑流量控制部486。另外,亦可在第1溫度控制部中含加熱器463,基座冷卻劑流路464。更亦可含冷卻劑供給單元491,外部基座冷卻劑流路489,冷卻劑溫度檢測部492,加熱器電力供給線487。並且,將加熱器463,基座冷卻劑流路464歸納稱為第1溫度調整機構。 The first temperature control unit is configured to include at least a heater temperature control unit 485 and a coolant flow rate control unit 486. Further, the first temperature control unit may include a heater 463 and a susceptor coolant flow path 464. Further, the coolant supply unit 491, the external susceptor coolant flow path 489, the coolant temperature detecting unit 492, and the heater power supply line 487 may be further included. Further, the heater 463 and the susceptor coolant flow path 464 are collectively referred to as a first temperature adjustment mechanism.

(第2處理單元) (2nd processing unit)

第2處理單元510是與第1處理單元410同樣以乾式處理來氣體蝕刻的處理單元,例如以無電漿來實施蝕刻處理的處理單元。但,並不限於此,例如亦可在半導體基板上形成預定的膜之處理單元,或對於半導體基板上所形成的膜實施電漿蝕刻的處理單元。 The second processing unit 510 is a processing unit that performs gas etching by dry processing in the same manner as the first processing unit 410, and is, for example, a processing unit that performs etching processing without plasma. However, it is not limited thereto, and for example, a processing unit that forms a predetermined film on a semiconductor substrate, or a processing unit that performs plasma etching on a film formed on the semiconductor substrate.

(第3處理單元) (3rd processing unit)

利用圖16及圖17來說明有關第3處理單元。圖16是用以實施半導體裝置的製造方法的單片式基板處理裝置(以下簡稱基板處理裝置)的處理時的要部剖面圖。圖17是同基板處理裝置的概略剖面圖,顯示基座459下降而處於可進行搬送工程的搬送位置的狀態的圖。另外,第3處理單元是具有在圖4所示的基座459,該基座459的詳細是揭示於圖4。因此,在圖16及圖17是有圖示省略的零件(加熱器單元等)。 The third processing unit will be described with reference to Figs. 16 and 17 . FIG. 16 is a cross-sectional view of an essential part of a process of a monolithic substrate processing apparatus (hereinafter simply referred to as a substrate processing apparatus) for carrying out a method of manufacturing a semiconductor device. 17 is a schematic cross-sectional view of the same substrate processing apparatus, showing a state in which the susceptor 459 is lowered and is in a transport position at which a transporting project can be performed. Further, the third processing unit has the susceptor 459 shown in FIG. 4, and the details of the susceptor 459 are disclosed in FIG. Therefore, FIG. 16 and FIG. 17 are components (heater units and the like) which are not shown.

在圖16及圖17中,基板處理裝置20是具有:處理基板60的處理容器30、及與處理容器30鄰接而於之間搬送基板60的基板搬送容器39。 In FIG. 16 and FIG. 17 , the substrate processing apparatus 20 is a processing container 30 having a processing substrate 60 and a substrate transfer container 39 that is adjacent to the processing container 30 and transports the substrate 60 therebetween.

處理容器30是由:上部開口的容器本體31、及堵塞容器本體31的上部開口的蓋體32所構成,而於內部形成密閉構造的處理室50。另外,亦可以蓋體32及基座459所包圍的空間來形成處理室50。又,有關基座459是利用圖4來詳細說明,所以在此省略說明。 The processing container 30 is composed of a container body 31 having an upper opening and a lid body 32 that closes an upper portion of the container body 31, and a processing chamber 50 having a sealed structure is formed inside. Further, the processing chamber 50 may be formed by a space surrounded by the lid body 32 and the susceptor 459. In addition, since the base 459 is demonstrated in detail using FIG. 4, it abbreviate|omits description here.

在蓋體32是設有淋浴頭105及處理氣體供給管線106a、106b以及惰性氣體供給管線。作為氣體供給部的淋浴頭105是與處理室50內的基板60對向而設,為了對處理室50內供給處理氣體而設。此淋浴頭105是設在蓋體32的內面上部,由圖示省略的氣體分散板及圖示省略的混合室所構成,該氣體分散板是具有多數的氣體 孔,使氣體分散成淋浴狀,該混合室是混合複數的氣體。 The lid body 32 is provided with a shower head 105, processing gas supply lines 106a and 106b, and an inert gas supply line. The shower head 105 as a gas supply unit is provided to face the substrate 60 in the processing chamber 50, and is provided to supply a processing gas into the processing chamber 50. The shower head 105 is provided on the inner surface of the lid body 32, and is composed of a gas dispersion plate (not shown) and a mixing chamber (not shown). The gas dispersion plate has a large amount of gas. The pores disperse the gas into a shower, and the mixing chamber is a mixture of a plurality of gases.

氣體供給管線106a、106b是被連接至淋浴頭105,構成經由淋浴頭105來供給處理氣體至基板處理室50內。具體而言,氣體供給管線是具備:連接至淋浴頭105來與混合室連通的氣體供給管115a、115b、及設在氣體供給管115a、115b的氣體流量控制器(質量流控制器:MFC)116a、116b,構成可以所望的氣體流量、所望的氣體比率來供給所望的氣體種類至基板處理室50內。另外,亦可將氣體供給源117a、117b構成含在氣體供給管線(氣體供給部)中。 The gas supply lines 106a and 106b are connected to the shower head 105, and the processing gas is supplied to the substrate processing chamber 50 via the shower head 105. Specifically, the gas supply line includes gas supply pipes 115a and 115b connected to the shower head 105 to communicate with the mixing chamber, and a gas flow controller (mass flow controller: MFC) provided in the gas supply pipes 115a and 115b. 116a and 116b constitute a desired gas flow rate and a desired gas ratio to supply the desired gas type to the substrate processing chamber 50. Further, the gas supply sources 117a and 117b may be included in the gas supply line (gas supply unit).

在容器本體31中設有內藏排氣口107、搬送口108、及加熱器單元的基座459。排氣口107是設在容器本體31的上側部,與形成於容器本體31的上部內周的環狀路114連通,構成經由環狀路114來將基板處理室50內排氣。並且,搬送口108是設在比容器本體31的排氣口107更下方的一側部,構成從搬送容器39內所形成的基板搬送室140經由搬送口108來將矽晶圓等的處理前的基板60搬入至處理容器30內的基板處理室50,或從基板處理室50搬出處理後的基板60至基板搬送室140。另外,在容器本體31的搬送口108是開閉自如地設有進行基板搬送室140與基板處理室50的環境隔離之開閉閥109。 The container body 31 is provided with a susceptor 459 having a built-in exhaust port 107, a transfer port 108, and a heater unit. The exhaust port 107 is provided in the upper side portion of the container body 31, and communicates with the annular passage 114 formed on the inner periphery of the upper portion of the container body 31, and vents the inside of the substrate processing chamber 50 via the annular passage 114. In addition, the conveyance port 108 is provided on the side below the exhaust port 107 of the container main body 31, and the substrate transfer chamber 140 formed in the transfer container 39 is configured to process the wafer or the like via the transfer port 108. The substrate 60 is carried into the substrate processing chamber 50 in the processing container 30, or the processed substrate 60 is transferred from the substrate processing chamber 50 to the substrate transfer chamber 140. In addition, the opening/closing valve 109 that separates the substrate transfer chamber 140 from the substrate processing chamber 50 is provided in the transfer port 108 of the container body 31 so as to be openable and closable.

在處理容器30的基板處理室50內,前述的基座459會被設成昇降自如,基板60會被保持於基座 459的表面。基板60是可藉由省略圖示之圖4所示的加熱器463經由基座459來加熱。 In the substrate processing chamber 50 of the processing container 30, the aforementioned susceptor 459 is set to be freely movable, and the substrate 60 is held on the pedestal. The surface of 459. The substrate 60 is heated via a susceptor 459 by a heater 463 shown in FIG. 4 (not shown).

在基板支撐銷上下機構111設有複數的支撐銷104,該等的支撐銷104是可貫通加熱器單元及基座459,構成可對應於基座459及基板支撐銷上下機構111的昇降來從基座459的表面出没自如。 The substrate support pin upper and lower mechanism 111 is provided with a plurality of support pins 104 which are permeable to the heater unit and the base 459 and configured to correspond to the elevation of the base 459 and the substrate support pin upper and lower mechanism 111. The surface of the base 459 is free.

基板處理裝置是當基座459下降而處於可進行搬送工程的位置時(圖17,以下將此位置稱為搬送位置A),複數的支撐銷104會從基座459突出而可在複數的支撐銷104上支撐基板60,構成可在基板處理室50與基板搬送室140之間經由搬送口108來進行基板60的搬送、搬出。又,基板處理裝置是當基座459上昇而處於可經由比搬送位置A還上方的中間位置來進行處理工程的位置時(圖16,以下將此位置稱為基板處理位置B),支撐銷4是不參與,在基座459上載置基板60。 The substrate processing apparatus is a position where the susceptor 459 is lowered and can be transported (FIG. 17, hereinafter, this position is referred to as a transport position A), and a plurality of support pins 104 protrude from the base 459 to support a plurality of supports. The pin 104 supports the substrate 60, and the substrate 60 can be transported and carried out between the substrate processing chamber 50 and the substrate transfer chamber 140 via the transfer port 108. In addition, the substrate processing apparatus is a position where the susceptor 459 is raised and can be processed through an intermediate position higher than the transport position A (FIG. 16, this position is referred to as a substrate processing position B hereinafter), and the support pin 4 It is not involved, and the substrate 60 is placed on the susceptor 459.

基座459是設成其支撐軸124會被連接至昇降機構而昇降於基板處理室50內。在支撐軸124的外周是設有用以密封支撐軸的直線運動之圖示省略的波紋管。昇降機構是在基板搬入工程、基板處理工程、基板搬出工程等的各工程,構成可多階段地調整基板處理室50內的基座459的上下方向的位置(搬送位置A、基板處理位置B等)。 The base 459 is configured such that its support shaft 124 is connected to the lifting mechanism to be raised and lowered in the substrate processing chamber 50. The outer circumference of the support shaft 124 is a bellows that is omitted from the illustration for providing a linear motion for sealing the support shaft. The elevating mechanism is a project in which the susceptor 459 in the substrate processing chamber 50 can be adjusted in a vertical direction (transport position A, substrate processing position B, etc.) in various steps such as a substrate loading process, a substrate processing process, and a substrate unloading process. ).

又,基座459是形成可旋轉。亦即,藉由圖示省略的旋轉機構來使前述筒狀的支撐軸124旋轉自如, 以支撐軸為中心,旋轉自如地設置內藏加熱器的基座459,在保持基板60的狀態下構成可以任意的速度來旋轉基座459。另一方面,設在基座459內的電阻加熱加熱器是設為固定,藉由插通於筒狀的支撐軸124內之未圖示的固定部來支撐。藉由如此將基座459設為旋轉自如,將電阻加熱加熱器設為固定,可使基座459對於電阻加熱加熱器相對旋轉。 Also, the base 459 is formed to be rotatable. That is, the cylindrical support shaft 124 is rotatably rotated by a rotation mechanism (not shown). The base 459 of the built-in heater is rotatably provided around the support shaft, and the base 459 can be rotated at an arbitrary speed while holding the substrate 60. On the other hand, the resistance heating heater provided in the susceptor 459 is fixed and supported by a fixing portion (not shown) that is inserted into the cylindrical support shaft 124. By thus rotating the susceptor 459, the resistance heating heater is fixed, and the susceptor 459 can be relatively rotated with respect to the resistance heating heater.

如圖16所示般,在本實施形態中,尤其設在處理容器30的蓋體32上部的上述氣體供給管線是除了導入處理氣體的處理氣體供給管線106a以外,還有導入反應氣體控制用的非反應氣體的非反應氣體供給管線106b。並且,惰性氣體供給管線是被連接至與基板60的中心部對向的淋浴頭105的大致中心部。處理氣體供給管線106a、106b是被連接至與基板60的中心部對向的淋浴頭105的大致中心部以外的部分。 As shown in Fig. 16, in the present embodiment, in particular, the gas supply line provided in the upper portion of the lid body 32 of the processing container 30 is a control gas supply line 106a for introducing a processing gas, and is also provided for introducing a reaction gas. The non-reactive gas of the non-reactive gas is supplied to the line 106b. Further, the inert gas supply line is connected to a substantially central portion of the shower head 105 that faces the center portion of the substrate 60. The processing gas supply lines 106a and 106b are connected to a portion other than the substantially central portion of the shower head 105 that faces the center portion of the substrate 60.

具體而言,構成惰性氣體供給管線的惰性氣體供給管20是連接至與基板60的中心部對向的淋浴頭105的中心部。並且,構成處理氣體供給管線106a、106b的處理氣體供給管115a、115b是連接至與基板60的中心部對向的蓋板的中心以外的周邊部,偏離連接惰性氣體供給管20的淋浴頭105的中心部。在惰性氣體供給管112及處理氣體供給管115a、115b是分別設有MFC121、116a、116b,可個別控制供給至處理室50內的惰性氣體及處理氣體的流量。另外,在惰性氣體供給管20、反應 氣體供給管115a、115b是亦可分別連接惰性氣體供給源122、反應氣體供給源117a、反應氣體供給源117b。 Specifically, the inert gas supply pipe 20 constituting the inert gas supply line is connected to a central portion of the shower head 105 that faces the center portion of the substrate 60. Further, the processing gas supply pipes 115a and 115b constituting the processing gas supply lines 106a and 106b are peripheral portions other than the center of the cover plate facing the center portion of the substrate 60, and are offset from the shower head 105 to which the inert gas supply pipe 20 is connected. The center of the department. The inert gas supply pipe 112 and the process gas supply pipes 115a and 115b are provided with MFCs 121, 116a, and 116b, respectively, and the flow rates of the inert gas and the process gas supplied into the processing chamber 50 can be individually controlled. In addition, in the inert gas supply pipe 20, the reaction The gas supply pipes 115a and 115b may be connected to the inert gas supply source 122, the reaction gas supply source 117a, and the reaction gas supply source 117b, respectively.

另外,在本圖中控制昇降機構、旋轉機構、電阻加熱加熱器、MFC121、116(116a、116b)等各部的控制手段是省略,但作為控制手段的控制器的構造例是顯示於後述的圖6。可是,後述的圖6是配合第1處理單元來賦予號碼,因此即使是同零件,也有與第3處理單元的零件號碼不同的情況。 In addition, in the figure, the control means for controlling each of the elevating mechanism, the rotating mechanism, the resistance heating heater, and the MFCs 121 and 116 (116a, 116b) is omitted. However, the configuration example of the controller as the control means is shown in the following description. 6. However, FIG. 6 which will be described later is provided with the number in accordance with the first processing means. Therefore, even if it is the same part, the part number of the third processing unit may be different.

在如上述般的基板處理裝置中為了使基板上的薄膜除去,而在搬送工程將基板60搬入至處理室50內,在處理工程經由淋浴頭105來將處理氣體及非處理氣體供給至被搬入處理室50內的基板60,處理基板60,在搬出工程從處理室50內搬出被處理的基板60。 In the substrate processing apparatus as described above, in order to remove the thin film on the substrate, the substrate 60 is carried into the processing chamber 50 in the transporting process, and the processing gas is supplied to the processed gas via the shower head 105. The substrate 60 in the processing chamber 50 is processed, and the substrate 60 is processed, and the substrate 60 to be processed is carried out from the processing chamber 50 in the unloading process.

在搬入工程中,基座459是處於搬送位置A可加熱基板60的狀態,處理容器30的開閉閥109是開著。基板60是藉由圖示省略的搬送機構來從基板搬送室140經由搬送口108搬入至基板處理室50,被複數的支撐銷104支撐(圖17)。開閉閥109是在基板搬入後關閉。利用真空泵P經由環狀路114來將基板處理室50內排氣。被排氣的氣體是從排氣口107通過排氣管142來排出至未圖示的工廠內的排氣機構。 In the carry-in process, the susceptor 459 is in a state where the substrate 60 can be heated at the transport position A, and the opening and closing valve 109 of the processing container 30 is opened. The substrate 60 is carried into the substrate processing chamber 50 from the substrate transfer chamber 140 via the transfer port 108 by a transport mechanism (not shown), and is supported by a plurality of support pins 104 (FIG. 17). The on-off valve 109 is closed after the substrate is carried in. The inside of the substrate processing chamber 50 is exhausted through the annular path 114 by the vacuum pump P. The exhausted gas is exhausted from the exhaust port 107 through the exhaust pipe 142 to an exhaust mechanism in a factory (not shown).

在處理工程中,首先藉由昇降機構,基座459從搬送位置A(圖17)上昇至基板處理位置B(圖16),但在到達基板處理位置B之前,基板60會從支撐 銷104移載至基座459,利用加熱器單元經由基座459來直接加熱基板60。在基板處理位置B被移載至基座459上的基板60是與淋浴頭105對向(圖16)。在此狀態下,因應所需,藉由旋轉機構來旋轉基座459而使基板60旋轉。 In the process, the susceptor 459 is first raised from the transfer position A (FIG. 17) to the substrate processing position B (FIG. 16) by the elevating mechanism, but the substrate 60 is supported from the support before reaching the substrate processing position B. The pin 104 is transferred to the susceptor 459, and the substrate 60 is directly heated by the heater unit via the susceptor 459. The substrate 60 transferred to the susceptor 459 at the substrate processing position B is opposed to the shower head 105 (Fig. 16). In this state, the base 60 is rotated by rotating the base 459 by a rotating mechanism as needed.

然後,經由淋浴頭105從氣體供給管線106(106a、106b)如箭號所示般一面供給處理氣體至處理室50內之旋轉的基板60的表面,一面從排氣口107排氣。在此過程,基板60上的預定的膜會被除去。處理氣體是從被連接至與基板60的中心部對向的淋浴頭105之反應氣體供給管線106a、106b來導入至淋浴頭105內。但,當然不限於此形態。 Then, the processing gas is supplied to the surface of the rotating substrate 60 in the processing chamber 50 from the gas supply line 106 (106a, 106b) via the shower head 105 as shown by the arrow, and is exhausted from the exhaust port 107. During this process, a predetermined film on the substrate 60 is removed. The processing gas is introduced into the shower head 105 from the reaction gas supply lines 106a and 106b connected to the shower head 105 opposed to the central portion of the substrate 60. However, of course, it is not limited to this form.

此時,惰性氣體是從被連接至與基板60的中心部對向的淋浴頭105的中心部之惰性氣體供給管線來供給至處理室50內。然後,亦可藉由供給惰性氣體來控制從淋浴頭105的中心部以外的部分導入至淋浴頭105內的處理氣體的流動。但,進行從淋浴頭105的中心部導入至處理室50內的惰性氣體之處理氣體的流動控制時,是以從淋浴頭105供給至基板60的中心部之處理氣體的流動不會產生停滯的方式,或以基板60的中心部不會因為處理氣體濃度分布的不均一而產生處理氣體不足那樣的形式進行。 At this time, the inert gas is supplied into the processing chamber 50 from the inert gas supply line connected to the center portion of the shower head 105 opposed to the central portion of the substrate 60. Then, the flow of the processing gas introduced into the shower head 105 from the portion other than the central portion of the shower head 105 can be controlled by supplying an inert gas. However, when the flow of the processing gas of the inert gas introduced into the processing chamber 50 from the central portion of the shower head 105 is controlled, the flow of the processing gas supplied from the shower head 105 to the central portion of the substrate 60 does not become stagnant. Alternatively, the center portion of the substrate 60 may not be formed in a form in which the processing gas is insufficient due to the non-uniformity of the processing gas concentration distribution.

在搬出工程中,基板處理後,基座459是下降至搬送位置A(圖17)。降下時,支撐銷104再度頂起 基板60,製作用以在基座459與基板60之間搬送的間隙。基板60是從搬送口108藉由搬送機構往基板搬送室140運出。 In the unloading process, after the substrate processing, the susceptor 459 is lowered to the transport position A (Fig. 17). When lowered, the support pin 104 is put up again The substrate 60 is formed with a gap for transporting between the susceptor 459 and the substrate 60. The substrate 60 is transported from the transfer port 108 to the substrate transfer chamber 140 by a transfer mechanism.

(氣體供給部) (gas supply unit)

在處理容器30的上部的蓋體32是附設有用以從圖中省略的氣體供給設備供給所要的複數的處理氣體之處理氣體供給管115a、115b。在氣體供給管115a、115b中,將作為處理氣體的含鹵元素氣體供給至基板的處理氣體供給部、將除去劑供給至基板的除去劑供給部、及供給其他氣體,在此是淨化用的N2氣體、洗滌用的三氟化氯(ClF3)氣體等的供給部(未圖示)會因應所需而設。另外,雖顯示供給氣體作為除去劑的例子,但並非限於此,亦可構成能夠藉由供給液體來除去。又,亦可流動氬等的稀有氣體,供給高頻電力來使電漿產生而以濺射除去。在氣體供給部是分別設有流量控制部的MFC116a、116b及開閉閥,可控制氣體供給量。又,亦可事前混合所使用的氣體之後流至氣體導入口。又,亦可因應所需形成使用淋浴板的構造。藉由流量控制部及APC閥V來調整供給量、排氣量,藉此將處理容器30及處理室50的壓力控制成所望的值。 The lid body 32 at the upper portion of the processing container 30 is provided with processing gas supply tubes 115a and 115b for supplying a desired plurality of processing gases from the gas supply device omitted from the drawing. In the gas supply pipes 115a and 115b, a halogen-containing element gas as a processing gas is supplied to a processing gas supply unit of the substrate, a removal agent supply unit that supplies the removal agent to the substrate, and a supply of other gas, which is used for purification. A supply unit (not shown) such as N2 gas or chlorine trifluoride (ClF 3 ) gas for washing is provided as needed. Further, although the supply gas is used as an example of the removing agent, the present invention is not limited thereto, and the configuration may be removed by supplying a liquid. Further, a rare gas such as argon may be supplied to supply high-frequency power to generate plasma and be removed by sputtering. The gas supply unit is the MFCs 116a and 116b and the on-off valve in which the flow rate control unit is provided, and the gas supply amount can be controlled. Further, the gas used may be mixed beforehand and then flowed to the gas introduction port. Further, a structure using a shower panel can be formed as needed. The supply amount and the exhaust amount are adjusted by the flow rate control unit and the APC valve V, whereby the pressures of the processing container 30 and the processing chamber 50 are controlled to a desired value.

(控制器:控制部) (Controller: Control Department)

其次,說明有關控制器600的構成。圖6是本實施形 態的控制器的構造圖。如圖6所示般,控制部(控制手段)的控制器600是構成具備CPU(Central Processing Unit)600a,RAM(Random Access Memory)600b,記憶裝置600c,及I/O埠600d的電腦。RAM600b,記憶裝置600c,I/O埠600d是構成可經由內部匯流排600e來與CPU600a交換資料。在控制器600連接例如以觸控面板等所構成的輸出入裝置601。另外,圖6的控制器構成是配合第1處理單元來附上號碼,因此即使是同零件,也會有與在後述的第3處理單元的零件號碼不同的情形。 Next, the configuration of the controller 600 will be described. Figure 6 is a form of the present embodiment The construction diagram of the controller of the state. As shown in FIG. 6, the controller 600 of the control unit (control means) is a computer including a CPU (Central Processing Unit) 600a, a RAM (Random Access Memory) 600b, a memory device 600c, and an I/O port 600d. The RAM 600b, the memory device 600c, and the I/O port 600d are configured to exchange data with the CPU 600a via the internal bus bar 600e. The controller 600 is connected to an input/output device 601 constituted by, for example, a touch panel or the like. In addition, since the controller of FIG. 6 has a number attached to the first processing unit, even if it is the same part, there is a case where the part number of the third processing unit to be described later is different.

記憶裝置600c是例如以快閃記憶體,HDD(Hard Disk Drive)等所構成。在記憶裝置600c內是儲存有可讀出的控制程式或製程處方等,該控制程式是控制基板處理裝置20的動作,該製程處方是記載有後述基板處理裝置20的基板處理的程序或條件等。而且,按處理氣體的蝕刻氣體的每個種類記載處理條件。在此,所謂處理條件是意指基板或基座的溫度帶,處理室的壓力,氣體的分壓,氣體供給量,冷卻劑流量,處理時間等,處理基板時的條件。 The memory device 600c is configured by, for example, a flash memory, an HDD (Hard Disk Drive), or the like. In the memory device 600c, a control program or a process recipe for storing the substrate processing device 20, which is a program or condition for describing substrate processing of the substrate processing device 20 to be described later, is stored. . Further, processing conditions are described for each type of etching gas of the processing gas. Here, the processing conditions mean the temperature band of the substrate or the susceptor, the pressure of the processing chamber, the partial pressure of the gas, the gas supply amount, the coolant flow rate, the processing time, and the like, and the conditions at the time of processing the substrate.

另外,製程處方是使後述的基板處理裝置20的基板處理工程的程序實行於控制器600,組合成可取得預定的結果者,作為程式機能。以下,亦將此製程處方或控制程式等簡稱為程式。另外,在本說明書中稱程式時,有只含製程處方單體時,只含控制程式單體時,或含其雙方時。 In addition, the process recipe is a program for causing a substrate processing project of the substrate processing apparatus 20 to be described later to be executed in the controller 600, and combined to obtain a predetermined result. Hereinafter, this process prescription or control program is also simply referred to as a program. In addition, when the program is referred to in this specification, when only the process prescription monomer is included, only the control program monomer is included, or both of them are included.

RAM600b是作為暫時性保持藉由CPU600a所讀出的程式或資料等的作業用記憶體區域(工作區域)。 The RAM 600b is a work memory area (work area) for temporarily holding a program or data read by the CPU 600a.

I/O埠600d是被連接至上述的昇降驅動部473,加熱器溫度控制部485,溫度檢測部488,壓力調整閥479,質量流控制器482c,482g,483c,開閉閥482d,482h,483d,排氣泵481,大氣搬送機器人130,閘閥311~314,真空搬送機器人320,冷卻劑流量控制部486等。 The I/O 埠 600d is connected to the above-described elevation drive unit 473, heater temperature control unit 485, temperature detection unit 488, pressure adjustment valve 479, mass flow controller 482c, 482g, 483c, on-off valves 482d, 482h, 483d. The exhaust pump 481, the atmospheric transfer robot 130, the gate valves 311 to 314, the vacuum transfer robot 320, the coolant flow rate control unit 486, and the like.

CPU600a是構成從記憶裝置600c讀出控制程式實行,且按照來自輸出入裝置501的操作指令的輸入等,從記憶裝置600c讀出製程處方。而且,CPU600a是構成可按照讀出後的製程處方的內容,控制昇降驅動部(473等)之昇降銷(413等)的上下動作,加熱器溫度控制部(485等)之晶圓60的加熱動作,壓力調整閥(479等)之壓力調整動作,質量流控制器(482c等)及開閉閥(482d等)之處理氣體的流量調整動作等。 The CPU 600a is configured to read out a control program from the memory device 600c, and reads a process recipe from the memory device 600c in accordance with an input of an operation command from the input/output device 501. Further, the CPU 600a is configured to control the vertical movement of the lift pins (413 and the like) of the elevation drive unit (473 or the like) in accordance with the contents of the process recipe after reading, and to heat the wafer 60 of the heater temperature control unit (485 or the like). The operation, the pressure adjustment operation of the pressure regulating valve (479, etc.), the mass flow controller (482c, etc.), and the flow rate adjustment operation of the process gas of the opening and closing valve (482d, etc.).

另外,控制器600是不限於作為專用的電腦構成時,亦可為泛用的電腦。例如,準備儲存上述程式的外部記憶裝置602,利用如此的外部記憶裝置602來將程式安裝於泛用的電腦等,藉此可構成本實施形態的控制器600。外部記憶裝置602是例如以磁帶,軟碟或硬碟等的磁碟,CD或DVD等的光碟,MO等的光磁碟,USB記憶體(USB Flash Drive)或記憶卡等的半導體記憶體所構成。 Further, the controller 600 is not limited to being a dedicated computer, and may be a general-purpose computer. For example, the external memory device 602 that stores the program is installed, and the external memory device 602 is used to install the program on a general-purpose computer or the like, whereby the controller 600 of the present embodiment can be configured. The external memory device 602 is, for example, a magnetic disk such as a magnetic tape, a floppy disk or a hard disk, a compact disk such as a CD or a DVD, a magnetic disk such as an MO, a USB memory (USB Flash Drive), or a semiconductor memory such as a memory card. Composition.

另外,用以供給程式至電腦的手段是不限於經由外部記憶裝置602來供給時。例如,亦可利用網際網路或專線等的通訊手段,不經由外部記憶裝置602來供給程式。 Further, the means for supplying the program to the computer is not limited to being supplied via the external memory device 602. For example, the communication means such as the Internet or the private line may be used to supply the program without the external memory device 602.

如以上般,記憶裝置600c或外部記憶裝置602是構成為電腦可讀取的記錄媒體。以下,亦將該等簡稱為記錄媒體。另外,在本說明書中稱記錄媒體時,有只含記憶裝置600c單體時,只含外部記憶裝置602單體時,或含其雙方時。 As described above, the memory device 600c or the external memory device 602 is a computer-readable recording medium. Hereinafter, these are also simply referred to as recording media. Further, in the present specification, when the recording medium is included, when only the memory device 600c is included, only when the external memory device 602 is alone or both.

2.基板處理工程 2. Substrate processing engineering

其次,以下利用圖5來說明有關本實施形態的第1處理單元或第3處理單元的基板處理方法所被實施的基板處理工程之一例。此基板處理工程是作為微細圖案的形成工程或半導體裝置的製造方法的一工程進行。圖5是表示本發明的實施形態的基板處理工程的處理流程的圖。圖7~圖13是分別表示本發明的實施形態的半導體裝置的製造方法的第1~6階段的圖。 Next, an example of a substrate processing project to be performed by the substrate processing method of the first processing unit or the third processing unit according to the present embodiment will be described below with reference to FIG. 5. This substrate processing is performed as a process of forming a fine pattern or a method of manufacturing a semiconductor device. Fig. 5 is a view showing a processing flow of a substrate processing project according to an embodiment of the present invention. 7 to 13 are views showing the first to sixth stages of the method of manufacturing the semiconductor device according to the embodiment of the present invention.

另外,在本實施形態的基板處理裝置20中,僅圖5的步驟S3(Step3)的Si選擇蝕刻(第3微細圖案形成)工程被實施,其他的步驟S1(Step1)或S2(Step2)、S4(Step4)是在基板處理裝置20以外的處理裝置或作為第1處理單元的處理單元410或後述的第3處理單元以外的處理單元中被實施。 Further, in the substrate processing apparatus 20 of the present embodiment, only the Si selective etching (third fine pattern formation) process of step S3 (Step 3) of FIG. 5 is performed, and other steps S1 (Step 1) or S2 (Step 2), S4 (Step 4) is implemented in a processing device other than the substrate processing apparatus 20 or a processing unit other than the processing unit 410 of the first processing unit or a third processing unit to be described later.

首先,在圖5的步驟S1(Step1),如圖8所 示般,所望的線寬的微細圖案(第1微細圖案)會形成於Si基板1的表面(Si3N4膜)上。此線寬是例如30~100nm,深度是例如300~4000nm。本實施的第1微細圖案形成工程是至少具有後述的圖7所示的層疊膜形成工程及圖8所示的第1蝕刻工程。詳細分別如後述的圖7所示的層疊膜形成工程及圖8所示的第1蝕刻工程般,在Si基板1的表面形成Si3N4膜2,且在此Si3N4膜2上重複預定次數SiO2膜3、Poly-Si膜4、SiO2膜3、Poly-Si膜4、及SiO2膜3與Poly-Si膜4的形成,而於形成所望的厚度的層疊膜之後,將含碳的硬質遮罩之碳硬質遮罩(CHM)膜成膜,使用乾蝕刻以所望的線寬及深度切削形成微細圖案(第1微細圖案)。 First, in step S1 (Step 1) of FIG. 5, as shown in FIG. 8, a fine pattern (first fine pattern) of a desired line width is formed on the surface (Si 3 N 4 film) of the Si substrate 1. This line width is, for example, 30 to 100 nm, and the depth is, for example, 300 to 4000 nm. The first fine pattern forming process of the present embodiment is at least a laminated film forming process shown in FIG. 7 which will be described later and a first etching process shown in FIG. In the laminated film forming process shown in FIG. 7 to be described later and the first etching process shown in FIG. 8, the Si 3 N 4 film 2 is formed on the surface of the Si substrate 1 and is on the Si 3 N 4 film 2, respectively. The SiO 2 film 3, the Poly-Si film 4, the SiO 2 film 3, the Poly-Si film 4, and the SiO 2 film 3 and the Poly-Si film 4 are formed a predetermined number of times, and after the laminated film of the desired thickness is formed, A carbon hard mask (CHM) film containing a carbon hard mask is formed into a film, and a fine pattern (first fine pattern) is formed by cutting with a desired line width and depth using dry etching.

圖7是表示3DNAND快閃記憶體製作製程的層疊膜形成(層疊膜形成工程)後的剖面圖。在此,於圖7所示的層疊膜的形成是在矽基板上例如形成Si3N4膜2,且在其上交替形成SiO2膜3及Poly-Si膜4的層疊膜。在此,Si3N4膜2是例如以CVD(Chemical Vapor Deposition)法來成膜。厚度是30~60nm程度,成膜溫度是400~800℃。由降低膜應力的觀點,最好成膜溫度低。作為乾蝕刻時的阻擋膜是除了本案的Si3N4膜2以外,估計碳膜或SiC膜在SiO2膜3、Poly-Si膜4的雙方可確保乾蝕刻時的高選擇性。但,在製造製程中的高溫工程,碳(C)會擴散各處,因此Si3N4膜2為理想。並且,SiO2膜3、Poly-Si膜4是膜厚分別為30~60nm程度,例如成 膜溫度400~800℃,皆藉由CVD法來成膜。並且,SiO2膜、Poly-Si膜也分別由降低膜應力的觀點來看,最好成膜溫度低。另外,Poly-Si膜4是亦可為非晶形矽(α-Si)膜。層疊膜是例如重複形成多晶矽膜及氧化膜24次,而使能夠形成1440nm。另外,多晶矽膜與氧化膜為同膜厚,但並非限於此膜厚,多晶矽膜及氧化膜是氧化膜較厚為理想,藉此設想取得位元間干擾的緩和之效果。 Fig. 7 is a cross-sectional view showing the formation of a laminated film (layered film forming process) in a 3D NAND flash memory manufacturing process. Here, the formation of the laminated film shown in FIG. 7 is a laminated film in which, for example, the Si 3 N 4 film 2 is formed on the tantalum substrate, and the SiO 2 film 3 and the Poly-Si film 4 are alternately formed thereon. Here, the Si 3 N 4 film 2 is formed, for example, by a CVD (Chemical Vapor Deposition) method. The thickness is about 30 to 60 nm, and the film formation temperature is 400 to 800 °C. From the viewpoint of lowering the film stress, it is preferable that the film formation temperature is low. As the barrier film in the dry etching, in addition to the Si 3 N 4 film 2 of the present invention, it is estimated that the carbon film or the SiC film can ensure high selectivity in dry etching in both the SiO 2 film 3 and the Poly-Si film 4. However, in the high temperature engineering in the manufacturing process, carbon (C) is diffused everywhere, so the Si 3 N 4 film 2 is ideal. Further, the SiO 2 film 3 and the Poly-Si film 4 have a film thickness of about 30 to 60 nm, for example, a film formation temperature of 400 to 800 ° C, and are formed by a CVD method. Further, from the viewpoint of reducing the film stress, the SiO 2 film and the Poly-Si film are preferably low in film formation temperature. Further, the Poly-Si film 4 may be an amorphous yttrium (α-Si) film. The laminated film is, for example, repeatedly formed into a polycrystalline germanium film and an oxide film 24 times to form 1440 nm. Further, although the polycrystalline germanium film and the oxide film have the same film thickness, the film thickness is not limited thereto, and the polycrystalline germanium film and the oxide film are preferably thick oxide films, and it is conceivable to obtain the effect of alleviating the interference between the cells.

圖8是表示利用碳膜的硬質遮罩膜5在圖7所形成的層疊膜中形成通道用的貫通孔(第一孔)13(第1蝕刻工程)後的圖。作為硬質遮罩膜5的碳膜是藉由CVD法來成膜。膜厚是設為在蝕刻被蝕刻層的層疊膜時充分剩餘的膜厚。例如最好為400nm以上。成膜溫度是200~550℃。 FIG. 8 is a view showing a through hole (first hole) 13 (first etching process) for forming a channel in the laminated film formed in FIG. 7 by the hard mask film 5 of the carbon film. The carbon film as the hard mask film 5 is formed by a CVD method. The film thickness is a film thickness that is sufficiently left when the laminated film of the layer to be etched is etched. For example, it is preferably 400 nm or more. The film formation temperature is 200 to 550 °C.

另外,蝕刻被蝕刻層的層疊膜時的硬質遮罩膜5並不限於碳膜,只要是矽氮化(SiN)膜、作為碳化矽(SiC)膜的矽膜與碳膜的層疊膜等在蝕刻處理中能取得選擇性的膜即可。 In addition, the hard mask film 5 when the laminated film of the layer to be etched is etched is not limited to the carbon film, and may be a tantalum nitride (SiN) film or a laminated film of a tantalum film and a carbon film as a tantalum carbide (SiC) film. It is sufficient to obtain a selective film in the etching treatment.

上述層疊膜的乾蝕刻(第1蝕刻)處理是例如選擇SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一個。 The dry etching (first etching) treatment of the laminated film is, for example, one selected from the group consisting of SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 /O 2 mixed gas.

然後,例如藉由使用O2氣體的周知蝕刻處理來除去作為硬質遮罩膜5的CHM膜(CHM膜除去工程)。 Then, the CHM film (the CHM film removal process) as the hard mask film 5 is removed by, for example, a well-known etching process using O 2 gas.

其次,圖5的步驟S2(第2微細圖案形成工 程)是在第1蝕刻工程除去的部分形成所望的通道之後,更形成字元線(WL)形成用的預定的溝(第二孔)的圖案。例如,形成圖10所示那樣的微細圖案。在圖10中,線寬是例如30~100nm,深度是例如30~4000nm。本實施的第2微細圖案形成工程是至少具有通道形成工程及第2蝕刻工程。詳細是如分別顯示於後述的圖9所示的通道形成工程及圖10所示的第2蝕刻工程般,在第1蝕刻工程所形成的貫通孔(第一孔)的側面形成ONO膜9之後,形成多晶矽(Poly-Si)膜10,在上述貫通孔(第一孔)13形成通道。然後,以預定的圖案形成含碳的硬質遮罩之碳硬質遮罩(CHM)膜11,用乾蝕刻以所望的線寬及深度切削形成微細圖案(第2微細圖案)。 Next, step S2 of FIG. 5 (the second fine pattern forming worker The process is to form a pattern of a predetermined groove (second hole) for forming a word line (WL) after forming a desired channel in a portion removed by the first etching process. For example, a fine pattern as shown in FIG. 10 is formed. In FIG. 10, the line width is, for example, 30 to 100 nm, and the depth is, for example, 30 to 4000 nm. The second fine pattern forming process of the present embodiment has at least a channel forming process and a second etching process. In detail, as shown in the channel forming process shown in FIG. 9 to be described later and the second etching process shown in FIG. 10, after the ONO film 9 is formed on the side surface of the through hole (first hole) formed in the first etching process, A poly-Si film 10 is formed, and a via is formed in the through hole (first hole) 13. Then, a carbon hard mask carbon hard mask (CHM) film 11 is formed in a predetermined pattern, and a fine pattern (second fine pattern) is formed by dry etching at a desired line width and depth.

圖9是表示在作為形成通道用的第一孔的貫通孔13的內壁,例如形成SiO2膜6/Si3N4膜7/SiO2膜8的ONO膜9,然後形成多晶矽(Poly-Si)通道10的通道形成(通道形成工程)後的剖面圖。在此,有關ONO膜9,SiO2膜及Si3N4膜是分別被成膜,且被層疊於水平方向(橫方向)。膜厚是分別為0.5nm~7nm,溫度是400~800℃的範圍。並且,作為通道的多晶矽膜的成膜條件是為了埋溝而設定成充分的膜厚,例如堆積100nm程度以上。成膜溫度是400~800℃。由降低膜應力的觀點,最好成膜溫度低。多晶矽膜也同樣,最好以CVD法成膜。並且,以非晶形矽(α-Si)的代替亦也可能。使用非晶形矽時的成膜條件是在與多晶矽同等的成膜條件內成 膜。 Fig. 9 is a view showing an inner wall of a through hole 13 as a first hole for forming a channel, for example, an ONO film 9 in which a SiO 2 film 6 / Si 3 N 4 film 7 / SiO 2 film 8 is formed, and then polycrystalline germanium is formed (Poly- Si) A cross-sectional view of the channel formation of channel 10 (channel formation engineering). Here, the ONO film 9, the SiO 2 film, and the Si 3 N 4 film are formed separately, and are stacked in the horizontal direction (lateral direction). The film thickness is 0.5 nm to 7 nm, and the temperature is 400 to 800 °C. Further, the film formation conditions of the polycrystalline germanium film as the channel are set to a sufficient film thickness for the buried trench, and for example, a thickness of 100 nm or more is deposited. The film formation temperature is 400 to 800 °C. From the viewpoint of lowering the film stress, it is preferable that the film formation temperature is low. Similarly, the polycrystalline germanium film is preferably formed by a CVD method. Further, substitution with amorphous yttrium (α-Si) is also possible. The film formation conditions in the case of using an amorphous crucible are film formation under the same film formation conditions as polycrystalline germanium.

另外,在貫通孔(第一孔)13的內壁所形成的ONO膜9是作為後述的Si選擇蝕刻的抑止(阻擋)膜的機能。在此,由以往(2D)的Floating Gate型到3DNAND快閃記憶體製作製程是被改良成具有電荷不易洩漏,且單元間干擾小等的特徵之CTF(ChargeTrap Flash)型。亦即,在3DNAND快閃記憶體中,寫入或消去電荷的機構或構造為了製作與Floating型不同的CTF構造,上述的ONO膜為必須。 In addition, the ONO film 9 formed on the inner wall of the through hole (first hole) 13 functions as a suppressing (blocking) film for Si selective etching which will be described later. Here, the conventional (2D) Floating Gate type to 3D NAND flash memory manufacturing process is a CTF (Charge Trap Flash) type which is improved to have characteristics such that electric charges are not easily leaked and inter-cell interference is small. That is, in the 3D NAND flash memory, the mechanism or structure for writing or erasing charges is necessary in order to produce a CTF structure different from the floating type.

圖10是為了形成作為電極的字元線而在各通道間藉由乾蝕刻來形成溝(第二孔)的圖案(第2蝕刻工程)後的圖。另外,第2蝕刻處理是與第1蝕刻處理相同的處理條件。 FIG. 10 is a view showing a pattern (second etching process) in which grooves (second holes) are formed by dry etching between the respective channels in order to form word lines as electrodes. Further, the second etching process is the same processing condition as the first etching process.

作為硬質遮罩的碳膜11是藉由CVD法來成膜。膜厚是在蝕刻被蝕刻層的層疊膜時充分留下的膜厚。例如最好400nm以上。成膜溫度是200~550℃。 The carbon film 11 as a hard mask is formed by a CVD method. The film thickness is a film thickness that is sufficiently left when the laminated film of the layer to be etched is etched. For example, it is preferably 400 nm or more. The film formation temperature is 200 to 550 °C.

上述層疊膜的乾蝕刻(第2蝕刻處理)是例如SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一個。 The dry etching (second etching treatment) of the laminated film is, for example, any one of SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 /O 2 mixed gas.

在上述第1蝕刻工程及上述第2蝕刻工程的乾蝕刻處理是周知的技術,蝕刻條件也相同為理想。將蝕刻條件形成同樣的理由是可舉一旦切換氣體則形成微粒主要因素及引起蝕刻殘留的可能性會減少等。但,第1蝕刻後的通道形成是在通道形成前需要ONO膜9的形成,因 此亦可僅該ONO膜9的厚度,變更乾蝕刻的線寬。另外,乾蝕刻之溝14的深度是在第1蝕刻工程及第2蝕刻工程相同。 The dry etching treatment in the first etching process and the second etching process is a well-known technique, and the etching conditions are also preferably the same. The reason why the etching conditions are formed for the same reason is that the main factor of forming the fine particles and the possibility of causing the etching residue are reduced when the gas is switched. However, the formation of the channel after the first etching requires the formation of the ONO film 9 before the formation of the channel, because This may change the line width of the dry etching only by the thickness of the ONO film 9. Further, the depth of the dry etching trench 14 is the same in the first etching process and the second etching process.

另外,乾蝕刻後(第2蝕刻工程終了後)是進行RCA洗淨,除去乾蝕刻時的殘渣。此時,藉由上述RCA洗淨,Poly-Si膜4會有被氧化的情形,因此最好在其次的步驟(Step3)的氣體蝕刻處理前進行HF處理等作為前處理。 Further, after the dry etching (after the completion of the second etching process), the RCA was washed to remove the residue at the time of dry etching. At this time, since the Poly-Si film 4 is oxidized by the RCA cleaning, it is preferable to perform HF treatment or the like as a pretreatment before the gas etching process in the next step (Step 3).

其次,圖5的步驟S3(Step3)所示的Si選擇蝕刻工程(第3微細圖案形成處理),如後述般,藉由本發明技術的氣體蝕刻來進行高選擇除去多晶矽(Poly-Si)膜4的處理。詳細是如圖11所示般,不會有除去含矽率比以矽為主成分的第1膜(本實施形態的多晶矽膜4)更少的膜(例如,本實施形態的多晶矽氧化膜3,6或矽氧氮化膜或矽氮化膜2及碳膜等的硬質遮罩膜11)之第2膜的情形,亦即在留下前述第2膜的狀態下,藉由蝕刻處理來除去前述第1膜。在此本實施形態所使用的蝕刻氣體是可進行不僅選擇性還具有各向同性的蝕刻。因此,以本實施形態的多晶矽膜4(第1膜)及本實施形態的多晶矽氧化膜3(第2膜)所構成的層疊膜之中,可不蝕刻前述第2膜,僅蝕刻前述第1膜。在此,亦可將矽氮化膜(Si3N4膜)2定義為第3膜,此情況也是若根據本實施形態,則可不蝕刻前述第2膜及第3膜,僅蝕刻前述第1膜。 Next, in the Si selective etching process (third fine pattern forming process) shown in step S3 (Step 3) of FIG. 5, as described later, the polycrystalline germanium (Poly-Si) film 4 is removed by gas etching by the technique of the present invention. Processing. Specifically, as shown in FIG. 11, there is no film which removes a first film (polycrystalline germanium film 4 of the present embodiment) having a ruthenium ratio as a main component (for example, the polysilicon oxide film 3 of the present embodiment). In the case of the second film of the hard mask film 11) such as the tantalum oxynitride film or the tantalum nitride film 2 or the carbon film, that is, the second film is left, the etching is removed by etching. The first film described above. The etching gas used in the present embodiment can be etched which is not only selective but also isotropic. Therefore, in the laminated film including the polycrystalline silicon film 4 (first film) of the present embodiment and the polycrystalline silicon oxide film 3 (second film) of the present embodiment, the first film can be etched only without etching the second film. . Here, the tantalum nitride film (Si 3 N 4 film) 2 may be defined as the third film. In this case, according to the present embodiment, the first film and the third film may not be etched, and only the first film may be etched. membrane.

本實施形態之含氟的蝕刻氣體Si膜(多晶矽膜4等)以外選擇性高,因此不會有除去Si膜以外的膜(多晶矽氧化膜3等)(過蝕刻)的情形,可只除去基板表面的Si膜(多晶矽膜4等)。其理由是因為此含氟的蝕刻氣體對於第1膜及第2膜(多晶矽氧化膜3等)的選擇比例如與ClF3氣體、XeF2氣體作比較也十分高。因此,確保Si膜(多晶矽膜4等)充分被除去的時間,Si膜(多晶矽膜4等)被除去後,即使第2膜(多晶矽氧化膜3等)例如露出於基板表面也不會有過蝕刻的情形,實現蝕刻阻擋層的任務。 Since the fluorine-containing etching gas Si film (such as the polysilicon film 4) of the present embodiment has high selectivity, the film (such as the polysilicon oxide film 3) (over-etching) other than the Si film is not removed, and only the substrate can be removed. Si film on the surface (polysilicon film 4, etc.). The reason for this is that the selection ratio of the fluorine-containing etching gas to the first film and the second film (polysilicon oxide film 3, etc.) is also very high, for example, compared with ClF 3 gas or XeF 2 gas. Therefore, when the Si film (polysilicon film 4 or the like) is sufficiently removed, the Si film (polysilicon film 4 or the like) is removed, and even if the second film (polysilicon oxide film 3 or the like) is exposed on the substrate surface, for example, there is no possibility. In the case of etching, the task of etching the barrier layer is achieved.

在此,所謂「高選擇性」是意指將例如以矽為主成分的第1膜(本實施形態的多晶矽膜4)的蝕刻速率形成比含矽率少於第1膜的膜(本實施形態的矽氧化膜3,6或矽氧氮化膜或矽氮化膜2及碳膜等的硬質遮罩膜11)的第2膜更極為高。更好是意指不蝕刻第2膜,而蝕刻第1膜。並且,在此所謂「各向異性」是意指只在一方向在此是垂直方向蝕刻,所謂「各向同性」是意指除了垂直方向以外,在水平方向(橫方向)等的其他方向也蝕刻。 Here, the term "high selectivity" means that the etching rate of the first film (polycrystalline silicon film 4 of the present embodiment) containing ruthenium as a main component is formed to be smaller than that of the first film (this embodiment). The second film of the hard oxide film 3, 6 or the tantalum oxynitride film or the tantalum nitride film 2 and the hard mask film 11 such as a carbon film is extremely high. More preferably, the first film is etched without etching the second film. In addition, "anisotropy" as used herein means that the direction is etched in the vertical direction only in one direction, and "isotropic" means that in the other direction, such as the horizontal direction (horizontal direction), in addition to the vertical direction. Etching.

本實施形態是使用IF7氣體作為以矽為主成分的第1膜(本實施形態的多晶矽膜4)的除去處理的蝕刻氣體,使用以下的處理條件C1進行蝕刻處理。 In the present embodiment, an etching gas using IF 7 gas as a removal process of the first film (polycrystalline germanium film 4 of the present embodiment) containing ruthenium as a main component is used, and etching treatment is performed using the following processing condition C1.

處理條件C1是基板溫度為室溫(在此是30℃)~50℃的範圍,較理想是室溫~40℃的範圍,處理室445內的 壓力為100Pa~1000Pa,較理想是200~500Pa的範圍,IF7氣體的流量為0.5slm~4slm,較理想是0.5slm~1slm的範圍,載流氣體的N2氣體的流量為0slm~1slm的範圍。 The processing condition C1 is a range in which the substrate temperature is room temperature (here, 30 ° C) to 50 ° C, preferably in the range of room temperature to 40 ° C, and the pressure in the processing chamber 445 is 100 Pa to 1000 Pa, preferably 200 to 500 Pa. The range of the IF 7 gas is 0.5 slm to 4 slm, preferably 0.5 slm to 1 slm, and the flow rate of the N 2 gas of the carrier gas is in the range of 0 slm to 1 slm.

使用IF7氣體時,藉由在50℃以下進行,Si膜的蝕刻速率會提升,至少可維持與底層的Si3N4膜及構成層疊膜的SiO2膜的高選擇性(確保高選擇比)。並且,40℃以下時,可更確保高選擇比。又,壓力為100Pa~1000Pa時,可確保高選擇,200~500Pa時,可更確保高選擇比。又,流量為0.5slm~4slm時,可確保高選擇比,0.5slm~1slm時,可更確保高選擇比。 When IF 7 gas is used, the etching rate of the Si film is increased by 50 ° C or less, and at least the high selectivity to the underlying Si 3 N 4 film and the SiO 2 film constituting the laminated film can be maintained (ensure high selection ratio) ). Moreover, when it is 40 ° C or less, the high selection ratio can be ensured. In addition, when the pressure is 100Pa~1000Pa, high selection can be ensured, and when it is 200~500Pa, the high selection ratio can be ensured. Moreover, when the flow rate is 0.5 slm to 4 slm, the high selection ratio can be ensured, and when the ratio is 0.5 slm to 1 slm, the high selection ratio can be ensured.

在本實施形態中,被交替層疊SiO2膜3、Poly-Si膜4的層疊膜之中,Poly-Si膜4會在蝕刻工程被除去。其次,Poly-Si膜4被除去後,含氟的氣體蝕刻會與和前述SiO2膜3同膜種的前述ONO膜9的SiO2膜6(SiO2膜8)接觸。在此時間點,利用含氟的蝕刻氣體之除去終了。在形成於層疊膜的Poly-Si膜4全部被除去的時間點,利用含氟的蝕刻氣體之蝕刻工程終了。此時,即使Poly-Si膜4的除去速度在層疊膜的上下不同時,也不會成大問題。這是因為本實施形態的蝕刻氣體與其他膜種(SiO2膜3)的選擇性高很多。 In the present embodiment, among the laminated films in which the SiO 2 film 3 and the Poly-Si film 4 are alternately laminated, the Poly-Si film 4 is removed in an etching process. Next, after the Poly-Si film 4 is removed, the fluorine-containing gas is etched into contact with the SiO 2 film 6 (SiO 2 film 8) of the ONO film 9 which is the same as the SiO 2 film 3 . At this point in time, the removal by the fluorine-containing etching gas is terminated. At the time when all of the Poly-Si film 4 formed on the laminated film was removed, the etching process using the fluorine-containing etching gas was completed. At this time, even if the removal speed of the Poly-Si film 4 is different between the upper and lower sides of the laminated film, there is no problem. This is because the etching gas of the present embodiment is much more selective than other film species (SiO 2 film 3).

如此,對於構成層疊膜的SiO2膜3可持高的選擇性(高選擇性地)蝕刻Poly-Si膜4,且對於底層的Si3N4膜2也可高選擇性地蝕刻Poly-Si膜4。亦即,可一面抑制SiO2膜3或Si3N4膜2的蝕刻,一面高選擇性地蝕 刻除去Poly-Si膜4。然後,此時,藉由在50℃以下的溫度實施蝕刻,可防止在100℃以下或400℃以下的低溫成膜的SiO2膜因溫度而變化。 Thus, the Poly-Si film 4 can be etched with high selectivity (high selectivity) for the SiO 2 film 3 constituting the laminated film, and the Poly-Si can be etched with high selectivity for the underlying Si 3 N 4 film 2 Membrane 4. In other words, the Poly-Si film 4 can be etched and removed with high selectivity while suppressing etching of the SiO 2 film 3 or the Si 3 N 4 film 2. Then, at this time, by performing etching at a temperature of 50 ° C or lower, it is possible to prevent the SiO 2 film formed at a low temperature of 100 ° C or lower or 400 ° C or lower from changing due to temperature.

而且,蝕刻後,除去蝕刻氣體的淨化工程中,與利用IF7氣體的蝕刻一起,作為上述副生成物生成的IF5氣體也為氣體,因此可想像不會有附著於基板上的情形,可容易淨化。但,為了更確實地淨化副生成物,將基板溫度控制成副生成物的昇華溫度的95℃以上為理想。藉由如此一邊以惰性氣體淨化,一邊將基板溫度形成副生成物的昇華溫度以上,可期待淨化效率格外提升。但,有時在100℃以下形成SiO2膜,所以此時若加熱基板溫度,則會有不能無視溫度所產生的影響的情況,因此需要注意。 Further, in the purification process for removing the etching gas after the etching, the IF 5 gas generated as the by-product is also a gas together with the etching by the IF 7 gas, and therefore it is conceivable that it does not adhere to the substrate. Easy to purify. However, in order to purify the by-product more reliably, it is preferable to control the substrate temperature to 95 ° C or higher of the sublimation temperature of the by-product. By purifying the inert gas, the substrate temperature is equal to or higher than the sublimation temperature of the by-product, and the purification efficiency can be expected to be particularly improved. However, the SiO 2 film may be formed at 100 ° C or lower. Therefore, if the substrate temperature is heated at this time, there is a case where the influence of the temperature cannot be ignored. Therefore, care must be taken.

然後,藉由例如使用O2氣體的周知的蝕刻處理來除去作為硬質遮罩膜的CHM膜11(CHM膜除去工程)。另外,特別是非晶形碳膜的CHM膜時,因為對於在本基板處理工程之後的後工程進行的高溫退火製程、氧化製程、O2灰化機製程弱,所以為了在後工程中抑制基板背側的膜剝離所引起的微粒,需要除去。 Then, the CHM film 11 (CHM film removal process) as a hard mask film is removed by, for example, a well-known etching treatment using O 2 gas. In addition, especially in the case of the CHM film of the amorphous carbon film, since the high-temperature annealing process, the oxidation process, and the O 2 ashing mechanism are weak for the post-engineering process after the substrate processing, the back side of the substrate is suppressed in the post-engineering process. The particles caused by the peeling of the film need to be removed.

其次,圖5的步驟S4所示的電極形成工程(第4微細圖案形成處理)是如圖13所示般進行在藉由本發明技術的氣體蝕刻所形成的第3微細圖案中形成成為電極的預定的導電膜(例如金屬膜、金屬化合物等)之處理。藉此,以和第2微細圖案相同的線寬來形成第4微細 圖案。並且,形成第4微細圖案的工程是至少具有圖12所示的導電膜形成工程及圖13所示的第4蝕刻工程。 Next, the electrode forming process (fourth fine pattern forming process) shown in step S4 of FIG. 5 is a process of forming an electrode into a third fine pattern formed by gas etching according to the technique of the present invention as shown in FIG. Treatment of a conductive film (for example, a metal film, a metal compound, etc.). Thereby, the fourth fineness is formed by the same line width as the second fine pattern. pattern. Further, the process of forming the fourth fine pattern has at least the conductive film forming process shown in FIG. 12 and the fourth etching process shown in FIG.

圖12是將成為字元線的金屬電極予以成膜(導電膜形成工程)後的圖。在圖中顯示作為使用在電極的導電膜的鎢膜之一例。成膜方法是例如使用在CVD法。成膜溫度是150~500℃的範圍。並且,導電膜是除了鎢膜以外,亦可為TiN膜、TiN/Al膜、或TaN/W膜。 FIG. 12 is a view showing a state in which a metal electrode to be a word line is formed (conductive film formation process). An example of a tungsten film as a conductive film used in an electrode is shown in the drawing. The film formation method is, for example, used in a CVD method. The film formation temperature is in the range of 150 to 500 °C. Further, the conductive film may be a TiN film, a TiN/Al film, or a TaN/W film in addition to the tungsten film.

圖13是在將導電膜(本實施形態的鎢膜)成膜後藉由乾蝕刻來形成字元線(第4蝕刻處理)後的圖。 FIG. 13 is a view in which a word line (fourth etching process) is formed by dry etching after forming a conductive film (tungsten film of the present embodiment).

其次,如圖13所示般,藉由使用例如SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體之周知的乾蝕刻處理來加工前述預定的導電(金屬等)膜,以和第2微細圖案相同的線寬來形成本發明的第4微細圖案。另外,第4蝕刻處理是與第1(或第2)蝕刻處理相同。 Next, as shown in FIG. 13, the aforementioned processing is performed by a well-known dry etching treatment using, for example, SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 /O 2 mixed gas. The predetermined conductive (metal or the like) film forms the fourth fine pattern of the present invention with the same line width as the second fine pattern. Further, the fourth etching process is the same as the first (or second) etching process.

另外,在含多晶矽的層疊膜之中只將多晶矽高選擇蝕刻的例子是舉3DNAND的製程為例進行說明,但3DNAND的形成是不限於上述說明的3DNAND的形成製程。 Further, an example in which only the polycrystalline germanium is selectively etched in the polycrystalline germanium-containing stacked film is a 3D NAND process, but the formation of the 3D NAND is not limited to the above-described 3D NAND forming process.

(本實施形態的變形例) (Modification of this embodiment)

例如,在圖5所示的本實施形態的微細圖案形成方法的第2微細圖案形成工程中,如圖9所示般,形成多晶矽膜的通道。此通道形成工程是在將多晶矽成膜之前,在第 1微細圖案形成時所形成的貫通孔13的側面形成ONO膜9。亦可取代此ONO膜9,而使用Al2O3/Si3N4/SiO2的膜。此情況,Al2O3膜、Si3N4膜、SiO2膜是分別被成膜,被層疊。各膜厚是0.5nm~7nm的範圍中的任一,溫度是400~800℃的範圍中的任一。此情況,通道不是多晶矽,而是非晶形矽為理想。這是因為可抑制結晶粒界起因的裝置特性的偏差的影響。 For example, in the second fine pattern forming process of the fine pattern forming method of the present embodiment shown in FIG. 5, as shown in FIG. 9, a channel of the polysilicon film is formed. This channel formation process is such that the ONO film 9 is formed on the side surface of the through hole 13 formed at the time of forming the first fine pattern before the polycrystalline silicon is formed into a film. Instead of this ONO film 9, a film of Al 2 O 3 /Si 3 N 4 /SiO 2 may be used. In this case, the Al 2 O 3 film, the Si 3 N 4 film, and the SiO 2 film were each formed into a film and laminated. Each film thickness is any one of a range of 0.5 nm to 7 nm, and the temperature is any one of a range of 400 to 800 °C. In this case, the channel is not polycrystalline, but amorphous is ideal. This is because it is possible to suppress the influence of variation in device characteristics caused by crystal grain boundaries.

3.在本實施形態的基板處理裝置的基板處理方法 3. Substrate processing method of the substrate processing apparatus of the present embodiment

其次,在以下說明有關本實施形態的基板處理裝置20的基板處理工程的一例。此基板處理工程是進行上述的Si選擇蝕刻工程S3者,Si選擇蝕刻工程(第3蝕刻工程)S3是利用第1處理單元410(510)來實施。此基板處理工程是例如作為在基板上製造半導體裝置的半導體製造工程的一工程實施。在此基板處理工程中,基板處理裝置20的各構成部的動作是藉由控制器600來控制。將以下說明的S21~S80稱為本實施形態的基板處理裝置20的基板處理工程。 Next, an example of the substrate processing work of the substrate processing apparatus 20 of the present embodiment will be described below. This substrate processing is performed by the above-described Si selective etching process S3, and the Si selective etching process (third etching process) S3 is performed by the first processing unit 410 (510). This substrate processing project is, for example, an engineering implementation as a semiconductor manufacturing process for manufacturing a semiconductor device on a substrate. In this substrate processing project, the operations of the respective components of the substrate processing apparatus 20 are controlled by the controller 600. S21 to S80 described below are referred to as substrate processing works of the substrate processing apparatus 20 of the present embodiment.

(初期冷卻劑流量控制工程S21) (Initial coolant flow control project S21)

在第1處理單元410中,冷卻劑流量控制部486是控制冷卻劑供給單元491,使被調整成預先被設定的流量及溫度的冷卻劑,在外部基座冷卻劑流路489a,基座冷卻劑流路464,外部基座冷卻劑流路489b中循環於箭號 489c的方向。 In the first processing unit 410, the coolant flow rate control unit 486 controls the coolant supply unit 491 to adjust the coolant to the flow rate and temperature set in advance, and the base susceptor coolant flow path 489a is cooled by the susceptor. The agent flow path 464, the external base coolant flow path 489b is circulated in the arrow Direction of 489c.

(初期加熱器溫度調整工程S22) (Initial heater temperature adjustment project S22)

在第1處理單元410中,加熱器溫度控制部485是將預先被設定的初期電力供給至加熱器463,以基座平台411能夠成為所望的溫度之方式使加熱器463發熱。 In the first processing unit 410, the heater temperature control unit 485 supplies the initial power set in advance to the heater 463, and causes the heater 463 to generate heat so that the base stage 411 can reach a desired temperature.

在第2處理單元510中也是第2處理單元510的加熱器溫度控制部會進行與第1處理單元410的加熱器溫度控制部485同樣的控制。 In the second processing unit 510, the heater temperature control unit of the second processing unit 510 performs the same control as the heater temperature control unit 485 of the first processing unit 410.

(基座溫度檢測工程S23) (Base temperature detection project S23)

初期冷卻劑流量控制工程S21及初期加熱器溫度調整工程S22之後,第1處理單元410的溫度檢測部488是檢測出基座459的溫度。在第2處理單元510中也是第2處理單元510的溫度檢測部會檢測出基座的溫度。被檢測出的基座溫度的資訊是被輸入至控制器600。 After the initial coolant flow rate control project S21 and the initial heater temperature adjustment process S22, the temperature detecting unit 488 of the first processing unit 410 detects the temperature of the susceptor 459. In the second processing unit 510, the temperature detecting unit of the second processing unit 510 detects the temperature of the susceptor. Information of the detected susceptor temperature is input to the controller 600.

(基座溫度判定工程S24) (Base temperature determination project S24)

控制器600是當所被檢測出的溫度資料(基座459的溫度)判定為預定的溫度範圍時,亦即「Yes」時,移至其次的基板載置工程S31。 When the detected temperature data (the temperature of the susceptor 459) is determined to be a predetermined temperature range, that is, "Yes", the controller 600 moves to the next substrate mounting project S31.

當所被檢測出的溫度資料為與預定的溫度範圍不同的資訊時,亦即「No」時,至形成預定的溫度為止,重複初期冷卻劑流量控制工程S21及初期加熱器溫度 調整工程S22,及之後的基座溫度檢測工程S23。 When the detected temperature data is information different from the predetermined temperature range, that is, "No", the initial coolant flow control project S21 and the initial heater temperature are repeated until a predetermined temperature is formed. The adjustment project S22, and the subsequent susceptor temperature detection project S23.

S21~S24是處理晶圓之前的準備階段,在此是將S21~S24稱為初期工程。 S21~S24 are the preparation stages before processing the wafer. Here, S21~S24 are called initial projects.

(第1處理工程) (first processing project)

其次,實施由以下的S31~S40所構成,包含第1蝕刻處理工程的第1處理工程。 Next, the first processing project including the first etching process is performed by the following S31 to S40.

(晶圓載置工程S31) (Wafer Mounting Project S31)

基座溫度成為預定的溫度範圍之後,真空搬送機器人320會朝處理室445搬送晶圓60。具體而言,搭載晶圓60的真空搬送機器人320的手指321會進入處理室445,手指321會將晶圓60載置於上昇的昇降銷413。藉由載置晶圓60的昇降銷413下降,晶圓60會被載置於基座平台411上。 After the susceptor temperature reaches a predetermined temperature range, the vacuum transfer robot 320 transports the wafer 60 toward the processing chamber 445. Specifically, the finger 321 of the vacuum transfer robot 320 on which the wafer 60 is mounted enters the processing chamber 445, and the finger 321 places the wafer 60 on the raised lift pin 413. The wafer 60 is placed on the susceptor stage 411 by the lowering of the lift pins 413 on which the wafer 60 is placed.

在此晶圓60是施以前述的圖5所示的步驟S1及S2。詳細是在晶圓60的表側,如圖10所示般,形成第2微細圖案。更詳細是此晶圓60會在交替層疊至少2層以上以矽為主成分的第1膜(本實施形態的多晶矽膜4)及含矽率比前述第1膜更少的膜的第2膜之層疊膜中設有複數的貫通孔(第一孔),且在埋設於前述複數的貫通孔(第一孔)13的通道10間形成溝(第二孔)14。 In this wafer 60, steps S1 and S2 shown in FIG. 5 described above are applied. Specifically, on the front side of the wafer 60, as shown in FIG. 10, a second fine pattern is formed. More specifically, the wafer 60 is formed by alternately stacking at least two or more layers of a first film containing ruthenium as a main component (the polysilicon film 4 of the present embodiment) and a second film having a film having a lower enthalpy ratio than the first film. A plurality of through holes (first holes) are formed in the laminated film, and grooves (second holes) 14 are formed between the channels 10 embedded in the plurality of through holes (first holes) 13.

(第3蝕刻處理工程S32) (3rd etching process S32)

一旦被施以步驟S1~S5的晶圓60載置於基座平台411上,則晶圓60會藉由溫度控制部來加熱至後述的預定的溫度範圍維持。在此,所謂預定的溫度範圍是即使蝕刻氣體無法取得來自外部的強力的能量(例如高頻電力),還是可維持高的選擇性的溫度範圍。例如,七氟化碘時,30℃以上,50℃以下,較理想是30℃以上,40℃以下。此時,溫度的下限是例如考慮溫度的控制性或氣體不液化的溫度而決定。 When the wafer 60 to which the steps S1 to S5 are applied is placed on the susceptor stage 411, the wafer 60 is heated by the temperature control unit to a predetermined temperature range to be described later. Here, the predetermined temperature range is a temperature range in which high selectivity can be maintained even if the etching gas cannot obtain strong energy (for example, high-frequency power) from the outside. For example, in the case of iodine hexafluoride, it is 30 ° C or more and 50 ° C or less, preferably 30 ° C or more and 40 ° C or less. At this time, the lower limit of the temperature is determined, for example, in consideration of the controllability of the temperature or the temperature at which the gas is not liquefied.

其次,控制第2氣體供給單元483,將作為稀釋氣體的氮氣體供給至處理室445內。且併行控制第1氣體供給單元482,從氣體導入口433往處理室445內供給蝕刻氣體(例如IF7氣體)。被供給的蝕刻氣體是碰撞於淋浴板484的板部484a,經由孔部484b在被擴散的狀態下供給至晶圓60。在擴散下均一地供給氣體至晶圓60上,因此可均一地蝕刻晶圓面內。 Next, the second gas supply unit 483 is controlled to supply a nitrogen gas as a diluent gas into the processing chamber 445. The first gas supply unit 482 is controlled in parallel to supply an etching gas (for example, IF 7 gas) from the gas introduction port 433 into the processing chamber 445. The supplied etching gas collides with the plate portion 484a of the shower plate 484, and is supplied to the wafer 60 in a state of being diffused via the hole portion 484b. The gas is uniformly supplied to the wafer 60 under diffusion, so that the wafer surface can be uniformly etched.

此時,在第1氣體供給單元482中,來自第1氣體源482b的IF7氣體的流量是0.5slm~4slm之中,設定成預定的氣體流量,較理想是1slm。來自惰性氣體源482f的N2氣體(載流氣體)的流量是0slm~1slm之中,設定成預定的氣體流量。來自第2氣體供給單元483的N2氣體(稀釋氣體)的流量是0.1slm~3slm之中,設定成預定的氣體流量,較理想是0.5slm。處理室445內的壓力是例如100Pa~1000Pa之中,設定成預定的壓力,較理想是200Pa~500Pa。 At this time, in the first gas supply unit 482, the flow rate of the IF 7 gas from the first gas source 482b is 0.5 slm to 4 slm, and is set to a predetermined gas flow rate, preferably 1 slm. The flow rate of the N 2 gas (carrier gas) from the inert gas source 482f is 0 slm to 1 slm, and is set to a predetermined gas flow rate. The flow rate of the N 2 gas (dilution gas) from the second gas supply unit 483 is 0.1 slm to 3 slm, and is set to a predetermined gas flow rate, preferably 0.5 slm. The pressure in the processing chamber 445 is, for example, 100 Pa to 1000 Pa, and is set to a predetermined pressure, and is preferably 200 Pa to 500 Pa.

可是,上述蝕刻氣體是具有一旦與矽膜接觸反應則發熱的性質。所產生的反應熱會藉由熱傳導來傳導至金屬膜或基板,其結果可想像會發生金屬膜的特性劣化或基板的彎曲。而且,可想像晶圓60的溫度會脫離預定的溫度範圍,蝕刻氣體失去高的選擇性。 However, the above etching gas has a property of generating heat upon reaction with the ruthenium film. The generated reaction heat is conducted to the metal film or the substrate by heat conduction, and as a result, it is conceivable that deterioration of characteristics of the metal film or bending of the substrate occurs. Moreover, it is conceivable that the temperature of the wafer 60 will deviate from the predetermined temperature range, and the etching gas loses high selectivity.

蝕刻氣體的濃度與蝕刻速率有比例關係,且蝕刻速率與反應熱量有比例關係,因此提高蝕刻氣體的濃度來使蝕刻速率上昇時,上述的現象更顯著。 The concentration of the etching gas is proportional to the etching rate, and the etching rate is proportional to the heat of reaction. Therefore, when the etching gas concentration is increased to increase the etching rate, the above phenomenon is more remarkable.

於是,與蝕刻氣體一起將稀釋氣體供給至處理室445,藉此使蝕刻氣體的濃度變薄,抑制反應熱所造成過度的溫度上昇。稀釋氣體的供給量是例如比蝕刻氣體的供給量更多為理想。 Then, the dilution gas is supplied to the processing chamber 445 together with the etching gas, whereby the concentration of the etching gas is made thin, and an excessive temperature rise caused by the reaction heat is suppressed. The supply amount of the diluent gas is preferably, for example, more than the supply amount of the etching gas.

另外,在此是幾乎同時開始稀釋氣體與蝕刻氣體的供給,但不限於此,更佳是在供給稀釋氣體之後供給蝕刻氣體為理想。此情況,蝕刻氣體是例如含鹵之類,比稀釋氣體更重的物質,且可不取得來自外部的強力的能量進行蝕刻的氣體為理想。假設同時供給含鹵的氣體及稀釋氣體時,含鹵的氣體會比稀釋氣體更先到達基板上。亦即,濃度高的蝕刻氣體會比稀釋氣體更先到達基板上。此情況,因為被急劇地蝕刻,所以溫度會急劇地上昇,可想像失去高的蝕刻選擇性。為了予以防止,最好在供給稀釋氣體之後供給蝕刻氣體。 In addition, here, the supply of the diluent gas and the etching gas is started almost at the same time, but it is not limited thereto, and it is more preferable to supply the etching gas after supplying the diluent gas. In this case, the etching gas is preferably a halogen-containing material which is heavier than the diluent gas, and is preferably a gas which is etched without obtaining strong energy from the outside. Assuming that the halogen-containing gas and the diluent gas are simultaneously supplied, the halogen-containing gas reaches the substrate earlier than the diluent gas. That is, the etching gas having a high concentration reaches the substrate earlier than the diluent gas. In this case, since the temperature is sharply etched, the temperature rises abruptly, and it is conceivable that the high etching selectivity is lost. In order to prevent it, it is preferable to supply an etching gas after supplying the diluent gas.

更佳是在稀釋氣體環境充滿處理室的狀態下,處理室的壓力安定之後供給蝕刻氣體。這在稀釋氣體 量相對於蝕刻氣體量充分多時,例如控制蝕刻的深度的製程等有效。由於在壓力安定的狀態下進行蝕刻,因此可使蝕刻速率安定。其結果,容易控制蝕刻的深度。 More preferably, the etching gas is supplied after the pressure of the processing chamber is stabilized in a state where the dilution gas atmosphere is filled in the processing chamber. This is in the dilution gas When the amount is sufficiently large with respect to the amount of etching gas, for example, a process of controlling the depth of etching or the like is effective. Since the etching is performed under a pressure stable state, the etching rate can be stabilized. As a result, it is easy to control the depth of etching.

而且,在本實施形態中,藉由在蝕刻氣體與晶圓接觸的期間,將晶圓60維持於所望的溫度範圍,可同時達成高蝕刻速率的維持,構成基板的膜的特性劣化的防止,基板的彎曲的防止,高蝕刻選擇性的維持之任一方或該等的任一方的組合。 Further, in the present embodiment, by maintaining the wafer 60 in a desired temperature range while the etching gas is in contact with the wafer, the high etching rate can be maintained at the same time, and the deterioration of the characteristics of the film constituting the substrate can be prevented. One of the prevention of the bending of the substrate and the maintenance of the high etching selectivity or a combination of any of the above.

(晶圓溫度檢測工程S33) (Wafer Temperature Inspection Engineering S33)

如前述般,在蝕刻氣體與晶圓60接觸的期間,藉由反應熱來加熱晶圓60。在此是溫度檢測部488會檢測出藉由反應熱來加熱的晶圓60的溫度。 As described above, the wafer 60 is heated by the reaction heat while the etching gas is in contact with the wafer 60. Here, the temperature detecting unit 488 detects the temperature of the wafer 60 heated by the reaction heat.

(晶圓溫度判定工程S34) (Wafer temperature judgment project S34)

在晶圓溫度檢測工程S33所被檢測出的溫度資料是被輸入至控制器600。控制器600判定溫度資料是否為預定的溫度的範圍。為預定的溫度範圍時,亦即「Yes」時,移至S37的加熱器‧冷卻劑控制維持工程。當所被檢測出的溫度資料不是所望的溫度的範圍時,亦即「No」時,移至調整溫度控制部而使晶圓溫度能夠成為所望的溫度之工程(S35,S36)。 The temperature data detected at the wafer temperature detecting project S33 is input to the controller 600. The controller 600 determines whether the temperature data is a range of predetermined temperatures. When the temperature is within the predetermined temperature range, that is, "Yes", the heater is moved to S37 and the coolant control is maintained. When the detected temperature data is not in the range of the desired temperature, that is, "No", the process proceeds to the adjustment temperature control unit to enable the wafer temperature to be a desired temperature (S35, S36).

(加熱器溫度調整工程S35) (heater temperature adjustment project S35)

一旦在晶圓溫度判定工程S34判定晶圓溫度不是預定的溫度範圍,則加熱器溫度控制部485會控制往加熱器463的電力供給量。本實施形態的情況,晶圓60的溫度會藉由反應熱來上昇至比預定的溫度範圍的上限值更高的溫度,因此為了維持於預定的溫度而使加熱器463的溫度下降。 When the wafer temperature determination process S34 determines that the wafer temperature is not the predetermined temperature range, the heater temperature control unit 485 controls the amount of electric power supplied to the heater 463. In the case of the present embodiment, the temperature of the wafer 60 is raised to a temperature higher than the upper limit of the predetermined temperature range by the heat of reaction. Therefore, the temperature of the heater 463 is lowered in order to maintain the predetermined temperature.

(冷卻劑流量調整工程S36) (Coolant flow adjustment project S36)

一旦判定晶圓溫度不是預定的溫度範圍,則冷卻劑流量控制部486會控制冷卻劑的流量或溫度。本實施形態的情況,晶圓60的溫度會藉由反應熱來上昇至比預定的溫度範圍的上限值更高的溫度,因此為了維持於預定的溫度,而使冷卻劑的流量增加或使冷卻劑的溫度降低。如此一來,可提高晶圓60的冷卻效率。 Once it is determined that the wafer temperature is not a predetermined temperature range, the coolant flow rate control unit 486 controls the flow rate or temperature of the coolant. In the case of the present embodiment, the temperature of the wafer 60 is raised to a temperature higher than the upper limit of the predetermined temperature range by the heat of reaction. Therefore, the flow rate of the coolant is increased or maintained in order to maintain the temperature at a predetermined temperature. The temperature of the coolant is lowered. As a result, the cooling efficiency of the wafer 60 can be improved.

像加熱器溫度調整工程S35或冷卻劑流量調整工程S36那樣控制加熱器463及冷卻劑流量之下,晶圓60會調整成預定的溫度範圍。調整後,移至晶圓溫度檢測工程S33。如此至晶圓60形成預定的溫度範圍為止,重複S33~S36。 The wafer 60 is adjusted to a predetermined temperature range under the control of the heater 463 and the coolant flow rate as in the heater temperature adjustment process S35 or the coolant flow adjustment process S36. After adjustment, move to wafer temperature inspection project S33. Thus, until the wafer 60 forms a predetermined temperature range, S33 to S36 are repeated.

另外,本實施形態是在加熱器溫度調整工程S35之後實施冷卻劑流量調整工程S36,但並非限於此。例如,亦可在晶圓溫度判定工程S34之後進行冷卻劑流量調整工程S36,然後實施加熱器溫度調整工程S35。或者在晶圓溫度判定工程S34之後,並行實施冷卻劑流量調整 工程S36與加熱器溫度調整工程S35。 Further, in the present embodiment, the coolant flow rate adjustment project S36 is performed after the heater temperature adjustment process S35, but the present invention is not limited thereto. For example, the coolant flow rate adjustment project S36 may be performed after the wafer temperature determination process S34, and then the heater temperature adjustment process S35 may be performed. Or perform coolant flow adjustment in parallel after wafer temperature determination project S34 Engineering S36 and heater temperature adjustment project S35.

並且,在本實施形態中,為了使晶圓60的溫度下降,而控制成使加熱器463的溫度下降,使冷卻劑的流量增加,但並不限於此,只要藉由加熱器463的控制與冷卻劑流量的控制的協調動作,控制成晶圓60的溫度結果降低形成預定的溫度範圍即可。 Further, in the present embodiment, in order to lower the temperature of the wafer 60, the temperature of the heater 463 is controlled to decrease, and the flow rate of the coolant is increased. However, the present invention is not limited thereto, and is controlled by the heater 463. The coordinated action of the control of the coolant flow rate is controlled so that the temperature of the wafer 60 is lowered to form a predetermined temperature range.

又,當晶圓60的溫度比預定的溫度範圍的下限值更低時,只要藉由加熱器463的控制與冷卻劑流量的控制的協調動作,控制成晶圓60的溫度結果上昇即可。 Further, when the temperature of the wafer 60 is lower than the lower limit value of the predetermined temperature range, the temperature of the wafer 60 can be controlled to rise as long as the control of the heater 463 and the control of the coolant flow rate are coordinated. .

(加熱器‧冷卻劑控制維持工程S37) (Heater ‧ Coolant Control Maintenance Engineering S37)

一旦在晶圓溫度判定工程S34判定晶圓溫度為預定的溫度範圍,則為了予以維持,而維持加熱器463的控制及冷卻劑流量的控制,維持晶圓60的溫度。 When the wafer temperature determination process S34 determines that the wafer temperature is within a predetermined temperature range, the control of the heater 463 and the control of the coolant flow rate are maintained to maintain the temperature of the wafer 60 in order to maintain it.

(處理時間判定工程S38) (Processing time determination project S38)

判定S32的蝕刻處理時間是否經過預定的時間,亦即對於晶圓60的蝕刻處理是否終了。當判定經過預定的時間時,亦即「Yes」時,移至S39。當判定未經過預定的時間時,亦即「No」時,回到S32繼續進行蝕刻處理。 It is determined whether or not the etching processing time of S32 has elapsed for a predetermined time, that is, whether the etching process for the wafer 60 is finished. When it is determined that the predetermined time has elapsed, that is, "Yes", the process proceeds to S39. When it is determined that the predetermined time has not elapsed, that is, "No", the process returns to S32 to continue the etching process.

如此,不會有除去含矽率比以矽為主成分的第1膜(本實施形態的多晶矽膜4)更少的膜(本實施形態的矽氧化膜3或矽氧氮化膜或矽氮化膜2及碳膜等的硬質遮罩膜5)之第2膜的情形,只將前述第1膜藉由蝕刻 處理來除去。然後,在蝕刻處理終了的階段,在留下構成晶圓60的層疊膜的SiO2膜3的狀態下除去Poly-Si膜4的全部。 Thus, there is no film which removes the first film (the polysilicon film 4 of the present embodiment) having a higher enthalpy ratio than yttrium as the main component (the ruthenium oxide film 3 or the ruthenium oxynitride film or the ruthenium nitride of the present embodiment). In the case of the second film of the hard mask film 5) such as the film 2 and the carbon film, only the first film is removed by etching. Then, at the stage where the etching process is completed, all of the Poly-Si film 4 is removed while leaving the SiO 2 film 3 constituting the laminated film of the wafer 60.

(氣體供給停止工程S39) (Gas supply stop project S39)

一旦在處理時間判定工程S38判定經過預定的時間,則控制第1氣體供給單元482,停止蝕刻氣體的供給。停止蝕刻氣體的供給之後,以蝕刻氣體不會留在處理室445內的方式,控制第1氣體供給單元482的淨化氣體供給系來將氣體供給管482a的殘留氣體排出,且控制第2氣體供給單元483來將惰性氣體供給至處理室445內,將處理室445內的環境排出。如此一來,將處理室445內的環境置換成惰性氣體。 When the processing time determination process S38 determines that a predetermined time has elapsed, the first gas supply unit 482 is controlled to stop the supply of the etching gas. After the supply of the etching gas is stopped, the purge gas supply system of the first gas supply unit 482 is controlled to discharge the residual gas of the gas supply pipe 482a, and the second gas supply is controlled so that the etching gas does not remain in the processing chamber 445. Unit 483 supplies inert gas into processing chamber 445 to vent the environment within processing chamber 445. As such, the environment within the processing chamber 445 is replaced with an inert gas.

另外,若一邊供給惰性氣體來淨化處理室445內,一邊進行加熱器463的控制,而使晶圓溫度能夠形成預定的溫度(例如藉由蝕刻氣體與第1膜的熱分解所產生的副生成物的昇華溫度)以上,則更為理想。但,第2膜之中若以100℃以下的低溫成膜,則淨化工程時的加熱,即使淨化效率變佳,也會有可能使上述的第2膜遭到不良影響。 Further, when the inert gas is supplied to purify the inside of the processing chamber 445, the heater 463 is controlled to form a predetermined temperature (for example, by the thermal decomposition of the etching gas and the first film). Above the sublimation temperature of the substance), it is more desirable. However, when the film is formed at a low temperature of 100 ° C or lower in the second film, heating in the purification process may adversely affect the above-described second film even if the purification efficiency is improved.

(晶圓搬出工程S40) (Wafer Removal Project S40)

將處理室445內的環境置換成惰性氣體之後,以和載置晶圓60相反的程序,真空搬送機器人320會將晶圓60從處理室445搬出至傳送模組310。 After replacing the environment in the processing chamber 445 with an inert gas, the vacuum transfer robot 320 carries the wafer 60 out of the processing chamber 445 to the transfer module 310 in a procedure opposite to the mounting of the wafer 60.

接著,真空搬送機器人320會將傳送模組310內的晶圓60搬送至裝載鎖定腔室部200的緩衝單元210,其次,大氣搬送機器人130會將緩衝單元210內的晶圓60搬送至裝載埠120上的FOUP110。 Next, the vacuum transfer robot 320 transports the wafer 60 in the transfer module 310 to the buffer unit 210 of the load lock chamber unit 200, and then the atmospheric transfer robot 130 transports the wafer 60 in the buffer unit 210 to the load cassette. FOUP110 on 120.

4.在本實施形態的基板處理裝置的基板處理方法 4. Substrate processing method of the substrate processing apparatus of the present embodiment

接著,利用圖18來說明有關作為第3處理單元的半導體製造工程之一工程實施的基板處理工程。如此的工程是藉由上述的基板處理裝置來實施。在以下的說明中,構成基板處理裝置的各零件的動作是藉由控制器600來控制。 Next, a substrate processing project relating to one of the semiconductor manufacturing processes as the third processing unit will be described with reference to FIG. Such a work is carried out by the above substrate processing apparatus. In the following description, the operations of the respective components constituting the substrate processing apparatus are controlled by the controller 600.

(基板的搬入工程S10) (Substrate loading project S10)

首先,如圖18所示般,具有含矽膜的基板60會從基板搬送室140藉由基板搬送機器人來經由搬送口108搬送至基板處理室50。另外,與第3處理單元的基板處理同樣,此基板60會在交替層疊至少2層以上以矽為主成分的第1膜(本實施形態的多晶矽膜4)及含矽率比前述第1膜更少的膜的第2膜之層疊膜中設有複數的貫通孔(第一孔),且在埋設於前述複數的貫通孔(第一孔)13的通道10間形成溝(第二孔)14。 First, as shown in FIG. 18, the substrate 60 having the ruthenium-containing film is transported from the substrate transfer chamber 140 to the substrate processing chamber 50 via the transfer port 108 by the substrate transfer robot. Further, similarly to the substrate processing of the third processing unit, the substrate 60 is alternately laminated with at least two or more layers of a first film containing ruthenium as a main component (the polysilicon film 4 of the present embodiment) and a ruthenium ratio higher than that of the first film. A plurality of through holes (first holes) are formed in the laminated film of the second film of less film, and grooves (second holes) are formed between the channels 10 embedded in the plurality of through holes (first holes) 13 14.

(矽膜除去工程S20) (film removal engineering S20)

其次,使基板支撐銷上下機構111下降,將基板60 載置於基座459上。在此,基板支撐銷上下機構111的昇降是藉由昇降驅動部來昇降而進行。在基座459中所具備的加熱器是預先加熱至預定的溫度,將基板60加熱成預定的基板溫度。因應所需,用以將過剩的熱(反應熱)排熱的冷卻機構也併用。在此,基板溫度是被控制成後述的除去氣體或處理氣體充分地氣化的溫度帶,形成於晶圓(基板)60的膜特性不會變質的溫度。另外,亦可在第3處理單元也以處理條件C1進行。但,第1處理單元與第3處理單元因為裝置構成有不同,所以處理條件C1未必是最適條件。該情況是需要變更處理條件C1。 Next, the substrate support pin upper and lower mechanism 111 is lowered, and the substrate 60 is placed. Placed on the base 459. Here, the elevation of the substrate support pin vertical/lowering mechanism 111 is performed by raising and lowering the elevation drive unit. The heater provided in the susceptor 459 is previously heated to a predetermined temperature to heat the substrate 60 to a predetermined substrate temperature. A cooling mechanism for exhausting excess heat (reaction heat) is also used in combination as needed. Here, the substrate temperature is a temperature band controlled to be sufficiently vaporized by the removal gas or the processing gas to be described later, and the film characteristics formed on the wafer (substrate) 60 are not deteriorated. Alternatively, the third processing unit may perform the processing condition C1. However, since the first processing unit and the third processing unit are different in device configuration, the processing condition C1 is not necessarily an optimum condition. In this case, it is necessary to change the processing condition C1.

接著,使基座459或基座459及基板支撐銷上下機構111上昇,往基板處理位置B移動,使基板60能夠載置於基座459上。 Next, the susceptor 459 or the susceptor 459 and the substrate support pin vertical mechanism 111 are raised, and moved to the substrate processing position B, so that the substrate 60 can be placed on the susceptor 459.

其次,從氣體供給管106a、106b經由淋浴頭105來將預定的處理氣體供給至基板60,自基板60以處理條件C1進行矽膜的蝕刻。矽膜的蝕刻處理是藉由將處理氣體供給至基板60上來進行。蝕刻處理氣體是使用含鹵氣體,例如由氟(F)、氯(Cl)、溴(Br)、碘(I)之中含二個以上的鹵元素的氣體。較理想是使用含2種類鹵元素的氣體。例如,有五氟化碘(IF5)、七氟化碘(IF7)、三氟化溴(BrF3)、五氟化溴(BrF5)、二氟化氙(XeF2)、三氟化氯(ClF3)等。更理想是使用IF7。IF7是可使含矽膜一面維持高選擇性一面(高選擇性地)除去。 Next, a predetermined processing gas is supplied from the gas supply pipes 106a and 106b via the shower head 105 to the substrate 60, and the ruthenium film is etched from the substrate 60 under the processing condition C1. The etching process of the ruthenium film is performed by supplying the processing gas onto the substrate 60. The etching treatment gas is a gas containing a halogen-containing gas, for example, fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) containing two or more halogen elements. It is preferred to use a gas containing two kinds of halogen elements. For example, there are iodine pentafluoride (IF 5 ), iodine hexafluoride (IF 7 ), bromine trifluoride (BrF 3 ), bromine pentafluoride (BrF 5 ), xenon difluoride (XeF 2 ), trifluorobenzene. Chlorine (ClF 3 ) and the like. More ideally, use IF 7 . IF 7 allows the ruthenium-containing film to be removed (highly selective) while maintaining a highly selective side.

矽膜的蝕刻後,具備新的其次工程,進行必要的淨化處理為理想。 After the etching of the ruthenium film, it is desirable to have a new secondary process and perform necessary purification treatment.

另外,在含矽膜上形成有數原子程度的自然氧化膜等的氧化膜時,在供給上述的處理氣體之前,將除去氣體供給至基板為理想。儘管此氧化膜是數原子層的厚度,也無法以例如至少含一個氟(F)原子的蝕刻氣體等的處理氣體來除去,阻礙含矽膜的除去。藉由供給除去氣體,可維持含矽膜或其他的膜構成不動除去含矽膜表面的氧化膜,例如可使含氟的蝕刻氣體等的處理氣體之含矽膜的微細除去成為可能。 In addition, when an oxide film such as a natural oxide film of a certain atomic degree is formed on the ruthenium containing film, it is preferable to supply the removed gas to the substrate before supplying the above-described processing gas. Although the oxide film is a thickness of the atomic layer, it cannot be removed by a processing gas such as an etching gas containing at least one fluorine (F) atom, and the removal of the ruthenium-containing film is inhibited. By supplying the gas to be removed, it is possible to maintain the oxide film containing the ruthenium film or other film in order to remove the surface of the ruthenium-containing film. For example, it is possible to finely remove the ruthenium-containing film of the treatment gas such as a fluorine-containing etching gas.

(淨化工程S30) (Purification Engineering S30)

使用在蝕刻處理的蝕刻氣體是藉由設在處理室50的側面之與環狀路114連通的排氣口107來排出。接著,從惰性氣體供給管112是從淋浴頭105的大致中心部分供給惰性氣體例如氮氣體至基板60上。藉由如此的構成來供給氮氣體之下,可有效地淨化基板60表面的殘渣,因此排氣體效率變佳。又,亦可由淋浴頭5的全面,在本實施形態中是由惰性氣體供給管112、氣體供給管106a、106b來供給氮氣體。此情況是構成調整從各供給管112、106a、106b供給的惰性氣體的流量來提升淨化效率。 The etching gas used in the etching process is discharged by the exhaust port 107 which is provided in the side surface of the processing chamber 50 and communicates with the annular path 114. Next, an inert gas such as a nitrogen gas is supplied from the inert gas supply pipe 112 to the substrate 60 from a substantially central portion of the shower head 105. By supplying the nitrogen gas under such a configuration, the residue on the surface of the substrate 60 can be effectively purified, so that the exhaust gas efficiency is improved. Further, in the present embodiment, the nitrogen gas can be supplied from the inert gas supply pipe 112 and the gas supply pipes 106a and 106b. In this case, the flow rate of the inert gas supplied from each of the supply pipes 112, 106a, and 106b is adjusted to improve the purification efficiency.

而且,在淨化工程中,不僅供給淨化用氣體(例如惰性氣體),還藉由加熱器來加熱使基板溫度形成比蝕刻處理更高的溫度為理想。特別是將基板溫度調整成 在蝕刻工程產生的副生成物及殘渣的任一方或雙方的昇華溫度以上之後供給淨化用的惰性氣體更佳。藉此,可使蝕刻時產生的副生成物的除去效率更提升。而且,基板溫度是被調整成在蝕刻工程產生的副生成物及殘渣的任一方或雙方的昇華溫度以上,形成於基板上的電路的耐熱溫度或設於基板處理室50的周圍的O型環的耐熱溫度以下為理想。例如,至少基板溫度是被調整成副生成物的昇華溫度以上的預定的溫度(例如100℃以上)為理想。 Further, in the purification process, it is preferable to supply not only a purifying gas (for example, an inert gas) but also a heater to heat the substrate to a temperature higher than the etching treatment. Especially adjust the substrate temperature to It is more preferable to supply the inert gas for purification after the sublimation temperature of either or both of the by-products and the residue generated in the etching process. Thereby, the removal efficiency of by-products generated at the time of etching can be further improved. Further, the substrate temperature is adjusted to be higher than the sublimation temperature of either or both of the by-products and the residue generated in the etching process, and the heat-resistant temperature of the circuit formed on the substrate or the O-ring provided around the substrate processing chamber 50 The heat resistance temperature below is ideal. For example, it is preferable that at least the substrate temperature is a predetermined temperature (for example, 100 ° C or more) adjusted to be higher than the sublimation temperature of the by-product.

並且,在此淨化工程中所被供給的氮氣體是亦可在藉由加熱部123來加熱的狀態下供給。此情也是所被供給的惰性氣體加熱至比蝕刻處理更高的溫度更佳。藉由如此將惰性氣體加熱至比蝕刻處理更高的溫度,可使蝕刻時產生的副生成物的除去效率提升。而且,供給至基板處理室50的惰性氣體的溫度是被加熱至在蝕刻工程產生的副生成物及殘渣的任一方或雙方的昇華溫度以上而供給至基板上更佳。 Further, the nitrogen gas supplied in the purification process may be supplied while being heated by the heating unit 123. It is also preferable that the supplied inert gas is heated to a higher temperature than the etching treatment. By heating the inert gas to a higher temperature than the etching treatment in this manner, the removal efficiency of by-products generated during etching can be improved. Further, it is more preferable that the temperature of the inert gas supplied to the substrate processing chamber 50 is heated to a sublimation temperature of one or both of the by-products and the residue generated in the etching process to be supplied to the substrate.

藉由APC閥V來調整排氣量,藉此將基板處理室50內的壓力維持於預定的壓力。例如維持於0.1~100Pa。蝕刻氣體流量是在0.1~10SLM程度的範圍內設定成預定的流量。例如設定成3SLM。又,亦可將基板處理室50的環境排氣之後供給預定的氣體。又,由於供給蝕刻氣體後隨即開始含矽膜的蝕刻,因此最好壓力或氣體流量是迅速地設定成預定的值。 The amount of exhaust gas is adjusted by the APC valve V, whereby the pressure in the substrate processing chamber 50 is maintained at a predetermined pressure. For example, it is maintained at 0.1~100Pa. The flow rate of the etching gas is set to a predetermined flow rate in the range of 0.1 to 10 SLM. For example, set to 3SLM. Further, a predetermined gas may be supplied after the environment of the substrate processing chamber 50 is exhausted. Further, since the etching of the ruthenium-containing film is started immediately after the supply of the etching gas, it is preferable that the pressure or the gas flow rate is rapidly set to a predetermined value.

一旦必要的除去工程終了,則停止處理氣體 的供給,將處理容器30及處理室50的環境氣體排氣。然後,待機至基板60的溫度為可搬送的溫度。又,亦可使支撐銷104上昇,令基板60離開基座459,冷卻至可搬送的溫度。 Stop processing gas once the necessary removal process is completed The supply of the ambient gas of the processing vessel 30 and the processing chamber 50 is exhausted. Then, the temperature until the substrate 60 is standby is a temperature that can be transported. Further, the support pin 104 can be raised to separate the substrate 60 from the susceptor 459 and cooled to a temperature at which it can be transported.

(基板搬出工程S40) (substrate removal project S40)

一旦基板60被冷卻至可搬送的溫度,從處理室搬出的準備完備,則以和上述的基板搬入工程S10相反的程序搬出。 When the substrate 60 is cooled to a temperature that can be transported, and the preparation for carrying out from the processing chamber is completed, the substrate 60 is carried out in a procedure opposite to the above-described substrate loading process S10.

若根據本實施形態的基板處理方法,則可取得以下所示的(a)~(c)的效果之中至少1個或複數個的效果。 According to the substrate processing method of the present embodiment, at least one or a plurality of effects of the effects (a) to (c) described below can be obtained.

(a)在以基板支撐銷來支撐基板之後供給惰性氣體之下,基板的表面與惰性氣體的供給口的距離會變短,可使從基板往基板的外側排出副生成物或殘渣的效率提升。 (a) Under the supply of the inert gas after supporting the substrate with the substrate supporting pin, the distance between the surface of the substrate and the supply port of the inert gas is shortened, and the efficiency of discharging the by-product or residue from the substrate to the outside of the substrate can be improved. .

(b)又,藉由從基板的中心側供給惰性氣體,可使從基板中心側往基板的外側排出副生成物或殘渣的效率提升。 (b) Further, by supplying the inert gas from the center side of the substrate, the efficiency of discharging the by-product or the residue from the center side of the substrate to the outside of the substrate can be improved.

(c)又,藉由使基板溫度加熱成比蝕刻處理溫度更高的溫度,可使從處理氣體生成的副生成物的除去效率提升。 (c) Further, by heating the substrate temperature to a temperature higher than the etching treatment temperature, the removal efficiency of the by-product generated from the processing gas can be improved.

5.本實施形態的效果 5. Effects of the embodiment

若根據上述的本實施形態,則可取得以下的(1)~(9)之中至少一個以上的效果。 According to the present embodiment described above, at least one of the following effects (1) to (9) can be obtained.

(1)在Si選擇蝕刻工程中,對於構成層疊膜之以矽為主成分的第1膜(本實施形態的多晶矽膜)及含矽率少的膜(本實施形態的矽氧化膜或矽氧氮化膜或矽氮化膜及碳膜等的硬質遮罩膜)的第2膜,對於Si以外的膜的矽氧化膜(SiO2膜)及矽氮化膜(Si3N4膜),可高選擇比來蝕刻作為前述第1膜的多晶矽。 (1) In the Si selective etching process, the first film (the polycrystalline germanium film of the present embodiment) containing ruthenium as a main component of the laminated film and the film having a small ruthenium ratio (the ruthenium oxide film or the ruthenium oxide of the present embodiment) a second film of a nitride film, a hard mask film such as a tantalum nitride film or a carbon film, and a tantalum oxide film (SiO 2 film) and a tantalum nitride film (Si 3 N 4 film) for a film other than Si. The polycrystalline germanium as the first film can be etched with a high selectivity.

(2)由於將第3蝕刻處理(Si選擇蝕刻處理)的基板溫度設於30~50℃,因此可高選擇性地以無電漿僅蝕刻Si。又,較理想是設於30~40℃,可更高選擇性地以無電漿僅蝕刻Si。而且,在蝕刻後的淨化工程中,藉由將基板溫度加熱至副生成物的昇華溫度以上,可有效地除去基板表面的殘渣。 (2) Since the substrate temperature of the third etching treatment (Si selective etching treatment) is set at 30 to 50 ° C, it is possible to selectively etch only Si without plasma. Further, it is preferably set at 30 to 40 ° C to selectively etch only Si without plasma. Further, in the purification process after the etching, by heating the substrate temperature to a temperature higher than the sublimation temperature of the by-product, the residue on the surface of the substrate can be effectively removed.

(3)由於本發明技術的第3蝕刻處理(Si選擇蝕刻處理)是各向同性蝕刻,因此對於含矽率少的膜(本實施形態的矽氧化膜等)可以高選擇比來蝕刻在周知技術的乾蝕刻無法蝕刻的領域之以矽為主成分的第1膜(本實施形態的多晶矽膜)。 (3) Since the third etching treatment (Si selective etching treatment) of the present invention is isotropic etching, it is possible to etch a film having a high defect ratio (such as a tantalum oxide film of the present embodiment) with high selectivity. The first film (the polycrystalline germanium film of the present embodiment) containing ruthenium as a main component in the field of dry etching which cannot be etched by the technique.

(4)具體而言,藉由第3蝕刻處理(Si選擇蝕刻處理),除了垂直方向以外,在水平方向(橫方向)也可高選擇性地僅蝕刻Si膜。因此,藉由在除去此Si膜的除去部形成預定的含金屬膜,可進行3D構造的CTM的製作之 金屬電極的形成。 (4) Specifically, by the third etching treatment (Si selective etching treatment), only the Si film can be selectively etched in the horizontal direction (lateral direction) in addition to the vertical direction. Therefore, by forming a predetermined metal-containing film by removing the removed portion of the Si film, the CTM of the 3D structure can be produced. Formation of metal electrodes.

(5)另外,本實施形態是藉由第3蝕刻處理(Si選擇蝕刻處理),除了垂直方向以外,在水平方向(橫方向)也可高選擇性地僅蝕刻Si膜,可予以適用在半導體裝置(裝置)的製造,因此在以往的各向異性蝕刻(電漿蝕刻)困難之3D的裝置製造的適用,本實施的氣體蝕刻(各向同性蝕刻)技術為可能。 (5) In the present embodiment, the third etching process (Si selective etching process) can selectively apply only the Si film in the horizontal direction (lateral direction) in addition to the vertical direction, and can be applied to the semiconductor. Since the device (device) is manufactured, it is possible to apply the gas etching (isotropic etching) technique of the present embodiment to the application of the conventional 3D device which is difficult to anisotropic etching (plasma etching).

(6)又,若比較:乾蝕刻(第2蝕刻處理)後,藉由實行碳硬質膜除去工程、RCA洗淨工程、Si蝕刻工程來形成微細圖案的以往方法,與乾蝕刻(第2蝕刻處理)後,藉由實行RCA洗淨工程、Si蝕刻工程、碳硬質膜除去工程來形成微細圖案的本實施形態的微細圖案形成方法,則在利用IF7氣體的氣體蝕刻是SiO2/Poly-Si的選擇比為1:1000,相對的在通常的乾蝕刻是SiO2/Poly-Si的選擇比為1:50程度,因此可格外縮短蝕刻時間。 (6) In comparison, after the dry etching (second etching treatment), a conventional method of forming a fine pattern by performing a carbon hard film removal process, an RCA cleaning process, or a Si etching process, and dry etching (second etching) After the treatment, the fine pattern forming method of the present embodiment in which the fine pattern is formed by the RCA cleaning process, the Si etching process, and the carbon hard film removal process is performed, and the gas etching using the IF 7 gas is SiO 2 /Poly- The selection ratio of Si is 1:1000, and the usual dry etching is that the selection ratio of SiO 2 /Poly-Si is about 1:50, so the etching time can be particularly shortened.

(7)並且,在RCA洗淨工程,恐有蝕刻對象的Poly-Si膜的表面被氧化之虞。因此,本實施的微細圖案形成方法是最好在RCA洗淨工程之後進行利用HF的前處理,藉由進行此HF前處理工程,在水平方向(橫方向)也可高選擇性地僅蝕刻Si膜。在此,即使包含HF前處理工程,也如上述般,在利用IF7氣體的氣體蝕刻是SiO2/Poly-Si的選擇比為1:1000,在通常的乾蝕刻是SiO2/Poly-Si的選擇比為1:50程度,蝕刻速度為20倍不同,因此處理能力上不成問題。 (7) Further, in the RCA cleaning process, it is feared that the surface of the Poly-Si film to be etched is oxidized. Therefore, in the fine pattern forming method of the present embodiment, it is preferable to perform pretreatment using HF after the RCA cleaning process, and by performing this HF pretreatment process, only Si can be selectively etched in the horizontal direction (lateral direction) with high selectivity. membrane. Here, even if the HF pretreatment project is included, as in the above, the gas etching using the IF 7 gas is a selection ratio of SiO2/Poly-Si of 1:1000, and the usual dry etching is SiO 2 /Poly-Si. The selection ratio is about 1:50, and the etching speed is different by 20 times, so the processing ability is not a problem.

(8)又,Si蝕刻工程是具有除去Si膜的工程、及藉由惰性氣體來除去蝕刻氣體的殘渣的淨化工程為理想,藉由進行此淨化工程,不僅蝕刻氣體的殘渣,還可有效地進行副生成物的排出。 (8) Further, it is preferable that the Si etching process is a purification process in which the Si film is removed and the residue of the etching gas is removed by an inert gas. By performing the purification process, not only the residue of the gas but also the gas can be effectively used. The discharge of the by-products is performed.

(9)又,由於一旦殘渣或副生成物殘留於基板的表面,則會成為微粒等的原因,因此在淨化工程中,若更將基板溫度加熱至副生成物的昇華溫度以上,則可更有效地排出成為其原因的副生成物。 (9) Further, since the residue or by-products remain on the surface of the substrate, they may become particles or the like. Therefore, in the purification process, if the substrate temperature is further heated to a sublimation temperature of the by-product, the The by-products that are the cause thereof are effectively discharged.

本發明並不限於前述實施形態,當然可不脫離其要旨的範圍實施各種變更。 The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit and scope of the invention.

前述實施形態是在第1處理單元中利用加熱器及冷卻劑供給路來調整晶圓溫度,但並非限於此,只要是液化溫度比室溫低的溫度的蝕刻氣體,亦可不使用加熱器,以冷卻劑來進行溫度調整。並且,在使循環之調整液溫下,亦可作為持有冷卻及加熱的雙方機能的溫度控制機構。 In the above embodiment, the temperature of the wafer is adjusted by the heater and the coolant supply path in the first processing unit. However, the present invention is not limited thereto, and the etching gas may be used without using a heater as long as the liquefaction temperature is lower than the room temperature. Coolant for temperature adjustment. Further, it is also possible to use a temperature control mechanism that functions both cooling and heating at the temperature of the circulating adjustment liquid.

並且,在前述實施形態中,進行電漿處理的第2處理單元是構成含電漿生成室,但不限於此,亦可構成不將電漿帶進處理室內的遠距電漿方式的成膜處理或不使用電漿的成膜處理。 Further, in the above-described embodiment, the second processing unit that performs the plasma treatment constitutes the plasma-containing plasma generating chamber. However, the present invention is not limited thereto, and may be configured to form a film by a remote plasma method in which plasma is not carried into the processing chamber. Film forming treatment with or without plasma.

又,不使用電漿的成膜處理是亦可在第1處理單元進行,此情況,第2處理單元是不要。此情況,朝處理室內導入IF7氣體,進行IF7氣體之蝕刻處理,然後,以惰性氣體來置換處理室內。之後,朝處理室內導入 預定的處理氣體,進行預定的處理氣體之成膜處理,然後,以惰性氣體來置換處理室內。之後,亦可因應所需,構成進行IF7氣體之蝕刻處理。 Further, the film formation process without using plasma may be performed in the first processing unit. In this case, the second processing unit is not required. In this case, the IF 7 gas was introduced into the processing chamber, and the IF 7 gas was etched, and then the inside of the processing chamber was replaced with an inert gas. Thereafter, a predetermined processing gas is introduced into the processing chamber to perform a predetermined film forming process of the processing gas, and then the processing chamber is replaced with an inert gas. Thereafter, an etch treatment of the IF7 gas may be performed as needed.

又,前述本實施形態是構成在搬送至處理單元410之前使形成有第2微細圖案的基板在處理單元410(510)進行蝕刻處理,但亦可構成在1台的基板處理裝置中進行蝕刻處理及成膜處理,又,此情況是構成至少使蝕刻處理及成膜處理分別在不同的處理單元進行為理想。 Further, in the above-described embodiment, the substrate on which the second fine pattern is formed is subjected to etching treatment in the processing unit 410 (510) before being transferred to the processing unit 410. However, it may be configured to perform etching processing in one substrate processing apparatus. Further, in this case, it is preferable that at least the etching treatment and the film formation processing are performed in different processing units.

又,前述實施形態是以單片式裝置為例進行說明,但亦可為能一次處理複數片的基板的多單片式裝置,又,本發明亦可適用在例如在基板保持具(例如晶舟)上堆疊複數個水平姿勢的基板,將該晶舟搬入至處理室內的狀態下進行處理的縱型裝置。 Further, although the above embodiment has been described by taking a monolithic device as an example, it may be a multi-monolithic device capable of processing a plurality of substrates at a time, and the present invention is also applicable to, for example, a substrate holder (for example, a crystal A vertical device in which a plurality of substrates in a horizontal posture are stacked on the boat and the wafer boat is carried into a processing chamber.

又,本發明是可適用在半導體記憶體之一種類的DRAM的元件構造或電晶體的閘極電極形成等各種的SADP法。又,本發明是不限於位在SADP製程的底層之多層硬遮罩的構造。亦可為按照製程的種類,例如在Si基板上具有SiO2,Si3N4,SiO2的3層硬遮罩的情況,或具有Si3N4膜及SiO2膜的2層硬遮罩的情況,或除此以外。 Further, the present invention is applicable to various SADP methods such as an element structure of a DRAM of one type of semiconductor memory or a gate electrode formation of a transistor. Further, the present invention is not limited to the construction of a multilayer hard mask located at the bottom of the SADP process. It may be in the case of a process type such as a three-layer hard mask having SiO 2 , Si 3 N 4 , SiO 2 on a Si substrate, or a 2-layer hard mask having a Si 3 N 4 film and a SiO 2 film. The situation, or otherwise.

並且,在本發明中,藉由組合:在使用含氟的蝕刻氣體之Si膜的選擇乾蝕刻中,除去存在於除去對象的含矽膜表面的膜(自然氧化膜等)之工程,及抑制新的膜(自然氧化膜等)的發生之工程,及除去存在於被除 去對象的含矽膜所覆蓋之處的膜(自然氧化膜等)之工程,提供一種可一邊除去不要的膜(自然氧化膜等),一邊進行矽的選擇除去可能之基板處理方法及基板處理裝置,不是以基板的同時處理片數,保持基板的方向,稀釋用氣體或淨化用氣體的種類,洗滌方法,基板處理室或加熱機構及冷卻機構的形狀等來限定實施範圍者。 Further, in the present invention, in the selective dry etching of the Si film using the fluorine-containing etching gas, the process of removing the film (natural oxide film or the like) existing on the surface of the ruthenium-containing film to be removed, and suppressing it The engineering of the occurrence of new membranes (natural oxide membranes, etc.), and the removal present in the removal The process of removing the film (natural oxide film, etc.) where the target film is covered by the ruthenium film, and providing a method of removing the unnecessary film (natural oxide film, etc.) while removing the possible substrate processing method and substrate processing The device is not limited to the number of sheets processed at the same time, the direction in which the substrate is held, the type of the gas for dilution or the gas to be purified, the method of washing, the shape of the substrate processing chamber, the heating mechanism, and the cooling mechanism, and the like.

又,本發明是不限於乾蝕刻形成於基板的膜(自然氧化膜等)及含矽膜的任一方或雙方之工程,亦可進行堆積於基板處理室內的含矽膜的除去(洗滌)工程。 Further, the present invention is not limited to the dry etching of a film (natural oxide film or the like) formed on a substrate and a process of either or both of the ruthenium-containing films, and the ruthenium-containing film removal (washing) process may be performed in the substrate processing chamber. .

並且,在本實施形態中,以往為了更進一步謀求高集成化而使圖案的微細化進展,但隨著微細化進展,會產生微細化後之圖案固有的問題。其一例,可舉溼蝕刻時的液體的表面張力所造成的圖案倒塌。例如,在矽(Si)的除去工程中,於氫氧化四甲銨水溶液(TMAH)等之蝕刻後純水洗淨,一邊以表面張力比純水小的異丙醇(IPA)置換一邊進行乾燥,藉此防止洗淨液的表面張力所造成的圖案倒塌。然而,隨著圖案的微細化,即使利用此方法也無法完全防止圖案的倒塌。作為解決此問題的手段,若根據藉由本發明之含碘的蝕刻氣體來進行矽的除去之乾蝕刻,則在今後的圖案的微細化也可適用。 In addition, in the present embodiment, in order to further advance the miniaturization of the pattern in order to further increase the integration, there is a problem inherent in the pattern after miniaturization as the miniaturization progresses. As an example, the pattern collapse caused by the surface tension of the liquid during wet etching can be mentioned. For example, in the removal process of cerium (Si), it is washed with pure water after etching such as tetramethylammonium hydroxide aqueous solution (TMAH), and dried while being replaced with isopropyl alcohol (IPA) having a surface tension lower than that of pure water. Thereby, the pattern caused by the surface tension of the washing liquid is prevented from collapsing. However, as the pattern is miniaturized, even if this method is used, the collapse of the pattern cannot be completely prevented. In the dry etching which removes cerium by the iodine-containing etching gas of the present invention, it is also possible to refine the pattern in the future.

而且,在本實施形態中,在NAND快閃記憶體等的3D構造的裝置的製造中,就以往使用電漿的反應性離子蝕刻而言,難以對於多晶矽以外的膜(例如矽氧化(SiO2)膜,矽氮化(SiN)膜,矽氧氮化(SiON)膜, 碳(C)膜等)高選擇性地除去多晶矽(Poly-Si)膜。亦即,以多晶矽(Poly-Si)膜及矽氧化(SiO2)膜的層疊構造來貫穿貫通溝之後露出於側壁的多晶矽(Poly-Si)膜及矽氧化(SiO2)膜的層之中,只蝕刻多晶矽(Poly-Si)膜的情形,就以往使用電漿的反應性離子蝕刻而言,因為與多晶矽以外的膜的選擇性的問題或需要各向同性蝕刻的點,所以非常困難。並且,也有與硬遮罩膜(例如碳膜等)的選擇性的問題。難對應於隨如此的圖案的微細化而令裝置構造的繁雜化。作為解決此問題的手段,若根據本發明之含氟的蝕刻氣體,以無電漿進行矽的除去之乾蝕刻,則藉由各向同性蝕刻,今後的圖案的微細化也可適用。特別是藉由使用含七氟化碘的含碘氣體(含碘的氣體)作為含氟的蝕刻氣體,與既存的蝕刻氣體作比較,可由其化學的性質與矽以外的膜的選擇性佳地進行矽的除去。因此,可適用在今後隨圖案的微細化而令裝置構造的繁雜化。 Further, in the present embodiment, in the production of a device having a 3D structure such as a NAND flash memory, it is difficult for a reactive ion etching using plasma to be used for a film other than polycrystalline germanium (for example, cerium oxide (SiO 2 ). A film, a tantalum nitride (SiN) film, a hafnium oxynitride (SiON) film, a carbon (C) film, or the like) selectively removes a poly-Si film. That is, in order to then polysilicon (Poly-Si) film and silicon oxide (SiO 2) film laminated structure to penetrate through the silicon oxide film and the exposed trench sidewalls in the polysilicon (Poly-Si) into (SiO 2) film layer In the case of etching only a poly-Si film, in the conventional reactive ion etching using a plasma, it is extremely difficult because of the problem of selectivity of a film other than polysilicon or the point of isotropic etching. Further, there is a problem of selectivity with a hard mask film (for example, a carbon film or the like). It is difficult to cope with the complication of the device structure with the miniaturization of such a pattern. As a means for solving this problem, according to the fluorine-containing etching gas of the present invention, dry etching by removing the ruthenium without plasma can be applied by isotropic etching to refine the pattern in the future. In particular, by using an iodine-containing gas containing an iodine-containing iodine (a gas containing iodine) as a fluorine-containing etching gas, compared with an existing etching gas, the chemical properties thereof and the selectivity of a film other than ruthenium are preferable. Remove the cockroaches. Therefore, it is applicable to the complication of the structure of the apparatus in the future as the pattern is miniaturized.

又,本發明不只是半導體製造裝置,亦可適用在像LCD製造裝置那樣製造玻璃基板的裝置。又,本發明是亦可適用在一列式型或群集型等各型的單片式裝置或橫型的基板處理裝置等。 Moreover, the present invention is not limited to a semiconductor manufacturing apparatus, and can be applied to a device for manufacturing a glass substrate like an LCD manufacturing apparatus. Further, the present invention is also applicable to a single-piece type device such as a one-row type or a cluster type, or a horizontal type substrate processing apparatus.

以下附記有關本發明的較佳形態。 The following supplementary notes pertain to preferred embodiments of the invention.

<附記1> <Note 1>

若根據本發明之一形態,則可提供一種半導體裝置的 製造方法,其係具有:形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜之層疊膜之工程;在前述層疊膜中形成複數的貫通孔(第一孔)之第1蝕刻工程;在前述複數的貫通孔(第一孔)形成通道之工程;在前述通道間形成溝(第二孔)之第2蝕刻工程;及供給含氟的蝕刻氣體,除去與前述溝(第二孔)鄰接之包含前述第1膜及前述第2膜的層疊膜之中前述第1膜之第3蝕刻工程,在前述第3蝕刻工程中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 According to an aspect of the present invention, a semiconductor device can be provided The manufacturing method includes forming a laminated film including a first film containing ruthenium as a main component and a second film having a lower enthalpy ratio than the first film; and forming a plurality of through holes in the laminated film ( a first etching process of the first hole); a process of forming a channel in the plurality of through holes (first holes); a second etching process of forming a groove (second hole) between the channels; and supplying an etching gas containing fluorine Removing the third etching process of the first film in the laminated film including the first film and the second film adjacent to the groove (second hole), and the etching gas reaches the etching process in the third etching process The first film is removed until a film of the channel formed by the film of the second film is formed.

<附記2> <附记2>

如附記1的半導體裝置的製造方法,最好前述第1膜為導電膜,為多晶矽(Poly-Si)膜或非晶形矽(α-Si)膜。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the first film is a conductive film and is a poly-Si film or an amorphous germanium (α-Si) film.

<附記3> <附记3>

如附記2的半導體裝置的製造方法,最好前述第1膜及前述第2膜的前述成膜條件係膜厚30nm~60nm程度,成膜溫度400℃~800℃。 In the method of manufacturing a semiconductor device according to the second aspect, it is preferable that the film formation conditions of the first film and the second film are about 30 nm to 60 nm, and the film formation temperature is 400 to 800 °C.

<附記4> <附记4>

如附記1的半導體裝置的製造方法,最好前述第2膜為絕緣膜,為矽膜(Si膜)以外的膜,包含矽氮化膜(Si3N4膜)、二氧化矽膜(SiO2膜)、矽氧氮化膜(SiON膜)、碳化矽膜(SiC膜)的其中至少一個。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the second film is an insulating film and is a film other than the ruthenium film (Si film), and includes a ruthenium nitride film (Si 3 N 4 film) or a ruthenium dioxide film (SiO). At least one of 2 film), a hafnium oxynitride film (SiON film), and a tantalum carbide film (SiC film).

<附記5> <附记5>

如附記1的半導體裝置的製造方法,最好前述溝(第二孔)係寬100nm以下,相對於前述溝的寬,深度的比為10以上,例如寬30nm~100nm,深度300nm~4000nm。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the groove (second hole) has a width of 100 nm or less and a depth to a width of the groove of 10 or more, for example, a width of 30 nm to 100 nm and a depth of 300 nm to 4000 nm.

<附記6> <附记6>

如附記1的半導體裝置的製造方法,最好前述貫通孔(第一孔)係寬30nm~100nm,深度300nm~4000nm。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the through hole (first hole) has a width of 30 nm to 100 nm and a depth of 300 nm to 4000 nm.

<附記7> <附记7>

如附記1的半導體裝置的製造方法,最好前述第1蝕刻工程係具有:在前述層疊膜上形成硬質遮罩膜之工程;及形成前述貫通孔(第一孔)之工程。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the first etching process includes a process of forming a hard mask film on the laminated film, and a process of forming the through hole (first hole).

<附記8> <附记8>

如附記7的半導體裝置的製造方法,最好前述硬質遮罩膜係成膜方法為CVD法,膜厚為400nm以上,成膜溫 度為200℃~550℃。 In the method of manufacturing a semiconductor device according to the seventh aspect, it is preferable that the hard mask film forming method is a CVD method, and the film thickness is 400 nm or more, and the film forming temperature is The degree is from 200 ° C to 550 ° C.

<附記9> <附记9>

如附記7的半導體裝置的製造方法,最好前述硬質遮罩膜為碳膜、碳化矽膜、矽膜與碳膜的層疊膜的其中任一個。 In the method of manufacturing a semiconductor device according to the seventh aspect, it is preferable that the hard mask film is any one of a carbon film, a tantalum carbide film, and a laminated film of a tantalum film and a carbon film.

<附記10> <附记10>

如附記1或附記6的半導體裝置的製造方法,最好形成前述貫通孔(第一孔)的工程係實行前述層疊膜的乾蝕刻。 In the method of manufacturing a semiconductor device according to the first or sixth aspect of the invention, it is preferable that the step of forming the through hole (first hole) performs dry etching of the laminated film.

<附記11> <附记11>

如附記10的半導體裝置的製造方法,最好前述層疊膜的乾蝕刻係使用SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一氣體。 In the method of manufacturing a semiconductor device according to the tenth aspect, it is preferable that the dry etching of the laminated film is performed using SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 /O 2 mixed gas. a gas.

<附記12> <附记12>

如附記1的半導體裝置的製造方法,最好形成前述通道的工程具有:在前述貫通孔(第一孔)的內壁形成第1預定膜之工程;及形成作為前述通道的第2預定膜之工程。 In the method of manufacturing a semiconductor device according to the first aspect, preferably, the process of forming the channel includes: forming a first predetermined film on an inner wall of the through hole (first hole); and forming a second predetermined film as the channel. engineering.

<附記13> <附记13>

如附記12的半導體裝置的製造方法,最好前述第1預定膜係以SiO2膜/Si3N4膜/SiO2膜所構成的ONO膜,前述SiO2膜及Si3N4膜係分別膜厚0.5nm~7nm,溫度為400~800℃的範圍其中任一。 In the method of manufacturing a semiconductor device according to the second aspect of the invention, preferably, the first predetermined film is an ONO film composed of a SiO 2 film/Si 3 N 4 film/SiO 2 film, and the SiO 2 film and the Si 3 N 4 film system are respectively The film thickness is 0.5 nm to 7 nm, and the temperature is in the range of 400 to 800 °C.

<附記14> <附记14>

如附記12的半導體裝置的製造方法,最好前述第2預定膜係以矽為主成分的膜,例如多晶矽(Poly-Si)膜或非晶形矽(α-Si)膜。 In the method of manufacturing a semiconductor device according to the second aspect, it is preferable that the second predetermined film is a film mainly composed of ruthenium, for example, a poly-Si film or an amorphous yttrium-(a-Si) film.

<附記15> <附记15>

如附記1的半導體裝置的製造方法,最好前述第2蝕刻(溝形成)工程係與前述第1蝕刻(貫通孔形成)工程相同的處理條件。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the second etching (groove forming) is the same processing condition as the first etching (through hole forming).

<附記16> <附记16>

如附記1的半導體裝置的製造方法,最好前述貫通孔(第一孔)及前述溝(第二孔)係以同處理形成,各寬及深度為相同。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the through hole (first hole) and the groove (second hole) are formed by the same process, and the width and the depth are the same.

<附記17> <附记17>

如附記1的半導體裝置的製造方法,最好在前述第3蝕刻工程中使用:對於矽顯示高的蝕刻速率,對於前述第 2膜持高的選擇性之含碘的蝕刻氣體。 The method of manufacturing a semiconductor device according to the first aspect of the invention is preferably used in the third etching process: a high etching rate is displayed for 矽, and the foregoing 2 The film holds a highly selective iodine-containing etching gas.

<附記18> <附记18>

如附記1的半導體裝置的製造方法,最好前述蝕刻氣體例如為七氟化碘(IF7)氣體、三氟化氯(ClF3)、二氟化氙(XeF2)、三氟化溴(BrF3)、五氟化溴(BrF5)、五氟化碘(IF5)之中的任一氣體。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the etching gas is, for example, an iodine heptafluoride (IF7) gas, chlorine trifluoride (ClF3), xenon difluoride (XeF2), or bromine trifluoride (BrF3). Any of pentahafluoride (BrF5) and iodine pentafluoride (IF5).

<附記19> <附记19>

如附記1的半導體裝置的製造方法,最好前述第3蝕刻為各向同性蝕刻,前述第1或第2蝕刻為各向異性蝕刻。 In the method of manufacturing a semiconductor device according to the first aspect, it is preferable that the third etching is isotropic etching, and the first or second etching is anisotropic etching.

<附記20> <附记20>

如附記1的半導體裝置的製造方法,最好更在前述第3蝕刻工程之後,具有形成成為字元線的金屬電極等的導電膜之工程,形成前述金屬電極的工程係具有:形成前述導電膜的工程;及以能夠留下在前述第3蝕刻工程中被除去的部分成膜的金屬膜之方式,除去前述金屬膜的工程。 In the method of manufacturing a semiconductor device according to the first aspect of the invention, it is preferable to have a process of forming a conductive film such as a metal electrode as a word line after the third etching process, and the engineering system for forming the metal electrode includes: forming the conductive film. And the process of removing the metal film in such a manner as to leave a portion of the metal film which is removed in the third etching process.

<附記21> <附记 21>

如附記20的半導體裝置的製造方法,最好除去前述 金屬膜的工程係實施具有各向異性的乾蝕刻。 The method of manufacturing the semiconductor device according to supplementary note 20 is preferably removed as described above. The engineering of the metal film implements an anisotropic dry etching.

<附記22> <附记22>

如附記21的半導體裝置的製造方法,最好在前述乾蝕刻中,使用SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一氣體。 In the method of manufacturing a semiconductor device according to the supplementary note 21, it is preferable to use any of SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 /O 2 mixed gas in the dry etching. gas.

<附記23> <附记23>

如附記20的半導體裝置的製造方法,最好前述金屬膜係由鎢(W)膜、TiN膜、TiN/Al膜、或、TaN/W膜所選擇的膜。 In the method of manufacturing a semiconductor device according to supplementary note 20, it is preferable that the metal film is a film selected from a tungsten (W) film, a TiN film, a TiN/Al film, or a TaN/W film.

<附記24> <附记24>

若根據本發明的其他形態,則可提供一種半導體裝置的製造方法,其係具有:第1圖案形成工程,其係具有:形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜之層疊膜之工程、及在前述層疊膜中形成貫通孔(第一孔)之第1蝕刻工程;第2圖案形成工程,其係具有:在前述貫通孔(第一孔)形成通道之工程、及在前述通道間形成溝(第二孔)之第2蝕刻工程;及第3蝕刻工程,其係供給蝕刻氣體,除去與前述溝(第二孔)鄰接之前述第1膜及前述第2膜之中前述第1 膜,在前述第3蝕刻工程中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 According to still another aspect of the present invention, a method of manufacturing a semiconductor device comprising: forming a first film containing ruthenium as a main component; and forming a semiconductor device having a ruthenium ratio a first etching process in which a laminated film of a second film having a smaller film is formed, and a first etching process in which a through hole (first hole) is formed in the laminated film; and a second pattern forming process: the through hole (the first through hole) a hole forming a channel and a second etching process for forming a groove (second hole) between the channels; and a third etching process for supplying an etching gas to remove the abutting groove (second hole) The first film among the first film and the second film In the film, in the third etching process, the first film is removed until the etching gas reaches a film forming the channel formed by the film of the second film.

<附記25> <附记25>

若根據本發明的其他形態,則可提供一種微細圖案形成方法,其係具有:在形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜之層疊膜之後,在前述層疊膜中設置貫通孔(第一孔)而形成第1微細圖案之工程;在前述貫通孔(第一孔)中形成通道之後,在前述通道之間設置溝(第二孔)而形成第2微細圖案之工程;及對前述第2微細圖案供給蝕刻氣體,除去與前述溝(第二孔)鄰接之包含前述第1膜及前述第2膜的層疊膜之中前述第1膜之蝕刻工程,在前述蝕刻工程中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 According to another aspect of the present invention, there is provided a method of forming a fine pattern, comprising: forming a first film including ruthenium as a main component and a second film having a lower ruthenium ratio than the first film; After the film, a through hole (first hole) is formed in the laminated film to form a first fine pattern; after the channel is formed in the through hole (first hole), a groove is formed between the channels (second hole) a process of forming a second fine pattern; and supplying an etching gas to the second fine pattern, and removing the first layer of the laminated film including the first film and the second film adjacent to the groove (second hole) In the etching process of the film, in the etching process, the first film is removed until the etching gas reaches a film forming the channel formed by the film of the second film.

<附記26> <附记26>

若根據本發明的另外其他形態,則可提供一種基板處理裝置,其係具有:處理室,其係收容基板,該基板係於包含以矽為主成 分的第1膜(矽膜)及含矽率比第1膜更少的膜的第2膜(包含矽以外的膜的含矽膜)之層疊膜中設置複數的貫通孔(第一孔)之後,在前述貫通孔(第一孔)中形成通道,且在所被形成的通道間設置溝(第二孔);氣體供給部,其係將蝕刻氣體供給至前述處理室,該蝕刻氣體係除去露出於前述溝(第二孔)的側面之前述第1膜及前述第2膜之中前述第1膜;及控制部,其係於供給前述蝕刻氣體的期間,將前述基板的溫度控制成預定的溫度範圍。 According to still another aspect of the present invention, there is provided a substrate processing apparatus comprising: a processing chamber that houses a substrate, the substrate being comprised of a crucible A plurality of through holes (first holes) are provided in the laminated film of the first film (the ruthenium film) and the second film (the ruthenium film containing the film other than ruthenium) having a lower film than the first film. Thereafter, a channel is formed in the through hole (first hole), and a groove (second hole) is provided between the formed channels; and a gas supply portion supplies an etching gas to the processing chamber, the etching gas system The first film and the control unit are removed from the first film and the second film exposed on the side surface of the groove (second hole), and the control unit controls the temperature of the substrate to be constant during the supply of the etching gas. The predetermined temperature range.

<附記27> <附记27>

若根據本發明的另外其他形態,則可提供一種基板處理裝置,其係具備實行至少包含下列程序的程式之控制器,該程式係至少包含:形成包含以矽為主成分的第1膜(矽膜)及含矽率比前述第1膜更少的膜的第2膜(包含矽以外的膜的含矽膜)的層疊膜之程序;在前述層疊膜形成複數的貫通孔(第一孔)之程序;在前述複數的貫通孔(第一孔)中所被埋設的通道間形成溝(第二孔)之程序;及供給蝕刻氣體,只除去與前述溝(第二孔)鄰接之前述第1膜及前述第2膜之中前述第1膜之程序,前述控制器係於除去前述第1膜的程序中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道 的膜為止,使前述第1膜除去。 According to still another aspect of the present invention, there is provided a substrate processing apparatus comprising: a controller that executes a program including at least the following program, the program comprising at least: forming a first film containing ruthenium as a main component (矽a film and a process of laminating a film of a second film (including a ruthenium film including a film other than ruthenium) having a film having a lower enthalpy than the first film; forming a plurality of through holes (first holes) in the laminated film a program for forming a groove (second hole) between the channels embedded in the plurality of through holes (first holes); and supplying an etching gas to remove only the foregoing portion adjacent to the groove (second hole) In the first film of the first film and the second film, the controller is in the process of removing the first film, and the etching gas reaches the channel formed by forming the film with the second film. The first film is removed until the film is removed.

<附記28> <附记28>

若根據本發明的另外其他形態,則可提供一種記錄媒體,其係可讀取程式,該程式係使下列程序實行於電腦,形成包含以矽為主成分的第1膜(矽膜)及含矽率比前述第1膜更少的膜的第2膜(包含矽以外的膜的含矽膜)的層疊膜之程序;在前述層疊膜形成複數的貫通孔(第一孔)之程序;在前述複數的貫通孔(第一孔)中所被埋設的通道間形成溝(第二孔)之程序;及供給蝕刻氣體,只除去與前述溝(第二孔)鄰接之前述第1膜及前述第2膜之中前述第1膜之程序,前述控制器係使除去前述第1膜的程序,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 According to still another aspect of the present invention, there is provided a recording medium which is a readable program which is implemented in a computer to form a first film (film) containing ruthenium as a main component and a procedure of laminating a film of a second film (including a ruthenium-containing film including a film other than ruthenium) having a lower rate than the first film; and forming a plurality of through holes (first holes) in the laminated film; a process of forming a groove (second hole) between the channels embedded in the plurality of through holes (first holes); and supplying an etching gas to remove only the first film adjacent to the groove (second hole) and the foregoing In the first film of the second film, the controller removes the first film and removes the etching gas until the film forming the channel formed by the film of the second film is removed. The first film described above.

<附記29> <附记29>

若根據本發明的另外其他形態,則可提供一種程式,其係至少包含:形成包含以矽為主成分的第1膜(矽膜)及含矽率比前述第1膜更少的膜的第2膜(包含矽以外的膜的含矽膜)的層疊膜之程序;在前述層疊膜形成複數的貫通孔(第一孔)之程序; 在前述複數的貫通孔(第一孔)中所被埋設的通道間形成溝(第二孔)之程序;及供給蝕刻氣體,只除去與前述溝(第二孔)鄰接之前述第1膜及前述第2膜之中前述第1膜之程序,在除去前述第1膜的程序中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,使前述第1膜除去。 According to still another aspect of the present invention, there is provided a program comprising: forming at least a first film (ruthenium film) containing ruthenium as a main component and a film having a lower ruthenium ratio than the first film; a procedure for laminating a film of 2 films (including a ruthenium film other than ruthenium); and forming a plurality of through holes (first holes) in the laminate film; a process of forming a groove (second hole) between the channels embedded in the plurality of through holes (first holes); and supplying an etching gas to remove only the first film adjacent to the groove (second hole) and In the procedure of removing the first film in the second film, in the procedure of removing the first film, until the etching gas reaches a film forming the channel formed by the film of the second film, 1 membrane removed.

<附記30> <附记30>

若根據本發明的另外其他形態,則可提供一種基板處理裝置,其係至少具備:第1處理室,其係收容基板,只除去露出於前述溝(第二孔)的側面之前述第1膜及前述第2膜的交替的層之中前述第1膜,該基板係於交替層疊至少2層以上以矽為主成分的第1膜及含矽率比前述第1膜更少的膜的第2膜的層疊膜中設有複數的貫通孔(第一孔),且在前述複數的貫通孔(第一孔)中所被埋設的通道間形成有溝(第二孔);第2處理室,其係於除去前述第1膜的部分形成含金屬膜;第3處理室,其係除去前述含金屬膜。 According to still another aspect of the present invention, a substrate processing apparatus including at least a first processing chamber for accommodating a substrate and removing only the first film exposed on a side surface of the groove (second hole) And the first film in the alternating layers of the second film, wherein the substrate is formed by alternately stacking at least two or more layers of a first film containing ruthenium as a main component and a film having a lower ruthenium ratio than the first film. a plurality of through holes (first holes) are formed in the laminated film of the film, and grooves (second holes) are formed between the channels buried in the plurality of through holes (first holes); the second processing chamber The metal film is formed in a portion where the first film is removed, and the metal film is removed in the third processing chamber.

<附記31> <附记31>

若根據本發明的另外其他形態,則可提供一種半導體 裝置的製造方法,其係具有:在具有以矽為主成分的第1膜的基板的表面,將組成與前述第1膜不同的第3膜成膜之工程;在前述第3膜的表面形成包含前述第1膜及含矽率比前述第1膜更少的第2膜的層疊膜之工程;在前述層疊膜形成複數的貫通孔(第一孔)之第1蝕刻工程;在前述複數的貫通孔(第一孔)形成通道之工程;在前述通道之間形成溝(第二孔)之第2蝕刻工程;使蝕刻氣體接觸於前述第1膜、前述第2膜、前述第3膜的各表面,除去與前述溝(第二孔)鄰接之包含前述第1膜及前述第2膜的層疊膜之中前述第1膜之第3蝕刻工程,在前述第3蝕刻工程中,不除去前述第2膜及前述第3膜,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 According to still another aspect of the present invention, a semiconductor can be provided In the method of producing a device, the third film having a composition different from the first film is formed on the surface of the substrate having the first film containing ruthenium as a main component, and the film is formed on the surface of the third film. a first etching process including a first film and a second film having a second film having a lower enthalpy ratio than the first film; and a first etching process in which a plurality of through holes (first holes) are formed in the laminated film; a through hole (first hole) forming a channel; a second etching process for forming a groove (second hole) between the channels; and contacting the etching gas with the first film, the second film, and the third film The third etching process of the first film in the laminated film including the first film and the second film adjacent to the groove (second hole) is removed from each surface, and the third etching process is not removed. The second film and the third film are removed from the first film until the etching gas reaches a film forming the channel formed by the film of the second film.

<附記32> <附记32>

如附記1的半導體裝置的製造方法,更理想係具有:在表面具有前述第1膜的基板,組成與前述第1膜及前述第2膜不同的第3膜係形成於前述第1膜的至少一部的表面之工程。 More preferably, the method for producing a semiconductor device according to the first aspect of the invention includes the substrate having the first film on the surface, and the third film having a composition different from the first film and the second film is formed on at least the first film. The work of a surface.

<附記33> <附记33>

如附記1的半導體裝置的製造方法,最好前述第3蝕刻工程係具有:除去前述第1膜之工程、及除去前述蝕刻氣體的殘渣之淨化工程,前述淨化工程係將基板溫度設定成比蝕刻處理更高的溫度。 In the method of manufacturing a semiconductor device according to the first aspect, preferably, the third etching process includes a process of removing the first film and a process of removing a residue of the etching gas, and the cleaning process sets the substrate temperature to a specific etching process. Handle higher temperatures.

<附記34> <附记34>

如附記1的半導體裝置的製造方法,最好前述第3蝕刻工程係具有:除去前述第1膜之工程、及除去前述蝕刻氣體的殘渣之淨化工程,前述淨化工程係將基板溫度設定成比在除去前述第1膜的工程所產生的副生成物的昇華溫度更高。 In the method of manufacturing a semiconductor device according to the first aspect of the invention, preferably, the third etching process includes a process of removing the first film and a process of removing a residue of the etching gas, wherein the purification process sets the substrate temperature to be higher than The sublimation temperature of the by-product produced by the removal of the first film is higher.

<附記35> <附记35>

如附記33或附記34的半導體裝置的製造方法,最好在除去前述第1膜的工程中,前述基板溫度係被設定成比前述蝕刻氣體不會液化的溫度更高。 In the method of manufacturing a semiconductor device according to supplementary note 33 or supplementary note 34, preferably, in the process of removing the first film, the substrate temperature is set to be higher than a temperature at which the etching gas does not liquefy.

<附記36> <附记36>

若根據本發明的另外其他形態,則可提供一種基板處理裝置,其係具備:處理室,其係收容基板,該基板係於交替層疊至少2層以上以矽為主成分的第1膜及含矽率比前述第1膜更少的膜的第2膜的層疊膜中設有複數的貫通孔(第一孔), 且在前述複數的貫通孔(第一孔)中所被埋設的通道間形成有溝(第二孔);基板載置部,其係載置前述基板;搬送機構,其係使前述基板載置部上下;氣體供給部,其係對前述基板供給蝕刻氣體;及控制部,其係控制前述氣體供給部、前述搬送機構,而使前述基板從載置前述基板的位置接近前述氣體供給部,對前述基板供給前述蝕刻氣體,只除去露出於前述溝(第二孔)的側面之前述第1膜及前述第2膜的交替的層之中前述第1膜。 According to still another aspect of the present invention, there is provided a substrate processing apparatus including: a processing chamber for accommodating a substrate, wherein the substrate is formed by alternately stacking at least two or more layers of a first film containing ruthenium as a main component and a plurality of through holes (first holes) are provided in the laminated film of the second film having a lower rate than the first film. a groove (second hole) is formed between the channels embedded in the plurality of through holes (first holes), a substrate mounting portion is mounted on the substrate, and a transfer mechanism is configured to mount the substrate a gas supply unit that supplies an etching gas to the substrate, and a control unit that controls the gas supply unit and the transfer mechanism to bring the substrate closer to the gas supply unit from a position at which the substrate is placed, The substrate is supplied with the etching gas, and only the first film is removed from the alternating layers of the first film and the second film exposed on the side surface of the groove (second hole).

<附記37> <附记37>

如附記36的基板處理裝置,最好前述控制部係至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,使前述第1膜除去。 In the substrate processing apparatus according to supplementary note 36, preferably, the control unit removes the first film until the etching gas reaches a film forming the channel formed by the film of the second film.

<附記38> <附记38>

如附記36的基板處理裝置,最好更具備對前述基板的中心部供給惰性氣體之惰性氣體供給部,前述控制部係前述第1膜的除去終了後,對前述基板供給惰性氣體,在前述基板的表面形成從基板中心部往基板端部之惰性氣體的流動,將滯留於前述基板的表面之前述蝕刻氣體排出。 Preferably, the substrate processing apparatus according to the attachment 36 further includes an inert gas supply unit that supplies an inert gas to a central portion of the substrate, and the control unit supplies an inert gas to the substrate after the removal of the first film. The surface forms a flow of inert gas from the central portion of the substrate to the end portion of the substrate, and the etching gas remaining on the surface of the substrate is discharged.

<附記39> <附记39>

如附記36的基板處理裝置,最好更具備將前述基板控制成預定的基板溫度之加熱部,前述控制部係前述第1膜的除去終了後,加熱前述基板,將前述基板溫度控制成比在前述蝕刻氣體與基板表面的反應下產生的副生成物的昇華溫度更高的溫度。 Preferably, the substrate processing apparatus according to the attachment 36 further includes a heating unit that controls the substrate to a predetermined substrate temperature, and the control unit heats the substrate after the removal of the first film, and controls the substrate temperature to be compared. The sublimation temperature of the by-product generated by the reaction between the etching gas and the surface of the substrate is higher.

<附記40> <附记40>

如附記36的基板處理裝置,更理想是更具備:對前述基板供給惰性氣體之惰性氣體供給部、及將前述基板控制成預定的基板溫度之加熱部,前述控制部係前述第1膜的除去終了後,對前述基板供給惰性氣體,且加熱前述基板,在前述基板的表面形成從基板中心部往基板端部之惰性氣體的流動,且將基板溫度控制成比在前述蝕刻氣體與基板表面的反應下產生的副生成物的昇華溫度更高的溫度。 More preferably, the substrate processing apparatus according to the attachment 36 further includes: an inert gas supply unit that supplies an inert gas to the substrate; and a heating unit that controls the substrate to a predetermined substrate temperature, wherein the control unit removes the first film After the end, the inert gas is supplied to the substrate, and the substrate is heated to form a flow of the inert gas from the central portion of the substrate toward the end of the substrate on the surface of the substrate, and the substrate temperature is controlled to be higher than that of the etching gas and the substrate surface. The sublimation temperature produced by the reaction is higher than the sublimation temperature.

Claims (30)

一種微細圖案形成方法,其特徵係具有:形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜之層疊膜,在所被形成的層疊膜設置複數的第一孔而形成第1微細圖案之工程;分別在前述複數的第一孔形成通道之後,在前述各通道間設置第二孔而形成第2微細圖案之工程;及對前述第2微細圖案供給含氟的蝕刻氣體,而除去與前述第二孔鄰接的前述第1膜之蝕刻工程,在前述蝕刻工程中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 A method for forming a fine pattern, comprising: forming a first film including ruthenium as a main component and a second film having a second film having a lower enthalpy ratio than the first film; and providing a plurality of laminated films formed thereon a first hole forming a first fine pattern; after forming a channel in the plurality of first holes, respectively forming a second hole between the respective channels to form a second fine pattern; and the second fine pattern Supplying a fluorine-containing etching gas to remove an etching process of the first film adjacent to the second hole, and in the etching process, the etching gas reaches a channel formed by forming a film with the second film The first film is removed until the film is removed. 一種半導體裝置的製造方法,其特徵係具有:形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的第2膜的層疊膜之工程;在前述層疊膜形成複數的第一孔之第1蝕刻工程;在前述複數的第一孔形成通道之工程;在前述通道間形成第二孔之第2蝕刻工程;及供給含氟的蝕刻氣體,而除去與前述第二孔鄰接的前述第1膜之第3蝕刻工程,在前述第3蝕刻工程中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 A method for producing a semiconductor device, comprising: forming a laminated film including a first film containing ruthenium as a main component and a second film having a lower enthalpy ratio than the first film; and forming a plurality of the laminated film a first etching process of the first hole; a process of forming a channel in the plurality of first holes; a second etching process of forming a second hole between the channels; and supplying a fluorine-containing etching gas to remove the second In the third etching process of the first film adjacent to the hole, in the third etching process, the first film is removed until the etching gas reaches a film forming the channel formed by the film of the second film. . 一種基板處理裝置,其特徵係具備實行至少包含 下列程序的程式之控制器,該程式係至少包含:形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的膜的第2膜的層疊膜之程序;在前述層疊膜形成複數的第一孔之程序;在前述複數的第一孔形成通道之程序;在前述通道間形成第二孔之程序;及供給含氟的蝕刻氣體,而除去與前述第二孔鄰接的前述第1膜之程序,前述控制器係於除去前述第1膜的程序中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,使前述第1膜除去。 A substrate processing apparatus characterized in that the implementation includes at least The program of the program of the following program includes at least a program for forming a laminated film including a first film containing ruthenium as a main component and a second film containing a film having a lower enthalpy ratio than the first film; a process of forming a plurality of first holes by laminating a film; a process of forming a channel in the plurality of first holes; a process of forming a second hole between the channels; and supplying a fluorine-containing etching gas to be adjacent to the second hole In the procedure of the first film, the controller is configured to remove the first film, and the first etching step is performed until the etching gas reaches a film forming the channel formed by the film of the second film. The membrane was removed. 一種記錄媒體,係於控制器可讀取至少使下列程序實行的程式,形成包含以矽為主成分的第1膜及含矽率比前述第1膜更少的膜的第2膜的層疊膜之程序;在前述層疊膜形成複數的第一孔之程序;在前述複數的第一孔形成通道之程序;在前述通道間形成第二孔之程序;及供給含氟的蝕刻氣體,而除去與前述第二孔鄰接的前述第1膜之程序,前述控制器係於除去前述第1膜的程序中,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,使前述第1膜除去。 A recording medium in which a controller can read a program in which at least the following program is executed, and form a laminated film including a first film containing ruthenium as a main component and a second film containing a film having a lower enthalpy ratio than the first film. a program for forming a plurality of first holes in the laminated film; a process of forming a channel in the plurality of first holes; a process of forming a second hole between the channels; and supplying a fluorine-containing etching gas to remove In the procedure of the first film adjacent to the second hole, the controller is in a process of removing the first film until the etching gas reaches a film forming the channel formed by the film of the second film. The first film is removed. 如申請專利範圍第2項之半導體裝置的製造方 法,其中,前述第1膜為導電膜,為多晶矽(Poly-Si)膜或非晶形矽(α-Si)膜。 Manufacturer of a semiconductor device as claimed in claim 2 The first film is a conductive film and is a poly-Si film or an amorphous germanium (α-Si) film. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第2膜為絕緣膜,為矽膜(Si膜)以外的膜,包含矽氮化膜(Si3N4膜)、二氧化矽膜(SiO2膜)、矽氧氮化膜(SiON膜)、碳化矽膜(SiC膜)的其中至少一個。 The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the second film is an insulating film, and is a film other than a ruthenium film (Si film), comprising a ruthenium nitride film (Si 3 N 4 film), and dioxide. At least one of a ruthenium film (SiO 2 film), a hafnium oxynitride film (SiON film), and a tantalum carbide film (SiC film). 如申請專利範圍第2項之半導體裝置的製造方法,其中,在形成前述通道的工程中,具有:在前述第一孔的內壁形成第1預定膜之工程、及形成作為前述通道的第2預定膜之工程。 The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the process of forming the channel includes: forming a first predetermined film on an inner wall of the first hole; and forming a second channel as the channel The film is scheduled to work. 如申請專利範圍第7項之半導體裝置的製造方法,其中,前述第1預定膜係以SiO2膜/Si3N4膜/SiO2膜所構成的ONO膜。 The method of manufacturing a semiconductor device according to claim 7, wherein the first predetermined film is an ONO film composed of a SiO 2 film/Si 3 N 4 film/SiO 2 film. 如申請專利範圍第7項之半導體裝置的製造方法,其中,前述第2預定膜為多晶矽(Poly-Si)膜或非晶形矽(α-Si)膜。 The method of manufacturing a semiconductor device according to claim 7, wherein the second predetermined film is a poly-Si film or an amorphous germanium (α-Si) film. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第2蝕刻工程係與前述第1蝕刻工程同處理條件。 The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the second etching process is the same as the first etching process. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第一孔與前述第二孔的各寬及深度為相同。 The method of manufacturing a semiconductor device according to claim 2, wherein each of the first hole and the second hole has the same width and depth. 如申請專利範圍第10項之半導體裝置的製造方 法,其中,在前述第1蝕刻工程及前述第2蝕刻工程中,使用SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一氣體。 The method of manufacturing a semiconductor device according to claim 10, wherein in the first etching process and the second etching process, a mixed gas of SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 is used. Or any gas of a CF 4 /O 2 mixed gas. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述蝕刻氣體為七氟化碘(IF7)氣體、三氟化氯(ClF3)、二氟化氙(XeF2)、三氟化溴(BrF3)氣體、五氟化溴(BrF5)氣體、五氟化碘(IF5)氣體之中的任一氣體。 The method of manufacturing a semiconductor device according to claim 2, wherein the etching gas is iodine heptafluoride (IF7) gas, chlorine trifluoride (ClF3), xenon difluoride (XeF2), or bromine trifluoride ( Any of BrF3) gas, bromine pentoxide (BrF5) gas, and iodine pentafluoride (IF5) gas. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第3蝕刻工程係實施各向同性蝕刻,前述第1或第2蝕刻工程係實施各向異性蝕刻。 The method of manufacturing a semiconductor device according to claim 2, wherein the third etching process performs isotropic etching, and the first or second etching process performs anisotropic etching. 如申請專利範圍第2項之半導體裝置的製造方法,其中,更在前述第3蝕刻工程之後,具有形成成為字元線的金屬電極等的導電膜之工程,形成前述金屬電極的工程係具有:形成前述導電膜的工程;及以能夠留下在前述第3蝕刻工程中被除去的部分成膜的金屬膜之方式,除去前述金屬膜的工程。 The method of manufacturing a semiconductor device according to the second aspect of the invention, further comprising the step of forming a conductive film of a metal electrode or the like as a word line after the third etching process, wherein the engineering system for forming the metal electrode comprises: The process of forming the conductive film; and the process of removing the metal film by leaving a portion of the metal film formed in the third etching process. 如申請專利範圍第15項之半導體裝置的製造方法,其中,除去前述金屬膜的工程係實施各向異性蝕刻。 The method of manufacturing a semiconductor device according to claim 15, wherein the engineering for removing the metal film is anisotropic etching. 如申請專利範圍第15項之半導體裝置的製造方法,其中,在除去前述金屬膜的工程中,使用SF6、SiCl4、Cl2、CF4、CF4/H2混合氣體、或CF4/O2混合氣體的任一氣體。 The method of manufacturing a semiconductor device according to claim 15, wherein in the process of removing the metal film, SF 6 , SiCl 4 , Cl 2 , CF 4 , CF 4 /H 2 mixed gas, or CF 4 / is used. Any gas of O 2 mixed gas. 如申請專利範圍第15項之半導體裝置的製造方法,其中,前述金屬膜係由鎢(W)膜、TiN膜、TiN/Al膜、或TaN/W膜所選擇的膜。 The method of manufacturing a semiconductor device according to claim 15, wherein the metal film is a film selected from a tungsten (W) film, a TiN film, a TiN/Al film, or a TaN/W film. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第3蝕刻工程係具有:除去前述第1膜的工程、及除去前述蝕刻氣體的殘渣之淨化工程,在前述淨化工程中,將基板溫度設定成比蝕刻處理更高的溫度。 The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the third etching process includes a process of removing the first film and a cleaning process for removing the residue of the etching gas, and in the cleaning process, The substrate temperature is set to a higher temperature than the etching process. 如申請專利範圍第2項之半導體裝置的製造方法,其中,前述第3蝕刻工程係具有:除去前述第1膜的工程、及除去前述蝕刻氣體的殘渣之淨化工程,在前述淨化工程中,基板溫度係設定成比在除去前述第1膜的工程所產生的副生成物的昇華溫度更高。 The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the third etching process includes a process of removing the first film and a process of removing a residue of the etching gas, and in the cleaning process, the substrate The temperature system is set to be higher than the sublimation temperature of the by-product generated in the process of removing the first film. 一種半導體裝置的製造方法,其特徵係具有:在具有以矽為主成分的第1膜之基板的表面形成組成與前述第1膜相異的第3膜之工程;在前述第3膜的表面形成包含前述第1膜及含矽率比前述第1膜更少的第2膜的層疊膜之工程;在前述層疊膜形成複數的貫通孔(第一孔)之第1蝕刻工程;在前述複數的貫通孔(第一孔)形成通道之工程;在前述通道之間形成溝(第二孔)之第2蝕刻工程;及使蝕刻氣體接觸於前述第1膜、前述第2膜、前述第 3膜的各表面,除去與前述溝(第二孔)鄰接之包含前述第1膜及前述第2膜的層疊膜之中前述第1膜之第3蝕刻工程,在前述第3蝕刻工程中,不除去前述第2膜及前述第3膜,至前述蝕刻氣體到達形成以和前述第2膜同膜種所形成的前述通道的膜為止,除去前述第1膜。 A method for producing a semiconductor device, comprising: forming a third film having a composition different from that of the first film on a surface of a substrate having a first film containing ruthenium as a main component; and forming a surface of the third film a process of forming a laminated film including the first film and a second film having a lower than the first film; and forming a plurality of through holes (first holes) in the laminated film; a through hole (first hole) forming a channel; a second etching process for forming a groove (second hole) between the channels; and contacting the etching gas with the first film, the second film, and the first The third etching process of the first film in the laminated film including the first film and the second film adjacent to the groove (second hole) is removed from each surface of the film, and in the third etching process, The first film and the third film are not removed, and the first film is removed until the etching gas reaches a film forming the channel formed by the film of the second film. 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述第1膜為導電膜,為多晶矽(Poly-Si)膜或非晶形矽(α-Si)膜。 The method of manufacturing a semiconductor device according to claim 21, wherein the first film is a conductive film and is a poly-Si film or an amorphous germanium (α-Si) film. 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述第2膜為絕緣膜,包含矽氮化膜(Si3N4膜)、二氧化矽膜(SiO2膜)、矽氧氮化膜(SiON膜)、碳化矽膜(SiC膜)的其中至少一個。 The method of manufacturing a semiconductor device according to claim 21, wherein the second film is an insulating film, and includes a tantalum nitride film (Si 3 N 4 film), a hafnium oxide film (SiO 2 film), and xenon-oxygen nitrogen. At least one of a film (SiON film) and a tantalum carbide film (SiC film). 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述第3膜係使矽氮化的膜。 The method of manufacturing a semiconductor device according to claim 21, wherein the third film is a film in which tantalum is nitrided. 如申請專利範圍第21項之半導體裝置的製造方法,其中,在形成前述通道的工程中,具有:在前述第一孔的內壁形成第1預定膜之工程、及形成作為前述通道的第2預定膜之工程。 The method of manufacturing a semiconductor device according to claim 21, wherein in the process of forming the channel, the first predetermined film is formed on the inner wall of the first hole, and the second channel is formed as the channel. The film is scheduled to work. 如申請專利範圍第25項之半導體裝置的製造方法,其中,前述第1預定膜係以SiO2膜/Si3N4膜/SiO2膜所構成的ONO膜。 The method of manufacturing a semiconductor device according to claim 25, wherein the first predetermined film is an ONO film composed of a SiO 2 film/Si 3 N 4 film/SiO 2 film. 如申請專利範圍第25項之半導體裝置的製造方法,其中,前述第2預定膜為多晶矽(Poly-Si)膜或非晶 形矽(α-Si)膜。 The method of manufacturing a semiconductor device according to claim 25, wherein the second predetermined film is a poly-Si film or an amorphous film. Shaped α (α-Si) film. 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述蝕刻氣體為七氟化碘(IF7)氣體、三氟化氯(ClF3)、二氟化氙(XeF2)、三氟化溴(BrF3)氣體、五氟化溴(BrF5)氣體、五氟化碘(IF5)氣體之中的任一氣體。 The method of manufacturing a semiconductor device according to claim 21, wherein the etching gas is iodine heptafluoride (IF7) gas, chlorine trifluoride (ClF3), xenon difluoride (XeF2), or bromine trifluoride ( Any of BrF3) gas, bromine pentoxide (BrF5) gas, and iodine pentafluoride (IF5) gas. 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述第3蝕刻工程係具有:除去前述第1膜的工程、及除去前述蝕刻氣體的殘渣之淨化工程,在前述淨化工程中,將基板溫度設定成比蝕刻處理更高的溫度。 The method of manufacturing a semiconductor device according to claim 21, wherein the third etching process includes a process of removing the first film and a cleaning process for removing a residue of the etching gas, and in the cleaning process, The substrate temperature is set to a higher temperature than the etching process. 如申請專利範圍第21項之半導體裝置的製造方法,其中,前述第3蝕刻工程係具有:除去前述第1膜的工程、及除去前述蝕刻氣體的殘渣之淨化工程,在前述淨化工程中,基板溫度係設定成比在除去前述第1膜的工程所產生的副生成物的昇華溫度更高。 The method of manufacturing a semiconductor device according to claim 21, wherein the third etching process includes a process of removing the first film and a process of removing a residue of the etching gas, and in the cleaning process, the substrate The temperature system is set to be higher than the sublimation temperature of the by-product generated in the process of removing the first film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI784658B (en) * 2020-08-31 2022-11-21 日商斯庫林集團股份有限公司 Substrate processing method and substrate processing device
TWI836261B (en) * 2020-09-25 2024-03-21 日商國際電氣股份有限公司 Semiconductor device manufacturing method, substrate processing device and program

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6434877B2 (en) * 2015-08-26 2018-12-05 東芝メモリ株式会社 Semiconductor device
TWI675905B (en) * 2015-11-14 2019-11-01 日商東京威力科創股份有限公司 Method of treating a microelectronic substrate using dilute tmah
JP6623943B2 (en) * 2016-06-14 2019-12-25 東京エレクトロン株式会社 Semiconductor device manufacturing method, heat treatment apparatus, and storage medium.
JP2018022830A (en) * 2016-08-05 2018-02-08 東京エレクトロン株式会社 Method for processing object to be processed
JP6789314B2 (en) * 2016-11-30 2020-11-25 株式会社Kokusai Electric Substrate processing equipment, semiconductor equipment manufacturing methods and programs
US10651087B2 (en) 2017-08-31 2020-05-12 Yangtze Memory Technologies Co., Ltd. Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
US10529581B2 (en) * 2017-12-29 2020-01-07 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude SiN selective etch to SiO2 with non-plasma dry process for 3D NAND device applications
US10522750B2 (en) 2018-02-19 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices
JP7195060B2 (en) * 2018-05-17 2022-12-23 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus
CN112567515B (en) * 2018-07-27 2024-05-07 长江存储科技有限责任公司 Memory structure and forming method thereof
JP2020068221A (en) * 2018-10-22 2020-04-30 東京エレクトロン株式会社 Etching method and plasma processing apparatus
JP2020115511A (en) 2019-01-17 2020-07-30 キオクシア株式会社 Semiconductor storage device and manufacturing method of semiconductor storage device
JP7224268B2 (en) * 2019-10-16 2023-02-17 三菱電機株式会社 Manufacturing method of optical semiconductor device
JP7296912B2 (en) * 2020-04-07 2023-06-23 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus
JP2024083014A (en) * 2022-12-09 2024-06-20 東京エレクトロン株式会社 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008218984A (en) * 2007-02-06 2008-09-18 Hitachi Kokusai Electric Inc Semiconductor device manufacturing method and substrate processing apparatus
JP2010177652A (en) * 2009-02-02 2010-08-12 Toshiba Corp Method for manufacturing semiconductor device
KR101698193B1 (en) * 2009-09-15 2017-01-19 삼성전자주식회사 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same
JP2011192879A (en) * 2010-03-16 2011-09-29 Toshiba Corp Non-volatile memory device and method of manufacturing the same
KR101825539B1 (en) * 2010-10-05 2018-03-22 삼성전자주식회사 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same
KR101760658B1 (en) * 2010-11-16 2017-07-24 삼성전자 주식회사 Non-volatile memory device
WO2013027653A1 (en) * 2011-08-25 2013-02-28 大日本スクリーン製造株式会社 Pattern forming method
US9076879B2 (en) * 2012-09-11 2015-07-07 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI784658B (en) * 2020-08-31 2022-11-21 日商斯庫林集團股份有限公司 Substrate processing method and substrate processing device
TWI836261B (en) * 2020-09-25 2024-03-21 日商國際電氣股份有限公司 Semiconductor device manufacturing method, substrate processing device and program

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