TW201524299A - Manufacturing method of wiring board - Google Patents
Manufacturing method of wiring board Download PDFInfo
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- TW201524299A TW201524299A TW103132035A TW103132035A TW201524299A TW 201524299 A TW201524299 A TW 201524299A TW 103132035 A TW103132035 A TW 103132035A TW 103132035 A TW103132035 A TW 103132035A TW 201524299 A TW201524299 A TW 201524299A
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- layer
- opening
- wiring
- conductive layer
- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
本發明係關於一種佈線基板之製造方法。 The present invention relates to a method of manufacturing a wiring substrate.
已知有藉由無電解電鍍、電解電鍍、真空蒸鍍、濺鍍法形成佈線基板中之佈線層之晶種層(參照專利文獻2、專利文獻3)。 A seed layer for forming a wiring layer in a wiring board by electroless plating, electrolytic plating, vacuum deposition, or sputtering is known (see Patent Document 2 and Patent Document 3).
作為形成用以形成佈線基板中之佈線導體之均勻且較薄之金屬層之方法，代替利用無電解電鍍之方法，已知有濺鍍、或真空蒸鍍、或離子電鍍等方法(參照專利文獻1)。 As a method of forming a uniform and thin metal layer for forming a wiring conductor in a wiring substrate, a method of sputtering, vacuum evaporation, or ion plating is known instead of the method of electroless plating (refer to the patent literature). 1).
作為多層佈線基板、即所謂增層多層佈線基板中之多層導體電路之形成方法，已知有如下方法，即，於形成在基板上之樹脂絕緣層表面形成粗化層，並於該粗化層表面賦予無電解電鍍用觸媒核而形成無電解電鍍膜。其後，設置電鍍阻劑並於實施電解電鍍處理之後去除該電鍍阻劑，其後，對電鍍阻劑下之無電解電鍍膜進行蝕刻處理。藉此，對基板之兩面同時增層導體電路(參照專利文獻4)。 As a method of forming a multilayer conductor circuit in a multilayer wiring board, that is, a so-called build-up multilayer wiring board, a method is known in which a rough layer is formed on a surface of a resin insulating layer formed on a substrate, and the rough layer is formed. The surface is provided with a catalyst core for electroless plating to form an electroless plating film. Thereafter, a plating resist is provided and the plating resist is removed after the electrolytic plating treatment is performed, and thereafter, the electroless plating film under the plating resist is etched. Thereby, a conductor circuit is simultaneously added to both surfaces of the substrate (see Patent Document 4).
[專利文獻1]日本專利第4328196號公報 [Patent Document 1] Japanese Patent No. 4328196
[專利文獻2]日本專利特開2010-10639號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-10639
[專利文獻3]日本專利特開2008-218540號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2008-218540
[專利文獻4]日本專利特開2000-294926號公報 [Patent Document 4] Japanese Patent Laid-Open Publication No. 2000-294926
於對基板之兩面同時增層導體電路即佈線層之習知之方法中，藉由相同製程將佈線層積層在兩面，因此，兩面之佈線層皆為相同之構造。 In a conventional method of simultaneously adding a conductor circuit, that is, a wiring layer, to both sides of a substrate, the wiring layer is laminated on both sides by the same process, and therefore, the wiring layers on both sides have the same structure.
然而，於例如在佈線基板之一面搭載半導體晶片，在另一面連接其他佈線基板之情況下，較多為如下情況，即，要求半導體晶片搭載側之佈線層為細微，但不要求連接其他佈線基板側之佈線層為細微。 For example, when a semiconductor wafer is mounted on one surface of a wiring board and another wiring board is connected to the other surface, the wiring layer on the semiconductor wafer mounting side is required to be fine, but it is not required to connect other wiring substrates. The wiring layer on the side is subtle.
一般而言，形成細微之佈線層耗費成本，若如習知般，藉由相同製程對兩面積層細微之佈線層，則會使不要求為細微之側之佈線層之成本白費。 In general, it is costly to form a fine wiring layer, and as is conventionally known, the wiring layer of the two-area layer by the same process can make the cost of the wiring layer which is not required to be a fine side in vain.
本發明之目的在於提供一種佈線基板之製造方法，該佈線基板之製造方法係在對基板之兩面同時形成佈線層之方法中，不會伴隨著較大之製程之變更的狀態，而能夠形成於基板之一面可形成有細微之佈線之構造，及於另一面雖未對應於細微之佈線但為廉價之構造。 An object of the present invention is to provide a method of manufacturing a wiring board which can be formed in a method of simultaneously forming a wiring layer on both surfaces of a substrate without being changed in a state in which a large process is changed. One surface of the substrate can be formed with a fine wiring structure, and the other surface does not correspond to a fine wiring, but is inexpensive.
根據實施形態之一態樣，提供有一種佈線基板之製造方法，該佈線基板之製造方法之特徵在於包括有：第1步驟，其於核心基板之一面側，將已積層之第1絕緣層及第1保護層，以上述 第1絕緣層對向於上述核心基板之方式加以積層，並且於上述核心基板之另一面側，將已積層之第2絕緣層及第2保護層，以上述第2絕緣層對向於上述核心基板之方式加以積層；第2步驟，其於上述第1絕緣層及上述第1保護層，形成第1開口，並且於上述第2絕緣層及上述第2保護層，形成第2開口；第3步驟，其將上述第2保護層加以剝離；第4步驟，其同時對上述第1開口之內壁、上述第2絕緣層上及上述第2開口之內壁進行粗化；第5步驟，其於上述第1保護層上及上述第1開口之內壁，形成第1導電層，同時於上述第2絕緣層上及上述第2開口之內壁，形成第2導電層；第6步驟，其將上述第1保護層，與形成在上述第1保護層上之上述第1導電層一併加以去除；第7步驟，其藉由乾式製程，於上述第1絕緣層上及上述第1開口之內壁，形成第3導電層；及第8步驟，其藉由電解電鍍，將上述第3導電層作為供電層，於上述第3導電層上，形成第1佈線層，同時將上述第2導電層作為供電層，於上述第2導電層上，形成第2佈線層。 According to an aspect of the embodiment, there is provided a method of manufacturing a wiring board, characterized in that the method of manufacturing a wiring board includes a first step of laminating a first insulating layer on one side of a core substrate and First protective layer, as described above The first insulating layer is laminated on the core substrate, and the second insulating layer and the second protective layer which are laminated on the other surface side of the core substrate are opposed to the core by the second insulating layer In the second step, the first opening is formed in the first insulating layer and the first protective layer, and the second opening is formed in the second insulating layer and the second protective layer; a step of peeling off the second protective layer; and a fourth step of roughening the inner wall of the first opening, the second insulating layer, and the inner wall of the second opening; and the fifth step Forming a first conductive layer on the first protective layer and the inner wall of the first opening, and forming a second conductive layer on the second insulating layer and the inner wall of the second opening; and a sixth step The first protective layer is removed together with the first conductive layer formed on the first protective layer; and the seventh step is performed on the first insulating layer and the first opening by a dry process The inner wall forms a third conductive layer; and the eighth step is performed by electrolysis , The above-described third conductive layer as a feeding layer, on said third conductive layer, forming a first wiring layer, while the second conductive layer as a feeding layer on said second conductive layer, forming a second wiring layer.
根據實施形態之一態樣，提供有一種佈線基板之製造方法，該佈線基板之製造方法之特徵在於包括有：第1步驟，其於核心基板之一面側，將已積層之第1絕緣層、第1導電層及第1保護層，以上述第1絕緣層對向於上述核心基板之方式加以積層，並且於上述核心基板之另一面側，將已積層之第2絕緣層及第2保護層，以上述第2絕緣層對向於上述核心基板之方式加以積層；第2步驟，其於上述第1絕緣層、上述第1導電層及上述第1保護層，形成第1開口，並且於上述第2絕緣層及上述第2保護層，形成第2開口；第3步驟，其將上述第2保護層加以剝離；第4步驟，其 同時對上述第1開口之內壁、上述第2絕緣層上及上述第2開口之內壁進行粗化；第5步驟，其於上述第1保護層上及上述第1開口之內壁，形成第2導電層，同時於上述第2絕緣層上及上述第2開口之內壁，形成第3導電層；第6步驟，其將上述第1保護層，與形成在上述第1保護層上之上述第2導電層一併加以去除；及第7步驟，其藉由電解電鍍，將上述第1導電層及形成在上述第1開口之內壁的上述第2導電層作為供電層，於上述第1導電層上及上述第2導電層上，形成第1佈線層，同時將上述第3導電層作為供電層，於上述第3導電層上，形成第2佈線層。 According to an aspect of the embodiment, there is provided a method of manufacturing a wiring board, characterized in that the method of manufacturing a wiring board includes a first step of laminating a first insulating layer on one side of a core substrate The first conductive layer and the first protective layer are laminated such that the first insulating layer faces the core substrate, and the second insulating layer and the second protective layer are laminated on the other surface side of the core substrate. The second insulating layer is laminated to the core substrate, and the second step is to form a first opening in the first insulating layer, the first conductive layer, and the first protective layer. The second insulating layer and the second protective layer form a second opening; the third step of peeling off the second protective layer; and the fourth step At the same time, the inner wall of the first opening, the second insulating layer and the inner wall of the second opening are roughened, and the fifth step is formed on the first protective layer and the inner wall of the first opening. a second conductive layer simultaneously forming a third conductive layer on the second insulating layer and an inner wall of the second opening; and a sixth step of forming the first protective layer on the first protective layer The second conductive layer is collectively removed; and in the seventh step, the first conductive layer and the second conductive layer formed on the inner wall of the first opening are used as a power supply layer by electrolytic plating. A first wiring layer is formed on the conductive layer and the second conductive layer, and the third conductive layer is used as the power supply layer, and the second wiring layer is formed on the third conductive layer.
根據揭示之佈線基板之製造方法，可於對基板之兩面同時形成佈線層之方法中，不伴隨較大之製程之變更，而於基板之一面形成可形成有細微之佈線之構造、並於另一面形成雖未對應於細微之佈線但為廉價之構造。 According to the method for manufacturing a wiring board disclosed above, in the method of simultaneously forming a wiring layer on both surfaces of the substrate, a structure in which fine wiring can be formed on one surface of the substrate can be formed without changing a large process, and It is a structure which is inexpensive, but does not correspond to a fine wiring.
10‧‧‧佈線基板 10‧‧‧ wiring substrate
12‧‧‧核心基板 12‧‧‧ core substrate
14‧‧‧貫通電極 14‧‧‧through electrode
14a、14b、14c、14d‧‧‧導電層 14a, 14b, 14c, 14d‧‧‧ conductive layer
16、17‧‧‧絕緣層 16, 17‧‧‧ insulation
18、19‧‧‧佈線層 18, 19‧‧‧ wiring layer
20、21‧‧‧阻焊劑層 20, 21‧‧‧ solder resist layer
20a、21a‧‧‧開口 20a, 21a‧‧‧ openings
22‧‧‧凸塊(連接端子) 22‧‧‧Bumps (connection terminals)
24‧‧‧凸塊(連接端子) 24‧‧‧Bumps (connection terminals)
26‧‧‧底填充樹脂 26‧‧‧ bottom filled resin
28‧‧‧半導體晶片 28‧‧‧Semiconductor wafer
30‧‧‧覆銅積層板 30‧‧‧Copper laminate
32‧‧‧核心基板 32‧‧‧ core substrate
34、36‧‧‧導電層 34, 36‧‧‧ conductive layer
38‧‧‧開口 38‧‧‧ openings
40‧‧‧導電層 40‧‧‧ Conductive layer
42‧‧‧樹脂 42‧‧‧Resin
43‧‧‧貫通電極 43‧‧‧through electrode
46‧‧‧導電層 46‧‧‧ Conductive layer
48‧‧‧感光性樹脂膜 48‧‧‧Photosensitive resin film
50、51‧‧‧佈線層 50, 51‧‧‧ wiring layer
52‧‧‧保護層 52‧‧‧Protective layer
54‧‧‧絕緣層 54‧‧‧Insulation
56‧‧‧保護膜 56‧‧‧Protective film
58‧‧‧層間絕緣材料 58‧‧‧Interlayer insulation
59‧‧‧輥 59‧‧‧ Roll
60‧‧‧絕緣層 60‧‧‧Insulation
62‧‧‧保護層 62‧‧‧Protective layer
64‧‧‧絕緣層 64‧‧‧Insulation
66‧‧‧保護層 66‧‧‧Protective layer
68、70‧‧‧開口 68, 70‧‧‧ openings
72、74‧‧‧導電層 72, 74‧‧‧ conductive layer
76‧‧‧晶種層 76‧‧‧ seed layer
78、80‧‧‧光阻層 78, 80‧‧‧ photoresist layer
82、84‧‧‧導電層 82, 84‧‧‧ conductive layer
86、88‧‧‧佈線層 86, 88‧‧‧ wiring layer
90‧‧‧絕緣層 90‧‧‧Insulation
92‧‧‧保護層 92‧‧‧Protective layer
94‧‧‧絕緣層 94‧‧‧Insulation
96‧‧‧保護層 96‧‧‧Protective layer
98、100‧‧‧開口 98, 100‧‧‧ openings
102‧‧‧保護層 102‧‧‧Protective layer
104‧‧‧轉印銅層 104‧‧‧Transfer copper layer
106‧‧‧絕緣層 106‧‧‧Insulation
108‧‧‧保護膜 108‧‧‧Protective film
110‧‧‧附轉印銅層之層間絕緣材料 110‧‧‧Interlayer insulation material with transfer copper layer
111‧‧‧輥 111‧‧‧ Roll
112‧‧‧絕緣層 112‧‧‧Insulation
114‧‧‧保護層 114‧‧‧Protective layer
116‧‧‧絕緣層 116‧‧‧Insulation
118‧‧‧轉印銅層 118‧‧‧Transfer copper layer
120‧‧‧保護層 120‧‧‧Protective layer
122、124‧‧‧開口 122, 124‧‧‧ openings
126、128‧‧‧導電層 126, 128‧‧‧ conductive layer
129、130‧‧‧光阻層 129, 130‧‧‧ photoresist layer
132、134‧‧‧導電層 132, 134‧‧‧ conductive layer
136、138‧‧‧佈線層 136, 138‧‧‧ wiring layer
140‧‧‧絕緣層 140‧‧‧Insulation
142‧‧‧保護層 142‧‧‧Protective layer
144‧‧‧絕緣層 144‧‧‧Insulation
146‧‧‧轉印銅層 146‧‧‧Transfer copper layer
148‧‧‧保護層 148‧‧‧Protective layer
150、152‧‧‧開口 150, 152‧‧‧ openings
圖1係表示第1實施形態之佈線基板之圖。 Fig. 1 is a view showing a wiring board of the first embodiment.
圖2(a)至(c)係表示第1實施形態之佈線基板之製造方法之步驟 剖面圖(其1)。 2(a) to 2(c) show the steps of a method of manufacturing a wiring board according to the first embodiment. Sectional view (1).
圖3(a)至(c)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其2)。 3 (a) to (c) are cross-sectional views (2) of the steps of the method of manufacturing the wiring board of the first embodiment.
圖4(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其3)。 4(a) and 4(b) are cross-sectional views (3) showing the steps of the method of manufacturing the wiring board of the first embodiment.
圖5係表示於第1實施形態之佈線基板之製造方法中使用之層 間絕緣材料之圖。 Fig. 5 is a view showing a layer used in the method of manufacturing a wiring board of the first embodiment; A diagram of the insulating material.
圖6(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其4)。 6(a) and 6(b) are cross-sectional views showing the steps of the method of manufacturing the wiring board of the first embodiment (part 4).
圖7(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其5)。 (a) and (b) of FIG. 7 are sectional views (5) of the method of manufacturing the wiring board of the first embodiment.
圖8(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其6)。 (a) and (b) of FIG. 8 are sectional views (6) of the method of manufacturing the wiring board of the first embodiment.
圖9(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其7)。 (a) and (b) of FIG. 9 are sectional views (7) of the method of manufacturing the wiring board of the first embodiment.
圖10(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其8)。 (a) and (b) of FIG. 10 are sectional views (8) of the method of manufacturing the wiring board of the first embodiment.
圖11(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其9)。 (a) and (b) of FIG. 11 are sectional views (9) of the method of manufacturing the wiring board of the first embodiment.
圖12(a)及(b)係表示第1實施形態之佈線基板之製造方法之步驟剖面圖(其10)。 (a) and (b) of FIG. 12 are cross-sectional views (10) of the method of manufacturing the wiring board of the first embodiment.
圖13係表示於第2實施形態之佈線基板之製造方法中使用之層間絕緣材料之圖。 Fig. 13 is a view showing an interlayer insulating material used in the method of manufacturing a wiring board of the second embodiment.
圖14(a)及(b)係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其1)。 (a) and (b) of FIG. 14 are cross-sectional views showing a step of manufacturing a wiring board according to a second embodiment (part 1).
圖15(a)及(b)係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其2)。 15(a) and 15(b) are cross-sectional views showing the steps of the method of manufacturing the wiring board of the second embodiment (part 2).
圖16(a)及(b)係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其3)。 (a) and (b) of FIG. 16 are sectional views (3) of the method of manufacturing the wiring board of the second embodiment.
圖17(a)及(b)係表示第2實施形態之佈線基板之製造方法之步 驟剖面圖(其4)。 17(a) and (b) show the steps of the method of manufacturing the wiring board of the second embodiment. A cross-sectional view (4).
圖18(a)及(b)係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其5)。 18 (a) and (b) are cross-sectional views (5) of the steps of the method of manufacturing the wiring board of the second embodiment.
圖19(a)及(b)係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其6)。 19(a) and (b) are cross-sectional views (6) of the method of manufacturing the wiring board of the second embodiment.
圖20係表示第2實施形態之佈線基板之製造方法之步驟剖面圖(其7)。 Fig. 20 is a cross-sectional view (7) showing a step of manufacturing the wiring board of the second embodiment.
使用圖1對第1實施形態之佈線基板進行說明。圖1係於本實施形態之佈線基板搭載半導體晶片後之狀態之剖面圖。 The wiring board of the first embodiment will be described with reference to Fig. 1 . Fig. 1 is a cross-sectional view showing a state in which a semiconductor wafer is mounted on a wiring board of the embodiment.
本實施形態之佈線基板10係如圖1所示般具有由樹脂形成之核心基板12。核心基板12例如約為100~400μm之厚度。 The wiring board 10 of the present embodiment has a core substrate 12 made of a resin as shown in FIG. The core substrate 12 is, for example, approximately 100 to 400 μm thick.
作為形成核心基板12之樹脂，可使用酚醛紙基板、環氧樹脂紙基板、玻璃環氧樹脂基板、玻璃複合基板、可撓性材等。 As the resin forming the core substrate 12, a phenol paper substrate, an epoxy resin paper substrate, a glass epoxy substrate, a glass composite substrate, a flexible material, or the like can be used.
於核心基板12形成有複數個貫通電極14。貫通電極14例如於中心填充有樹脂14a，並於樹脂14a之周圍及兩端形成有導電層14b、14c、14d。貫通電極14例如約為100~200μm之直徑。 A plurality of through electrodes 14 are formed on the core substrate 12. The through electrode 14 is filled with a resin 14a at the center, for example, and conductive layers 14b, 14c, and 14d are formed around and at both ends of the resin 14a. The through electrode 14 is, for example, approximately 100 to 200 μm in diameter.
樹脂14a係由例如紫外線硬化油墨、熱硬化性樹脂、導電性樹脂形成。樹脂14a例如約為80~180μm之直徑。 The resin 14a is formed of, for example, an ultraviolet curable ink, a thermosetting resin, or a conductive resin. The resin 14a is, for example, about 80 to 180 μm in diameter.
導電層14b、14c、14d例如由銅形成。導電層14b、14c、14d分別例如約為5~15μm之厚度。 The conductive layers 14b, 14c, 14d are formed, for example, of copper. The conductive layers 14b, 14c, and 14d are each, for example, approximately 5 to 15 μm thick.
於核心基板12之上側之面，交替地積層有絕緣層16及佈線層18，於核心基板12之下側之面，交替地積層有絕緣層17及佈線層19。 On the upper surface of the core substrate 12, an insulating layer 16 and a wiring layer 18 are alternately laminated, and an insulating layer 17 and a wiring layer 19 are alternately laminated on the lower surface of the core substrate 12.
絕緣層16、17可使用例如環氧樹脂、聚醯亞胺等。絕緣層16、17例如約為20~70μm之厚度。 As the insulating layers 16, 17, for example, an epoxy resin, a polyimide or the like can be used. The insulating layers 16, 17 are, for example, approximately 20 to 70 μm thick.
佈線層18、19例如由銅形成。佈線層18、19例如約為5~15μm之厚度。 The wiring layers 18, 19 are formed, for example, of copper. The wiring layers 18, 19 are, for example, approximately 5 to 15 μm thick.
本實施形態之佈線基板10於上側之面搭載有半導體晶片28，並經由下側之面搭載於其他佈線基板(未圖示)。 In the wiring board 10 of the present embodiment, the semiconductor wafer 28 is mounted on the upper surface, and is mounted on another wiring board (not shown) via the lower surface.
佈線基板10之上側之面之佈線層18為了連接於半導體晶片28之連接端子(未圖示)而被要求為細微。佈線層18中之佈線之寬度例如約為1~10μm。相對於此，佈線基板10之下側之面之佈線層19因連接於其他佈線基板(未圖示)而不如上側之面之佈線層18般細微。佈線層19中之佈線之寬度例如約為10~40μm。佈線層18中之佈線之寬度小於佈線層19中之佈線之寬度。 The wiring layer 18 on the upper surface of the wiring board 10 is required to be fine for connection to a connection terminal (not shown) of the semiconductor wafer 28. The width of the wiring in the wiring layer 18 is, for example, about 1 to 10 μm. On the other hand, the wiring layer 19 on the lower surface side of the wiring board 10 is finer than the wiring layer 18 on the upper surface side by being connected to another wiring board (not shown). The width of the wiring in the wiring layer 19 is, for example, about 10 to 40 μm. The width of the wiring in the wiring layer 18 is smaller than the width of the wiring in the wiring layer 19.
如此，本實施形態之佈線基板10於上側之面與下側之面，佈線層18、19之細微度不同。 As described above, in the wiring board 10 of the present embodiment, the wiring layers 18 and 19 have different fineness on the upper surface and the lower surface.
核心基板12之上下兩面之最外層之絕緣層16、17及佈線層18、19係由阻焊劑層20、21被覆。於阻焊劑層20，形成有到達佈線層18之開口20a。於阻焊劑層21，形成有到達佈線層19之開口21a。阻焊劑層20、21例如約為10~30μm之厚度。 The insulating layers 16 and 17 and the wiring layers 18 and 19 which are the outermost layers of the upper and lower surfaces of the core substrate 12 are covered with the solder resist layers 20 and 21. In the solder resist layer 20, an opening 20a reaching the wiring layer 18 is formed. In the solder resist layer 21, an opening 21a reaching the wiring layer 19 is formed. The solder resist layers 20, 21 are, for example, about 10 to 30 μm thick.
於佈線基板10之上側之面之阻焊劑層20之開口20a，形成有用以連接於半導體晶片28之凸塊(連接端子)22。於佈線基板10之下側之面之阻焊劑層21之開口21a，形成有用以連接 於其他佈線基板(未圖示)之凸塊(連接端子)24。凸塊(連接端子)22及凸塊(連接端子)24例如由焊料形成。 The opening 20a of the solder resist layer 20 on the upper side of the wiring substrate 10 forms a bump (connection terminal) 22 for connection to the semiconductor wafer 28. The opening 21a of the solder resist layer 21 on the lower surface of the wiring substrate 10 is formed to be useful for connection A bump (connection terminal) 24 of another wiring board (not shown). The bump (connection terminal) 22 and the bump (connection terminal) 24 are formed of, for example, solder.
於佈線基板10之上側之面搭載有半導體晶片28，且藉由凸塊(連接端子)22而電性連接。於佈線基板10與半導體晶片28之間填充有底填充樹脂26。 The semiconductor wafer 28 is mounted on the upper surface of the wiring board 10, and is electrically connected by bumps (connection terminals) 22. An underfill resin 26 is filled between the wiring substrate 10 and the semiconductor wafer 28.
(佈線基板之製造方法) (Method of Manufacturing Wiring Substrate)
使用圖2至圖12對第1實施形態之佈線基板之製造方法進行說明。圖2至4及圖6至圖12係表示第1實施形態之佈線基板之製造方法之步驟剖面圖。圖5係表示於第1實施形態之佈線基板之製造方法中使用之層間絕緣材料之圖。 A method of manufacturing the wiring board of the first embodiment will be described with reference to Figs. 2 to 12 . 2 to 4 and 6 to 12 are step sectional views showing a method of manufacturing the wiring board of the first embodiment. Fig. 5 is a view showing an interlayer insulating material used in the method of manufacturing a wiring board of the first embodiment.
首先，準備成為佈線基板之核心基板之覆銅積層板30(圖2(a))。覆銅積層板30係於核心基板32之兩面貼附有導電層34、36之積層板。 First, a copper clad laminate 30 which is a core substrate of a wiring board is prepared (Fig. 2(a)). The copper clad laminate 30 is a laminated board in which the conductive layers 34 and 36 are attached to both surfaces of the core substrate 32.
核心基板32係例如使以環氧樹脂等樹脂作為主成分之清漆含浸於由玻璃纖維製作之玻璃布而成者。核心基板32例如約為200μm之厚度。 The core substrate 32 is made of, for example, a varnish containing a resin such as an epoxy resin as a main component, and a glass cloth made of glass fiber. The core substrate 32 is, for example, approximately 200 μm thick.
導電層34、36例如由銅形成。導電層34、36例如約為10~20μm之厚度。 The conductive layers 34, 36 are formed, for example, of copper. The conductive layers 34, 36 are, for example, approximately 10 to 20 μm thick.
其次，於覆銅積層板30，藉由例如鑽孔加工，形成貫通電極用開口38(圖2(b))。開口38例如約為100~200μm之直徑。 Next, the through-electrode opening 30 is formed in the copper clad laminate 30 by, for example, drilling (Fig. 2(b)). The opening 38 is, for example, about 100 to 200 μm in diameter.
接著，對形成有開口38之覆銅積層板30進行除膠渣處理。由於若藉由鑽孔加工於覆銅積層板30形成開口38，則於開口38之內壁殘留因鑽孔加工而熔化之樹脂(膠渣)，故而藉由除膠渣 處理將該膠渣去除。 Next, the copper clad laminate 30 on which the opening 38 is formed is subjected to desmear treatment. Since the opening 38 is formed by the drilling process on the copper clad laminate 30, the resin (slag) which is melted by the drilling process remains on the inner wall of the opening 38, and thus the desmear is removed. The treatment removes the slag.
作為除膠渣處理，可進行濕式除膠渣處理或者乾式除膠渣處理。 As the desmear treatment, wet desmear treatment or dry desmear treatment can be performed.
於濕式除膠渣處理中，將被處理物於例如過錳酸鉀溶液等藥液中且於60℃~80℃之處理溫度下浸漬10~30分鐘。 In the wet desmear treatment, the material to be treated is immersed in a chemical solution such as potassium permanganate solution at a treatment temperature of 60 ° C to 80 ° C for 10 to 30 minutes.
於乾式除膠渣處理中，向電漿裝置(未圖示)導入例如氧氣(O2)與四氟化碳(CF4)之混合氣體而產生電漿，並將被處理物暴露於電漿中1~10分鐘。 In the dry desmear treatment, a mixed gas such as oxygen (O 2 ) and carbon tetrafluoride (CF 4 ) is introduced into a plasma device (not shown) to generate a plasma, and the treated object is exposed to the plasma. 1 to 10 minutes.
其次，於形成有開口38之覆銅積層板30形成導電層40。於覆銅積層板30之上表面及下表面上以及開口38之內壁，藉由於無電解電鍍之後實施電解電鍍而形成導電層40(圖2(c))。導電層40係藉由例如無電解鍍銅及電解鍍銅而形成之銅層。導電層40例如約為0.5~1.5μm之厚度。 Next, a conductive layer 40 is formed on the copper clad laminate 30 having the opening 38 formed therein. On the upper surface and the lower surface of the copper clad laminate 30 and the inner wall of the opening 38, the conductive layer 40 is formed by electrolytic plating after electroless plating (Fig. 2(c)). The conductive layer 40 is a copper layer formed by, for example, electroless copper plating and electrolytic copper plating. The conductive layer 40 is, for example, about 0.5 to 1.5 μm thick.
繼而，向形成有導電層40之覆銅積層板30之開口38內填充樹脂42(圖3(a))。樹脂42為例如紫外線硬化油墨、熱硬化性樹脂、導電性樹脂等。 Then, the opening 42 of the copper clad laminate 30 on which the conductive layer 40 is formed is filled with the resin 42 (Fig. 3(a)). The resin 42 is, for example, an ultraviolet curable ink, a thermosetting resin, a conductive resin, or the like.
覆銅積層板30之開口38內之導電層40及樹脂42成為將核心基板32之上表面及下表面電性連接之貫通電極43。 The conductive layer 40 and the resin 42 in the opening 38 of the copper clad laminate 30 serve as through electrodes 43 for electrically connecting the upper surface and the lower surface of the core substrate 32.
接著，對填充有樹脂42之覆銅積層板30進行除膠渣處理。藉由該除膠渣處理，對貫通電極43之樹脂42上表面及下表面進行粗化。 Next, the copper clad laminate 30 filled with the resin 42 is subjected to desmear treatment. The upper surface and the lower surface of the resin 42 of the through electrode 43 are roughened by the desmear treatment.
作為除膠渣處理，可進行如上所述之濕式除膠渣處理或者乾式除膠渣處理。 As the desmear treatment, wet desmear treatment or dry desmear treatment as described above can be performed.
其次，於填充有樹脂42之覆銅積層板30形成導電層 46。於覆銅積層板30之上表面及下表面上，藉由於無電解電鍍之後實施電解電鍍而形成導電層46(圖3(b))。導電層46係藉由例如無電解鍍銅及電解鍍銅而形成之銅層。導電層46例如約為0.5~1.5μm之厚度。 Next, a conductive layer is formed on the copper clad laminate 30 filled with the resin 42 46. On the upper surface and the lower surface of the copper clad laminate 30, a conductive layer 46 is formed by electrolytic plating after electroless plating (Fig. 3(b)). The conductive layer 46 is a copper layer formed by, for example, electroless copper plating and electrolytic copper plating. The conductive layer 46 is, for example, about 0.5 to 1.5 μm thick.
繼而，於覆銅積層板30之上表面及下表面之導電層46上，貼附感光性樹脂膜48。感光性樹脂膜48為例如光硬化性光阻、化學增幅型光阻等膜。感光性樹脂膜48例如約為10~25μm之厚度。 Then, the photosensitive resin film 48 is attached to the conductive layer 46 on the upper surface and the lower surface of the copper clad laminate 30. The photosensitive resin film 48 is a film such as a photocurable photoresist or a chemically amplified photoresist. The photosensitive resin film 48 is, for example, about 10 to 25 μm thick.
接著，藉由對感光性樹脂膜48進行曝光、顯影，而圖案化成既定之形狀(圖3(c))。 Then, the photosensitive resin film 48 is exposed and developed to be patterned into a predetermined shape (Fig. 3(c)).
其次，將經圖案化之感光性樹脂膜48作為罩幕，對導電層46、40及導電層34、36進行蝕刻，而圖案化成既定之形狀(圖4(a))。 Next, the patterned photosensitive resin film 48 is used as a mask to etch the conductive layers 46 and 40 and the conductive layers 34 and 36 to form a predetermined shape (Fig. 4(a)).
繼而，將感光性樹脂膜48去除。以此方式於核心基板32之上表面及下表面，形成被圖案化成既定之形狀之導電層34、36、40、46(圖4(b))。 Then, the photosensitive resin film 48 is removed. In this way, on the upper surface and the lower surface of the core substrate 32, conductive layers 34, 36, 40, 46 patterned into a predetermined shape are formed (Fig. 4(b)).
經圖案化之導電層34、40、46中之位於核心基板32之上表面側之部分成為直接連接於核心基板32之貫通電極43的上表面側之最下層之佈線層50。 A portion of the patterned conductive layers 34, 40, 46 located on the upper surface side of the core substrate 32 is a wiring layer 50 which is directly connected to the lowermost layer on the upper surface side of the through electrode 43 of the core substrate 32.
經圖案化之導電層36、40、46中之位於核心基板32之下表面側之部分成為直接連接於核心基板32之貫通電極43的下表面側之最下層之佈線層51。 A portion of the patterned conductive layers 36, 40, 46 located on the lower surface side of the core substrate 32 is a wiring layer 51 which is directly connected to the lowermost layer on the lower surface side of the through electrode 43 of the core substrate 32.
其次，如圖5所示般，準備於保護層52上積層有絕緣層54與保護膜56之三層構造之層間絕緣材料58。層間絕緣材料 58被捲於輥59而被提供。 Next, as shown in FIG. 5, an interlayer insulating material 58 having a three-layer structure of an insulating layer 54 and a protective film 56 is laminated on the protective layer 52. Interlayer insulation 58 is wound on the roll 59 to be provided.
保護層52為例如PET(聚對苯二甲酸乙二酯：Polyethylene terephthalate)。絕緣層54為例如ABF(Ajinomoto Build-Up Film)。保護膜56為例如OPP(延伸聚丙烯：oriented polypropylene)。 The protective layer 52 is, for example, PET (polyethylene terephthalate). The insulating layer 54 is, for example, ABF (Ajinomoto Build-Up Film). The protective film 56 is, for example, OPP (oriented polypropylene).
在本實施形態中，準備絕緣層54之厚度不同之複數種層間絕緣材料58。保護層52例如約為30~40μm之厚度。絕緣層54例如約為20~70μm之厚度。保護膜56例如約為10~20μm之厚度。 In the present embodiment, a plurality of interlayer insulating materials 58 having different thicknesses of the insulating layer 54 are prepared. The protective layer 52 is, for example, about 30 to 40 μm thick. The insulating layer 54 is, for example, approximately 20 to 70 μm thick. The protective film 56 is, for example, about 10 to 20 μm thick.
其次，將保護膜56自三層構造之層間絕緣材料58剝離，並將絕緣層54及保護層52暫時貼附於核心基板32之下表面。絕緣層54例如約為50μm之厚度。又，將絕緣層54及保護層52暫時貼附於核心基板32之上表面。絕緣層54例如約為40μm之厚度(圖6(a))。即，暫時貼附於核心基板32之上表面之層間絕緣材料58之絕緣層54較暫時貼附於核心基板32之下表面之層間絕緣材料58之絕緣層54更薄。再者，亦可使暫時貼附於核心基板32之上表面之層間絕緣材料58之絕緣層54之厚度與暫時貼附於核心基板32之下表面之層間絕緣材料58之絕緣層54之厚度相等(例如約40μm之厚度)。 Next, the protective film 56 is peeled off from the interlayer insulating material 58 of the three-layer structure, and the insulating layer 54 and the protective layer 52 are temporarily attached to the lower surface of the core substrate 32. The insulating layer 54 is, for example, about 50 μm thick. Further, the insulating layer 54 and the protective layer 52 are temporarily attached to the upper surface of the core substrate 32. The insulating layer 54 is, for example, approximately 40 μm thick (Fig. 6(a)). That is, the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the upper surface of the core substrate 32 is thinner than the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface of the core substrate 32. Furthermore, the thickness of the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the upper surface of the core substrate 32 may be equal to the thickness of the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface of the core substrate 32. (for example, a thickness of about 40 μm).
再者，絕緣層54及保護層52向核心基板32之下表面及核心基板32之上表面之暫時貼附既可逐面地進行，亦可兩面同時進行。 Further, the temporary adhesion of the insulating layer 54 and the protective layer 52 to the lower surface of the core substrate 32 and the upper surface of the core substrate 32 may be performed face by face or simultaneously on both sides.
接著，若如圖6(a)所示般使用例如真空積層裝置，對核心基板32進行加壓、加熱，則於核心基板32之上表面側之佈線 層50上積層有絕緣層64及保護層66，於下表面側之佈線層51上積層有絕緣層60及保護層62(圖6(b))。 Then, as shown in FIG. 6(a), the core substrate 32 is pressurized and heated by, for example, a vacuum lamination device, and the wiring on the upper surface side of the core substrate 32 is used. An insulating layer 64 and a protective layer 66 are laminated on the layer 50, and an insulating layer 60 and a protective layer 62 are laminated on the wiring layer 51 on the lower surface side (Fig. 6(b)).
其次，於上表面側之絕緣層64及保護層66，藉由例如雷射加工，形成到達佈線層50之開口68(圖7(a))。開口68為錐形狀，且其底部例如約為10~30μm之直徑。 Next, the insulating layer 64 and the protective layer 66 on the upper surface side are formed, for example, by laser processing, to form an opening 68 reaching the wiring layer 50 (Fig. 7(a)). The opening 68 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 10 to 30 μm.
若如此自保護膜66上藉由雷射加工於保護膜66及絕緣層64形成開口68，則與於將保護膜66剝離之後藉由雷射加工於絕緣層64形成開口68之情況相比，可形成較小直徑之開口68。 If the opening 68 is formed by the laser processing on the protective film 66 and the insulating layer 64 from the protective film 66, the opening 68 is formed by the laser processing on the insulating layer 64 after the protective film 66 is peeled off. An opening 68 of smaller diameter can be formed.
同樣地，於下表面側之絕緣層60及保護層62，藉由例如雷射加工，形成到達佈線層51之開口70(圖7(a))。開口70為錐形狀，且其底部例如約為30~50μm之直徑。開口68之底部之直徑小於開口70之底部之直徑。 Similarly, the insulating layer 60 and the protective layer 62 on the lower surface side are formed, for example, by laser processing, to form an opening 70 reaching the wiring layer 51 (Fig. 7(a)). The opening 70 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 30 to 50 μm. The diameter of the bottom of the opening 68 is smaller than the diameter of the bottom of the opening 70.
若如此自保護膜62上藉由雷射加工於保護膜62及絕緣層60形成開口70，則與於將保護膜62剝離之後藉由雷射加工於絕緣層60形成開口70之情況相比，可形成較小直徑之開口70。 If the opening 70 is formed by the laser processing on the protective film 62 and the insulating layer 60 from the protective film 62, the opening 70 is formed by the laser processing on the insulating layer 60 after the protective film 62 is peeled off. An opening 70 of smaller diameter can be formed.
繼而，將下表面側之保護層62剝離(圖7(b))。使用例如自動剝膜機將保護層62剝離。或者，作業人員用手將保護層62剝離。 Then, the protective layer 62 on the lower surface side is peeled off (FIG. 7(b)). The protective layer 62 is peeled off using, for example, an automatic stripper. Alternatively, the operator peels off the protective layer 62 by hand.
接著，進行除膠渣處理。作為除膠渣處理，可進行如上所述之濕式除膠渣處理或者乾式除膠渣處理。 Next, a desmear treatment is performed. As the desmear treatment, wet desmear treatment or dry desmear treatment as described above can be performed.
藉此，去除因雷射加工而產生之膠渣(樹脂殘渣)，並且對下表面側之絕緣層60之表面、及開口70之內壁進行粗化。又，對上表面側之開口68之內壁進行粗化。上表面側之絕緣層64之表面由於被保護層66所覆蓋故而不會被粗化。 Thereby, the slag (resin residue) generated by the laser processing is removed, and the surface of the insulating layer 60 on the lower surface side and the inner wall of the opening 70 are roughened. Further, the inner wall of the opening 68 on the upper surface side is roughened. The surface of the insulating layer 64 on the upper surface side is not covered by the protective layer 66 and is not roughened.
再者，於上述實施形態中，在於上表面側之絕緣層64及保護層66形成開口68，並於下表面側之絕緣層60及保護層62形成開口70之後，將下表面側之保護層62剝離。 Further, in the above embodiment, the insulating layer 64 and the protective layer 66 on the upper surface side are formed with the opening 68, and after the opening 70 is formed on the insulating layer 60 and the protective layer 62 on the lower surface side, the protective layer on the lower surface side is formed. 62 peeling.
然而，亦可於將下表面側之保護層62剝離之後，於上表面側之絕緣層64及保護層66形成開口68，於下表面側之絕緣層60形成開口70。 However, after the protective layer 62 on the lower surface side is peeled off, the opening 68 may be formed on the insulating layer 64 and the protective layer 66 on the upper surface side, and the opening 70 may be formed in the insulating layer 60 on the lower surface side.
其次，藉由無電解電鍍形成導電層72、74(圖8(a))。於上表面側之保護層66上及開口68內壁形成導電層72，於下表面側之絕緣層60上及開口70內壁形成導電層74。導電層72、74係藉由例如無電解鍍銅而形成之銅層。導電層72、74例如約為0.5~1.5μm之厚度。 Next, the conductive layers 72, 74 are formed by electroless plating (Fig. 8(a)). A conductive layer 72 is formed on the protective layer 66 on the upper surface side and the inner wall of the opening 68, and a conductive layer 74 is formed on the insulating layer 60 on the lower surface side and the inner wall of the opening 70. The conductive layers 72, 74 are copper layers formed by, for example, electroless copper plating. The conductive layers 72, 74 are, for example, approximately 0.5 to 1.5 μm thick.
繼而，將上表面側之保護層66剝離而使絕緣層64露出(圖8(b))。例如，使用自動剝膜機將保護層66剝離。或者，作業人員用手將保護層66剝離。形成於保護層66上之導電層72亦與保護層66一起被剝離，但開口68內壁之導電層72不會被剝離。 Then, the protective layer 66 on the upper surface side is peeled off to expose the insulating layer 64 (Fig. 8(b)). For example, the protective layer 66 is peeled off using an automatic stripper. Alternatively, the operator peels off the protective layer 66 by hand. The conductive layer 72 formed on the protective layer 66 is also peeled off together with the protective layer 66, but the conductive layer 72 on the inner wall of the opening 68 is not peeled off.
繼而，於上表面側之絕緣層64上及開口68內壁之導電層72上，利用例如濺鍍技術，形成晶種層76(圖9(a))。於下表面側，由於存在作為晶種層之導電層74，故而不會進而形成晶種層。利用濺鍍技術，可藉由晶種層76而良好地被覆上表面側之細微之段差。晶種層76例如為利用將銅作為靶之濺鍍技術而形成之銅層。晶種層76例如約為0.1~0.5μm之厚度。 Then, on the insulating layer 64 on the upper surface side and on the conductive layer 72 on the inner wall of the opening 68, the seed layer 76 is formed by, for example, a sputtering technique (Fig. 9(a)). On the lower surface side, since the conductive layer 74 is present as a seed layer, the seed layer is not formed further. By the sputtering technique, the fineness of the surface side can be favorably covered by the seed layer 76. The seed layer 76 is, for example, a copper layer formed by a sputtering technique using copper as a target. The seed layer 76 is, for example, about 0.1 to 0.5 μm thick.
再者，作為形成晶種層76之方法並不限於上述濺鍍技術。亦可藉由真空蒸鍍或離子電鍍等其他乾式製程形成晶種層76。 Further, the method of forming the seed layer 76 is not limited to the above sputtering technique. The seed layer 76 can also be formed by other dry processes such as vacuum evaporation or ion plating.
繼而，於上表面側及下表面側，分別積層感光性乾膜光阻之光阻層78、80。乾膜光阻層78、80例如約為10~25μm之厚度。 Then, on the upper surface side and the lower surface side, photoresist layers 78 and 80 of photosensitive dry film photoresist are laminated, respectively. The dry film photoresist layers 78, 80 are, for example, about 10 to 25 μm thick.
接著，對光阻層78、80，曝光用以形成第2層佈線層之既定之圖案，其後，進行顯影。藉此，光阻層78、80被圖案化成既定之圖案(圖9(b))。 Next, the photoresist layers 78 and 80 are exposed to form a predetermined pattern of the second wiring layer, and then developed. Thereby, the photoresist layers 78, 80 are patterned into a predetermined pattern (Fig. 9(b)).
其次，藉由電解電鍍，於上表面側及下表面側，形成導電層82、84(圖10(a))。將經圖案化之光阻層78、80作為罩幕，上表面側將晶種層76作為供電層對導電層82進行電解電鍍，下表面側將導電層74作為供電層對導電層84進行電解電鍍。導電層82、84係藉由例如電解鍍銅而形成之銅層。導電層82、84例如約為5~15μm之厚度。 Next, conductive layers 82 and 84 are formed on the upper surface side and the lower surface side by electrolytic plating (Fig. 10(a)). The patterned photoresist layers 78 and 80 are used as a mask, the upper surface side is subjected to electrolytic plating of the conductive layer 82 using the seed layer 76 as a power supply layer, and the lower surface side is used to electrolyze the conductive layer 84 by using the conductive layer 74 as a power supply layer. plating. The conductive layers 82, 84 are copper layers formed by, for example, electrolytic copper plating. The conductive layers 82, 84 are, for example, approximately 5 to 15 μm thick.
下表面側將經粗化之導電層74作為供電層對導電層84進行電解電鍍。由於導電層74被粗化，故而不適合形成細微之圖案之導電層。導電層74之表面粗度Ra例如約為200~400nm。 The lower surface side is subjected to electrolytic plating of the conductive layer 84 using the roughened conductive layer 74 as a power supply layer. Since the conductive layer 74 is roughened, it is not suitable for forming a fine pattern of the conductive layer. The surface roughness Ra of the conductive layer 74 is, for example, about 200 to 400 nm.
另一方面，上表面側由於將藉由濺鍍而形成之晶種層76作為供電層對導電層82進行電解電鍍，故而可形成細微之圖案之導電層82。導電層82之表面粗度Ra例如約為20~60nm。導電層82之表面粗度Ra小於導電層74之表面粗度Ra。 On the other hand, on the upper surface side, the conductive layer 82 is electrolytically plated by using the seed layer 76 formed by sputtering as a power supply layer, so that the conductive layer 82 having a fine pattern can be formed. The surface roughness Ra of the conductive layer 82 is, for example, about 20 to 60 nm. The surface roughness Ra of the conductive layer 82 is smaller than the surface roughness Ra of the conductive layer 74.
其次，將上表面側及下表面側之光阻層78、80剝離(圖10(b))。 Next, the photoresist layers 78 and 80 on the upper surface side and the lower surface side are peeled off (Fig. 10(b)).
繼而，將因光阻層78、80之剝離而露出至絕緣層60、64上之晶種層76、導電層74，藉由例如快速蝕刻(flash etching)而去除(圖11(a))。 Then, the seed layer 76 and the conductive layer 74 exposed to the insulating layers 60 and 64 by the peeling of the photoresist layers 78 and 80 are removed by, for example, flash etching (Fig. 11(a)).
其結果為，藉由上述半加成法，而於核心基板32之上表面側及下表面側分別形成有第2層佈線層86、88(圖11(a))。 As a result, the second layer wiring layers 86 and 88 are formed on the upper surface side and the lower surface side of the core substrate 32 by the above-described semi-additive method (FIG. 11(a)).
上表面側之佈線層86為了連接於半導體晶片28之連接端子(未圖示)而被要求為細微。上表面側之佈線層86中之佈線之寬度例如約為1~10μm。相對於此，下表面側之佈線層88由於連接於其他佈線基板(未圖示)，故而不如上表面側之佈線層86般細微。下表面側之佈線層88中之佈線之寬度例如約為10~40μm。上表面側之佈線層86中之佈線之寬度小於下表面側之佈線層88中之佈線之寬度。 The wiring layer 86 on the upper surface side is required to be fine in order to be connected to a connection terminal (not shown) of the semiconductor wafer 28. The width of the wiring in the wiring layer 86 on the upper surface side is, for example, about 1 to 10 μm. On the other hand, since the wiring layer 88 on the lower surface side is connected to another wiring substrate (not shown), it is not as fine as the wiring layer 86 on the front surface side. The width of the wiring in the wiring layer 88 on the lower surface side is, for example, about 10 to 40 μm. The width of the wiring in the wiring layer 86 on the upper surface side is smaller than the width of the wiring in the wiring layer 88 on the lower surface side.
其次，為了於上表面側及下表面側形成第3層佈線層，而將保護膜56自圖5所示之三層構造之層間絕緣材料58剝離，並將絕緣層54及保護層52暫時貼附於上表面側。絕緣層54例如約為25μm之厚度。又，將絕緣層54及保護層52暫時貼附於下表面側。絕緣層54例如約為30μm之厚度(圖11(b))。即，暫時貼附於核心基板32之上表面側(佈線層86之上表面)之層間絕緣材料58之絕緣層54較暫時貼附於核心基板32之下表面側(佈線層88之下表面)之層間絕緣材料58之絕緣層54更薄。再者，亦可使暫時貼附於核心基板32之上表面側之層間絕緣材料58之絕緣層54之厚度與暫時貼附於核心基板32之下表面側之層間絕緣材料58之絕緣層54之厚度相等(例如約25μm之厚度)。 Next, in order to form the third wiring layer on the upper surface side and the lower surface side, the protective film 56 is peeled off from the interlayer insulating material 58 of the three-layer structure shown in FIG. 5, and the insulating layer 54 and the protective layer 52 are temporarily attached. Attached to the upper surface side. The insulating layer 54 has a thickness of, for example, about 25 μm. Moreover, the insulating layer 54 and the protective layer 52 are temporarily attached to the lower surface side. The insulating layer 54 is, for example, approximately 30 μm thick (Fig. 11 (b)). That is, the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the upper surface side (the upper surface of the wiring layer 86) of the core substrate 32 is temporarily attached to the lower surface side of the core substrate 32 (the lower surface of the wiring layer 88) The insulating layer 54 of the interlayer insulating material 58 is thinner. Further, the thickness of the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the upper surface side of the core substrate 32 may be made to be the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface side of the core substrate 32. The thickness is equal (for example, a thickness of about 25 μm).
接著，若如圖11(b)所示般使用例如真空積層裝置，對核心基板32進行加壓、加熱，則於核心基板32之上表面側之佈線層86上積層有絕緣層90及保護層92，並於下表面側之佈線層88上積層有絕緣層94及保護層96(圖12(b))。 Then, as shown in FIG. 11(b), the core substrate 32 is pressurized and heated by, for example, a vacuum lamination device, and an insulating layer 90 and a protective layer are laminated on the wiring layer 86 on the upper surface side of the core substrate 32. 92, an insulating layer 94 and a protective layer 96 are laminated on the wiring layer 88 on the lower surface side (Fig. 12(b)).
繼而，於上表面側之絕緣層90及保護層92，藉由例如雷射加工，形成到達佈線層86之開口98(圖12(b))。開口98為錐形狀，且其底部例如約為10~30μm之直徑。 Then, the insulating layer 90 and the protective layer 92 on the upper surface side are formed, for example, by laser processing, to form an opening 98 reaching the wiring layer 86 (Fig. 12(b)). The opening 98 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 10 to 30 μm.
同樣地，於下表面側之絕緣層94及保護層96，藉由例如雷射加工，形成到達佈線層88之開口100(圖12(b))。開口100為錐形狀，且其底部例如約為30~50μm之直徑。開口98之底部之直徑小於開口100之底部之直徑。 Similarly, the insulating layer 94 and the protective layer 96 on the lower surface side are formed into the opening 100 of the wiring layer 88 by, for example, laser processing (Fig. 12(b)). The opening 100 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 30 to 50 μm. The diameter of the bottom of the opening 98 is smaller than the diameter of the bottom of the opening 100.
圖12(b)之步驟係對應於圖7(a)之步驟。圖12(b)之步驟之後，重複與自圖7(b)至圖11(a)相同之步驟，而形成第3層佈線層。 The steps of Figure 12(b) correspond to the steps of Figure 7(a). After the step of Fig. 12 (b), the same steps as in Fig. 7 (b) to Fig. 11 (a) are repeated to form a third wiring layer.
之後，重複上述步驟，並根據需要，藉由上述半加成法，形成第4層、第5層、…之佈線層。 Thereafter, the above steps are repeated, and if necessary, the wiring layers of the fourth layer, the fifth layer, ... are formed by the above-described semi-additive method.
以此方式，可不大幅變更對基板之兩面同時形成佈線層之製程，而於佈線基板之搭載有半導體晶片之側之面、及連接於其他佈線基板之側之面，形成細微度不同之佈線層。所謂細微度不同，係指例如形成於佈線基板之搭載有半導體晶片之側之佈線層中之佈線之寬度、與形成於佈線基板之連接於其他佈線基板之側之佈線層中之佈線之寬度不同。 In this way, the process of forming the wiring layer on both sides of the substrate can be largely changed, and the wiring layer having different fineness can be formed on the surface on the side where the semiconductor wafer is mounted on the wiring substrate and on the side connected to the other wiring substrate. . The difference in the degree of the difference is, for example, the width of the wiring formed in the wiring layer on the side where the semiconductor wafer is mounted on the wiring substrate, and the width of the wiring formed in the wiring layer on the side of the wiring substrate connected to the other wiring substrate. .
使用圖13至圖20對第2實施形態之佈線基板之製造方法進行說明。圖13係表示於第2實施形態之佈線基板之製造方法中使用之層間絕緣材料之圖。圖14至圖20係表示第2實施形態之佈線基 板之製造方法之步驟剖面圖。 A method of manufacturing the wiring board of the second embodiment will be described with reference to Figs. 13 to 20 . Fig. 13 is a view showing an interlayer insulating material used in the method of manufacturing a wiring board of the second embodiment. 14 to 20 show the wiring base of the second embodiment. A cross-sectional view of the steps of the method of manufacturing the board.
於本實施形態中，與第1實施形態同樣地，於上側之面及下側之面，製造佈線層之細微度不同之佈線基板。 In the present embodiment, as in the first embodiment, a wiring board having different wiring layers is manufactured on the upper surface and the lower surface.
首先，與第1實施形態同樣地，依次執行圖2(a)至圖4(c)之步驟，而於核心基板32之上表面及下表面，形成被圖案化成既定之形狀之導電層34、36、40、46。 First, in the same manner as in the first embodiment, the steps of FIGS. 2(a) to 4(c) are sequentially performed, and a conductive layer 34 patterned into a predetermined shape is formed on the upper surface and the lower surface of the core substrate 32, 36, 40, 46.
經圖案化之導電層34、40、46中之位於核心基板32之上表面側之部分成為直接連接於核心基板32之貫通電極43的上表面側之最下層之佈線層50。 A portion of the patterned conductive layers 34, 40, 46 located on the upper surface side of the core substrate 32 is a wiring layer 50 which is directly connected to the lowermost layer on the upper surface side of the through electrode 43 of the core substrate 32.
經圖案化之導電層36、40、46中之位於核心基板32之下表面側之部分成為直接連接於核心基板32之貫通電極43的下表面側之最下層之佈線層51。 A portion of the patterned conductive layers 36, 40, 46 located on the lower surface side of the core substrate 32 is a wiring layer 51 which is directly connected to the lowermost layer on the lower surface side of the through electrode 43 of the core substrate 32.
其次，如圖13所示般，準備於保護層102積層有轉印銅層104、絕緣層106及保護膜108之四層構造之附轉印銅層之層間絕緣材料110。附轉印銅層之層間絕緣材料110被捲於輥111而被提供。 Next, as shown in FIG. 13, an interlayer insulating material 110 having a transfer copper layer of a four-layer structure of a transfer copper layer 104, an insulating layer 106, and a protective film 108 is laminated on the protective layer 102. An interlayer insulating material 110 with a transfer copper layer is wound around the roller 111 to be provided.
保護層102為例如PET(聚對苯二甲酸乙二酯：Polyethylene terephthalate)。絕緣層106為例如ABF(Ajinomoto Build-Up Film)。保護膜108為例如OPP(延伸聚丙烯：oriented polypropylene)。 The protective layer 102 is, for example, PET (polyethylene terephthalate). The insulating layer 106 is, for example, ABF (Ajinomoto Build-Up Film). The protective film 108 is, for example, OPP (oriented polypropylene).
保護層102例如約為30~40μm之厚度。轉印銅層104例如約為0.5~1.5μm之厚度。絕緣層106例如約為20~50μm之厚度。保護膜108例如約為10~20μm之厚度。 The protective layer 102 is, for example, about 30 to 40 μm thick. The transfer copper layer 104 is, for example, about 0.5 to 1.5 μm thick. The insulating layer 106 is, for example, approximately 20 to 50 μm thick. The protective film 108 is, for example, about 10 to 20 μm thick.
又，如圖5所示般，準備於保護層52積層有絕緣層 54及保護膜56之三層構造之層間絕緣材料58。層間絕緣材料58被捲於輥59而被提供。 Moreover, as shown in FIG. 5, an insulating layer is formed on the protective layer 52. An interlayer insulating material 58 of a three-layer structure of 54 and a protective film 56. The interlayer insulating material 58 is wound around the roller 59 to be provided.
其次，如圖5所示般，將保護膜56自三層構造之層間絕緣材料58剝離，並將絕緣層54及保護層52暫時貼附於核心基板32之下表面(圖14(a))。絕緣層54例如約為50μm之厚度。 Next, as shown in FIG. 5, the protective film 56 is peeled off from the interlayer insulating material 58 of the three-layer structure, and the insulating layer 54 and the protective layer 52 are temporarily attached to the lower surface of the core substrate 32 (FIG. 14(a)). . The insulating layer 54 is, for example, about 50 μm thick.
又，如圖13所示般，將保護膜108自四層構造之層間絕緣材料110剝離，並將絕緣層106、轉印銅層104及保護層102暫時貼附於核心基板32之上表面(圖14(a))。絕緣層106例如約為40μm之厚度。即，暫時貼附於核心基板32之上表面之層間絕緣材料110之絕緣層106較暫時貼附於核心基板32之下表面之層間絕緣材料58之絕緣層54更薄。再者，亦可使暫時貼附於核心基板32之上表面之層間絕緣材料110之絕緣層106之厚度與暫時貼附於核心基板32之下表面之層間絕緣材料58之絕緣層54之厚度相等(例如約30μm之厚度)。 Further, as shown in FIG. 13, the protective film 108 is peeled off from the interlayer insulating material 110 having a four-layer structure, and the insulating layer 106, the transferred copper layer 104, and the protective layer 102 are temporarily attached to the upper surface of the core substrate 32 ( Figure 14 (a)). The insulating layer 106 is, for example, about 40 μm thick. That is, the insulating layer 106 of the interlayer insulating material 110 temporarily attached to the upper surface of the core substrate 32 is thinner than the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface of the core substrate 32. Furthermore, the thickness of the insulating layer 106 of the interlayer insulating material 110 temporarily attached to the upper surface of the core substrate 32 may be equal to the thickness of the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface of the core substrate 32. (for example, a thickness of about 30 μm).
再者，絕緣層54及保護層52向核心基板32之下表面之暫時貼附、以及絕緣層106、轉印銅層104及保護層102向核心基板32之上表面之暫時貼附既可逐面地進行，亦可兩面同時進行。 Moreover, the temporary attachment of the insulating layer 54 and the protective layer 52 to the lower surface of the core substrate 32, and the temporary attachment of the insulating layer 106, the transfer copper layer 104, and the protective layer 102 to the upper surface of the core substrate 32 may be performed. It can be carried out on the surface or on both sides.
接著，若如圖14(a)所示般使用例如真空積層裝置，對核心基板32進行加壓、加熱，則於核心基板32之上表面側之佈線層50上積層有絕緣層116、轉印銅層118及保護層120，並於下表面側之佈線層51上積層有絕緣層112及保護層114(圖14(b))。 Then, when the core substrate 32 is pressurized and heated by using, for example, a vacuum laminating apparatus as shown in FIG. 14(a), an insulating layer 116 is deposited on the wiring layer 50 on the upper surface side of the core substrate 32, and transfer is performed. The copper layer 118 and the protective layer 120 are laminated with an insulating layer 112 and a protective layer 114 on the wiring layer 51 on the lower surface side (FIG. 14(b)).
繼而，於上表面側之絕緣層116、轉印銅層118及保護層120，藉由例如雷射加工，形成到達佈線層50之開口122(圖 15(a))。開口122為錐形狀，且其底部例如約為30~50μm之直徑。 Then, on the upper surface side of the insulating layer 116, the transfer copper layer 118 and the protective layer 120, an opening 122 reaching the wiring layer 50 is formed by, for example, laser processing (Fig. 15(a)). The opening 122 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 30 to 50 μm.
若如此自保護膜120上藉由雷射加工於保護膜120、轉印銅層118及絕緣層116形成開口122，則與於將保護膜120剝離之後藉由雷射加工於轉印銅層118及絕緣層116形成開口122之情況相比，可形成較小直徑之開口122。 If the opening 122 is formed on the protective film 120 by the laser processing on the protective film 120, the transfer copper layer 118, and the insulating layer 116, the transfer of the protective film 120 is performed by laser processing on the transfer copper layer 118. As compared to the case where the insulating layer 116 forms the opening 122, the opening 122 of a smaller diameter can be formed.
同樣地，於下表面側之絕緣層112及保護層114，藉由例如雷射加工，形成到達佈線層51之開口124(圖15(a))。開口124為錐形狀，且其底部例如約為30~50μm之直徑。開口122之底部之直徑小於開口124之底部之直徑。 Similarly, the insulating layer 112 and the protective layer 114 on the lower surface side are formed into the opening 124 of the wiring layer 51 by, for example, laser processing (Fig. 15 (a)). The opening 124 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 30 to 50 μm. The diameter of the bottom of the opening 122 is smaller than the diameter of the bottom of the opening 124.
若如此自保護膜112上藉由雷射加工於保護膜114及絕緣層113形成開口124，則與於將保護膜112剝離之後藉由雷射加工於絕緣層113形成開口124之情況相比，可形成較小直徑之開口124。 If the opening 124 is formed by the laser processing on the protective film 114 and the insulating layer 113 from the protective film 112, the opening 124 is formed by the laser processing on the insulating layer 113 after the protective film 112 is peeled off. An opening 124 of smaller diameter can be formed.
其次，將下表面側之保護層114剝離(圖15(b))。使用例如自動剝膜機將保護層114剝離。或者，作業人員用手將保護層114剝離。 Next, the protective layer 114 on the lower surface side is peeled off (Fig. 15 (b)). The protective layer 114 is peeled off using, for example, an automatic stripper. Alternatively, the operator peels off the protective layer 114 by hand.
接著，進行除膠渣處理。作為除膠渣處理，可進行如上所述之濕式除膠渣處理或者乾式除膠渣處理。 Next, a desmear treatment is performed. As the desmear treatment, wet desmear treatment or dry desmear treatment as described above can be performed.
藉此，將因雷射加工而產生之膠渣(樹脂殘渣)去除，並且對下表面側之絕緣層112之表面、及開口124之內壁進行粗化。又，對上表面側之開口122之內壁進行粗化。上表面側之絕緣層116之表面由於被轉印銅層118及保護層120所覆蓋，故而不會被粗化。 Thereby, the slag (resin residue) generated by the laser processing is removed, and the surface of the insulating layer 112 on the lower surface side and the inner wall of the opening 124 are roughened. Further, the inner wall of the opening 122 on the upper surface side is roughened. The surface of the insulating layer 116 on the upper surface side is covered by the transferred copper layer 118 and the protective layer 120, so that it is not roughened.
再者，於上述實施形態中，於上表面側之絕緣層116、 轉印銅層118及保護層120形成開口122，並於下表面側之絕緣層112及保護層114形成開口124，之後將下表面側之保護層114剝離。 Furthermore, in the above embodiment, the insulating layer 116 on the upper surface side, The transfer copper layer 118 and the protective layer 120 form the opening 122, and the opening 124 is formed on the insulating layer 112 and the protective layer 114 on the lower surface side, and then the protective layer 114 on the lower surface side is peeled off.
然而，亦可於將下表面側之保護層114剝離之後，於上表面側之絕緣層116、轉印銅層118及保護層120形成開口122，並於下表面側之絕緣層112形成開口124。 However, after the protective layer 114 on the lower surface side is peeled off, the opening 122 is formed on the insulating layer 116 on the upper surface side, the transfer copper layer 118 and the protective layer 120, and the opening 124 is formed in the insulating layer 112 on the lower surface side. .
其次，藉由無電解電鍍形成導電層126、128(圖16(a))。於上表面側之保護層120上及開口122內壁形成導電層126，於下表面側之絕緣層112上及開口124內壁形成導電層128。導電層126、128係藉由例如無電解鍍銅而形成之銅層。導電層126、128例如約為0.5~1.5μm之厚度。 Next, the conductive layers 126, 128 are formed by electroless plating (Fig. 16 (a)). A conductive layer 126 is formed on the protective layer 120 on the upper surface side and the inner wall of the opening 122, and a conductive layer 128 is formed on the insulating layer 112 on the lower surface side and the inner wall of the opening 124. The conductive layers 126, 128 are copper layers formed by, for example, electroless copper plating. The conductive layers 126, 128 are, for example, approximately 0.5 to 1.5 μm thick.
繼而，將上表面側之保護層120剝離而使轉印銅層118露出(圖16(b))。例如，使用自動剝膜機將保護層120剝離。或者，作業人員用手將保護層120剝離。 Then, the protective layer 120 on the upper surface side is peeled off to expose the transfer copper layer 118 (FIG. 16(b)). For example, the protective layer 120 is peeled off using an automatic stripper. Alternatively, the operator peels off the protective layer 120 by hand.
形成於保護層120上及作為保護層120之側面之開口122內壁之導電層126亦與保護層120一起被剝離，但形成於作為絕緣層116之側面之開口122內壁之導電層126不會被剝離。其結果為，於上表面側，殘存轉印銅層118、及形成於開口122內壁之導電層126(圖16(b))。 The conductive layer 126 formed on the protective layer 120 and the inner wall of the opening 122 as the side surface of the protective layer 120 is also peeled off together with the protective layer 120, but the conductive layer 126 formed on the inner wall of the opening 122 as the side of the insulating layer 116 is not Will be stripped. As a result, on the upper surface side, the transfer copper layer 118 and the conductive layer 126 formed on the inner wall of the opening 122 remain (FIG. 16(b)).
其次，於上表面側及下表面側，分別積層感光性乾膜光阻之光阻層129、130。光阻層129、130例如約為10~25μm之厚度。 Next, photosensitive resistive photoresist layers 129 and 130 are laminated on the upper surface side and the lower surface side, respectively. The photoresist layers 129 and 130 have a thickness of, for example, about 10 to 25 μm.
接著，對光阻層129、130曝光用以形成第2層佈線層之既定之圖案，其後，進行顯影。藉此，光阻層129、130被圖 案化成既定之圖案(圖17(a))。 Next, the photoresist layers 129 and 130 are exposed to form a predetermined pattern for forming the second wiring layer, and then developed. Thereby, the photoresist layers 129, 130 are patterned The case is turned into an established pattern (Fig. 17(a)).
繼而，藉由電解電鍍，於上表面側及下表面側，形成導電層132、134(圖17(b))。將經圖案化之光阻層129、130作為罩幕，上表面側將轉印銅層118及導電層126作為供電層對導電層132進行電解電鍍，下表面側將導電層128作為供電層對導電層134進行電解電鍍。導電層132、134係藉由例如電解鍍銅而形成之銅層。導電層132、134例如約為5~15μm之厚度。 Then, conductive layers 132 and 134 are formed on the upper surface side and the lower surface side by electrolytic plating (Fig. 17 (b)). The patterned photoresist layers 129 and 130 are used as a mask, and the conductive layer 132 is electrolytically plated by using the transfer copper layer 118 and the conductive layer 126 as a power supply layer on the upper surface side, and the conductive layer 128 is used as a power supply layer on the lower surface side. The conductive layer 134 is subjected to electrolytic plating. The conductive layers 132, 134 are copper layers formed by, for example, electrolytic copper plating. The conductive layers 132, 134 are, for example, approximately 5 to 15 μm thick.
下表面側將經粗化之導電層128作為供電層對導電層134進行電解電鍍。由於導電層128被粗化，故而不適合形成細微之圖案之導電層。導電層128之表面粗度Ra例如約為200~400nm。 The lower surface side is subjected to electrolytic plating of the conductive layer 134 using the roughened conductive layer 128 as a power supply layer. Since the conductive layer 128 is roughened, it is not suitable for forming a fine pattern of the conductive layer. The surface roughness Ra of the conductive layer 128 is, for example, about 200 to 400 nm.
另一方面，上表面側將轉印銅層118作為供電層對導電層132進行電解電鍍。由於轉印銅層118係作為四層構造之層間絕緣材料110而被提供，故而可形成細微之圖案之導電層132。導電層132之表面粗度Ra例如約為20~60nm。導電層132之表面粗度Ra小於導電層134之表面粗度Ra。 On the other hand, the upper surface side is subjected to electrolytic plating of the conductive layer 132 using the transfer copper layer 118 as a power supply layer. Since the transfer copper layer 118 is provided as the interlayer insulating material 110 of a four-layer structure, the conductive layer 132 of a fine pattern can be formed. The surface roughness Ra of the conductive layer 132 is, for example, about 20 to 60 nm. The surface roughness Ra of the conductive layer 132 is smaller than the surface roughness Ra of the conductive layer 134.
其次，將上表面側及下表面側之光阻層129、130剝離(圖18(a))。 Next, the photoresist layers 129 and 130 on the upper surface side and the lower surface side are peeled off (Fig. 18 (a)).
繼而，將因光阻層129、130之剝離而露出至絕緣層116、112上之轉印銅層118、導電層128藉由例如快速蝕刻而去除(圖18(b))。 Then, the transfer copper layer 118 exposed to the insulating layers 116, 112 by the peeling of the photoresist layers 129, 130, and the conductive layer 128 are removed by, for example, rapid etching (Fig. 18 (b)).
其結果為，藉由上述半加成法，於核心基板32之上表面側及下表面側分別形成第2層佈線層136、138(圖18(b))。上表面側之佈線層136為了連接於半導體晶片28之連接端子(未圖示) 而被要求為細微。上表面側之佈線層136中之佈線之寬度例如約為1~10μm。相對於此，下表面側之佈線層138由於連接於其他佈線基板(未圖示)，故而不如上表面側之佈線層136般細微。下表面側之佈線層138中之佈線之寬度例如約為10~40μm。上表面側之佈線層136中之佈線之寬度小於下表面側之佈線層138中之佈線之寬度。 As a result, the second layer wiring layers 136 and 138 are formed on the upper surface side and the lower surface side of the core substrate 32 by the above-described semi-additive method (Fig. 18(b)). The wiring layer 136 on the upper surface side is connected to a connection terminal (not shown) of the semiconductor wafer 28 It was asked to be subtle. The width of the wiring in the wiring layer 136 on the upper surface side is, for example, about 1 to 10 μm. On the other hand, since the wiring layer 138 on the lower surface side is connected to another wiring substrate (not shown), it is not as fine as the wiring layer 136 on the front surface side. The width of the wiring in the wiring layer 138 on the lower surface side is, for example, about 10 to 40 μm. The width of the wiring in the wiring layer 136 on the upper surface side is smaller than the width of the wiring in the wiring layer 138 on the lower surface side.
其次，為了於上表面側及下表面側形成第3層佈線層，如圖5所示般，將保護膜56自三層構造之層間絕緣材料58剝離，並將絕緣層54及保護層52暫時貼附於核心基板32之下表面側(圖19(a))。絕緣層54例如約為30μm之厚度。 Next, in order to form the third wiring layer on the upper surface side and the lower surface side, as shown in FIG. 5, the protective film 56 is peeled off from the interlayer insulating material 58 of the three-layer structure, and the insulating layer 54 and the protective layer 52 are temporarily It is attached to the lower surface side of the core substrate 32 (Fig. 19 (a)). The insulating layer 54 is, for example, about 30 μm thick.
又，如圖13所示般，將保護膜108自四層構造之層間絕緣材料110剝離，並將絕緣層106、轉印銅層104及保護層102暫時貼附於核心基板32之上表面側(圖19(a))。絕緣層106例如約為25μm之厚度。即，暫時貼附於核心基板32之上表面側之層間絕緣材料110之絕緣層106較暫時貼附於核心基板32之下表面側之層間絕緣材料58之絕緣層54更薄。再者，亦可使暫時貼附於核心基板32之上表面側之層間絕緣材料110之絕緣層106之厚度與暫時貼附於核心基板32之下表面側之層間絕緣材料58之絕緣層54之厚度相等(例如約25μm之厚度)。 Further, as shown in FIG. 13, the protective film 108 is peeled off from the interlayer insulating material 110 having a four-layer structure, and the insulating layer 106, the transfer copper layer 104, and the protective layer 102 are temporarily attached to the upper surface side of the core substrate 32. (Fig. 19(a)). The insulating layer 106 is, for example, about 25 μm thick. That is, the insulating layer 106 of the interlayer insulating material 110 temporarily attached to the upper surface side of the core substrate 32 is thinner than the insulating layer 54 of the interlayer insulating material 58 temporarily attached to the lower surface side of the core substrate 32. Further, the thickness of the insulating layer 106 temporarily attached to the interlayer insulating material 110 on the upper surface side of the core substrate 32 and the insulating layer 54 temporarily attached to the interlayer insulating material 58 on the lower surface side of the core substrate 32 may be used. The thickness is equal (for example, a thickness of about 25 μm).
接著，若如圖19(a)所示般使用例如真空積層裝置，對核心基板32進行加壓、加熱，則於核心基板32之上表面側之佈線層136上積層有絕緣層144、轉印銅層146及保護層148，並於下表面側之佈線層138上積層有絕緣層140及保護層142(圖19(b))。 Then, when the core substrate 32 is pressurized and heated by using, for example, a vacuum laminating apparatus as shown in FIG. 19(a), an insulating layer 144 is deposited on the wiring layer 136 on the upper surface side of the core substrate 32, and transfer is performed. The copper layer 146 and the protective layer 148 are laminated with an insulating layer 140 and a protective layer 142 on the wiring layer 138 on the lower surface side (Fig. 19(b)).
繼而，於上表面側之絕緣層144、轉印銅層146及保 護層148，藉由例如雷射加工，形成到達佈線層136之開口150(圖20)。開口150為錐形狀，且其底部為例如約10~30μm之直徑。同樣地，於下表面側之絕緣層140及保護層142，藉由例如雷射加工，形成到達佈線層138之開口152(圖20)。開口152為錐形狀，且其底部例如約為30~50μm之直徑。開口150之底部之直徑小於開口152之底部之直徑。 Then, the insulating layer 144 on the upper surface side, the transfer copper layer 146, and the protection The cover layer 148 is formed to reach the opening 150 of the wiring layer 136 by, for example, laser processing (Fig. 20). The opening 150 has a tapered shape, and the bottom thereof has a diameter of, for example, about 10 to 30 μm. Similarly, the insulating layer 140 and the protective layer 142 on the lower surface side are formed into openings 152 (FIG. 20) that reach the wiring layer 138 by, for example, laser processing. The opening 152 has a tapered shape, and the bottom portion thereof has a diameter of, for example, about 30 to 50 μm. The diameter of the bottom of the opening 150 is smaller than the diameter of the bottom of the opening 152.
圖20之步驟係對應於圖15(a)之步驟。 The steps of Figure 20 correspond to the steps of Figure 15(a).
之後，重複上述步驟，並根據需要，藉由上述半加成法，形成第4層、第5層、…之佈線層。 Thereafter, the above steps are repeated, and if necessary, the wiring layers of the fourth layer, the fifth layer, ... are formed by the above-described semi-additive method.
以此方式，可不大幅變更對基板之兩面同時形成佈線層之製程，而於佈線基板之搭載有半導體晶片之側之面、及連接於其他佈線基板之側之面，形成細微度不同之佈線層。所謂細微度不同，係指例如形成於佈線基板之搭載有半導體晶片之側之佈線層中之佈線之寬度、與形成於佈線基板之連接於其他佈線基板之側之佈線層中之佈線之寬度不同。 In this way, the process of forming the wiring layer on both sides of the substrate can be largely changed, and the wiring layer having different fineness can be formed on the surface on the side where the semiconductor wafer is mounted on the wiring substrate and on the side connected to the other wiring substrate. . The difference in the degree of the difference is, for example, the width of the wiring formed in the wiring layer on the side where the semiconductor wafer is mounted on the wiring substrate, and the width of the wiring formed in the wiring layer on the side of the wiring substrate connected to the other wiring substrate. .
上述實施形態為一例，可根據需要進行各種變形。例如，於上述實施形態中係藉由半加成法形成佈線層，但亦可藉由全加成法、或減成法形成佈線層。 The above embodiment is an example, and various modifications can be made as needed. For example, in the above embodiment, the wiring layer is formed by a semi-additive method, but the wiring layer may be formed by a full addition method or a subtractive method.
又，作為佈線基板，亦可為於重疊堆積有在兩面具有圖案之兩面基板、絕緣層及佈線層之多層佈線基板、半導體晶片以及電路基板之間進行中繼之中介層(interposer)等所有種類之佈線基板。 In addition, as the wiring board, an interposer in which a double-sided wiring board having a pattern on both sides, a multilayer wiring board having an insulating layer and a wiring layer, and an interposer for relaying between the semiconductor wafer and the circuit board are stacked may be stacked. The wiring substrate.
又，作為佈線基板，不限於使用包含樹脂之絕緣層或核心基板之增層基板，亦可為其他態樣之各種佈線基板。 Further, the wiring substrate is not limited to a build-up substrate using an insulating layer or a core substrate containing a resin, and may be various wiring substrates of other aspects.
又，上述實施形態係將佈線基板經由焊料凸塊而與母板等其他基板連接，但作為將佈線基板連接於母板等其他基板之方法，亦可為接腳接觸、或打線接合等其他方法。 Further, in the above-described embodiment, the wiring board is connected to another board such as a mother board via a solder bump. However, as a method of connecting the wiring board to another board such as a mother board, other methods such as pin contact or wire bonding may be used. .
以上，對較佳之實施形態進行了詳細敍述，但並非限定於該等特定之實施形態，可於申請專利範圍所記載之主旨之範圍內，進行各種變形或變更。 The preferred embodiments are described in detail above, but are not limited to the specific embodiments, and various modifications and changes can be made without departing from the scope of the invention.
32‧‧‧核心基板 32‧‧‧ core substrate
34、36‧‧‧導電層 34, 36‧‧‧ conductive layer
40‧‧‧導電層 40‧‧‧ Conductive layer
42‧‧‧樹脂 42‧‧‧Resin
46‧‧‧導電層 46‧‧‧ Conductive layer
50、51‧‧‧佈線層 50, 51‧‧‧ wiring layer
60‧‧‧絕緣層 60‧‧‧Insulation
64‧‧‧絕緣層 64‧‧‧Insulation
72、74‧‧‧導電層 72, 74‧‧‧ conductive layer
76‧‧‧晶種層 76‧‧‧ seed layer
82、84‧‧‧導電層 82, 84‧‧‧ conductive layer
86、88‧‧‧佈線層 86, 88‧‧‧ wiring layer
90‧‧‧絕緣層 90‧‧‧Insulation
92‧‧‧保護層 92‧‧‧Protective layer
94‧‧‧絕緣層 94‧‧‧Insulation
96‧‧‧保護層 96‧‧‧Protective layer
Claims (12)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013-193882 | 2013-09-19 | ||
| JP2013193882A JP6234132B2 (en) | 2013-09-19 | 2013-09-19 | Wiring board manufacturing method |
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| Publication Number | Publication Date |
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| TW201524299A true TW201524299A (en) | 2015-06-16 |
| TWI635790B TWI635790B (en) | 2018-09-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW103132035A TWI635790B (en) | 2013-09-19 | 2014-09-17 | Manufacturing method of wiring substrate |
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| Country | Link |
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| JP (1) | JP6234132B2 (en) |
| KR (1) | KR102054198B1 (en) |
| TW (1) | TWI635790B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI771534B (en) * | 2017-12-08 | 2022-07-21 | 日商新光電氣工業股份有限公司 | Wiring board and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3299243B2 (en) | 1996-12-19 | 2002-07-08 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
| JP2002241440A (en) * | 2001-02-19 | 2002-08-28 | Toppan Printing Co Ltd | Alkaline soluble polymer and photosensitive resin composition |
| JP2004055618A (en) * | 2002-07-16 | 2004-02-19 | Kanegafuchi Chem Ind Co Ltd | Process for producing multilayer printed wiring board |
| JP4328196B2 (en) | 2003-12-24 | 2009-09-09 | 京セラ株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRIC DEVICE |
| JP2006108165A (en) * | 2004-09-30 | 2006-04-20 | Sumitomo Bakelite Co Ltd | Resin constituent, laminated body, wiring board, and wiring board manufacturing method |
| JP2008218540A (en) | 2007-03-01 | 2008-09-18 | Matsushita Electric Ind Co Ltd | Manufacturing method for wiring board |
| US20100230142A1 (en) * | 2007-10-23 | 2010-09-16 | Ube Industries, Ltd. | Method for manufacturing printed wiring board |
| CN101836511B (en) * | 2007-10-26 | 2013-04-03 | 纳幕尔杜邦公司 | Asymmetric dielectric films |
| JP5322531B2 (en) | 2008-05-27 | 2013-10-23 | 新光電気工業株式会社 | Wiring board manufacturing method |
| JP5231340B2 (en) * | 2009-06-11 | 2013-07-10 | 新光電気工業株式会社 | Wiring board manufacturing method |
| JP5539150B2 (en) * | 2010-10-25 | 2014-07-02 | 矢崎総業株式会社 | Wiring board manufacturing method |
| JP2013172137A (en) * | 2012-02-23 | 2013-09-02 | Kyocer Slc Technologies Corp | Wiring board and probe card using the same |
| JP5479551B2 (en) * | 2012-09-14 | 2014-04-23 | 新光電気工業株式会社 | Wiring board manufacturing method |
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2013
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| TWI771534B (en) * | 2017-12-08 | 2022-07-21 | 日商新光電氣工業股份有限公司 | Wiring board and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6234132B2 (en) | 2017-11-22 |
| TWI635790B (en) | 2018-09-11 |
| JP2015060960A (en) | 2015-03-30 |
| KR20150032629A (en) | 2015-03-27 |
| KR102054198B1 (en) | 2019-12-11 |
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