TW201448139A - 嵌埋式基板封裝構造及其製造方法 - Google Patents
嵌埋式基板封裝構造及其製造方法 Download PDFInfo
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Abstract
主要揭示一種嵌埋式基板封裝構造,以介電填充膠中之晶片為中心,上下各包含第一線路層、第二線路層、第一介電層與第二介電層。並且,導通孔貫穿介電填充膠,以縱向導通第一線路層與第二線路層。晶片之主動面設有銲墊,晶片之背面形成有晶粒貼附材料層,第一線路層局部嵌陷於晶粒貼附材料層中。在第一線路層上之介電填充膠嵌埋覆蓋晶片之側面並顯露主動面在同一平面。第二線路層形成於該平面上,局部貼附於主動面而連接至銲墊。第一介電層覆蓋第一線路層。第二介電層覆蓋第二線路層。藉以降低封裝厚度至無嵌埋凸塊之基板厚度與防止超薄化封裝構造之翹曲。
Description
本發明係有關於半導體封裝構造,特別係有關於一種嵌埋式基板封裝構造及其製造方法。
在今日的電子裝置中無不希望可以更小與更薄,半導體封裝構造亦然。尺寸的縮小將使半導體封裝構造內元件與線路變成更為密集,但材料間的熱膨脹係數不匹配,在更薄的封裝厚度中將更容易產生明顯的翹曲變形。特別是應用於微間距球閘陣列封裝構造(fine pitch BGA package)或需要往上堆疊其它半導體封裝構造以成為堆疊式封裝層疊結構(package-on-package,POP)時,對於翹曲變形的容許度將更為敏感,故在縮小封裝尺寸時,如何避免翹曲變形甚為重要。
本國發明專利I335652號「堆疊式封裝模組」揭示一種封裝結構,包含嵌埋有晶片之電路板,晶片容置於電路板之板材中空通孔,電路板具有複數外露之電性連接端、上表面之複數連接墊。晶片之電極墊係經由電路板中之導電盲孔與線路層電性連接至電性連接端及連接墊。電路板之上下表面各增設有上下兩增層結構,考慮到增層結構內線路層之間之導通柱以及增層結構內線路層至晶片電極墊之導通柱等凸塊厚度,使得該封裝結構之厚度將大
於該電路板之厚度。並且,其製造方法是先將電路板開設出中空通孔,再將晶片嵌入至電路板中,電路板本身對於晶片缺乏固定效果,尚須在中空通孔填入側向的填充黏膠。然而,事實上要在極微小的間隙內填入填充黏膠有相當的難度,其或上或下的溢膠現象都會影響增層結構內線路層的形成平坦度。而電路板本身又具有導電盲孔、線路層、電性連接端及連接墊,強行平坦化研磨容易破壞到電路板之內部線路結構。
為了解決上述之問題,本發明之主要目的係在於提供一種嵌埋式基板封裝構造及其製造方法,藉以降低封裝厚度至無嵌埋凸塊之基板厚度與防止超薄化封裝構造之翹曲。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種嵌埋式基板封裝構造,其係以在一介電填充膠中之一晶片為中心,上下各包含以下元件:一第一線路層、一第二線路層、一第一介電層與一第二介電層。該嵌埋式基板封裝構造係更包含複數個第一導通孔,係貫穿該介電填充膠,以縱向導通該第一線路層與該第二線路層。該晶片係設置於該第一線路層上,該晶片係具有一主動面與一背面,其中該主動面係設有複數個銲墊,該背面係形成有一晶粒貼附材料層,該第一線路層係局部嵌陷於該晶粒貼附材料層中。該介電填充膠係形成於該第一線路層上,以嵌埋覆蓋該晶片之複數個側面而顯露該主動面在同一平面。該第二線路層係形成於由該介電填充膠與該晶片構成之平面上,該第二線路層係局部貼附於該主動面而連接至該些銲墊。該第一介電層係覆蓋該第一線路層。該第二介電層係覆蓋該第二線路層。
本發明更揭示上述嵌埋式基板封裝構造之一製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述之嵌埋式基板封裝構造中,可另包含有複數個第一導電墊與第二導電墊,該些第一導電墊係設置於該第一線路層上且顯露於該第一介電層之外,該些第二導電墊係設置於該第二線路層上且顯露於該第二介電層之外。
在前述之嵌埋式基板封裝構造中,該第一線路層係可包含一散熱平墊,係對準於該晶片之下方並連接至該些第一導電墊之其中之一,故被連接之第一導電墊可用以導熱下方印刷電路板內例如導熱孔(thermal via)之導熱機構,以增強該嵌埋式基板封裝構造之散熱分佈能力,並且由該散熱平墊相對遠離該晶片之主動面,可達到該嵌埋式基板封裝構造之熱應力平衡。
在前述之嵌埋式基板封裝構造中,該些第二導電墊係可位於該晶片之該主動面之上方。
在前述之嵌埋式基板封裝構造中,該些第二導電墊係可對準於該些第一導通孔。
前述之嵌埋式基板封裝構造係可作為一球閘陣列封裝構造之封裝基板。
在前述之嵌埋式基板封裝構造中,可另包含一第二晶片,係設置於該第一介電層或該第二介電層上。
在前述之嵌埋式基板封裝構造中,可另包含有:一第三線路層,係形成於該第一介電層上;一第四線路層,係形成於該第二介電層上;以及複數個第二導通孔,縱向導通各線路層。
10‧‧‧暫時性載板
11‧‧‧黏著層
20‧‧‧第一金屬箔片
30‧‧‧第二金屬箔片
100‧‧‧嵌埋式基板封裝構造
110‧‧‧第一線路層
111‧‧‧散熱平墊
120‧‧‧晶片
121‧‧‧主動面
122‧‧‧背面
123‧‧‧銲墊
124‧‧‧晶粒貼附材料層
125‧‧‧側面
130‧‧‧介電填充膠
131‧‧‧平面
140‧‧‧第二線路層
150‧‧‧第一導通孔
161‧‧‧第一介電層
162‧‧‧第二介電層
171‧‧‧第一導電墊
172‧‧‧第二導電墊
180‧‧‧第二晶片
181‧‧‧凸塊
182‧‧‧銲料
183‧‧‧封膠體
184‧‧‧第二銲墊
185‧‧‧銲線
186‧‧‧銲球
200‧‧‧嵌埋式基板封裝構造
252、253‧‧‧第二導通孔
291‧‧‧第三線路層
292‧‧‧第四線路層
293‧‧‧第三介電層
294‧‧‧第四介電層
第1圖:依據本發明之第一具體實施例,一種嵌埋式基板封裝構造之截面示意圖。
第2A圖:依據本發明之第一具體實施例,該嵌埋式基板封裝構造搭載有另一晶片之截面示意圖。
第2B圖:依據本發明之第一具體實施例之一變化例,該嵌埋式基板封裝構造搭載有另一晶片之截面示意圖。
第3A至3H圖:依據本發明之第一具體實施例,該嵌埋式基板封裝構造之製造過程中各步驟之元件局部截面示意圖。
第4圖:依據本發明之第二具體實施例,另一種嵌埋式基板封裝構造之截面示意圖。
第5A至5F圖:依據本發明之第二具體實施例,該嵌埋式基板封裝構造之製造過程中延續第3F圖步驟之後之後製程步驟之元件局部截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例,一種嵌埋式基板封裝構造舉例說明於第1圖之截面示意圖、第2A圖搭載
有一晶片之截面示意圖、第2B圖變化例搭載有另一晶片之截面示意圖,第3A至3H圖則有關於其製造過程中各步驟之元件局部截面示意圖。該嵌埋式基板封裝構造100係以在一介電填充膠130中之一晶片120為中心,上下各包含以下元件:一第一線路層110、一第二線路層140、一第一介電層161與一第二介電層162。該嵌埋式基板封裝構造100係更包含複數個第一導通孔150,係貫穿該介電填充膠130,以縱向導通該第一線路層110與該第二線路層140。
該晶片120係設置於該第一線路層110上,該晶片120係具有一主動面121與一背面122。其中,該晶片120係可為具有積體電路之半導體元件,該主動面121係設有複數個銲墊123,以連接至該晶片120之內部積體電路。該背面122係形成有一晶粒貼附材料層124,該第一線路層110係局部嵌陷於該晶粒貼附材料層124中。
該介電填充膠130係形成於該第一線路層110上,以嵌埋覆蓋該晶片120之複數個側面125而顯露該主動面121在同一平面131。該介電填充膠130係可為一種液態封裝材料,例如包含熱固性或光固性環氧化合物。故以該介電填充膠130與該晶片120作為一基板核心結構。
該第二線路層140係形成於由該介電填充膠130與該晶片120構成之平面131上,該第二線路層140係局部貼附於該主動面121而連接至該些銲墊123。該第一介電層161係覆蓋該第一線路層110。該第二介電層162係覆蓋該第二線路層140。
更具體地,該嵌埋式基板封裝構造100係可另包含有複數個第一導電墊171與第二導電墊172,該些第一導電墊171係設置於該第一線路層110上且顯露於該第一介電層161之外,該些第二導電墊172係設置於該第二
線路層140上且顯露於該第二介電層162之外。較佳地,該第一線路層110係可包含一散熱平墊111,係對準於該晶片120之下方並連接至該些第一導電墊171之其中之一,故被連接之第一導電墊171可用以導熱下方印刷電路板內例如導熱孔(thermal via)之導熱機構,以增強該嵌埋式基板封裝構造100之散熱分佈能力,並且由該散熱平墊111相對遠離該晶片120之主動面121,可達到該嵌埋式基板封裝構造100之熱應力平衡。在一具體型態中,該散熱平墊111之尺寸係可略大於該晶片120之背面122。
因此,本發明第一實施例提供之一種嵌埋式基板封裝構造100係能降低封裝厚度至無嵌埋凸塊之基板厚度,並且由該介電填充膠130與該晶片120構成之一基板核心結構的上下方各有對稱熱膨脹係數與厚度之線路層與介電層,可用於防止該超薄化嵌埋式基板封裝構造100之翹曲。
此外,該嵌埋式基板封裝構造100可作為一封裝基板之使用,而進行再封裝。而該些第二導電墊172之位置係可依上方晶片之型態不同而調整改變。在第一實施例中,該些第二導電墊172係可位於該晶片120之該主動面121之上方。如第2A圖所示,該嵌埋式基板封裝構造100係可另包含一第二晶片180,係設置於該第二介電層162上,或者可設置於該第一介電層161上。當該第二晶片180係為覆晶型態或為具有矽穿孔(TSV)之立體晶粒堆疊型態時,該第二晶片180之下方係設有複數個凸塊181,例如銅柱凸塊,可利用銲料182接合至該些第二導電墊172。另以一封膠體183形成於該第二介電層162上,以密封該第二晶片180或至少密封該些凸塊181。另可利用複數個銲球186接合於該些第一導電墊171。
如第2B圖所示,在第一實施例之變化例中,該些第二導電墊172係可對準於該些第一導通孔150。該嵌埋式基板封裝構造100係可另包含一第二晶片180,係設置於該第二介電層162上,或者可設置於該第一介電層161上。當該第二晶片180係為打線連接之傳統晶片型態時,該第二晶片180朝上(遠離該第二介電層162之方向)之主動面係設有複數個第二銲墊184,可利用例如金線或銅線之銲線184連接該些第二銲墊184至該些第二導電墊172。另以一封膠體183形成於該第二介電層162上,以密封該第二晶片180與該些銲線184。另可利用複數個銲球186接合於該些第一導電墊171。
如第2A圖與第2B圖所示,較佳地,該第二晶
片180係設置於該第二介電層162上時,可提供一在該第一晶片120與該第二晶片180之最短導電路徑,藉以提升該第一晶片120與該第二晶片180間的傳輸速度與訊號品質。
如第3A至3H圖所示,本發明更揭示上述嵌埋式基板封裝構造100之一製造方法。
首先,如第3A圖所示,提供一第一線路層110,該第一線路層110係形成於一暫時性載板10,該暫時性載板10係具有一例如UV黏著膠或低黏度(low tack)之黏著層11,以暫時性黏接該第一線路層110,更具體地運用於晶圓封裝製程時,該暫時性載板10係可為一晶圓承載系統(WSS);該第一線路層110之形成方法係可為物理氣相沉積與圖案化蝕刻製程之組合或是圖案化沉積之舉離製程,亦或是銅箔與圖案化蝕刻製程之組合。之後,如第3B圖所示,以晶粒取放之方式設置一晶片120於該第一線路層110上,該晶片120係具有一主動面121與一背面122,其中
該主動面121係設有複數個銲墊123,該背面122係形成有一晶粒貼附材料層124,該第一線路層110係局部嵌陷於該晶粒貼附材料層124中。之後,如第3C圖所示,以印刷或是平板模封等方法形成一介電填充膠130於該第一線路層110上,以嵌埋覆蓋該晶片120之複數個側面125而顯露該主動面121在同一平面131。之後,如第3D圖所示,形成一第二線路層140於由該介電填充膠130與該晶片120構成之平面131上,該第二線路層140係局部貼附於該主動面121而連接至該些銲墊123;該第二線路層140之材質、厚度應與該第一線路層110之材質、厚度相同,以使該第二線路層140與該第一線路層110具有相同之熱膨脹特性。第二線路層140之形成方法係可為物理氣相沉積與圖案化蝕刻製程之組合或是光阻圖案化、物理氣相沉積與舉離製程,亦或是無電電鍍、圖案化蝕刻與電鍍加厚之組合。之後,如第3E圖所示,剝離該暫時性載板10,該暫時性載板10係可重覆回收使用。之後,如第3F圖所示,可利用鑽孔與孔內銅電鍍之方式形成複數個第一導通孔150,係貫穿該介電填充膠130,以縱向導通該第一線路層110與該第二線路層140。之後,如第3G圖所示,利用化學氣相沉積或是塗附方式形成一第一介電層161與一第二介電層162,該第一介電層161係覆蓋該第一線路層110,該第二介電層162係覆蓋該第二線路層140,該第二介電層162之材質、形成方法亦應與該第一介電層161之材質、形成方法相同。最後,如第3H圖所示,可利用電鍍方式形成複數個第一導電墊171與第二導電墊172,該些第一導電墊171係設置於該第一線路層110上且顯露於該第一介電層161之外,該些第二導電墊172係設置於該第二線路層140上且顯露於該第二介電層162之外。
依據本發明之第二具體實施例,另一種嵌埋式基板封裝構造舉例說明於第4圖之截面示意圖,第5A至5F圖則有關於其製造過程中延續第3F圖步驟之後之後製程步驟之元件局部截面示意圖。其中與第一實施例相同之元件將沿用相同圖號且不予贅述其細部相同之結構。該嵌埋式基板封裝構造200係以在一介電填充膠130中之一晶片120為中心,上下各包含以下元件:一第一線路層110、一第二線路層140、一第一介電層161與一第二介電層162。該嵌埋式基板封裝構造200係更包含複數個第一導通孔150,係貫穿該介電填充膠130,以縱向導通該第一線路層110與該第二線路層140。
該晶片120係設置於該第一線路層110上,該晶片120係具有一主動面121與一背面122,其中該主動面121係設有複數個銲墊123,該背面122係形成有一晶粒貼附材料層124,該第一線路層110係局部嵌陷於該晶粒貼附材料層124中。該介電填充膠130係形成於該第一線路層110上,以嵌埋覆蓋該晶片120之複數個側面125而顯露該主動面121在同一平面131。該第二線路層140係形成於由該介電填充膠130與該晶片120構成之平面131上,該第二線路層140係局部貼附於該主動面121而連接至該些銲墊123。該第一介電層161係覆蓋該第一線路層110。該第二介電層162係覆蓋該第二線路層140。
在本實施例中,該嵌埋式基板封裝構造200係可另包含有一形成於該第一介電層161上之第三線路層291、一形成於該第二介電層162上之第四線路層292、以及複數個第二導通孔252、253。該些第二導通孔252係貫穿該介電填充膠130、該第一介電層161與該第二介電層162,以縱向導通該第三線路層291與該第四線路層292,
或者另以複數個第二導通孔253僅貫穿該第一介電層161或該第二介電層162,以縱向導通該第三線路層291與該第一線路層110或該第四線路層292與該第二線路層140。
在一較佳型態中,該些第二導通孔252係可更縱向導通該第一線路層110與該第二線路層140。
該嵌埋式基板封裝構造200係可另包含有複數個第一導電墊171與第二導電墊172,該些第一導電墊171係設置於該第三線路層291上且顯露於該第三介電層293之外,該些第二導電墊172係設置於該第四線路層292上且顯露於該第四介電層294之外。
如5A至5F圖所示,本發明更揭示上述嵌埋式基板封裝構造200之一製造方法,其係延續第3F圖步驟之後之後製程步驟,即包含有第3A至3F圖之前製程步驟。在第3F圖中製造得到具有兩層線路層且嵌埋該晶片120之一基板型態封裝構造,並形成複數個第一導通孔150,係貫穿該介電填充膠130,以縱向導通該第一線路層110與該第二線路層140。之後,如第5A與5B圖所示,形成一第一介電層161與一第二介電層162,該第一介電層161係覆蓋該第一線路層110,該第二介電層162係覆蓋該第二線路層140;同時上下各層壓一第一金屬箔片20與一第二金屬箔片30。之後,如第5C圖所示,形成複數個第二導通孔252、253。其中,該些複數個第二導通孔252係貫穿該介電填充膠130、該第一介電層161與該第二介電層162。之後,如第5D圖所示,圖案化蝕刻一第一金屬箔片20與該第二金屬箔片30,以分別形成一第三線路層291於該第一介電層161上以及形成一第四線路層292於該第二介電層162上,並且該些第二導通孔252係縱向導通該第三線路層291與該第四線路層292。之後,如第5E圖所示,
形成一第三介電層293與一第四介電層294,該第三介電層293係覆蓋該第三線路層291,該第四介電層294係覆蓋該第四線路層292。最後,如第5F圖所示,以電鍍方式形成複數個第一導電墊171與第二導電墊172,該些第一導電墊171係設置於該第三線路層291上且顯露於該第三介電層293之外,該些第二導電墊172係設置於該第四線路層292上且顯露於該第四介電層294之外。因此,可上下疊壓相同數量之線路層與介電層,仍可維持上下的熱膨脹係數的平衡,不會造成該嵌埋式基板封裝構造200之翹曲。
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。
100‧‧‧嵌埋式基板封裝構造
110‧‧‧第一線路層
111‧‧‧散熱平墊
120‧‧‧晶片
121‧‧‧主動面
122‧‧‧背面
123‧‧‧銲墊
124‧‧‧晶粒貼附材料層
125‧‧‧側面
130‧‧‧介電填充膠
131‧‧‧平面
140‧‧‧第二線路層
150‧‧‧第一導通孔
161‧‧‧第一介電層
162‧‧‧第二介電層
171‧‧‧第一導電墊
172‧‧‧第二導電墊
Claims (11)
- 一種嵌埋式基板封裝構造,包含:一第一線路層;一晶片,係設置於該第一線路層上,該晶片係具有一主動面與一背面,其中該主動面係設有複數個銲墊,該背面係形成有一晶粒貼附材料層,該第一線路層係局部嵌陷於該晶粒貼附材料層中;一介電填充膠,係形成於該第一線路層上,以嵌埋覆蓋該晶片之複數個側面而顯露該主動面在同一平面;一第二線路層,係形成於由該介電填充膠與該晶片構成之平面上,該第二線路層係局部貼附於該主動面而連接至該些銲墊;複數個第一導通孔,係貫穿該介電填充膠,以縱向導通該第一線路層與該第二線路層;一第一介電層,係覆蓋該第一線路層;以及一第二介電層,係覆蓋該第二線路層。
- 依據申請專利範圍第1項之嵌埋式基板封裝構造,其中該第一介電層與該第二介電層係可為銲罩材料。
- 依據申請專利範圍第1項之嵌埋式基板封裝構造,另包含有複數個第一導電墊與第二導電墊,該些第一導電墊係設置於該第一線路層上且顯露於該第一介電層之外,該些第二導電墊係設置於該第二線路層上且顯露於該第二介電層之外。
- 依據申請專利範圍第3項之嵌埋式基板封裝構造,其中該第一線路層係包含一散熱平墊,係對準於該晶片之下方並連接至該些第一導電墊之其中之一。
- 依據申請專利範圍第3項之嵌埋式基板封裝構造,其中該些第二導電墊係位於該晶片之該主動面之上方。
- 依據申請專利範圍第3項之嵌埋式基板封裝構造,其中該些第二導電墊係對準於該些第一導通孔。
- 依據申請專利範圍第1項之嵌埋式基板封裝構造,另包含一第二晶片,係設置於該第二介電層上。
- 依據申請專利範圍第1項之嵌埋式基板封裝構造,另包含有:一第三線路層,係形成於該第一介電層上;一第四線路層,係形成於該第二介電層上;以及複數個第二導通孔,係貫穿該介電填充膠、該第一介電層與該第二介電層,以縱向導通該第三線路層與該第四線路層。
- 依據申請專利範圍第8項之嵌埋式基板封裝構造,其中該些第二導通孔係更縱向導通該第一線路層與該第二線路層。
- 一種嵌埋式基板封裝構造之製造方法,包含:提供一第一線路層,該第一線路層係形成於一暫時性載板;設置一晶片於該第一線路層上,該晶片係具有一主動面與一背面,其中該主動面係設有複數個銲墊,該背面係形成有一晶粒貼附材料層,該第一線路層係局部嵌陷於該晶粒貼附材料層中;形成一介電填充膠於該第一線路層上,以嵌埋覆蓋該晶片之複數個側面而顯露該主動面在同一平面;形成一第二線路層於由該介電填充膠與該晶片構成之平面上,該第二線路層係局部貼附於該主動面而連接至該些銲墊;剝離該暫時性載板;形成複數個第一導通孔,係貫穿該介電填充膠,以縱 向導通該第一線路層與該第二線路層;以及形成一第一介電層與一第二介電層,該第一介電層係覆蓋該第一線路層,該第二介電層係覆蓋該第二線路層。
- 依據申請專利範圍第10項之嵌埋式基板封裝構造之製造方法,其中在形成該第一介電層與該第二介電層之步驟中同時上下各層壓一第一金屬箔片與一第二金屬箔片,並且該製造方法另包含:形成複數個第二導通孔,係貫穿該介電填充膠、該第一介電層與該第二介電層;以及圖案化蝕刻一第一金屬箔片與該第二金屬箔片,以分別形成一第三線路層於該第一介電層上以及形成一第四線路層於該第二介電層上,並且該些第二導通孔係縱向導通該第三線路層與該第四線路層。
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TWI697081B (zh) * | 2019-06-10 | 2020-06-21 | 恆勁科技股份有限公司 | 半導體封裝基板及其製法與電子封裝件 |
CN111863689A (zh) * | 2019-04-25 | 2020-10-30 | 深圳市环基实业有限公司 | 一种封装载板、封装体及其工艺 |
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TWI753337B (zh) * | 2019-07-30 | 2022-01-21 | 財團法人工業技術研究院 | 晶片封裝結構 |
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TWI807022B (zh) * | 2018-11-06 | 2023-07-01 | 南韓商三星電子股份有限公司 | 半導體封裝 |
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TWI781336B (zh) * | 2019-04-12 | 2022-10-21 | 南韓商三星電機股份有限公司 | 半導體封裝 |
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TWI697081B (zh) * | 2019-06-10 | 2020-06-21 | 恆勁科技股份有限公司 | 半導體封裝基板及其製法與電子封裝件 |
TWI753337B (zh) * | 2019-07-30 | 2022-01-21 | 財團法人工業技術研究院 | 晶片封裝結構 |
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