TW201442290A - 發光二極體模組 - Google Patents

發光二極體模組 Download PDF

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Publication number
TW201442290A
TW201442290A TW102114711A TW102114711A TW201442290A TW 201442290 A TW201442290 A TW 201442290A TW 102114711 A TW102114711 A TW 102114711A TW 102114711 A TW102114711 A TW 102114711A TW 201442290 A TW201442290 A TW 201442290A
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light
emitting diode
circuit board
substrate
electrode
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TW102114711A
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English (en)
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Kai-Wen Wu
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Hon Hai Prec Ind Co Ltd
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Priority to TW102114711A priority Critical patent/TW201442290A/zh
Priority to US14/056,966 priority patent/US20140321129A1/en
Publication of TW201442290A publication Critical patent/TW201442290A/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

一種發光二極體模組,包括電路板及設置在電路板上的發光二極體封裝結構,所述發光二極體封裝結構包括基板、形成在基板上的引腳結構和反射杯、設置在引腳結構上的發光二極體晶片及覆蓋所述發光二極體晶片的封裝層,所述封裝層的表面形成一出光面,所述引腳結構自基板延伸至反射杯位於出光面一側的表面,所述引腳結構通過導電膠與電路板上的線路電性連接,所述發光二極體封裝結構的出光面朝向電路板,所述電路板對應出光面的區域鏤空形成一通孔,自所述出光面出射的光線經所述通孔出射。

Description

發光二極體模組
本發明涉及一種半導體元件,尤其涉及一種發光二極體模組。
發光二極體(Light Emitting Diode,LED)是一種可將電流轉換成特定波長範圍的光的半導體元件。發光二極體以其亮度高、工作電壓低、功耗小、易與積體電路匹配、驅動簡單、壽命長等優點,從而可作為光源而廣泛應用於照明領域。
習知的LED模組通常包括電路板以及設置在電路板上的LED封裝結構,該LED封裝結構包括兩電極。對於高功率的LED封裝結構而言,業界通常在該兩電極上設置複數金球,並通過金球將LED封裝結構的電極和電路板上的線路形成電性連接。然而,在兩電極上設置複數金球的制程相對繁瑣,且每一金球與電極的接觸面積有限,導致LED封裝結構的散熱效率較低。故,需進一步改進。
鑒於此,有必要提供一種具有較高散熱效率的發光二極體晶粒。
一種發光二極體模組,包括電路板及設置在電路板上的發光二極體封裝結構,所述發光二極體封裝結構包括基板、形成在基板上的引腳結構和反射杯、設置在引腳結構上的發光二極體晶片及覆蓋所述發光二極體晶片的封裝層,所述封裝層的表面形成一出光面,所述引腳結構自基板延伸至反射杯位於出光面一側的表面,所述引腳結構通過導電膠與電路板上的線路電性連接,所述發光二極體封裝結構的出光面朝向電路板,所述電路板對應出光面的區域鏤空形成一通孔,自所述出光面出射的光線經所述通孔出射。
發明中發光二極體封裝結構的引腳結構延伸至反射杯靠近出光面的一側並通過導電膠與電路板上的線路形成電性連接,由於引腳結構延伸至反射杯靠近出光側的表面的部分的尺寸遠大於傳統技術中金球的尺寸,使得發光二極體封裝結構與電路板之間的接觸面積比傳統技術中金球與電路的接觸面積大的多,從而提升發光二極體封裝結構的散熱效率。
100...發光二極體模組
10...發光二極體封裝結構
20...電路板
11...基板
111...第一表面
112...第二表面
12...引腳結構
121...第一電極
122...第二電極
13...反射杯
131...上表面
132...下表面
133...凹槽
14...發光二極體晶片
15...封裝層
151...出光面
21...線路
22...通孔
30...導電膠
圖1為本發明的發光二極體模組一較佳實施例的剖視圖。
如圖1所示,為本發明一較佳實施例提供的發光二極體模組100,該發光二極體模組100包括一發光二極體封裝結構10以及承載發光二極體封裝結構10的電路板20。
所述發光二極體封裝結構10包括基板11、設置於該基板11上的引腳結構12、設置於引腳結構12上的發光二極體晶片14、覆蓋該發光二極體晶片14的封裝層15及形成於基板11上且收容該發光二極體晶片14的反射杯13。
具體的,所述基板11呈平板狀,其包括一第一表面111和與第一表面111相對的第二表面112。本實施例中,該基板11為絕緣基板。
所述引腳結構12設置於基板11的第一表面,該引腳結構12包括相互間隔的第一電極121和第二電極122。每一電極121、122自該基板11的第一表面111延伸至反射杯13遠離基板11第一表面111的頂端。
所述反射杯13包括一上表面131和與上表面131相對的一下表面132,其中部形成有貫穿上表面131及下表面132的凹槽133,該凹槽132用於收容發光二極體晶片14於其內。該凹槽133的寬度自上表面131至下表面132逐漸減小。該凹槽133的內表面可形成有高反射材料。本實施例中,該反射杯13與該基板11通過嵌入注塑技術一體成型。所述第一電極121和第二電極122均自反射杯13的下表面132延伸至反射杯13 的上表面131,延伸至反射杯13上表面131的部分的電極121、122的尺寸遠大於傳統單個金球的尺寸。
所述發光二極體晶片14設置在第一電極電極121、靠近第二電極122一端的表面上且收容於凹槽133的底端。該發光二極體晶片14通過導線分別與第一電極121和第二電極122形成電性連接。在本步驟中,該發光二極體晶片14也可以晶片倒裝的形式固定在引腳結構12上。
所述封裝層15覆蓋所述發光二極體晶片14並填充滿所述凹槽133。該封裝層15的頂面與該反射杯13的上表面131齊平,從而封裝層15的該頂面形成一出光面151。該封裝層15由透明材料製成,其可由矽樹脂或其他樹脂,或者其他透光的混合材料製作而成。該封裝層15可根據發光二極體晶片14本身的出光顏色與實際發光需求而包含有螢光粉(圖未示)。
所述電路板20承載該發光二極體封裝結構10,其用於將所述發光二極體封裝結構10與外部電源電連接而為發光二極體封裝結構10提供電能。所述電路板20大致呈板狀,電路板20的上表面形成有線路21。所述電路板20對應所述出光面151的區域被鏤空形成一通孔22,該通孔22的形狀和尺寸與所述出光面151的形狀和尺寸相同。
組裝時,所述發光二極體封裝結構10被倒置於電路板20上,即所述出光面151朝向所述電路板20。具體的,所述第一電極121和第二電極122與電路板20上的線路21通過導電膠30形成電性連接。
本發明中發光二極體封裝結構10的第一電極121和第二電極122延伸至反射杯13上表面131的一側並通過導電膠30與電路板20上的線路21形成電性連接,由於電極121、122延伸至反射杯13上表面131的部分的尺寸遠大於傳統技術中金球的尺寸,使得本實施例中發光二極體封裝結構10與電路板20之間的接觸面積比傳統技術中金球與電路的接觸面積大的多,從而提升發光二極體封裝結構10的散熱效率。此外,該發光二極體模組工作時,所述發光二極體晶片14發出光線自出光面151朝向電路板20射出,進而經所述通孔22出射,從而滿足發光二極體模組100的特定發光需要。同時,採用導電膠30進行塗膠連接的制程簡便,可降低發光二極體模組100的製造成本。
綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
100...發光二極體模組
10...發光二極體封裝結構
20...電路板
11...基板
111...第一表面
112...第二表面
12...引腳結構
121...第一電極
122...第二電極
13...反射杯
131...上表面
132...下表面
133...凹槽
14...發光二極體晶片
15...封裝層
151...出光面
21...線路
22...通孔
30...導電膠

Claims (6)

  1. 一種發光二極體模組,包括電路板及設置在電路板上的發光二極體封裝結構,所述發光二極體封裝結構包括基板、形成在基板上的引腳結構和反射杯、設置在引腳結構上的發光二極體晶片及覆蓋所述發光二極體晶片的封裝層,所述封裝層的表面形成一出光面,其改良在於:所述引腳結構自基板延伸至反射杯位於出光面一側的表面,所述引腳結構通過導電膠與電路板上的線路電性連接,所述發光二極體封裝結構的出光面朝向電路板,所述電路板對應出光面的區域鏤空形成一通孔,自所述出光面出射的光線經所述通孔出射。
  2. 如申請專利範圍第1項所述之發光二極體模組,其中,該通孔的形狀和尺寸與所述出光面的形狀和尺寸相同。
  3. 如申請專利範圍第1項所述之發光二極體模組,其中,所述基板為絕緣基板,所述反射杯與所述基板一體成型。
  4. 如申請專利範圍第1項所述之發光二極體模組,其中,所述反射杯包括靠近基板的下表面和靠近出光面且與下表面相對的一上表面,所述反射杯中部形成有貫穿上表面和下表面的凹槽,所述發光二極體晶片位於所述凹槽中,所述封裝層填充滿所述凹槽。
  5. 如申請專利範圍第1項所述之發光二極體模組,其中,所述出光面與反射杯的上表面齊平,所述引腳結構包括相互間隔的第一電極和第二電極,所述第一電極和第二電極位於反射杯上表面的部分通過導電膠與電路板上的線路電性連接。
  6. 如申請專利範圍第1項所述之發光二極體模組,其中,所述發光二極體晶片設置在第一電極的、靠近第二電極一端的表面上,所述發光二極體晶片通過導線分別與第一電極和第二電極形成電性連接。
TW102114711A 2013-04-24 2013-04-24 發光二極體模組 TW201442290A (zh)

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JP5869961B2 (ja) * 2012-05-28 2016-02-24 株式会社東芝 半導体発光装置

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