TW201342556A - 半導體裝置的封裝體及半導體裝置的封裝方法 - Google Patents
半導體裝置的封裝體及半導體裝置的封裝方法 Download PDFInfo
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- TW201342556A TW201342556A TW102103887A TW102103887A TW201342556A TW 201342556 A TW201342556 A TW 201342556A TW 102103887 A TW102103887 A TW 102103887A TW 102103887 A TW102103887 A TW 102103887A TW 201342556 A TW201342556 A TW 201342556A
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Abstract
本發明一實施例提供一種半導體裝置的封裝體,包括:一基板;一接觸墊(contact pad),設置在該基板的一第一表面,該接觸墊具有一第一側及相對於該第一側的一第二側;一導電線路(conductive trace),耦接至該接觸墊的該第一側;該導電線路的一延伸部,耦接至該接觸墊的該第二側;以及多個接合墊(bonding pad),設置在該基板的一第二表面。
Description
本發明係有關於半導體裝置封裝體及其形成方法。
在各種電子應用中,如個人電腦、手機、數位相機等,都有使用半導體裝置。一般而言,數以十計、百計的積體電路(IC)晶粒形成於單一半導體晶圓上。藉由沿著繪線切割積體電路以分別各晶粒。而後,例如在多晶片模組或其他種封裝體中,分別封裝各晶粒。
藉由持續縮減最小元件尺寸而在給定區域中能夠積體化更多元件,半導體工業持續提升各種電子元件(例如:電晶體、二極體、電阻、電容等)的積體化密度。在一些應用中,這些較小的電子元件也需要比過去更小的封裝。對半導體裝置而言,晶圓級晶片尺寸封裝(wafer level chip-scale packaging;WLCSP)為一種較小的封裝體之一,其一般包括重新分佈層(redistribution layer;RDL),以扇出(fan out)積體電路晶粒的接觸墊之配線,因而可在比晶粒的接觸墊更大的節距(pitch)上形成電子接觸。
這些較小的積體電路及封裝積體電路晶粒通常用
於手持裝置,如手機。然而,若使用者將這些含積體電路的終端產品掉落下來,則會發生積體電路的失效,也就是終端產品的失效。
目前需要可應用於半導體裝置之堅固的小尺寸封裝體。
在本發明一實施例中,提供一種半導體裝置的封裝體,包括:一基板;一接觸墊(contact pad),設置在該基板的一第一表面,該接觸墊具有一第一側及相對於該第一側的一第二側;一導電線路(conductive trace),耦接至該接觸墊的該第一側;該導電線路的一延伸部,耦接至該接觸墊的該第二側;以及多個接合墊(bonding pad),設置在該基板的一第二表面。
在本發明另一實施例中,提供一種封裝半導體裝置,包括:一封裝體,該封裝體包括:一基板;一接觸墊(contact pad),設置在該基板的一頂表面,該接觸墊具有一第一側及相對於該第一側的一第二側;一導電線路(conductive trace),耦接至該接觸墊的該第一側;該導電線路的一延伸部,耦接至該接觸墊的該第二側;以及多個接合墊(bonding pad),設置在該基板的一底表面;以及一積體電路晶粒,耦接至該封裝體的該基板的該頂表面上的該接觸墊。
在本發明又一實施例中,提供一種半導體裝置的封裝方法,包括:提供一封裝體,該封裝體包括:一基板;一陣列區,包括多個第一接觸墊(contact pad)以及多個第二接觸
墊設置在該基板的一第一表面,該陣列區具有多個角落(corners),其中各第一接觸墊設置在該陣列區的各角落,該些第一接觸墊具有一第一側以及相對該第一側的一第二側;一導電線路(conductive trace),耦接至各第一接觸墊的該第一側;該導電線路的一延伸部,耦接至各第一接觸墊的該第二側;以及多個接合墊(bond pad),設置在該基板的一底表面;以及提供一積體電路晶粒;以及將該積體電路晶粒耦接至該封裝體的該陣列中的該些第二接觸墊及該些第一接觸墊。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
102‧‧‧封裝體
100‧‧‧積體電路晶粒
132‧‧‧接觸頭
104、142、148‧‧‧焊料球
108、108’‧‧‧接觸墊
106‧‧‧基板
112‧‧‧角落
114‧‧‧角落區
120、120a、120b‧‧‧導電線路
103‧‧‧頂表面
130‧‧‧焊料接合
110‧‧‧半導體裝置
124‧‧‧延伸部
116‧‧‧通孔
118‧‧‧絕緣材料
136‧‧‧接合墊
122‧‧‧連接區邊界
150‧‧‧凸塊下金屬
126、126a、126b、128、128a、128b、128c‧‧‧邊緣
134‧‧‧配線
140‧‧‧直通基板穿孔
144‧‧‧下填材料
146‧‧‧模鑄化合物
152‧‧‧導電元件
160‧‧‧流程圖
162、164、166、168、170‧‧‧步驟
第1圖顯示在本發明一實施例中以新穎的封裝體封裝半導體裝置的透視圖。
第2圖顯示在一實施例中經過第1圖所示封裝製程後之封裝的半導體裝置的透視圖。
第3圖顯示封裝體的頂表面的上視圖,其上形成有多個接觸墊以及導電線路。
第4A圖顯示接觸墊之更詳細的上視圖,其中接觸墊具有導電線路耦接至一側。
第4B及4C圖顯示在本發明一些實施例中,第4A圖中所示的導電線路的延伸部耦接至接觸墊的一側,該側相對於具有導電線路的一側。
在第4D及4E圖所示的實施例中,第4A圖所示的導電線路的三個延伸部耦接至接觸墊。
第5A圖更詳細的顯示具有耦接至接觸墊兩側的二個導電線路的接觸墊。
第5B、5C、5D圖顯示在本發明一些實施例中,在第5A圖中所示的二個導電線路的延伸部耦接至接觸墊。
第6圖顯示在一實施例中封裝積體電路的剖面圖,其中在積體電路晶粒及封裝體之間形成焊料接合。
第7圖顯示在一實施例中,在封裝體的一部分具有凸塊下金屬結構設置在接觸墊上。
第8圖顯示在一實施例中焊料接合的詳細的剖面圖。
第9圖為在本發明一實施例中,封裝半導體裝置的流程圖。
以下依本發明之不同特徵舉出數個不同的實施例。本發明中特定的元件及安排係為了簡化,但本發明並不以這些實施例為限。舉例而言,於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例,亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外,為簡明起見,本發明在不同例子中以重複的元件符號及/或字母表示,但不代表所述各實施例及/或結構間具有特定的關係。
首先,參照第1圖,第1圖顯示在本發明一實施例中以新穎的封裝體102封裝半導體裝置的透視圖。半導體裝置包括積體電路晶粒100,其包括在工作件(workpiece)上形成
積體電路。工作件可包括半導體基板,包括矽或其他半導體材料,且例如可利用絕緣層覆蓋。晶粒100的工作件例如可包括單晶矽上的氧化矽。例如可利用化合物半導體代替矽,如砷鎵、銦磷、矽/鍺、或碳化矽。具有積體電路晶粒100形成於其上的工作件例如可包括絕緣層上矽(SOI)或絕緣層上鍺(GOI)基板。在單一工作件上形成多個積體電路晶粒100,而後在繪線分割,使工作件分開為單一晶粒(single die)100。
積體電路晶粒100可包括形成在工作件中/或上的一或多個元件及/或電路(圖中未顯示)。積體電路晶粒100也可包括導電層及/或半導體元件,例如電晶體、二極體、電容等(圖中未顯示)。由上視圖來看,晶粒100可為方形或矩形的形狀。積體電路晶粒100例如可包括邏輯電路、記憶體裝置、或其他類型電路。積體電路晶粒100包括多個接觸頭(在第1圖中未顯示,參照第6圖中的接觸頭132)形成在其下底表面上。
在積體電路晶粒100的底表面上形成多個焊料球104,例如可形成在積體電路晶粒100的底表面上的多個接觸頭132上。焊料球104例如可包括微凸塊(microbumps)或焊料凸塊。焊料球104可設置在陣列的行及列中。焊料球104的圖案可為與封裝體102的頂表面上之接觸墊108及108’的陣列區115相同的圖案。
封裝體102包括基板106。在一些實施例中,基板106例如包括印刷電路板(PCB)。在一些實施例中,封裝體102例如包括晶圓級晶片尺寸封裝(wafer level chip-scale packaging;WLCSP)。基板106可包括直通基板穿孔
(through-substrate vias;TSVs)、導線、及重新分佈層(redistribution layer;RDL),之後將更進一步的敘述。或者,基板106可包括其他材料,封裝體102可包括其他類型的封裝體,以及基板106的導線可包括其他材料及型態。
基板106包括在其頂表面上的陣列區115中形成的接觸墊108及108’。接觸墊108設置在基板106上之陣列區115的角落區(未顯示於第1圖中,參照第3圖中的角落112及角落區114),且接觸墊108’設置在基板上的其他地方,如陣列區115的邊緣區(edge regions)及中心區(central regions)中。接觸墊108及108’例如包括金屬,如銅、鋁、其合金、其他金屬、或前述之組合。基板106也可包括導電線路(conductive trace)120(未顯示於第1圖中,參照第3圖)耦接至接觸墊108及108’,將於後續詳述。接觸墊108及108’以及導電線路120可包括在基板106的導電材料中的導線的蝕刻路線(etch runs)及/或線路(trace)。可藉由移除部分基板106或設置在基板106上的絕緣材料以暴露接觸墊108及108’,使得接觸墊108及108’例如在封裝製程中,可藉由晶粒100的焊料球104電性接觸。
為了封裝積體電路晶粒100,將積體電路晶粒100上的焊料球104附著至封裝體102的基板106的頂表面103上的接觸墊108及108’。利用回流焊接製程(solder reflow)將焊料球104的焊料回流,且將積體電路晶粒100附著至封裝體102,例如,電性及機械性的將焊料球104連接至基板106上的接觸墊108及108’,以及在晶粒100及封裝體102之間形成
焊料接合(參照第6圖焊料接合130)。或者,也可用其他方法將焊料球104附著至封裝體102的基板106。
例如,在一些實施例中,可選擇性的將焊料球(第1圖未顯示,參照第7圖的焊料球148)附著在封裝體102的接觸墊108及108’,而非附著至晶粒100的接觸頭132。在所述將焊料球104附著至晶粒100的接觸頭的實施例中,回流焊料球148的焊料材料。在另一實施例中,焊料球104及148可分別附著至晶粒100及封裝體102。
在一些實施例中,利用倒裝(flip-chip)軌道上接合(bond-on-trace;BOT)附著技術,將積體電路晶粒100附著至封裝體102。接觸墊108及108’可包括用以將晶粒100附著至基板102的軌道上的接合圖案(bond-on-trace pattern),其中藉由軌道上接合封裝技術以封裝積體電路晶粒100。或者,在其他實施例中,接觸墊108及108’的圖案可為一般用於焊料球的圖案。也可利用其他倒裝附著技術及其他類型的接觸墊108及108’,以將積體電路晶粒100附著至封裝體102。
第2圖顯示在一實施例中經過第1圖所示封裝製程後之封裝的半導體裝置110的透視圖。利用如第6圖所示的多個焊料接合130,將積體電路晶粒100上的焊料球104耦接至封裝體102上的接觸墊108及108’。
第3圖顯示封裝體102的頂表面103的上視圖,其上形成有多個接觸墊108及108’以及導電線路120。以虛線顯示晶粒100之後將被附著的區域。在此(例如在申請專利範圍內),也將接觸墊108稱為第一接觸墊108,且將接觸墊108’
稱為第二接觸墊108’。在本發明一實施例中,利用第6圖中所示的焊料接合130將積體電路晶粒100耦接至第一接觸墊108及第二接觸墊108’。
再次參照第3圖,在基板106上的接觸墊108及108’。其中,可在陣列區115的各角落112中各形成一個接觸墊108。或者,可在陣列區115的角落區114中形成多個接觸墊108。
第3圖顯示在一些實施例中的角落區114的圖案。在頂部左側角落區(top left corner region)114中,包括三個接觸墊108:角落接觸墊108、其右側的接觸墊108、以及在角落接觸墊108下的另一個接觸墊108。在頂部右側角落區(top right corner region)114中,包括二列接觸墊108,且也包括角落接觸墊108、及兩個相鄰的接觸墊108。在底部左側角落區(bottom left corner region)114中,包括3x3角落接觸墊的區塊。在底部右側角落區(bottom right corner region)114中,包括含角落接觸墊108的單一列的三個接觸墊108。或者,在角落區114中接觸墊108的圖案可視需要設計為各種其他不同的特徵。
以下將更進一步的敘述在一實施例中,在角落112及角落區114中,接觸墊108包括改良的焊料接合130(參照第6圖)的延伸部124(參照第4B圖)。再次參照第3圖,其他的接觸墊108’位於陣列區115的邊緣及/或位於陣列區115的中心。一或多個接觸墊108及108’可耦接至鄰近接觸墊108及108’的通孔116。在一些實施例中,通孔116可包括穿過基板
通孔(through-substrate via;TSV)。
在一些實施例中,在基板106的單一金屬化層上形成導電線路120及接觸墊108及108’。導電線路120及接觸墊108及108’的形成可利用沉積一層導電材料,以及利用微影圖案化該層導電材料。導電線路120及接觸墊108及108’的形成也可利用鑲嵌技術,藉由先沉積絕緣材料、圖案化該層絕緣材料、以及以導電材料填入圖案化的絕緣材料以形成導電線路120及接觸墊108及108’。在一些實施例中,導電線路120及接觸墊108及108’的形成例如利用單一微影罩幕及圖案化製程。或者,可利用其他方法形成導電線路120及接觸墊108及108’,且可形成在基板106的二或多個金屬化層中。
由基板106的表面上的絕緣材料118暴露出接觸墊108及108’。絕緣材料118可包括氮化矽、二氧化矽、其他絕緣材料、前述之組合、或前述之多層層狀物。導電線路120位於絕緣材料118下,並與接觸墊108及108’電性接觸(例如:耦接)。導電線路120可包括封裝體102的水平連接部,且可包括扇出線(fan-out wiring),其係耦接至在基板106另一側(例如:底部)上的接合墊(bond pad)136(未顯示於第3圖中,參照第6圖)。
根據本發明一實施例,導電線路120延伸入封裝體102的接觸墊108’及陣列區115角落112或角落區114中的接觸墊108。導電線路120延伸的材料在此稱為導電線路120的延伸部124(未顯示於第3圖中,參見第4B圖),其將在之後詳述。
第4A圖顯示接觸墊108之更詳細的上視圖,其中接觸墊108具有導電線路120耦接至一側。此結構顯示在進行本發明之前的原始設計佈局。虛線表示的圓圈顯示鄰近接觸墊108的連接區邊界(connection region boundary)122,此將於第7、8圖中更進一步的敘述。連接區邊界122包括焊料球著路區(landing region),其中將形成焊料接合130(參照第6圖)。在一些實施例中,連接區邊界122例如可包括設置在接觸墊108上的凸塊下金屬(UBM)結構150的一部分的邊緣(參照第7圖),或者包括可耦接至封裝體102的焊料接合130的最寬的部分(參照第8圖)。
第4B及4C圖顯示在本發明一些實施例中,第4A圖中所示的導電線路120的延伸部124耦接至接觸墊108的一側,該側相對於具有導電線路的一側。在第4B圖中,延伸部124包括長度d1,其中d1例如為數微米(μm)至數毫米(mm),或更小。或者,d1也可為其他長度。在此實施例中,延伸部124完全在鄰近接觸墊108的連接區邊界122之下延伸。例如,如圖示,延伸部124的邊緣126大抵與連接區邊界122對齊。由上視圖來看,導電線路的延伸部124的寬度大抵與導電線路120的寬度相同。
在導電材料的佈局(由接觸墊108及導電線路120形成)中加入延伸部124有助於後續形成連接至接觸墊108的焊料接合130(參照第6圖)。延伸部124在焊料接合130下提供額外的材料,並藉由鄰近焊料接合130的延伸部124,使得熱導電性增加,因而有助於改進焊料接合130的形成。
第4C圖顯示本發明其他實施例。在這些實施例中,導電線路120的延伸部124的長度大於長度d1。導電線路120的延伸部124可包括長度d2,其中長度d2例如小於數毫米或介於數毫米至數微米之間。或者,長度d2也可為其他長度。在此實施例中,延伸部124延伸過鄰近接觸墊108的連接區邊界122。在導電線路的延伸部124的上視圖中,延伸部124的寬度與導電線路120的寬度大抵相同。
在第4C圖所顯示的其他實施例中,導電線路120的延伸部124可延伸至封裝體102的基板106上的其他部分。延伸部124可延著基板106的縱長(lengthwise)延伸,且與另一接觸墊108或108’接觸,如第4C圖左側所示。在另一實施例中,導電線路120的延伸部124可沿著基板106的縱長延伸,也可不與另一接觸墊108或108’或其他導電元件接觸(圖中未顯示)。
在第4D及4E圖所示的實施例中,第4A圖所示的導電線路120的三個延伸部124a、124b及124c耦接至接觸墊108。在第4D圖中,延伸部124a耦接至接觸墊108的一側,該側相對於接觸墊108耦接至導電線路120的另一側。延伸部124a可延伸過連接區邊界122,且具有邊緣128a。或者,延伸部124a可具有與連接區邊界122大抵對其的邊緣126a,如虛線所示。在此實施例中,延伸部124a包括導電線路120的第一延伸部124a。導電線路120的第二延伸部124b耦接至接觸墊108的第三側,且導電線路120的第三延伸部124c耦接至接觸墊108的第四側。接觸墊108的第四側相對於接觸墊108
的第三側。第二延伸部124b及第三延伸部124c分別具有邊緣126a及126b,它們與連接區邊界122大抵對齊,如圖示。在一實施例中,第二延伸部124b及第三延伸部124c耦接至接觸墊108的方向與延伸部124a及導電線路120的方向大抵垂直。
或者,如第4E圖所示,第二延伸部124b及第三延伸部124c的邊緣128b(以弧線表示)及128c可延伸過連接區邊界122至一預設距離d2(參照第4C圖),以達到另一接觸墊108或108’、或基板106的其他部分。
在第4B至4E圖中,接觸墊108可達到一個相稱(balanced)的結構,其中在連接區邊界122內或超過連接區邊界122的部分,延伸部124、124a、124b、及124c提供鄰近接觸墊108的額外的導電材料。鄰近接觸墊108的導電線路120的延伸部124、124a、124b、及124c可強化後續形成在接觸墊108上的焊料接合(參照第6圖中的焊料接合130),而在基板106的接觸墊陣列區115的角落112及角落區114內提供更堅固的連接。
在一些實施例中,如第5A圖之上視圖所示,二個導電線路120a及120b可耦接至一接觸墊108。接觸墊108具有二個導電線路120a及120b耦接至接觸墊108大抵垂直的兩側,亦即,分別耦接至接觸墊108的右側及上側。在此實施例中,導電線路120a及120b延伸至相對於路線120a及120b所形成的另一側,藉此以提供一相稱的結構,並強化後續形成的焊料接合(參照第6圖中的焊料接合130)。第5B、5C、5D圖顯示在本發明一些實施例中,在第5A圖中所示的二個導電線
路120a及120b的延伸部124a及124b耦接至接觸墊108。
在第5B圖中,延伸部124a耦接至接觸墊108的左側,其係與耦接至導電線路120a的右側相對。延伸部124b耦接至接觸墊108的下側,其係與耦接至導電線路120b的上側相對。延伸部124a及124b分別具有邊緣126a及126b,其係完全在連接區邊界122內延伸。或者,延伸部124a及124b分別具有邊緣128a及128b,其係延伸過連接區邊界122,如第5C圖所示。或者,一延伸部124a可具有邊緣128a,其係延伸過連接區邊界122,而另一延伸部124b可具有邊緣126a,其係完全在連接區邊界122內延伸,如第5D圖所示。延伸部124a及/或124b可延伸過連接區邊界122至一預定距離d2(參照第4C圖),以達到另一接觸墊108或108’、或基板106上的其他部分,如此處所描述的其他實施例所示。
第6圖顯示在一實施例中封裝積體電路110的剖面圖,其中在積體電路晶粒100及封裝體102之間形成焊料接合130。在積體電路晶粒100上的接觸頭132以及封裝體102上的接觸墊108及108’之間形成焊料接合130。在所示的實施例中,具有延伸部124的接觸墊108設置在接觸墊108’及108的陣列區115的角落區114中。封裝體102包括配線(wiring)134,配線134形成在一或多個金屬化層中,金屬化層則形成在基板106中。接觸墊108及108’、導電線路120、及延伸部124形成配線134在一或多個金屬化層中。基板106可包括形成於其中的重新分部層(非必要)。例如,配線134可包括一部分的重新分部層(RDL)。在另一實施例中,重新分部層
可包括扇出(fan out)區,以擴張晶粒的預定著陸區(footprint),使得封裝體102的底表面上的接合墊136的預定著陸區大於晶粒100上的接觸頭132的預定著陸區。
在一些實施例中,可在基板中形成多個直通基板穿孔(through-substrate vias;TSVs)140。在一些實施例中,直通基板穿孔140例如可耦接至第3圖所示的通孔116。如圖示,在封裝體102的底表面上形成多個接合墊136。接合墊136提供連接區,使得電性連接至封裝半導體裝置110,例如在終端應用中。根據應用上的設計,直通基板穿孔140可連接或不連接至接合墊136。如虛線所示,多個焊料球142可選擇性的附著至封裝半導體裝置110的接合墊136。
下填材料(underfill material)144包括絕緣材料,可選擇性的應用於晶粒100及封裝體102之間,如虛線所示。下填材料144例如可包括環氧樹脂或高分子。也包含有絕緣材料的模鑄化合物(molding compound)可選擇性的設置在晶粒100上,且暴露出部分封裝體102,如第6圖中的虛線所示。模鑄化合物146包括類似於下填材料144的材料。或者,模鑄材料146及下填材料144可包括其他材料,且可不被包括在封裝板導體裝置110中。
第7圖顯示在一實施例中,在封裝體102的一部分具有凸塊下金屬(under-ball metallization;UBM)結構150設置在接觸墊108上。在此實施例中,焊料球148耦接至封裝體102。在此實施例中,焊料球104可不耦接至晶粒100,或者焊料球104可耦接至晶粒100。在絕緣材料118上形成凸塊下金
屬結構150,絕緣材料118則設至於導電線路120、接觸墊108及延伸部124上。凸塊下金屬結構150包括導電元件152,導電元件152包括形成在絕緣層118中及絕緣層118上的金屬。可選擇性的(optional)形成凸塊下金屬結構150,且凸塊下金屬結構150有助於焊料球148的形成,且/或有助於將晶粒100上的焊料球104貼附至封裝體102。
在第7圖中顯示導電線路120、接觸墊108及延伸部124的剖面圖。在一實施例中,在左方焊料球148下的延伸部124包括邊緣126,其與連接區邊界122的邊緣大抵對齊,連接區邊界122係指在焊料球148下的UBM結構150的邊緣。連接區邊界122例如可包括設置於接觸墊108上的UBM結構150的一部分的一邊緣。此外,延伸部124完全在連接區邊界122下延伸。在右側焊料球148下的延伸部124包括一邊緣128,邊緣128延伸過連接區邊界122的邊緣。UBM結構150具有寬度d3,寬度d3例如可介於數微米至數毫米,但寬度d3也可為其他數值。在一實施例中,寬度d3顯示出連接區邊界122的大小及位置。
第8圖顯示在一實施例中焊料接合130的詳細的剖面圖。在此實施例中,焊料球104及148分別形成於晶粒100及封裝體102兩者上。在焊料回流製程後,焊料接合130包括焊料球104及焊料球148兩者的焊料材料。在第8圖中也顯示出導電線路120、接觸墊108、及延伸部124的剖面圖。在此實施例中,在焊料接合130下的延伸部124包括一邊緣128,邊緣128延伸過連接區邊界122的邊緣,連接區邊界122係指
焊料接合130最寬的部分。此外,延伸部124完全延伸至連接區邊界122下,且更延伸過連接區邊界122的邊緣。寬度d3為焊料接合130之最寬的部分的寬度,其例如可包括焊料球104及/或148的寬度。
在焊料球148附著至接觸墊108’之前,在接觸墊108上形成在絕緣層中的開口。開口的形成可使用用於非焊接屏蔽界定(non-solder mask defined;NSMD)製程或焊點屏蔽界定(solder mask defined;SMD)製程中的方法,例如用於球柵陣列(ball grid array)著路區(landing region)功能或其他技術。在此實施例中,接觸墊108/導電線路120結合形狀已經過改良,而包括導電層中的導電線路120的延伸部124。
第9圖為在本發明一實施例中,封裝半導體裝置的流程圖160。在步驟162中,提供封裝體102,封裝體102包括導電線路120耦接至接觸墊108的第一側,且導電線路120的延伸部124延伸至接觸墊108的第二側。在步驟164中,提供積體電路晶粒100。在步驟166中,將積體電路晶粒100耦接至接觸墊108,例如:多個接觸墊108及108’。在一可選擇性實施的步驟168中,在積體電路晶粒100及封裝體102之間可形成下填材料144。在一可選擇性實施的步驟170中,可在積體電路晶粒100上形成模鑄化合物146。或者,可省略步驟168及170。
在本發明一些實施例中包括半導體裝置封裝體102,且也包括含封裝體102的封裝半導體裝置110。在本發明的一些實施例中包括利用封裝體102封裝半導體裝置的方法。
本發明一些實施例的優點可包括提供新穎的封裝體102,封裝體102具有延伸部124、124a、124b、及124c耦接至接觸墊108與導電線路120相對的一側,該導電線路120係在陣列區115的角落112及角落區114中的導電線路120。延伸部124a、124a、124b、及124c可改進焊料接合130的形成,並因此增進墜落試驗的生命週期(drop test lifetime),例如,在墜落試驗時或終端應用中使用封裝的半導體裝置110。在一些實施例中的優點包括NSMD及UBM對接觸墊108及108’尺寸比率維持不變。
延伸部124a、124a、124b、及124c可包括在導電材料層中,該導電材料層中形成有導電線路120及接觸墊108及108’。因此,在這些實施例中不需要額外的微影罩幕或微影製程。相反的,可改良現有的微影罩幕以在導電材料部局中形成新穎的延伸部124a、124a、124b、及124c。
作為導電材料層而加在接觸墊108中的延伸部124a、124a、124b、及124c可在接觸墊108的二個方向相對(如第4B及4C圖所示),或者可在四個方向相對(如第4D及第5B至5D圖所示)。在一些實施例中,如第4C及5C圖所示,延伸部124、124a、124b、及124c提供對稱的導電材料鄰近於接觸墊108。在封裝體102及晶粒100的角落及角落區,將新穎的延伸部124、124a、124b、及124c加至接觸墊108,例如:在此所敘述在陣列區115的角落112或角落區114中的接觸墊108及108’。在一些實施例中,也可將延伸部124、124a、124b、及124c加至在陣列區115的其他區域中的其他接觸墊108’。
在一些應用中,若佈局中沒有導電線路120之新的延伸部124、124a、124b、及124c,接觸墊108及108’以及焊料球104及/或144之間容易形成接合裂縫,特別是在陣列區115的角落112及角落區114中的接觸墊108及108’。在本發明一些實施例中,導電線路120的延伸部124、124a、124b、及124c可改進焊料接合130的形成,其原因在於在焊料接合130下設置有額外的導電材料,其可增加焊料接合130的焊料材料的導熱性。此改進的、堅固的焊料接合130可提升封裝裝置110的產率、提升封裝裝置110的墜落試驗結果、且增加封裝裝置110的生命週期。此外,在此所述新穎的封裝體102及封裝方法易於應用在封裝製程中。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧封裝體
100‧‧‧積體電路晶粒
132‧‧‧接觸頭
104、148‧‧‧焊料球
108‧‧‧接觸墊
106‧‧‧基板
120‧‧‧導電線路
130‧‧‧焊料接合
124‧‧‧延伸部
118‧‧‧絕緣材料
122‧‧‧連接區邊界
128‧‧‧邊緣
Claims (10)
- 一種半導體裝置的封裝體,包括:一基板;一接觸墊(contact pad),設置在該基板的一第一表面,該接觸墊具有一第一側及相對於該第一側的一第二側;一導電線路(conductive trace),耦接至該接觸墊的該第一側;該導電線路的一延伸部,耦接至該接觸墊的該第二側;以及多個接合墊(bonding pad),設置在該基板的一第二表面。
- 如申請專利範圍第1項所述之半導體裝置的封裝體,其中該接觸墊位於該基板的一陣列區的一角落中。
- 如申請專利範圍第1項所述之半導體裝置的封裝體,其中該導電線路的該延伸部包括該導電線路的一第一延伸部,以及其中該接觸墊更包括一第三側及相對於該第三側的一第四側,更包括:該導電線路的一第二延伸部,耦接至該接觸墊的該第三側;以及該導電線路的一第三延伸部,耦接至該接觸墊的該第四側。
- 如申請專利範圍第1項所述之半導體裝置的封裝體,其中該導電線路包括一第一導電線路,以及其中該接觸墊更包括一第三側及相對於該第三側的一第四側,更包括:一第二導電線路,耦接至該接觸墊的該第三側;以及該第二導電線路的一延伸部,耦接至該接觸墊的該第四側。
- 如申請專利範圍第4項所述之半導體裝置的封裝體,其中該第二導電線路的該延伸部完全延伸在接近該接觸墊的一連接區邊界(connection region boundary)之下。
- 如申請專利範圍第5項所述之半導體裝置的封裝體,其中該第二導電線路的該延伸部延伸過該連接區邊界。
- 如申請專利範圍第1項所述之半導體裝置的封裝體,其中該連接區邊界包括一凸塊下金屬(under-ball metallization;UBM)結構的部分邊緣,該凸塊下金屬結構設置在該接觸墊上,或者該連接區包括邊界耦接至該封裝體的一焊料接合(solder joint)的一最寬部分。
- 如申請專利範圍第1項所述之半導體裝置的封裝體,其中該接觸墊包括一第一接觸墊,其中該導電線路的該延伸部延伸至一第二接觸墊,該第二接觸墊設置在該基板的該第一表面上。
- 一種半導體裝置的封裝方法,包括:提供一封裝體,該封裝體包括:一基板;一陣列區,包括多個第一接觸墊(contact pad)以及多個第二接觸墊設置在該基板的一第一表面,該陣列區具有多個角落(corners),其中各第一接觸墊設置在該陣列區的各角落,該些第一接觸墊具有一第一側以及相對該第一側的一第二側;一導電線路(conductive trace),耦接至各第一接觸墊的該第一側; 該導電線路的一延伸部,耦接至各第一接觸墊的該第二側;以及多個接合墊(bond pad),設置在該基板的一底表面;以及提供一積體電路晶粒;以及將該積體電路晶粒耦接至該封裝體的該陣列中的該些第二接觸墊及該些第一接觸墊。
- 如申請專利範圍第9項所述之半導體裝置的封裝方法,其中將該積體電路晶粒耦接至該些第二接觸墊及該第一接觸墊的步驟包括將多個焊料球附著至該積體電路晶粒的一表面上的多個接觸頭(contacts)、附著至該基板上該第一接觸墊及該些第二接觸墊、或附著至該積體電路晶粒的一表面上的多個接觸頭、該基板上該第一接觸墊及該些第二接觸墊;以及回焊該焊料球的一材料以形成該封裝體及該積體電路晶粒間的多個焊料接合。
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US20130270705A1 (en) | 2013-10-17 |
US9935038B2 (en) | 2018-04-03 |
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