TW201332053A - Substrate sustaining platform for plasma processing apparatus - Google Patents
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Description
本發明涉及半導體製造領域，尤其涉及一種用於等離子體處理裝置的載片台。 The present invention relates to the field of semiconductor manufacturing, and more particularly to a stage for a plasma processing apparatus.
半導體工藝件的邊緣效應是困擾半導體產業的一個問題。所謂半導體工藝件的邊緣效應是指在等離子體處理過程中，由於等離子體受電場控制，而上下兩極邊緣處的場強會受邊緣條件的影響，總有一部分電場線彎曲，而導致電場邊緣部分場強不均，進而導致該部分的等離子體濃度不均勻。在該種情況下，生產出的半導體工藝件周圍也存在一圈處理不均勻的區域。這一不均勻現象在射頻電場頻率越高時越明顯，在射頻頻率大於60 MHz甚至大於100 MHz時這一等離子濃度的不均勻性程度已經很難再用其他裝置如位於靜電夾盤邊緣的聚集環來調控。 The edge effect of semiconductor process parts is a problem that plagues the semiconductor industry. The edge effect of the so-called semiconductor process component means that during the plasma processing, since the plasma is controlled by the electric field, the field strength at the edge of the upper and lower poles is affected by the edge condition, and a part of the electric field line is always bent, resulting in the edge portion of the electric field. The field strength is uneven, which in turn causes the plasma concentration of the portion to be uneven. In this case, there is also a circle of uneven processing around the produced semiconductor process member. This unevenness is more obvious when the RF electric field frequency is higher. When the RF frequency is greater than 60 MHz or even greater than 100 MHz, the degree of non-uniformity of the plasma concentration is difficult to be reused by other devices such as the edge of the electrostatic chuck. Ring to regulate.
由於半導體工藝件是圓形的，因此愈外圈面積愈大，邊緣部分的各個工藝環節的均一性不佳將導致成品率顯著下降。在普遍採用300 mm製程的今天，半導體工藝件邊緣效應帶來的損失更為巨大。 Since the semiconductor process piece is circular, the larger the outer ring area, the poor uniformity of the various process steps at the edge portion will result in a significant drop in yield. Today, the 300 mm process is commonly used, and the edge effect of semiconductor process parts is even more significant.
因此，業內需要能夠簡單有效地改善邊緣效應，提高製程均一性。 Therefore, the industry needs to be able to simply and effectively improve edge effects and improve process uniformity.
針對先前技術中的上述問題，本發明提出了能夠改善均一性的用於等離子體處理裝置的載片台。 In view of the above problems in the prior art, the present invention proposes a stage for a plasma processing apparatus capable of improving uniformity.
本發明第一方面提供一種應用於等離子體處理裝置的用 於承載基片的載片台，其中，所述基片位於所述載片台上方，其中，所述載片台包括：第一電極，其與具有第一頻率的射頻電源連接，用於產生等離子體，靜電吸盤，其位於所述第一電極上方，其中，所述靜電吸盤包括：第一電介質層，其中設置有一個或多個真空空洞；第二電介質層，其位於所述第一電介質層上方，並埋設有用於產生靜電吸力的電極；第三電介質層，其植入所述第一電介質層中，其中，所述第三電介質層和所述第一電介質層的介電常數不同。 A first aspect of the invention provides a method for applying to a plasma processing apparatus And a substrate carrying a substrate, wherein the substrate is located above the stage, wherein the stage comprises: a first electrode connected to a radio frequency power source having a first frequency for generating a plasma, an electrostatic chuck, located above the first electrode, wherein the electrostatic chuck comprises: a first dielectric layer in which one or more vacuum voids are disposed; and a second dielectric layer located in the first dielectric Above the layer, an electrode for generating electrostatic attraction is embedded; a third dielectric layer is implanted in the first dielectric layer, wherein the third dielectric layer and the first dielectric layer have different dielectric constants.
可選地，所述第三電介質層植入於對應於所述基片中央區域下方的所述第一電介質層中，其中，所述第三電介質層的介電常數小於所述第一電介質層的介電常數。 Optionally, the third dielectric layer is implanted in the first dielectric layer corresponding to a lower portion of the central region of the substrate, wherein a dielectric constant of the third dielectric layer is smaller than the first dielectric layer Dielectric constant.
可選地，所述一個或多個真空空洞設置於對應於所述基片中央區域下方的所述第一電介質層中。 Optionally, the one or more vacuum voids are disposed in the first dielectric layer below the central region of the substrate.
可選地，所述一個或多個真空空洞分別設置於對應於所述基片中央區域和邊緣區域，以及位於所述中央區域和所述邊緣區域之間的中間區域的所述第一電介質層中。 Optionally, the one or more vacuum voids are respectively disposed on the first dielectric layer corresponding to the central region and the edge region of the substrate, and an intermediate region between the central region and the edge region in.
可選地，所述對應於所述基片中央區域的一個或多個真空空洞和所述對應於所述基片中間區域的一個或多個真空空洞的體積相同。 Optionally, the one or more vacuum voids corresponding to the central region of the substrate and the one or more vacuum voids corresponding to the intermediate region of the substrate are of the same volume.
進一步地，所述對應於基片中央區域的一個或多個空洞與所述對應於基片中間區域的一個或多個空洞相連，成為一體。 Further, the one or more voids corresponding to the central region of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate to be integrated.
可選地，所述對應於所述基片中央區域的一個或多個真空空洞的體積大於所述對應於所述基片中間區域的一個或多個 真空空洞的體積。 Optionally, the volume of the one or more vacuum voids corresponding to the central region of the substrate is greater than the one or more corresponding to the intermediate region of the substrate The volume of the vacuum cavity.
進一步地，所述對應於基片中央區域的一個或多個空洞與所述對應於基片中間區域的一個或多個空洞相連，成為一體。 Further, the one or more voids corresponding to the central region of the substrate are connected to the one or more voids corresponding to the intermediate portion of the substrate to be integrated.
其中，所述第一頻率為13M赫茲以上。 Wherein, the first frequency is above 13 MHz.
本發明第二方面還提供了一種等離子體處理裝置，其中，包括本發明第一方面提供的載片台。 A second aspect of the invention also provides a plasma processing apparatus comprising the stage provided by the first aspect of the invention.
其中，所述第一頻率為13M赫茲以上。 Wherein, the first frequency is above 13 MHz.
本發明提供的載片台及包括該載片台的等離子體處理裝置能夠簡單有效地改善邊緣效應，提高製程均一性。 The slide table provided by the present invention and the plasma processing apparatus including the same can easily and effectively improve the edge effect and improve the process uniformity.
以下結合附圖，對本發明的具體實施方式進行說明。 Specific embodiments of the present invention will be described below with reference to the accompanying drawings.
本發明通過在真空處理裝置的位於下電極和基片之間的電介質中設置一個或多個空洞，以及通過不同電介質的配置，來改變所述下電極和基片下表面之間等效電容的介電常數，從而進一步改變所述等效電容的大小，以實現對基片的製程均一性進行優化。 The present invention changes the equivalent capacitance between the lower electrode and the lower surface of the substrate by providing one or more voids in the dielectric between the lower electrode and the substrate of the vacuum processing apparatus, and by configuration of different dielectrics. The dielectric constant, thereby further changing the size of the equivalent capacitance, to optimize the process uniformity of the substrate.
圖1是本發明一個具體實施例的真空處理裝置的載片台結構示意圖。在下文將描述的具體實施例中，所述真空處理裝置特別地為刻蝕機台。如圖1所示，本發明提供了一種應用於等離子體處理裝置的用於承載基片W的載片台1，其中，所述基片W位於所述載片台1上方。其中，所述載片台1包括：第一電極13，所述第一電極13與具有第一頻率f的射頻電源15連接。需要說明的是，在刻蝕機台腔室上部分還包括一個與所述第一電極13平行的第二電極(未示出)，兩者結合起來用於產生製程用的等離子體，以對所述基片W進行刻蝕處理。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to an embodiment of the present invention. In a specific embodiment to be described hereinafter, the vacuum processing apparatus is in particular an etching machine. As shown in FIG. 1, the present invention provides a stage 1 for carrying a substrate W applied to a plasma processing apparatus, wherein the substrate W is positioned above the stage 1. The stage 1 includes a first electrode 13 connected to a radio frequency power source 15 having a first frequency f. It should be noted that the upper portion of the etching machine chamber further includes a second electrode (not shown) parallel to the first electrode 13, and the two are combined to generate a plasma for the process, The substrate W is subjected to an etching process.
其中，所述第一電極13是由電導體材料製程，特別地， 可由金屬鋁製成。 Wherein the first electrode 13 is made of an electrical conductor material, in particular, It can be made of metal aluminum.
靜電吸盤，其位於所述第一電極13上方，其中，包括：第一電介質層14，其中設置有一個或多個真空空洞。本發明對上述一個或多個真空空洞根據不同的技術需要有不同的配置方式，在下文中將進行具體講述。 An electrostatic chuck, located above the first electrode 13, includes a first dielectric layer 14 in which one or more vacuum voids are disposed. The present invention has different configurations for the above one or more vacuum voids according to different technical needs, which will be specifically described below.
第二電介質層11，其位於所述第一電介質層14上方，並埋設有電極12。所述電極12是一層電極膜，其連接於直流電源(未示出)，用於產生對基片W的靜電吸力。 A second dielectric layer 11 is located above the first dielectric layer 14 and is embedded with electrodes 12. The electrode 12 is an electrode film which is connected to a direct current power source (not shown) for generating electrostatic attraction to the substrate W.
第三電介質層16，其植入所述第一電介質層14中，其中，所述第三電介質層16和所述第一電介質層14的介電常數不同。 A third dielectric layer 16 is implanted in the first dielectric layer 14, wherein the third dielectric layer 16 and the first dielectric layer 14 have different dielectric constants.
為了更加簡明方便地說明本發明的發明機制，需要對基片進行區域劃分。需要說明的是，下文中對基片進行的區域劃分並不是實際存在的，而是為了方便說明本發明而對基片進行的虛擬劃分，並不能用以限定本發明。圖2是本發明對基片進行區域劃分的示意圖。如圖2所示，其示出了一個水平放置的基片的俯視圖，所述基片為圓盤形的，以圓盤形的基片的圓心為起點，將位於中央區域的圓形部分設定為基片的中央區域C’，位於所述中央區域C’外圍的圓環形區域設定為基片的中間區域M’，位於所述中間區域M’外圍的圓環區域設定為基片的邊緣區域E’。結合附圖1，在靜電吸盤中的第一電介質層14中，對應於所述基片W的中央區域C’的區域即為中央區域C，對應於所述基片W的中間區域M’的區域即為中間區域M，對應於基片W的邊緣區域E’的區域即為邊緣區域E。其中，所述中間區域M位於所述中央區域C和邊緣區域E之間。由於上述區域的劃分不是實際存在的，所以，根據技術需要，可對上述區域的劃分進行任意調整，例如，可將 刻蝕率降低到某一程度的基片區域所對應的區域劃分為邊緣區域，而並非一定要按照數字範圍進行劃分。 In order to explain the inventive mechanism of the present invention more concisely and conveniently, it is necessary to divide the substrate into regions. It should be noted that the zoning of the substrate in the following is not actually present, but the virtual division of the substrate for the convenience of the description of the present invention is not intended to limit the present invention. Fig. 2 is a schematic view showing the area division of a substrate of the present invention. As shown in Fig. 2, it shows a top view of a horizontally placed substrate which is disc-shaped, starting from the center of the disc-shaped substrate, and setting the circular portion in the central portion. For the central region C' of the substrate, the annular region located at the periphery of the central region C' is set as the intermediate region M' of the substrate, and the annular region located at the periphery of the intermediate region M' is set as the edge of the substrate. Area E'. Referring to FIG. 1, in the first dielectric layer 14 in the electrostatic chuck, a region corresponding to the central region C' of the substrate W is a central region C corresponding to the intermediate region M' of the substrate W. The area is the intermediate area M, and the area corresponding to the edge area E' of the substrate W is the edge area E. The intermediate region M is located between the central region C and the edge region E. Since the division of the above area is not actually present, the division of the above area may be arbitrarily adjusted according to technical needs, for example, The area corresponding to the substrate area where the etching rate is reduced to a certain extent is divided into edge areas, and is not necessarily divided according to the numerical range.
本發明的原始思路是通過改變腔體與上電極之間寄生電容來改變半導體工藝件邊緣電場密度，半導體工藝件邊緣效應得到改善。也就是說通過調節等離子體邊緣與腔體之間的寄生電容可以使半導體工藝件邊緣的電場重新分佈。一般來說，影響這個寄生電容值的因素有三個，即上電極邊緣與腔體的相對面積、上電極邊緣與腔體之間的距離，以及等離子體邊緣與腔體形成空間的等效介電常數。等離子處理腔室一旦製成，很明顯，其上電極邊緣與腔體的相對面積和它們之間的距離是固定的，而寄生電容與電場分佈的關係比較複雜，不同的射頻能量輸入也會影響這一關係，以及考慮到技術上的可行性，預先計算並製造出具有適當大小寄生電容的真空反應室是很困難的。 The original idea of the present invention is to change the edge electric field density of the semiconductor process member by changing the parasitic capacitance between the cavity and the upper electrode, and the edge effect of the semiconductor process component is improved. That is to say, the electric field at the edge of the semiconductor process piece can be redistributed by adjusting the parasitic capacitance between the plasma edge and the cavity. In general, there are three factors that affect the value of this parasitic capacitance, namely, the relative area of the edge of the upper electrode and the cavity, the distance between the edge of the upper electrode and the cavity, and the equivalent dielectric of the space between the plasma edge and the cavity. constant. Once the plasma processing chamber is fabricated, it is obvious that the relative area of the upper electrode edge to the cavity and the distance between them are fixed, and the relationship between the parasitic capacitance and the electric field distribution is complicated, and different RF energy inputs are also affected. This relationship, and considering the technical feasibility, it is difficult to pre-calculate and fabricate a vacuum reaction chamber having an appropriately sized parasitic capacitance.
因此，唯一有可能改變的就是等離子體與腔體相對空間的等效介電常數，也就是上文所述的第一電介質層的等效介電常數。本發明基於這樣的考慮，對該空間的等效介電常數進行調節來取得一個合適的寄生電容，使得電場重新分佈，進而使半導體工藝件等離子體處理效果均一。 Therefore, the only thing that is likely to change is the equivalent dielectric constant of the plasma to the cavity relative space, which is the equivalent dielectric constant of the first dielectric layer described above. The present invention is based on such considerations that the equivalent dielectric constant of the space is adjusted to achieve a suitable parasitic capacitance, such that the electric field is redistributed, thereby making the plasma processing effect of the semiconductor process piece uniform.
如圖1所示，結合圖2，所述第三電介質層16植入於對應於所述基片W中央區域下方的所述第一電介質層14中，其中，所述第三電介質層16的介電常數小於所述第一電介質層14的介電常數。 As shown in FIG. 1, in conjunction with FIG. 2, the third dielectric layer 16 is implanted in the first dielectric layer 14 corresponding to a lower portion of the central region of the substrate W, wherein the third dielectric layer 16 is The dielectric constant is less than the dielectric constant of the first dielectric layer 14.
將第一電極13和基片W按照中央區域C、中間區域M和邊緣區域E分別看做三個等效電容Cc、Cm、Ce，其中的第一電介質層14即充當了該等效電容其中的介質，因此，根據電容公式： C=εS/4πkd，其中，ε為介電常數，d為距離。 The first electrode 13 and the substrate W are regarded as three equivalent capacitors Cc, Cm, and Ce according to the central region C, the intermediate region M, and the edge region E, respectively, wherein the first dielectric layer 14 serves as the equivalent capacitance. The medium, therefore, according to the capacitance formula: C = εS / 4πkd, where ε is the dielectric constant and d is the distance.
由此，由於在本實施例中，由於將空洞H11設置於容易產生刻蝕速率較高的中央區域下方的第一電介質層14的中央區域C中，使得中央區域C中的電介質較其外圍的中間區域M和邊緣區域E的電介質少，即，中央區域C的等效電容Cc的介電常數降低，進而使得所述等效電容Cc降低，從而進一步地使得連接於第一電極13上的射頻電源15能夠到達基片中央區域C的減少，由此使得基片中央區域單位時間產生的等離子數量減少，從而使得產生的等離子和基片之間的相互作用活躍度降低，最終降低所述基片中央區域的刻蝕速率。並且，由於第三電介質層16的介電常數小於所述第一電介質層14，即，中央區域C的等效電容Cc的介電常數進一步降低，從而實現了對基片的製程均一性進行優化。 Thus, in the present embodiment, since the cavity H11 is disposed in the central region C of the first dielectric layer 14 below the central region where the etching rate is high, the dielectric in the central region C is made closer to the periphery thereof. The intermediate region M and the edge region E have less dielectric, that is, the dielectric constant of the equivalent capacitance Cc of the central region C is lowered, thereby causing the equivalent capacitance Cc to decrease, thereby further causing the radio frequency connected to the first electrode 13 The power source 15 is capable of reaching a reduction in the central region C of the substrate, thereby reducing the amount of plasma generated per unit time in the central region of the substrate, thereby reducing the activity of interaction between the generated plasma and the substrate, and ultimately reducing the substrate. The etch rate of the central region. Moreover, since the dielectric constant of the third dielectric layer 16 is smaller than the first dielectric layer 14, that is, the dielectric constant of the equivalent capacitance Cc of the central region C is further lowered, thereby optimizing the process uniformity of the substrate. .
其中，所述一個或多個真空空洞也可以分別設置於對應於所述基片中央區域和邊緣區域，以及位於所述中央區域和所述邊緣區域之間的中間區域的所述第一電介質層中。 Wherein the one or more vacuum voids may also be respectively disposed on the first dielectric layer corresponding to the central region and the edge region of the substrate, and an intermediate region between the central region and the edge region. in.
可選地，所述設置於對應於所述基片中央區域的一個或多個真空空洞和所述設置於對應於所述基片中間區域的一個或多個真空空洞的體積相同。參照圖3，在本實施例中，空洞H21的體積等於空洞H22的體積，則由此可以降低基片W中央區域C’和中間區域M’的刻蝕速率，使得基片W邊緣區域E的刻蝕速率變相得到補償，改善了基片W的邊緣效應。 Optionally, the one or more vacuum voids disposed in a central region corresponding to the substrate are the same volume as the one or more vacuum voids disposed in an intermediate region corresponding to the substrate. Referring to FIG. 3, in the present embodiment, the volume of the cavity H21 is equal to the volume of the cavity H22, whereby the etching rate of the central region C' and the intermediate region M' of the substrate W can be lowered, so that the edge region E of the substrate W is The etch rate is phase-shifted to compensate for the edge effect of the substrate W.
其中，所述對應於基片中央區域的一個或多個空洞H21與所述對應於基片中間區域的一個或多個空洞H22相連，成為一體。 The one or more holes H21 corresponding to the central region of the substrate are connected to the one or more holes H22 corresponding to the intermediate portion of the substrate to be integrated.
可選地，所述設置於對應於所述基片中央區域的一個或多 個真空空洞的體積大於所述設置於對應於所述基片中間區域的一個或多個真空空洞的體積。如圖4所示，在本實施例中，空洞H31的體積大於空洞H32的體積，則由此可以對基片W的刻蝕速率分別按照中央區域C’、中間M’和邊緣區域E’進行逐步調整。具體地，由於位於中央區域C中的真空空洞H31的體積最大，則對應於基片W的中央區域C’的刻蝕速率被降低得最多。其次，由於位於中間區域M的真空空洞H32的體積小於所述真空空洞H31，則對應於基片W的中間區域M’的刻蝕速率也得到了降低，但其必降低幅度低於對應於基片W的中央區域C’的刻蝕速率。再次，由於在本實施例中對應於基片W的邊緣區域E’的邊緣區域E並沒有設置任何真空空洞，其刻蝕速率沒有進行任何調整。因此，上述控制使得對應於基片W中央區域C’的刻蝕速率最低，對應於基片W的中間區域M’的刻蝕速率稍高於所述對應於基片W中央區域C’的刻蝕速率，而對應於基片W的邊緣區域E’的刻蝕速率最高。由此對邊緣效應進行了補償，進一步優化了製程均一性。 Optionally, the one or more of the central regions corresponding to the substrate are disposed The volume of the vacuum voids is greater than the volume of the one or more vacuum voids disposed in the intermediate region of the substrate. As shown in FIG. 4, in the present embodiment, the volume of the cavity H31 is larger than the volume of the cavity H32, so that the etching rate of the substrate W can be performed according to the central region C', the intermediate M', and the edge region E', respectively. Gradually adjust. Specifically, since the volume of the vacuum cavity H31 located in the central region C is the largest, the etching rate corresponding to the central region C' of the substrate W is lowered most. Secondly, since the volume of the vacuum cavity H32 located in the intermediate portion M is smaller than the vacuum cavity H31, the etching rate corresponding to the intermediate portion M' of the substrate W is also lowered, but it must be lower than the corresponding base. The etch rate of the central region C' of the sheet W. Again, since no vacuum cavity is provided in the edge region E corresponding to the edge region E' of the substrate W in this embodiment, the etching rate is not adjusted. Therefore, the above control makes the etching rate corresponding to the central region C' of the substrate W the lowest, and the etching rate corresponding to the intermediate portion M' of the substrate W is slightly higher than that of the central portion C' corresponding to the substrate W. The etch rate is the highest, and the etch rate corresponding to the edge region E' of the substrate W is the highest. The edge effect is compensated to further optimize the process uniformity.
所述對應於基片中央區域的一個或多個空洞H31與所述對應於基片中間區域的一個或多個空洞H32相連，成為一體。 The one or more voids H31 corresponding to the central region of the substrate are connected to the one or more voids H32 corresponding to the intermediate portion of the substrate to be integrated.
需要說明的是，本領域技術人員可以理解，本發明對上述實施例還包括若干變化例，例如，可在基片中央區域、中間區域、邊緣區域相對應的位置都設置一個或多個空洞，並且通過分別在基片中央區域、中間區域、邊緣區域相對應的位置配置介電常數不同的電介質層，只要實現中央區域的刻蝕速率最低，中間區域其次，邊緣區域最高就可以對刻蝕邊緣效應進行補償，從而實現發明目的。 It should be noted that those skilled in the art can understand that the present invention further includes several variations to the foregoing embodiments. For example, one or more holes may be disposed at positions corresponding to the central area, the intermediate area, and the edge area of the substrate. And by arranging dielectric layers having different dielectric constants at corresponding positions in the central region, the intermediate region, and the edge region of the substrate, as long as the etch rate of the central region is the lowest, the intermediate region is second, and the edge region is the highest to etch the edge. The effect is compensated to achieve the object of the invention.
進一步地，所述第一頻率f為13M赫茲以上，優選的為60 MHz以上，甚至100 MHz。 Further, the first frequency f is 13 MHz or more, preferably 60 MHz or more, or even 100 MHz.
進一步地，所述第一電介質層為圓柱形的。 Further, the first dielectric layer is cylindrical.
本發明還提供了一種等離子體處理裝置，其特徵在於，包括前述的載片台。 The present invention also provides a plasma processing apparatus including the aforementioned stage.
進一步地，所述第一頻率為13 M赫茲以上，優選的為60 MHz以上，甚至100 MHz。 Further, the first frequency is above 13 MHz, preferably above 60 MHz, or even 100 MHz.
進一步地，所述第一電介質層為圓柱形的。 Further, the first dielectric layer is cylindrical.
其中，本發明所應用的電介質材料可選自石英(Quarz)、陶瓷(Ceramic)、聚四氟乙烯(Tefflon)等。其中，所述石英的介電常數為3.58，聚四氟乙烯的介電常數為2.55，陶瓷的介電常數為3。本發明可以根據需要在不同區域根據大小設置上述電介質材料，例如，可在中央區域設置設置介電常數最小的聚四氟乙烯，在其他區域設置石英或陶瓷。 The dielectric material to which the present invention is applied may be selected from the group consisting of quartz (Quarz), ceramic (Ceramic), and polytetrafluoroethylene (Tefflon). Among them, the quartz has a dielectric constant of 3.58, the polytetrafluoroethylene has a dielectric constant of 2.55, and the ceramic has a dielectric constant of 3. The present invention can be provided with the above-mentioned dielectric materials according to the size in different regions as needed. For example, a polytetrafluoroethylene having a minimum dielectric constant can be disposed in a central region, and quartz or ceramic can be disposed in other regions.
參照圖5，其以基片的圓心為原點，以基片的直徑為橫軸，以刻蝕速率為Y軸確定了一個坐標軸。其中，S1是應用現有技術的載片台得到的基片的刻蝕速率曲線，可見，其在圓心周圍的中央區域刻蝕速率較高，而在其中間區域刻蝕速率有所降低，在其邊緣區域的刻蝕速率最低，其必然存在均一性的缺陷。S2和S3對應於應用了本發明提供的載片台得到的基片的刻蝕速率曲線。其中，S2僅對應於基片中央區域實施本發明，可見其中央區域的刻蝕速率得到顯著降低。S3則是對基片中央區域和中間區域都實施本發明，其中央區域和中間區域的刻蝕速率都得到了降低。由此說明了本發明的優越性，本發明能夠快速有效低功耗地改善邊緣效應，實現製程均一化。 Referring to Fig. 5, the center of the substrate is taken as the origin, the diameter of the substrate is plotted on the horizontal axis, and the coordinate axis is determined as the Y axis. Wherein, S1 is an etch rate curve of the substrate obtained by applying the prior art carrier table, and it can be seen that the etching rate in the central region around the center of the circle is higher, and the etching rate is reduced in the middle region thereof. The edge region has the lowest etch rate, which necessarily has the defect of uniformity. S2 and S3 correspond to an etch rate curve of a substrate obtained by applying the stage provided by the present invention. Wherein, S2 only implements the invention corresponding to the central region of the substrate, and it can be seen that the etching rate of the central region is significantly reduced. S3 implements the invention for both the central region and the intermediate region of the substrate, and the etching rates of the central region and the intermediate region are all reduced. Thus, the advantages of the present invention are demonstrated, and the present invention can improve edge effects quickly and efficiently, and achieve process uniformity.
儘管本發明的內容已經通過上述優選實施例作了詳細介 紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的專利範圍來限定。 Although the content of the present invention has been described in detail through the above preferred embodiments However, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.
1‧‧‧載片台 1‧‧‧Slide
11‧‧‧第二電介質層 11‧‧‧Second dielectric layer
12‧‧‧電極 12‧‧‧ electrodes
13‧‧‧第一電極 13‧‧‧First electrode
14‧‧‧第一電介質層 14‧‧‧First dielectric layer
15‧‧‧射頻電源 15‧‧‧RF power supply
16‧‧‧第三電介質層 16‧‧‧ Third dielectric layer
C‧‧‧中央區域 C‧‧‧Central area
C’‧‧‧中央區域 C’‧‧‧Central Area
E‧‧‧邊緣區域 E‧‧‧Edge area
E’‧‧‧邊緣區域 E’‧‧‧Edge area
H11‧‧‧空洞 H11‧‧‧ hollow
H21‧‧‧空洞 H21‧‧‧ hollow
H22‧‧‧空洞 H22‧‧‧ hollow
H31‧‧‧空洞 H31‧‧‧ hollow
H32‧‧‧空洞 H32‧‧‧ hollow
M‧‧‧中間區域 M‧‧‧Intermediate area
M’‧‧‧中間區域 M’‧‧‧ intermediate area
S1‧‧‧刻蝕速率曲線 S1‧‧‧etch rate curve
S2‧‧‧刻蝕速率曲線 S2‧‧‧etch rate curve
S3‧‧‧刻蝕速率曲線 S3‧‧‧etch rate curve
W‧‧‧基片 W‧‧‧ substrates
圖1是本發明的優選實施例的真空處理裝置的載片台結構示意圖；圖2是本發明對基片進行區域劃分的示意圖；圖3是本發明的第一具體實施例的真空處理裝置的載片台結構示意圖；圖4是本發明的第二具體實施例的真空處理裝置的載片台結構示意圖；圖5是本發明的發明效果示意圖。 1 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to a preferred embodiment of the present invention; FIG. 2 is a schematic view showing the area division of the substrate of the present invention; and FIG. 3 is a view of the vacuum processing apparatus of the first embodiment of the present invention. FIG. 4 is a schematic view showing the structure of a stage of a vacuum processing apparatus according to a second embodiment of the present invention; and FIG. 5 is a schematic view showing the effect of the invention.
1‧‧‧載片台 1‧‧‧Slide
11‧‧‧第二電介質層 11‧‧‧Second dielectric layer
12‧‧‧電極 12‧‧‧ electrodes
13‧‧‧第一電極 13‧‧‧First electrode
14‧‧‧第一電介質層 14‧‧‧First dielectric layer
15‧‧‧射頻電源 15‧‧‧RF power supply
16‧‧‧第三電介質層 16‧‧‧ Third dielectric layer
C‧‧‧中央區域 C‧‧‧Central area
E‧‧‧邊緣區域 E‧‧‧Edge area
H11‧‧‧空洞 H11‧‧‧ hollow
M‧‧‧中間區域 M‧‧‧Intermediate area
W‧‧‧基片 W‧‧‧ substrates
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