TW201322391A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201322391A
TW201322391A TW101112571A TW101112571A TW201322391A TW 201322391 A TW201322391 A TW 201322391A TW 101112571 A TW101112571 A TW 101112571A TW 101112571 A TW101112571 A TW 101112571A TW 201322391 A TW201322391 A TW 201322391A
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Taiwan
Prior art keywords
semiconductor
recessed portion
semiconductor die
wafer
layer
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TW101112571A
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English (en)
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TWI490991B (zh
Inventor
Chih-Hao Chen
Long-Hua Lee
Chun-Hsing Su
Yi-Lin Tsai
Kung-Chen Yeh
Chung-Yu Wang
Jui-Pin Hung
Jing-Cheng Lin
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Taiwan Semiconductor Mfg
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Publication of TW201322391A publication Critical patent/TW201322391A/zh
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Publication of TWI490991B publication Critical patent/TWI490991B/zh

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Abstract

一種晶圓級封裝，包括一接合至支撐晶圓的半導體晶粒。半導體晶粒在其基板具有至少一個階梯式凹陷。一底膠層形成於半導體晶粒及支撐晶圓之間。再者，底膠層的高度受限於階梯式凹陷。在晶圓級封裝的製程中，階梯式凹陷幫助降低晶圓級封裝上的應力。

Description

半導體裝置及其製造方法
本發明係有關一種晶圓級封裝。
因各式電子元件(例如電晶體、二極體、電阻、電容等)之積集度的增進，半導體工業已經歷急速的成長。積集度的增進大抵是由於半導體製程節點縮小(例如朝著次20奈米的節點縮小)造成。隨著要達到微型化的需求，更高的運作速度、更大的頻寬、更低的耗電量及延遲已在近來成長，且對於較小且較有創意的半導體晶粒封裝技術的需求已經產生。
隨著半導體科技演化，出現了使用多晶片晶圓級封裝(multi-chip wafer level package)的半導體裝置以作為更進一步減少半導體晶片實際尺寸的有效替代方案。在使用多晶圓級封裝的半導體裝置中，例如邏輯、記憶體、處理電路等的主動電路被製造在不同晶圓上，且每一個晶圓晶粒經由拾放技術(pick-and-place techniques)被堆疊在另一晶圓晶粒上。可藉由使用多晶片半導體裝置達到高出許多的密度。再者，多晶片半導體裝置可達到更小的形狀因子、成本高效益、增進的性能、及較低耗電。
一個三維積體電路可包括一頂部主動電路層、一底部主動電路層、及複數個中間層。在一三維積體電路中，可藉由複數個凸塊接合兩個晶粒，且藉由複數個穿透導孔(through vias)使兩個晶粒彼此電性連接。凸塊及導孔提供三維積體電路垂直軸中的電性內連線。因此，兩個半導體晶粒之間的訊號路徑比傳統三維積體電路中的短，其中在傳統三維積體電路中，不同的晶粒是使用內連線技術來接合不同的晶粒，例如使用打線接合的晶片堆疊封裝。一個三維積體電路可包括各式堆疊在一起的半導體晶粒。複數個半導體晶粒是在晶圓切割之前被封裝。晶圓級封裝科技有一些好處。將複數個半導體晶粒使用晶圓級封裝的一個好處是多晶片晶圓級封裝可降低製造成本。另一好處是藉由使用凸塊及導孔，寄生損失減少了。
本發明係有關一種半導體裝置，包括：一半導體基板，具有一凹陷部分及一非凹陷部分，其中一第一凹陷位於該凹陷部分；一隔離層，形成於該半導體基板的非凹陷部分上；一重分佈層，形成於該隔離層上；一凸塊下金屬結構，形成於該重分佈層上；及一第一凸塊，形成於該凸塊下金屬結構上。
本發明亦有關一種半導體裝置的製造方法，包括：使用一第一切割鋸切割進入一半導體晶粒一第一切割深度；使用一第二切割鋸切割該半導體晶粒，使該第二切割鋸具有一與該第一切割鋸的一第一刀片不同的第二刀片；形成一階梯式凹陷於該半導體晶粒的一側邊；將該半導體晶粒翻面；及將該半導體晶粒的一第一側邊連接至一封裝基板的一第一側邊。
本發明更有關一種半導體裝置，包括：一半導體晶粒，具有：一第一半導體基板，具有一第一凹陷部份，一第一頂部非凹陷部分、及一第一側邊非凹陷部分，其中一第一階梯式凹陷位於該第一凹陷部份；一第一隔離層，形成於該第一半導體基板的第一頂部非凹陷部份上；一第一凸塊，形成於該第一隔離層上；一第二半導體晶粒，具有：一第二半導體基板，具有一第二凹陷部份、一第二頂部非凹陷部份、及一第二側邊非凹陷部份，其中一第二階梯式凹陷位於該第二凹陷部份；一第二隔離層，形成於該第二半導體基板的第二頂部非凹陷部份；一第二凸塊，形成於該第二隔離層上；一封裝基板，具有一第一側邊，連接至該第一半導體晶粒的第一凸塊及該第二半導體晶粒的第二凸塊；一第二側邊，具有一第三凸塊；及一底膠層，形成於該第一半導體晶粒、該第二半導體晶粒、及該封裝基板之間，其中該第一頂部非凹陷部份、該第一凹陷部份、該第二頂部非凹陷部份及該第二凹陷部份埋於該底膠層中。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
將在以下詳細討論本實施例的形成於使用。應能理解的是本揭露提供許多可應用的發明概念，其可在各種特定情況下實施。在此討論的特定實施例僅說明一些特定形成及使用本揭露的方式，且並不限定本揭露。
以下將配合一三維積體電路的晶圓級封裝之實施例來敘述本揭露。然而本揭露也可應用在各種積體電路。
首先參見第1圖，其根據一實施例顯示一晶圓在切割製程後的剖面示意圖。如第1圖所示，晶圓100可包括複數個積體電路。在一切割製程後，半導體晶粒(例如半導體晶粒110)從晶圓100分離。沿虛線x-x’剖開得到一第一剖面圖。第一剖面圖包括一第一半導體晶粒110及一第二半導體晶粒120。同樣地，沿虛線y-y’剖開得到一第二剖面圖。第二剖面圖包括第一半導體晶粒110及一第三半導體晶粒160。
根據一實施例，第1圖所示的半導體晶粒110、120及160具有實質相同的結構。為簡化起見，在以下僅詳細討論第一半導體晶粒110。應注意的是，為提供對於各實施例發明面向的基本認識，第一半導體晶粒110、第二半導體晶粒120、及第三半導體晶粒160並未被詳細繪示。然而，應注意的是，第一半導體晶粒110、第二半導體晶粒120、及第三半導體晶粒160可包括基本半導體層，其為例如主動電路層、基板層、內層界電層及金屬間介電層(未繪示)。
如第1圖所示，第一半導體晶粒110包括一基板102。基板102可為一矽基板。或者，基板102可為一絕緣體上覆矽基板。基板102可更包括各式電路(未繪示)。形成於基板102上的電路可為任何適合用於一特定應用的電路。
根據於一實施例，電路可包括各式n型金氧半導體(NMOS)及/或p型金氧半導體(PMOS)裝置，例如電晶體、電容、電阻、二極體、光電二極體、熔絲、及上述之類似物。可使電路內連線以執行一個或更多的功能。上述功能可包括記憶結構、處理結構、感測器、放大器、配電器、輸入/輸出電路、或上述之類似物。一般技藝人士能理解的是，以上範例僅是為了更進一步說明本揭露的應用，且並不意圖限定本發明。
形成一隔離層104於基板102上。隔離層104可由例如一低介電常數材料製成，其中低介電常數材料為例如氧化矽。可藉由任何已知的合適方法形成隔離層104，例如藉由旋轉塗佈、化學氣相沉積、及電漿輔助化學氣相沉積。應注意的是，一般技藝人士能理解的是，隔離層104可更包括複數個介電層。
形成一重分佈層(redistribution layer,RDL)106於隔離層104上。第一半導體晶粒110的主動電路層(未繪示)可藉由RDL層106橋接，使第一半導體晶粒110的主動電路層可電性耦合至半導體晶粒110的輸入/輸出端。複數個凸塊下金屬結構108形成於RDL層106的頂部。形成內連線凸塊112、114、及116於凸塊下金屬結構108的頂部。凸塊下金屬結構108可在提供低電阻之電性連接的同時，幫助避免內連線凸塊(例如內連線凸塊112)以及第一半導體晶粒110的積體電路之間的擴散。內連線凸塊(例如內連線凸塊112)提供一種有效的方式以連接第一半導體晶粒110與外部電路(未顯示)。內連線凸塊為第一半導體晶粒110的輸入/輸出端。根據一實施例，內連線凸塊(例如內連線凸塊112)可為複數個焊球。或者，內連線凸塊可為複數個基板柵格陣列(land grid array,LGA)焊墊。
第1圖更顯示在每個半導體晶粒的基板上可有四個階梯式凹陷。舉例來說，第一半導體晶粒110可包括分別位於第一半導體晶粒110之主體四側邊的四個階梯式凹陷。特別是第一半導體晶粒110的的兩個階梯式凹陷被顯示於沿著虛線x-x’剖開的第一剖面。類似地，第一半導體晶粒110的其他兩個階梯式凹陷顯示於沿著虛線y-y’剖開的第一剖面。根據一實施例，階梯式凹陷具有一垂直凹陷深度a1，其範圍為約20微米到約300微米。階梯式凹陷長度b1的範圍從約20微米到約200微米。以下將配合第2圖詳細描述形成階梯式凹陷的製程。
第2圖顯示根據一實施例產生階梯式凹陷的製程。在一兩步驟切割製程中，根據於一晶圓202本身的切割圖案切割該晶圓202。一第一切割鋸(dicing saw)(未繪示)切割穿過隔離層104的整個厚度且切割進入基板102約100微米。第一切割鋸(未繪示)的刀片的厚度為約40微米到約400微米。如此一來，形成一溝槽201於基板102中。晶圓204顯示可有複數個積體電路埋設其中，且每一個積體電路都被溝槽(例如溝槽201)圍繞。再者，使用一具有薄刀片的第二切割鋸(未繪示)切割穿過基板102的整個厚度。如此一來，半導體晶粒(例如半導體晶粒210)從晶圓206分離。
此種兩步驟切割製程所形成的是一半導體晶粒(例如半導體晶粒210)，其分別在主體之四側邊具有四個階梯式凹陷。應注意的是，在先前範例中使用的尺寸之選擇僅為示範說明用，且並不意圖限定各種實施例使其具有特定的尺寸。一般技藝人士可認知有許多變化例、替代例、或改良例。舉例來說，可藉由控制第一切割步驟的切割深度或者使用一具有不同刀片寬度的切割鋸來調整溝槽的尺寸以及階梯式凹陷的尺寸。應注意的是，雖然在上述範例中是使用兩個切割鋸來產生階梯式凹陷，一般技藝人士將可認知到可藉由其他切割工具產生階梯式凹陷，例如藉由雷射切割工具。雷射切割工具的操作原理為習知，且因此不在此詳細討論。
第3-7圖為根據一實施例在製造三維積體電路的中間階段之剖面示意圖。第3圖顯示在一支撐晶圓上堆疊複數個半導體晶粒的製程。在第2圖所示的兩步驟切割製程之後，半導體晶粒210及220被翻面，且進一步藉由一回焊製程被接合至支撐晶圓310上。支撐晶圓310或可被稱作一封裝基板。封裝基板可由陶瓷材料、有機材料等製成。如第3圖所示，支撐晶圓310可包括複數個埋設於支撐晶圓310之基板中的導孔。在將半導體晶粒210及220接合至支撐晶圓310上之後，藉由一位於支撐晶圓上的RDL層所形成的導電通道使半導體晶粒(例如半導體晶粒210)的主動電路與支撐晶圓310的導孔電性耦合，其中內連線凸塊連接於支撐晶圓310及半導體晶粒(例如半導體晶粒210)之間。
第4圖顯示一三維積體電路之剖面示意圖，其中三維積體電路具有一底膠材料(underfill)形成於半導體晶粒與支撐晶圓之間。一底膠材料402可形成於支撐晶圓302與複數個設置於晶圓302頂部的半導體晶粒(例如第一半導體晶粒102)之間隙中。根據一實施例，底膠材料402可為一環氧樹脂，其被發配至支撐晶圓302與第一半導體晶粒102之間隙中。可以液體的形式塗覆環氧樹脂，且其可在一固化製程後硬化。
如第4圖所示，底膠材料層402的高度取決於階梯式凹陷(例如階梯式凹陷404)。這也就是說，使底膠材料層402的最高高度受限於此種階梯式凹陷。如第4圖所示，第一半導體晶粒210的一頂部非凹陷部分、第一半導體晶粒210的一凹陷、第二半導體晶粒220的頂部非凹陷部分、及第二半導體晶粒220的一凹陷被埋在底膠材料層402中。根據另一實施例，底膠層402可由可固化材料製成，例如聚合物基材料、樹脂基材料、聚醯亞胺層、環氧樹脂、及上述任意組合。底膠層402可由一旋轉塗佈製程、乾膜壓合(dry film lamination)製程、及/或上述之相似製程形成。使用底膠材料(例如底膠材料402)的一個優點是底膠材料402幫助避免晶圓堆疊裂開。再者，另一優點是底膠材料402可在晶圓堆疊400的製程中幫助降低機械及熱應力。
第5圖顯示一三維積體電路之剖面示意圖，其中三維積體電路具有一形成於晶圓堆疊頂部的成形化合物層(molding compound layer)。如第5圖所示，第一半導體晶粒210及第二半導體晶粒220埋在一成形化合物層502中。成形化合物層502可由可固化材料製成，例如聚合物基材料、樹脂基材料、聚醯亞胺層、環氧樹脂、及上述任意組合。可由一旋轉塗佈製程、射出成型製程、及/或其相似製程形成成形化合物層502。為了在例如晶圓堆疊背側研磨製程的製程步驟中可靠地處理操作支撐晶圓302及置於其上的半導體晶粒(例如第一半導體晶粒210)，使用成形化合物層502使支撐晶圓302及在支撐晶圓頂部的半導體晶粒不裂開、折彎(bending)、翹曲(warping)等。
第6圖顯示根據一實施例一晶圓堆疊背側的研磨製程。半導體晶粒210及220的背側經過一薄化製程。可實施一機械研磨製程(mechanical grinding process)、一化學研磨製程(chemical polishing process)、一蝕刻製程等作為薄化製程。藉由實施薄化製程，半導體晶粒210及220的背側可被研磨使半導體晶粒210及220具有約次100微米(sub-100μm)的厚度。根據一實施例，可減少半導體晶粒210及220的厚度至約20微米到約500微米。
第7圖顯示三維積體電路在支撐晶圓研磨製程後的剖面示意圖。相似於半導體晶粒的背側研磨製程，實施薄化製程以研磨支撐晶圓302直到埋設導孔(例如導孔312)的端點被暴露。接著，形成隔離層722以及重分佈層702、704、706、708於支撐晶圓302新被研磨的背側頂部。
可形成複數個凸塊下金屬結構(未繪示)於重分佈層702、704、706、708的頂部。凸塊下金屬結構可在提供低電阻之電性連接的同時幫助避免焊球與多晶片半導體裝置的積體電路之間的擴散。形成複數個凸塊712於凸塊下金屬結構的頂部。可形成一些凸塊712於導孔(例如導孔312)被暴露的端點頂部上。應注意的是，可形成凸塊712於導孔被暴露的端點頂部上之外的其他區域，且藉由重分佈層704與導孔(例如導孔314)重新連接。
第8圖顯示根據另一實施例一晶圓在兩步驟切割製程後的剖面示意圖。如第8圖所示，除了在切割製程的第二步驟時x-x’方向的溝槽的切割是藉由一薄刀片834沿著溝槽的一側壁而非溝槽的中線切割穿過之外，晶圓800的剖面視圖與第1圖所示晶圓100的剖面視圖相似。因此一半導體晶粒可包括三個階梯式凹陷而非第1圖所示的四個階梯式凹槽。舉例來說，半導體晶粒802可包括三個階梯式凹陷。不具有階梯式凹陷半導體晶粒802的一側邊以虛線圓812表示。晶圓的切割製程為習知，且因此不在此詳細討論。
第9圖顯示根據又一實施例一晶圓在兩步驟切割製程後的剖面示意圖。如第9圖所示，除了在切割製程的第二步驟時溝槽的切割是藉由一薄刀片934沿著溝槽的一側壁而非溝槽的中線切割穿過之外，晶圓900的剖面圖與第1圖所示晶圓100的剖面圖相似。因此一半導體晶粒可包括兩個階梯式凹陷。舉例來說，半導體晶粒902可包括兩個階梯式凹陷。半導體晶粒902不具有一階梯式凹陷的側邊以虛線圓912及916表示。
第10圖顯示根據又一實施例一晶圓在兩步驟切割製程後的剖面示意圖。如第10圖所示，除了在切割製程的第一步中，僅於y-y’方向的溝槽中使用厚刀片1032之外，晶圓1000的剖面圖與第1圖所示晶圓100的剖面圖相似。再者，在切割製程的第二步驟中，y-y’方向的溝槽是藉由一薄刀片1034沿著溝槽的一側壁而非溝槽的中線切割穿過。如此一來，半導體晶粒可包括一階梯式凹陷。舉例來說，半導體晶粒1002可包括一個階梯式凹陷。半導體晶粒1002不具有一階梯式凹陷的側邊以虛線圓1012及1014表示。
第11圖顯示根據又一實施例一晶圓在切割製程後的剖面示意圖。如第11圖所示，除了半導體1102的主體的每一側邊可具有一斜面而非一階梯式凹陷之外，晶圓1100的剖面圖與第1圖所示晶圓100的剖面圖相似。相似地，第12圖顯示根據又一實施例一晶圓在切割製程後的剖面示意圖。如第12圖所示，除了半導體1202的主體的每一側邊可具有一曲面(例如曲面1212、曲面1214)而非一階梯式凹陷之外，晶圓1200的剖面圖與第1圖所示晶圓100的剖面圖相似。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
再者，本說明書所敘述的製程、機器、產品、物質組成、手段、方法、及步驟之特定實施例並非用以限定本揭露的範疇。一般技藝人士已能從本揭露理解的是，可根據本揭露使用與在此敘述之相對應實施例實質執行相同功能或達到實質上相同的結果之現有的或以後發展的製程、機器、產品、物質組成、手段、方法、或步驟。因此，所附申請專利範圍並不意圖包括上述製程、機器、產品、物質組成、手段、方法、或步驟。
a1．．．垂直凹陷深度
b1．．．階梯式凹陷長度
x-x’、y-y’．．．虛線
100、204、206、800、900、1000、1100、1200．．．晶圓
102．．．基板
104．．．隔離層
106．．．重分佈層
108．．．凸塊下金屬結構
110．．．第一半導體晶粒
112、114、116．．．內連線凸塊
120．．．第二半導體晶粒
160．．．第三半導體晶粒
201．．．溝槽
210、220、802、902、1002．．．半導體晶粒
310．．．支撐晶圓
312．．．導孔
400．．．晶圓堆疊
402．．．底膠材料
404．．．階梯式凹陷
502．．．成形化合物層
702、704、706、708．．．重分佈層
712．．．凸塊
722．．．隔離層
812、912、916、1012、1014．．．虛線圓
934、1034．．．薄刀片
1032．．．厚刀片
1102、1202．．．半導體
1112、1114．．．斜面
第1圖顯示根據一實施例一晶圓在切割製程後的剖面示意圖。
第2圖顯示根據一實施例產生階梯式凹陷的製程。
第3圖顯示在一支撐晶圓上堆疊複數個半導體晶粒的製程。
第4圖顯示一三維積體電路之剖面示意圖，其中三維積體電路具有一底膠材料形成於半導體晶粒與支撐晶圓之間。
第5圖顯示一三維積體電路之剖面示意圖，其中三維積體電路具有一形成於晶圓堆疊頂部的成形化合物層。
第6圖顯示，根據一實施例一晶圓堆疊背側的研磨製程。
第7圖顯示三維積體電路在支撐晶圓研磨製程後的剖面示意圖。
第8圖顯示根據另一實施例一晶圓在兩步驟切割製程後的剖面示意圖。
第9圖顯示根據又一實施例一晶圓在兩步驟切割製程後的剖面示意圖。
第10圖顯示根據又一實施例一晶圓在兩步驟切割製程後的剖面示意圖。
第11圖顯示根據又一實施例一晶圓在切割製程後的剖面示意圖。
第12圖根據又一實施例一晶圓在切割製程後的剖面示意圖。
a1．．．垂直凹陷深度
b1．．．階梯式凹陷長度
x-x’、y-y’．．．虛線
100．．．晶圓
102．．．基板
104．．．隔離層
106．．．重分佈層
108．．．凸塊下金屬結構
110．．．第一半導體晶粒
112、114、116．．．內連線凸塊
120．．．第二半導體晶粒
160．．．第三半導體晶粒

Claims (10)

  1. 一種半導體裝置，包括：一半導體基板，具有一凹陷部分及一非凹陷部分，其中一第一凹陷位於該凹陷部分；一隔離層，形成於該半導體基板的非凹陷部分上；一重分佈層，形成於該隔離層上；一凸塊下金屬結構，形成於該重分佈層上；及一第一凸塊，形成於該凸塊下金屬結構上。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一凹陷在該半導體裝置的一第一側具有一階梯形狀。
  3. 如申請專利範圍第2項所述之半導體裝置，其中更包括：一第二凹陷，於該半導體裝置的一第二側具有該階梯形狀；及一第三凹陷，於該半導體裝置的一第三側具有該階梯形狀。
  4. 如申請專利範圍第1項所述之半導體裝置，其中更包括：一第二凹陷，於該半導體裝置的一第二側具有該階梯形狀。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該第一凹陷具有一斜面形狀或一曲面形狀。
  6. 一種半導體裝置的製造方法，包括：使用一第一切割鋸切割進入一半導體晶粒一第一切割深度；使用一第二切割鋸切割該半導體晶粒，使該第二切割鋸具有一與該第一切割鋸的一第一刀片不同的第二刀片；形成一階梯式凹陷於該半導體晶粒的一側邊；將該半導體晶粒翻面；及將該半導體晶粒的一第一側邊連接至一封裝基板的一第一側邊。
  7. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中更包括：形成一底膠層於該半導體晶粒與該封裝基板之間，其中該底膠層位於該階梯式凹陷下方。
  8. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中更包括：形成一化合物層於該封裝基板上，其中該半導體晶粒埋於該化合物層中。
  9. 如申請專利範圍第6項所述之半導體裝置的製造方法，其中更包括：薄化該封裝基板的一第二側邊直到暴露複數個導孔。
  10. 一種半導體裝置，包括：一第一半導體晶粒，具有：一第一半導體基板，具有一第一凹陷部份，一第一頂部非凹陷部分、及一第一側邊非凹陷部分，其中一第一階梯式凹陷位於該第一凹陷部份；一第一隔離層，形成於該第一半導體基板的第一頂部非凹陷部份上；一第一凸塊，形成於該第一隔離層上；一第二半導體晶粒，具有：一第二半導體基板，具有一第二凹陷部份、一第二頂部非凹陷部份、及一第二側邊非凹陷部份，其中一第二階梯式凹陷位於該第二凹陷部份；一第二隔離層，形成於該第二半導體基板的第二頂部非凹陷部份；一第二凸塊，形成於該第二隔離層上；一封裝基板，具有：一第一側邊，連接至該第一半導體晶粒的第一凸塊及該第二半導體晶粒的第二凸塊；一第二側邊，具有一第三凸塊；及一底膠層，形成於該第一半導體晶粒、該第二半導體晶粒、及該封裝基板之間，其中該第一頂部非凹陷部份、該第一凹陷部份、該第二頂部非凹陷部份及該第二凹陷部份埋於該底膠層中。
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US8772929B2 (en) 2014-07-08
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US20130119533A1 (en) 2013-05-16

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