201216793 六、發明說明-: 【發明所屬之技術領域】 本發明是關於一種將電子元件埋設於絕緣基材内的内 藏元件之基板。 【先前技術】 内藏元件之基板在專利文獻丨中得到揭示。專利文獻j 中所記載之内藏元件之基板包括絕緣基材、形成於其兩面 的導體電路及電子元件。此電子元件為—種内藏元件，其 埋設於絕緣基材之中，與端子部設置於基板側之連接端子 部連接，#連接至導體料。用來與此内^元件之基板的 連接端子連接的連接端子部在專利文獻1中被記載為使用 阻焊層形成的範例。 然而，阻焊層在篩網印刷後藉由曝光、顯影、紫外線 硬化或熱硬化而形成。因此’當在相鄰之内藏元件之間形 成阻焊層時’難以縮小内藏元件之間的間隔。換言之，難 以針對基板表面達到元件之高密度化。又，如專利文獻i 所不，當藉由轉印法製作基板時，導體圖樣設計得比與電 子元件連接之連接部大，所以，也難以達到配線之高密度 化。 [專利文獻1]特開2010-27917號公報 【發明内容】 【發明所欲解決的課題】 201216793 本發明為考慮上述習知技術之發明，目的在提供一種 内藏元件之基板，其可縮小内藏元件之間的間隔而配置， 於是’可達到元件之高密度化（提高元件之封裝密度），再 者’也可達到配線之高密度化。 【用以解決課題的手段】 為達成上述目的，在本發明中，提供一種内藏元件之 基板’其特徵在於：包括形成板狀的樹脂製之絕緣基材、 埋設於該絕緣基材内的複數個電子元件、該元件透過接合 材料封裝於其中一面且上述其中一面及周側面被上述絕緣 基材覆蓋的板狀之導電墊片及形成於該導電墊片之另一面 且相對於上述另一面之外緣形成於内側的導體圖樣。 更好的設計為，上述導體圖樣之形成方式為使上述另 一面之一部分露出，則會更好。 又，更好的設計為，在上述元件上設有複數個連接端 上述導電墊片透過上述接合材料與上述連接端子作電 子連接，藉由連接至各連接端子的各個上述導電墊片形成 墊片單元’在相鄰之上述墊片單元之間，僅存在上述絕緣 基材。 又，更好的設計為，上述連接端子設置於上述元件之 兩端部，上述墊片單元之配設為墊片對，與上述導電墊片 相向。 再者，更好的設計$，在形成上述墊片肖之上述導電 墊片之間’設有用來保持上述元件與上述絕緣基材之表面 之間隔的隔片。 201216793 又，上述接合材料為銲錫，上述隔片為阻焊膜。 .【發明效果】 本發明之内藏元件之基板包括絕緣基材、複數個元 件、導電塾片及導體圖樣，導體圖樣形成於比作為導電整 片之另一面的圖樣形成面之外緣還小的範圍。於是，不越 過導電墊片之外緣形成導體圖樣，各元件之間的間隔根據 導電塾片之大小來決定。藉此，可縮小導電塾片之間的間 隔而配置，所以，可提高元件之封裝密度。此時，導體圖 樣若形成於比另-面（圖樣形成面）之外緣還小的範圍，亦 即，使另一面之一部分露出，可確實提高元件之封裝密度。 又，藉由7G件之連接端子上分別連接的導電墊片形成 塾片對，在此墊片對之間僅存在絕緣基材。於是，習知之 阻焊層無法形成’所以’可縮小墊片對之間的間隔。因此， 可提高元件之封裝密度。此外，當形成整片對的有時是電 阻、電容器等雙端子元件，若為連接端子更多的多端子元 件（電晶體、1(：、1^等）’則藉由連接至各個連接端子的導 電墊片形成墊片單元。藉由墊片單元，也能發揮相同的效 果。 又’在形成墊片對之導電圖樣之間，設有用來保持元 :與絕緣基材之表面之間隔的隔片，藉此，可防止元件隱 ’又。特別是當連接材料為銲錫時’效果明顯。 用 阻焊膜。 且便用 【實施方式】 r* 201216793 如第1圖所示，本發明之内藏元件之基板1包括板狀之 絕緣基材2。此絕緣基材2為樹脂製，例如預浸材料。此絕 緣基材2埋設於電子元件3中。此元件3埋設於絕緣基材2 内。在此絕緣基材H步埋設板狀之導電圖樣4。具 體而a ’導電墊片4之其中-面(元件封裝面乜)及周側面被 絕緣基材2覆蓋.，另—面與絕緣純2之表面形成無段差狀 態。亦即，導電塾片4之另一面(後述之圖樣形成面嫩絕 緣基材2露出。導電墊片可為鍍金墊片。 上述之元件3封裝於此導電墊片4之其中一面（元件封 裝面4a)。具體而言，對應元件3之兩端部上分別設置的連 接端子5分別配置導電墊片4，透過接合材料6作電子連接。 接合材料6可使用銲錫或導電性之接著劑。又，藉由封裝同 一疋件3之各個導電墊片4(與各個連接端子5連接且為2個 組的導電塾片4)形成塾片對8。此外，在圖例中，是以電 阻電各器等雙端子元件為範例，然而，在電晶體、〗c、 LSI等連接端子更多之多端子元件中，墊片對8為墊片單 元。具體而言，墊片單元由3個以上之導電墊片4所構成。 在導電墊片4之另一面（圖樣形成面4b)上，，形成導體圖 樣7 °在第1圖及第2圖的範例中，相對於圖樣形成面4b之外 緣’形成導體圖樣7。如此，可在與圖樣形成面4b之外緣同 等或比外緣小的範圍内形成導體圖樣7，所以，無法越過導 電塾片4之外緣形成導體圖樣7。於是，各元件3之間的間 隔’亦即’墊片對8之間的間隔根據導電墊片4之大小來決 定。換言之，導體圖樣7之形成方式無法從導電墊片4露出， 201216793 所以，可縮小導電墊片4(實際上為墊片對8)之間的間隔而 配置。藉此，可針對元件3之製品基板提高封裝密度。 此時，如第1圖、第2圖所示，導體圖樣7若形成於比另 -面(圖樣形成面4b)之外緣小的範圍，亦即，形成方式為 使另一面之一部分露出，確實可提高元件3之封裝密度。 如第2圖所不，即使在元件3之間設置與導體圖樣7連接 之配線部9,可縮小元件3與配線部9之間的間隔於是可提 咼π件3之封裝密度。又，只要是可設置配線部9之位置， 就可靠近導電墊片4，所以，可達到配線之高密度化。 另一方面’在相鄰之墊片對8之間，僅存在絕緣基材2。 亦即，在相鄰之墊片對8之間，無法形成習知之阻焊曾。因 此墊片對8之間的間隔得以縮小。此種構造有助於提高元 件3之封裝密度。又，在形成墊片對8之導電墊片4之間，亦 即，元件3之下側，設有隔片1〇(在圖中記載為僅在一部分 之π件3設置隔片1〇)。此隔片1〇可用來保持元件3與絕緣基 材2之表面的間隔。藉由設置此隔片】〇，可防止元件3隱沒。 特別是當接合材料為銲錫時，效果顯著。隔片1〇宜使用阻 焊膜。亦可藉由變更此隔片10之形狀、高度來控制元件之 设置兩度。 以下將根據第3圖至第9圖說明本發明之内藏元件之基 板之製造方法之一例。 首先’如第3圖所示’在支持板η上形成導電層12。支 持板11可為SUS板。導電層2可為由鍍銅等所構成的銅薄 膜。接著，如第4圖所示，在導電層12上載置上述之導電墊 201216793 片4。當導電墊片4為鍍金墊片時，此導電墊片4對銅製之墊 片施以軟蝕刻處理，之後，施以鎳厚度l//m〜10//ιη(最好 為5//m)、金厚度〇.〇iym〜1//m(最好為〇〇3ym)的鍍金處 理。藉由軟蝕刻處理.，導電墊片4之表面若以表面粗度（Rz) 來表不時，為5/im，所以，形成平坦的形狀。此 外，作為對鍍金墊片7之表面進行平坦化處理的方法，亦可 使用微蝕刻、酸洗或電漿蝕刻。 另外，如第5圖所示，對導電層12之表面施以粗面化處 理，形成粗面12a。此粗面化處理之進行方式為.，使用黑化 還原處理、膠膜處理、CZ處理，針對導電層2之表面，對銅 表面進行蝕刻處理，形成有機皮膜。其表面粗度（Rz)為〇1 Am〜l〇vm。在此，所謂膠膜處理’是指使用at〇thch公司 所製造之藥液I進行的處理。纟由銅纟面之粗面化及 有機金屬皮膜之形成來提高樹脂密著性的處理。又，所謂 CZ處理，是指使用y、,夕公司所製造之藥液來進行的處理。 其為提高銅表面之粗面化及樹脂密著性的處理。 另外，如第6圖所示，在導電墊片4之元件封裝面4&配 置接合材料6。在圖中，表示出接合材料6為銲錫的範例。 另外，如第7圖所示，元件3之連接端子5與導電墊片4透過 接合材料6作電子連接。在圖例中，具體而言是進行回流焊 接。藉此，元件3封裝於導電墊片4上。此時，上述之粗面 12a形成於與導電墊片4之侧緣相接的位置’所以，可確實 防止焊接的擴張超過導電墊片4。換言之，可達到阻止藉由 粗面12a阻止和焊接之擴張的效果。於是’不需要形成^去 201216793 所使用之錫堤。由於不需要錫堤，所以，可縮小上述相鄰 之墊片對8之間的間隔。藉此’可縮小配置元件3的間隔， 進而提高元件3之封裝密度。又，由於不需要用來形成錫堤 之阻焊膜形成製程’所以製程可縮短，連帶也不需要使用 在該製程的材料，於是大大降低了成本。 另外’如第8圖所示’將元件3埋設於絕緣基材2内。具 體而言，導電層12與絕緣基材2之間夹持有元件3，相互壓 接導電層12與絕緣基材2。之後，去除支捋板11。 另外，如第9圖所示，在導電墊片4之圖樣形成面牝上 形成導體圖樣7。具體而言，去除導電層2之一部分而形成 導體圖樣7。此導體圖樣7對導電層12施以蝕刻處理而形 成此時，導電墊片4作為蝕刻阻劑，可防止接合材料6露 出。再者，可防止已封裝好之元件3之電子連接之可靠性下 降:此導體圖樣7如上所述，形成於與圖樣形成_之外緣 相等或比其小的範圍。在形成導電圖樣7的同時，可形成配 線部9。如此之外’在圖中表示出僅在基板之單面側形成導 體圖樣7的單面基板的範例，但本發明理所當然可應用於雙 面基板。X，本發明亦可應用於將以上組合起來之多層基 【圖式簡單說明】 第1圖為本發明之元件内藏基板的概略剖面圖。 第2圖為第1圖的a-a視圖。 第3圖為依序表示本發明 3之兀件内藏基板之製造方法 201216793 的概略圖。 第4圖' 圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 第5圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 第6圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 第7圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 第8圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 第9圖為依序表示本發明之元件内藏基板之製造方法 的概略圖。 【主要元件符號說明】 1内藏元件之基板 2絕緣基材 3元件 4導電墊片 4a元件封裝面（其中一面） 4b圖樣形成面（另一面） 5連接端子 6接合件 7導體圖樣 201216793 8墊片對 9配線部 10隔片 11支持板 12導電層 12 a粗面201216793 VI. Description of the Invention - [Technical Field] The present invention relates to a substrate in which an electronic component is embedded in an insulating component in an insulating substrate. [Prior Art] The substrate of the built-in element is disclosed in the patent document. The substrate of the built-in element described in Patent Document j includes an insulating base material, a conductor circuit formed on both surfaces thereof, and an electronic component. This electronic component is a built-in component which is embedded in an insulating base material, and is connected to a terminal portion of the terminal portion provided on the substrate side, and # is connected to the conductor material. The connection terminal portion for connecting to the connection terminal of the substrate of the internal component is described in Patent Document 1 as an example in which a solder resist layer is used. However, the solder resist layer is formed by screen exposure, development, ultraviolet curing or heat hardening after screen printing. Therefore, when a solder resist layer is formed between adjacent built-in elements, it is difficult to narrow the interval between the built-in elements. In other words, it is difficult to achieve high density of components for the surface of the substrate. Further, as in Patent Document 1, when the substrate is formed by the transfer method, the conductor pattern is designed to be larger than the connection portion to which the electronic component is connected, so that it is difficult to achieve high density of wiring. [Problem to be Solved by the Invention] 201216793 The present invention is an object of the above-described conventional technology, and an object of the invention is to provide a substrate having a built-in element which can be reduced in size Since the components are arranged at intervals, the density of the components can be increased (the package density of the components can be increased), and the wiring can be made higher in density. [Means for Solving the Problem] In order to achieve the above object, a substrate for a built-in element is provided, which is characterized in that it comprises a resin-made insulating substrate formed in a plate shape and embedded in the insulating substrate. a plurality of electronic components, the component is encapsulated on one side of the bonding material, and one of the one side and the circumferential side surface is covered by the insulating substrate and formed on the other side of the conductive spacer and opposite to the other side The outer edge is formed on the inner side of the conductor pattern. More preferably, it is preferable that the conductor pattern is formed in such a manner that one of the other surfaces is partially exposed. Moreover, it is better to provide a plurality of connecting ends on the component, wherein the conductive pad is electrically connected to the connecting terminal through the bonding material, and the spacer is formed by each of the conductive pads connected to each connecting terminal. The unit 'between the above-mentioned spacer units, only the above-mentioned insulating substrate exists. Further, it is preferable that the connection terminals are provided at both end portions of the element, and the spacer unit is disposed as a pair of pads facing the conductive pad. Further, a better design $ is provided between the above-mentioned conductive spacers forming the spacers, and a spacer for maintaining the distance between the above-mentioned elements and the surface of the insulating substrate is provided. 201216793 Further, the bonding material is solder, and the spacer is a solder resist film. [Effect of the Invention] The substrate of the built-in component of the present invention comprises an insulating substrate, a plurality of components, a conductive cymbal and a conductor pattern, and the conductor pattern is formed on a smaller outer edge than the pattern forming surface of the other surface of the conductive whole sheet. The scope. Thus, the conductor pattern is formed without crossing the outer edge of the conductive spacer, and the interval between the elements is determined according to the size of the conductive tab. Thereby, the interval between the conductive cymbals can be reduced and arranged, so that the packing density of the elements can be improved. At this time, if the conductor pattern is formed in a range smaller than the outer edge of the other surface (pattern forming surface), that is, a part of the other surface is exposed, the packing density of the element can be surely improved. Further, the pair of pads are respectively connected by the conductive pads respectively connected to the connection terminals of the 7G members, and only the insulating substrate exists between the pair of pads. Thus, the conventional solder resist layer cannot form 'so' to reduce the interval between the pair of spacers. Therefore, the packing density of the components can be increased. In addition, when forming a whole pair, it is sometimes a two-terminal element such as a resistor or a capacitor, and if it is a multi-terminal element (transistor, 1 (:, 1^, etc.) of a connection terminal, it is connected to each connection terminal. The conductive spacer forms a spacer unit. The same effect can be exerted by the spacer unit. Further, 'between the conductive patterns forming the spacer pair, there is provided a space for holding the element: the distance from the surface of the insulating substrate. The spacer can thereby prevent the component from being hidden. Especially when the connecting material is solder, the effect is obvious. The solder resist film is used. [Embodiment] r* 201216793 As shown in Fig. 1, the present invention The substrate 1 of the built-in component includes a plate-shaped insulating substrate 2. The insulating substrate 2 is made of a resin such as a prepreg. The insulating substrate 2 is embedded in the electronic component 3. The component 3 is embedded in the insulating substrate 2. In this case, the insulating substrate H is embedded with a plate-shaped conductive pattern 4. Specifically, the a-plane (component package surface 乜) and the circumferential side of the 'the conductive spacer 4 are covered by the insulating substrate 2. The surface of the insulating pure 2 forms a stepless state. That is, the conductive cymbal The other side of the surface (the pattern to be described later forms the surface of the insulating substrate 2 is exposed. The conductive spacer may be a gold-plated spacer. The above-mentioned component 3 is packaged on one side of the conductive spacer 4 (element package surface 4a). Specifically The conductive pads 4 are respectively disposed on the connection terminals 5 respectively provided at the opposite ends of the corresponding component 3, and are electrically connected through the bonding material 6. The bonding material 6 may be solder or a conductive adhesive. Each of the conductive pads 4 of the member 3 (the two types of conductive tabs 4 connected to the respective connection terminals 5) form a pair of dies. Further, in the illustrated example, a two-terminal element such as a resistor is used as an example. However, in a plurality of terminal elements such as a transistor, a c, or an LSI, the spacer pair 8 is a spacer unit. Specifically, the spacer unit is composed of three or more conductive spacers 4. On the other surface (pattern forming surface 4b) of the conductive spacer 4, the conductor pattern 7 is formed. In the examples of Figs. 1 and 2, the conductor pattern 7 is formed with respect to the outer edge ' of the pattern forming surface 4b. , can be equal to or the outer edge of the outer surface of the pattern forming surface 4b The conductor pattern 7 is formed in the range, so that the conductor pattern 7 cannot be formed beyond the outer edge of the conductive sheet 4. Thus, the interval between the elements 3, that is, the interval between the spacers 8 is based on the conductive spacer 4 In other words, the formation pattern of the conductor pattern 7 cannot be exposed from the conductive spacer 4, and 201216793 can therefore be arranged to reduce the interval between the conductive pads 4 (actually the spacer pair 8). The package density is increased for the product substrate of the element 3. At this time, as shown in Fig. 1 and Fig. 2, the conductor pattern 7 is formed in a range smaller than the outer edge (the pattern forming surface 4b), that is, The formation method is such that one part of the other surface is partially exposed, and the packing density of the element 3 can be surely increased. As shown in Fig. 2, even if the wiring portion 9 connected to the conductor pattern 7 is provided between the elements 3, the element 3 and the wiring portion can be reduced. The spacing between 9 can then increase the packing density of the π piece 3. Moreover, as long as the position of the wiring portion 9 can be provided, the conductive spacer 4 can be brought close to each other, so that the wiring can be made denser. On the other hand, only the insulating substrate 2 is present between adjacent pairs of spacers 8. That is, a conventional solder mask cannot be formed between adjacent pairs of spacers 8. Therefore, the interval between the spacer pairs 8 is reduced. This configuration contributes to an increase in the packing density of the component 3. Further, between the conductive spacers 4 forming the spacer pair 8, that is, on the lower side of the element 3, a spacer 1 is provided (in the figure, only a part of the π-piece 3 is provided with the spacer 1). . This spacer 1 can be used to maintain the spacing of the component 3 from the surface of the insulating substrate 2. By setting this spacer, you can prevent component 3 from being hidden. Especially when the bonding material is solder, the effect is remarkable. A solder mask should be used for the spacer 1. It is also possible to control the setting of the element by two degrees by changing the shape and height of the spacer 10. Hereinafter, an example of a method of manufacturing a substrate of the built-in element of the present invention will be described based on Figs. 3 to 9 . First, a conductive layer 12 is formed on the support plate η as shown in Fig. 3. The support plate 11 can be a SUS plate. The conductive layer 2 may be a copper film made of copper plating or the like. Next, as shown in Fig. 4, the above-mentioned conductive pad 201216793 is placed on the conductive layer 12. When the conductive pad 4 is a gold-plated pad, the conductive pad 4 is subjected to a soft etching treatment on the copper pad, and then a nickel thickness of l//m 10 10//m is preferably applied. ), gold thickness 〇. 〇iym ~ 1 / / m (preferably 〇〇 3ym) gold plating treatment. By the soft etching treatment, the surface of the conductive spacer 4 is 5/im when it is expressed by the surface roughness (Rz), so that a flat shape is formed. Further, as a method of planarizing the surface of the gold plating pad 7, micro etching, pickling or plasma etching may be used. Further, as shown in Fig. 5, the surface of the conductive layer 12 is subjected to a roughening treatment to form a rough surface 12a. This roughening treatment is carried out by using blackening reduction treatment, film treatment, and CZ treatment, and etching the copper surface on the surface of the conductive layer 2 to form an organic film. The surface roughness (Rz) is 〇1 Am~l〇vm. Here, the "film treatment" means a treatment using the chemical solution I produced by Atthth Corporation.处理 The treatment of improving the resin adhesion by roughening the copper surface and forming an organic metal film. In addition, the CZ process refers to a process performed using a chemical liquid manufactured by y, and a company. This is a treatment for improving the roughening of the copper surface and the resin adhesion. Further, as shown in Fig. 6, the bonding material 6 is disposed on the element package surface 4& of the conductive spacer 4. In the figure, an example in which the bonding material 6 is solder is shown. Further, as shown in Fig. 7, the connection terminal 5 of the element 3 and the conductive spacer 4 are electrically connected through the bonding material 6. In the illustration, specifically, reflow soldering is performed. Thereby, the component 3 is encapsulated on the conductive spacer 4. At this time, since the rough surface 12a is formed at a position in contact with the side edge of the conductive spacer 4, it is possible to surely prevent the expansion of the solder from exceeding the conductive spacer 4. In other words, the effect of preventing the expansion by the rough surface 12a and the welding can be achieved. So, there is no need to form a tin bank used in 201216793. Since the tin bank is not required, the interval between the adjacent pairs of spacers 8 can be reduced. Thereby, the interval between the elements 3 can be reduced, and the packing density of the elements 3 can be increased. Further, since the solder resist film forming process for forming the solder bank is not required, the process can be shortened, and the material used in the process is not required to be attached, so that the cost is greatly reduced. Further, the element 3 is embedded in the insulating base material 2 as shown in Fig. 8. Specifically, the element 3 is sandwiched between the conductive layer 12 and the insulating substrate 2, and the conductive layer 12 and the insulating substrate 2 are pressed against each other. Thereafter, the support plate 11 is removed. Further, as shown in Fig. 9, a conductor pattern 7 is formed on the pattern forming surface of the conductive spacer 4. Specifically, a portion of the conductive layer 2 is removed to form a conductor pattern 7. This conductor pattern 7 is formed by etching the conductive layer 12, and the conductive spacer 4 serves as an etching resist to prevent the bonding material 6 from being exposed. Further, the reliability of the electronic connection of the packaged component 3 can be prevented from being lowered: the conductor pattern 7 is formed in a range equal to or smaller than the outer edge of the pattern forming layer as described above. The wiring portion 9 can be formed while forming the conductive pattern 7. In this case, an example of a single-sided substrate in which the conductor pattern 7 is formed only on one side of the substrate is shown, but the present invention is of course applicable to a double-sided substrate. X, the present invention can also be applied to a multilayer base in which the above is combined. [Brief Description of the Drawings] Fig. 1 is a schematic cross-sectional view showing a substrate built in the component of the present invention. Figure 2 is a-a view of Figure 1. Fig. 3 is a schematic view showing a method of manufacturing the substrate built in the third embodiment of the present invention in the order of 201216793. Fig. 4 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order. Fig. 5 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order. Fig. 6 is a schematic view showing the method of manufacturing the element-embedded substrate of the present invention in order. Fig. 7 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order. Fig. 8 is a schematic view showing a method of manufacturing the element-embedded substrate of the present invention in order. Fig. 9 is a schematic view showing the method of manufacturing the element-embedded substrate of the present invention in order. [Main component symbol description] 1 Built-in component substrate 2 Insulation substrate 3 component 4 Conductive pad 4a Component package surface (one side) 4b pattern forming surface (the other side) 5 Connection terminal 6 bonding member 7 Conductor pattern 201216793 8 pad Sheet pair 9 wiring portion 10 spacer 11 support plate 12 conductive layer 12 a rough surface