TW201212168A - Memory architecture of 3D array with diode in memory string - Google Patents
Memory architecture of 3D array with diode in memory string Download PDFInfo
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- TW201212168A TW201212168A TW100120044A TW100120044A TW201212168A TW 201212168 A TW201212168 A TW 201212168A TW 100120044 A TW100120044 A TW 100120044A TW 100120044 A TW100120044 A TW 100120044A TW 201212168 A TW201212168 A TW 201212168A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
201212168 六、發明說明： 【發明所屬之技術領域】 本發明係關於高密度記憶裝置，特別是關於具有多層平面 記憶胞的記憶裝置以提供三維陣列。 【先前技術】 當積體電路中的裝置之臨界尺寸縮減至通常記憶胞技術的 極限時’設計者則轉而尋求記憶胞的多重堆疊平面技術以達成 更高的儲存密度，以及每一個位元較低的成本。舉例而言，薄 膜電晶體技術已經應用在電荷捕捉記憶體之中，可參閱如賴等 人的論文 A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Device Meeting, 2006 年 12 月 11 〜13 日；及 Jung 等人的論文"xjjjfee Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm201212168 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to high density memory devices, and more particularly to memory devices having multiple layers of planar memory cells to provide a three dimensional array. [Prior Art] When the critical size of the device in the integrated circuit is reduced to the limit of the usual memory cell technology, the designer turns to the multi-stack plane technology of the memory cell to achieve a higher storage density, and each bit Lower cost. For example, thin film transistor technology has been applied to charge trapping memory. See, for example, A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Device Meeting, December 11-13, 2006; and Jung et al.'s paper "xjjjfee Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm
Node”，IEEE Int’l Electron Device Meeting, 2006 年 12 月 11 〜13 曰。 此外，交會點陣列技術也已經應用在反熔絲記憶體之中， 可參閱如 Johnson 等人的論文”512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells", IEEE J. of Solid-state Circuits, vol. 38, no. 11, 2003 年 Π 月。在 Johnson 等 人所描述的設計中’多層字元線及位元線被使用，其具有記憶 元件於交會點。此記憶元件包含P+多晶矽陽極與字元線連 接，及n+多晶矽陰極與位元線連接，而陰極與陽極之間由反 私絲材料分隔。 在由賴、Jung、等人所描述的製程中，每一個記憶層使用 201212168 一 多道關鍵微影步驟。因此，製造此裝置所需的闕鍵微:影步驟的 數目會是其所使用記憶層數目的倍數。因此，雖然可以藉由使 用三維陣列達到較高的密度，然而較高的製造成本也限制了此 技術的使用範圍。 另一種使用垂直反及閘記憶胞結構於電荷捕捉記憶體中的 技術也已經在Tanaka等人的論文"Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory ", 2007 Symposium on VLSI Technology Digest ofNode", IEEE Int'l Electron Device Meeting, December 11 ~ 13 2006 2006. In addition, the intersection point array technology has also been applied to anti-fuse memory, see the paper by Johnson et al. "512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells", IEEE J. of Solid-state Circuits, vol. 38, no. 11, 2003. In the design described by Johnson et al., 'multilayer word lines and bit lines are used, which have memory elements at the intersection. The memory element includes a P+ polysilicon anode connected to the word line, and an n+ polysilicon cathode connected to the bit line, and the cathode and anode are separated by an anti-wire material. In the process described by Lai, Jung, et al., each memory layer uses 201212168 as a key lithography step. Therefore, the number of 阙 key micro-shadow steps required to fabricate the device will be a multiple of the number of memory layers used. Therefore, although higher density can be achieved by using a three-dimensional array, higher manufacturing costs also limit the scope of use of this technology. Another technique for using vertical inverse gate memory cell structures in charge trapping memory has also been published in the paper by Tanaka et al. "Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory ", 2007 Symposium on VLSI Technology Digest of
Technical Papers，pp. 14〜15,2007 年 6 月 12〜14 日，有所描述。 於Tanaka等人描述的結構中，包括多閘極場效電晶體結構， 其具有類似反及閘操作的垂直通道，使用矽氧氮氧矽 (SONOS)型態電荷捕捉記憶胞結構，以在每一個閘極/ 垂直通道介面處產生儲存位置。此記憶結構是基於安排 2為垂直通道的柱狀半導體材料而構成多閘極記憶胞，且 有-較低的選擇閘極靠近基板，及一較高的選擇間極於其上 方。複數個纟平控制閘極係使用與柱狀物相 形成。作為水平控制_平面電極層並 ==:而!每一個，憶胞而言仍是^ 鍵锨衫步驟。此外，此方法的多層結構 仍是有所限制，其係由例如是垂直通道&電性、所= 的程式化及抹除操作等因素來決定。 吏用 因此需要提供一種低製造成本的三維 構，其包括可靠、非常小記憶元件。隹積體電路記憶體 【發明内容】 此處所描職術為一種記憶裝置，包含一積體電路基板 201212168 複數個長條半導體材料堆疊，複數條字元線，記憶元件及二極 ，。此複數個長條半導體材料堆疊延伸出該積體電路基板，該 複數個堆疊具有山脊狀且包括至少兩個長條半導體材料由絕 ，層分隔而成為複數個平面位置中的不同平面位置。此複數條 字元線安排成正交於該複數個堆叠之上，且與該複數個堆疊順 形，如此於該複數個堆疊的表面與該複數條字元線交會點建立 -個三維陣顺交會區域。此記憶元件於該交會區域，盆經由 該長條半導體材料與該複數條字元線建立可存取之該三 成串列介於位元線結構與源極線 無㈣祕，齡於記憶射顺位元線結 構及源極線其中一者之間。 在某些實施例令，該串列是反及閘串列。 梅2 例巾’触x線結射的—航位元線、該源 ==複=元線中的-特定字元線的 胞。、擇了以辨識出该二維陣列的記憶胞中的一特定記憶 在某些實施例中，該二極體與該串 _列與該位元線結構之間。 雜係7丨於記憶胞 在某些實施例中，該二極體與該 串列與該源極線之間。 耦接係^於記憶胞 某些實施例包括一串列選擇線及 擇線安排成正交於额數個料 此串列選 形，如此於該複數個堆疊的表面與該串列個堆叠順 且與該概賴概個料之上， 選擇線交會點建立接地^擇1^^數個堆疊的表面與該接地 201212168 在某些實施例中，該二極體耦接於該串列選擇 元線結構之間。在某些實施例巾，該二極體 ;地^ 裝置與該_狀_。 ' 在某些實施例中，該交會區域中的記憶元件分 隧層、一電荷捕捉層及一阻擋層。 牙 在某些實施例中，該長條半導體材料包含n型石夕而該 體包含-p _域_長條半導歸射。麵㈣施 該長條半導體材料包含η财而該二極體包含 長條半導體材料接觸。 土/、邊 某些實施例包括賴以於程式倾記憶猶施加反向偏壓 至该記憶胞未選取串列中的二極體。 本發明之另-目的為提供—種記憶褒置，包含—積體電路 基板以及-個三維陣列的記憶胞於該積體電路基板中。此三 陣列包含反及閘串列記憶胞的堆4;以及二極體與該串列麵 接，係介於記憶胞串列與位元線結構及源極線其中一者之間。 某些實施例中，該位元線結構中的一特定位元線、該_ 中的-特定雜線及該複數條字元線巾的―特定字^線的组 合選擇’可以辨識出該三維陣列的記憶胞中的一特定記憶胞。 在某些實施例中，該二極體與該串列耦接，係介於記憶胞 串列與雜元線結構之㈤。在$㈣施财，該二極體與 列耦接，係介於記憶胞串列與該源極線之間。 某些實施例包括-串列選擇褒置介於該位元線結構與該記 隱胞串列之間，以及-接地選擇褒置介於該源極線與該記憶胞 串列之間。 在某些實施例中，該二極體耦接於該串列選擇裝置與該位 7 201212168 該二極體粞接於該接地選擇 元線結構之間。在某些實施例中 農置與該源極線之間。 一在某些實施射’該交會區域巾的電荷捕捉結構分別包含 一穿隧層、一電荷捕捉層及一阻擋層。 本發明之再一目的為提供一種操作三維反及閘快閃記憶體 的方法。其步驟包含施加—財化酿偏祕舰該三維反及 間快閃記憶體，該三維_包含二極體與該串肋接，使得該 -極體係介於記憶胞㈣與位元線結構及源極線結構其中一 者之間。 〃 一條或多條未選取的串列被充電，其中該未選取串列並不 包含即將被_式侧整程式化的記憶胞。在不同的實施 例中，此充電係自源極線結構或自位元線結構進行。在不同的 實施例中’此充電係經由二極體或不經由二極體進行。將該位 π線結構及源極線結構自該未選取串列及包含即將被該程 化調整偏壓程式化的記憶胞之—者或多者的—選取串^解^ 輕接。程式化電壓經由即將被該程式化調整偏壓程式化的記^ 胞之一條或多條字元線而施加至該未選取串列及該選取串1列= 該記憶元件安排成串列介於位元線結構與共同源極線之 間，且包括二極體與該串列耦接，係介於各自的串列之記憶月巧 串列與位it線結構及源極線其中-者之間。第—選擇閉 如串列選測極SSL)可以於對應的位元線結構與該記^ 胞串列之間，且第二選擇閘極(例如接地選擇閘極GSL)可以 接於對應的共同源極線與該記憶胞串列之間。該二極體可以^ 接介於第-選擇閘極與該對應的位元線結構之間。該二極^ 以耦接介於第二選擇閘極與該對應的共同源極線之間。过 此三維記憶裝置包含複數個山脊狀堆4，其是由複數個長 201212168 條半導體材料由絕緣層分隔而成，在此處所描述的範例中安排 成串列，其可以經由解碼電路而與感測放大器耦接。該複數個 長條半導體材料具有側表面於該複數個堆疊的側面。在此範例 中丄此複數條作為字元線的導線可以與列解碼器她，安排成 f父於賴數瓣4之上。此導線具有與該複數鋒疊順形的 表面(例如絲面）。’如此獅的表面組轉致在與該長 導體材料的側表面與複數條導線交會點建立—個多層的交合 區域^記憶元件安·介於長條半導體獅的織二與導^ ^的父會區域中。記航件是可程式化的，類似於以下實施例 中所描述?可程式電阻結構或是電荷捕捉結構。於特定交會區 1!!該順料線、記憶元件及該長條半導體材料的 陣堆疊。此陣列結構的結果可以提供該三維 此複數個山脊狀堆疊及複數條導線是利用自動對準的方式 形成記憶胞。舉例而言’複數個山脊狀堆 ，可以使用單-_幕罩定義，導致形成交錯的難 =對深的且堆射的長條半導體材料_表面是垂直地或 =形成溝麵山脊傾斜_面對準。此記憶元件可以使用二 二或數層全面沈餅堆疊之上晴料戦 ^對準步_触軸。此外，概解線可 件的材料之上，之後再二 早-蝕刻幕罩疋義出導線的_製程 氮化 .維、埋藏通道、無接 此外’此處也描述-種根基於能隙工程多晶石夕-氧化石夕· 石夕-氧化矽-氧化矽(BE-SONOS)技術之 面的反及閘快閃結構。 201212168 本發明對三維垂直閘極反及閘快閃設計提供一種非 常有效率的陣列解碼方式。其晶粒尺寸可以適用於目前 的浮動閘極反及閘快閃設計中而又可以將密度擴展至 一兆位元。 本發明也對超高密度三維反及閘快閃設計提供了一 種可行的電路設計架構。 本發明之目的，特徵，和實施例，會在下列實施方式的 早郎中搭配圖式被描述。 【實施方式】 本發明以下的實施例描述係搭配圖式1到41進行說明。 第1圖顯示一個三維可程式化電阻記憶陣列之一個 記憶胞部分的示意圖，在圖中將填充材料省略以清 楚的表示構成此三維陣列之長條半導體材料的堆疊及 正交的導線。在此圖式中，僅顯示兩個平面。然而，平 面的數目可以擴展至非常大的數目。如第〗圖中所示， 此記憶陣列形成於具有一絕緣層1〇於其下的半導體或 其他結構（未示）上方的積體電路基板之上。此記憶陣列 包括複數個長條半導體材料的堆疊n、12、13、14彼 此由絕緣材料21、22、23、24分隔。此堆疊為山脊形 狀且沿著圖中的Y轴方向延伸，所以長條半導體材料 11〜14可以組態為位元線，且延伸出基板。長條半導體 材料11、13可以做為第—記憶平面上的位it線，而長 條半導體材料12、14可以做為第二記憶平面上的位元 f。一層記憶材料15，例如是反炼絲材料，在此範例 :包覆於長條半導體材料之上，且在其他的範例中，至 >形成於長條半導體材料的側^。複數條導線Μ、 10 201212168 條半導體材料堆疊正交。複數條 ί此:隹，，長條半導體材料堆叠順形的表面:並填入由 刪(例如2°)之令，且在介 交會點之卜^隹疊與複數條導線16、17之間侧表面 (例如矽化Τ義々多層陣列的介面區域。一層金屬矽化物 線16、結、石夕化欽)18、19形成於複數條導 矽二意i才:f15 ’可以包含例如是二氧化矽'氮氧化 ^ 太匕石夕的反賴料’舉例而言，具有介於 料，例：t，、級的厚度。也可以利用其他的反炫絲材 -導=二夕。長條半導體材料n〜14可以是具有第 :电笙1、（例如P型）的半導體材料。導線16、17可 =具有第二導電型態(例如n型）的半導體材料。舉例 錄長條半導體材料11〜14可以使用p型多晶矽而導 ^ 可以使用濃摻雜的n+型多晶矽。長條半導體 、广、寬度必須足以提供二極體操作所需的空乏區 域。因此，記憶胞包含一個形成於三維交會點陣列中介 於長條多晶矽及導線整流器間的PN接面，此PN接面 ^有一可程式反熔絲層於陰極與陽極之間。在其他的實 鉍例中，可以使用不同的可程式電阻記憶材料，包括轉 換金屬氧化物，例如鎢上方的氧化鎢或是摻雜金屬氡化 物的長條半導體材料。如此的材料可以被程式化及抹 除，且可以在儲存多位元於一記憶胞中的操作應用。 #第2圖顯示在導線16與長條半導體材料14交會處沿 著記憶胞Z-X平面的剖面圖。主動區域25、26形成長 條半導體材料14的兩侧及介於導線16與長條半導體材 料14之間。在自然狀態’反熔絲記憶材料層15具有高 電阻於長式化之後，此反溶絲記憶材料崩潰，導致反 201212168 熔絲記憶材料内的主動區域25、26之一或兩者回到一 低電阻狀態。在此處所描述的實施例中，每一個記憶胞 具有兩個主動區域25、26形成長條半導體材料14的兩 侧。第3圖顯示在導線16、17與長條半導體材料14交 曰處/σ著§己憶胞χ_γ平面的剖面圖。圖中顯示自由導 線16疋義的字元線經過反熔絲記憶材料層15至長條半 導體材料14的電流路禋。 、電子的流動是由第3圖中的虛線顯示，自η+導線16 進入Ρ型長條半導體材料14，且沿著長條半導體材料 14(，線箭頭）至感測放大器，在感測放大器處可以量測 乂才曰示所選取s己憶胞的狀態。在一典型實施例中，係使 用約1奈米厚的氧化矽作為反熔絲材料，且利用第ρ ，中的晶片内控制電路施加包含5〜7伏特脈衝及脈衝 寬度約為1微秒的程式化脈衝。而讀取脈衝是利用 厂圖中的晶片内控制電路施加包含卜2伏特脈衝及盘 相關的脈衝寬度。此讀取脈衝可以遠短於裎式化^ 第4圖顯示兩個記憶胞平面，每一個平面具 憶胞。這些記憶胞由具有介於陰極與陽極之間^ : ，虛線代表)之二極體標示來表示。此兩個 =、 =由作為第—字元線WLn和第二字元線机州的導 Γ 與分_為位元線 BLn、BLn+1 * BLn+2 、第 第一和第三長條半導體材料堆疊51、52， 54和55、56交會處定義出此陣列的第一和 / 憶胞的第-平面包括在長條半導體材㈣# 5 ° ^ 憶胞30、31’在長條半導體材料堆疊54上的記 ^己 ]3以及在長條半導體材料堆疊5 6 _L的記憶胞3二，: 記憶胞的第二平面包括在長條半導體材料堆疊Μ上的 12 201212168 • 城胞4()、4卜在長條半導體材料堆疊53上的記憶胞 42 43以及在長條半導體材料堆疊55上的記憶胞44、 45。如圖中所不’導線6〇係作為字元線WLn，其包括 垂直延伸的6G_1、6G-2、6G-3與第1圖中介於堆疊間的 溝渠内的材料對應，以將導線6G與每一個平面中的3 個例示長條半導體材料堆疊耦接。一個陣列可以實施成 如此處所描述般具有許多層，以構成接近或到達每晶片 兆位兀之非常高密度的記憶體。 第5圖顯示一個三維可程式化電阻記憶陣列之一個 =2記憶胞部分的示意圖，在圖中具有填充材料以清楚 ，f不與構成此三維陣列之長條半導體材料的堆疊及 ϋ的導線相對關係。在此圖式中，僅顯示兩層。然而， 層二人的數目可以擴展至非常大的數目。如第5圖中所 二’、此記憶陣列形成於具有一絕緣層110於其下的半導 ，或，他結構(未示)上方的積體電路基板之上。此記憶 陣列包括複數個長條半導體材料的堆卜二 料 121、122、123、124分隔。此堆 著圖中的γ轴方向延伸，所以長條 f導體⑽ui〜114可以組態為位元線，且延伸出其 條；導體材料出、113可以做為第-記憶平： 的4兀線，而長條半導體材料112 二記憶平面上的位元線。 』以做為第 絕中介於長條半導體材料ηι*112之間的 113 ^以及在第二堆疊中介於長條半導體材料 和114之間的絕緣材料i 2 3具有大於 氧化層厚度⑽丁)，其中等效氧化層厚度(EOT) 料f厚度乘以氧化㈣絕緣層之介電常數 、之氧化層厚度。此處所使用的名詞'，約40奈 201212168 米”是考慮典型如此裝置的製程中約10%數量級變動的 結果。此絕緣層的厚度對於減少此結構中相鄰記憶胞間 的干擾具有重要的影響。在某些實施例中，絕緣材料的 等效氧化層厚度（EOT)可以最小達到3〇奈米而仍能在 相鄰層間具有足夠的隔離。 一層記憶材料115 ’例如是介電電荷捕捉結構，在此 範例中包覆於長條半導體材料之上。複數條導線116、 117與這些長條半導體材料堆疊正交。複數條導線116、 117具有與這些長條半導體材料堆疊順形的表面，並填 入由這些堆疊所定義的溝渠（例如12〇)之中，且在介於 長條半導體材料111〜114堆疊與複數條導線116、117 之間側表面交會點之處定義多層陣列的介面區域。一層 金屬矽化物（例如矽化鎢、矽化鈷、矽化鈦）118、119形 成於複數條導線116、117的上表面。 奈米線的金氧半場效電晶體型態藉由提供奈米線或 奈米管結構於導線111〜114之上的通道區域而也被組態 成此種方式’如同Pau丨等人的論文"linpact of a Pr〇cess Variation on Nanowire and Nanotube Device Performance " IEEE Transactions on Electron Device, Vol. 54, No. 9, 2007 年 9 月11〜13日’在此引為參考資料。 因此，可以形成組態為反及閘快閃陣列的三維陣列的 SONOS型癌a己憶胞。源極、波極和通道形成於石夕長條 半導體材料111〜114中，記憶材料層115包括氧化矽(〇) 的穿隧介電層97、氮化矽(N)的電荷儲存層卯、氧化矽 (〇)的阻擋介電層99及多晶矽（S)的導線116、in。 長條半導體材料111〜114可以是p型半導體材料而導 線116、117可以使用相同或不同的半導體材料(例如p+ 型態）。舉例而言’長條半導體材料111〜114可以是p 201212168 •型多晶矽，或是p型磊晶單晶矽，而導線116、117 以使用相對濃換雜的P+多晶碎。 替代地’長條半導體材料U1〜114可以是半導體 材料而導線116、117可以使用相同或不同導電型態的 半導體材料(例如P+型態）。此n型半導體材料安排導致 埋藏-通道空乏型態的電荷捕捉記憶胞。舉例而言， 條半導體材料111〜114可以是η型多晶矽，或是η型磊 晶單晶矽，而導線116、117可以使用相對濃摻雜的二 多晶矽。典型η型長條半導體材料的摻雜濃度約為 1018/cm3，可使用實施例的範圍大約在1〇n/cm3到 1019/cm3之間。使用n型長條半導體材料對於無接面的 實施例是較佳的選擇，因為可以改善沿著反及閘串列的 導電率及因此允許更高的讀取電流。 因此，包含場效電晶體的此記憶胞具有電荷儲存結構 形成於此交會點的三維陣列結構中。使用約25奈米數 量級的長條半導體材料和導線厚度，且具有山脊形狀堆 疊的間距也是約25奈米數量級，具有數十層（例如三十 層）的裝置在單晶片中可以達到兆（1 〇12)位元的容量。 此記憶材料層Π 5可以包含其他的電荷儲存結構。舉例 而言，可以使用能隙工程(BE)之SONOS電荷儲存結構所取 代，其包括介電穿隧層97，且層次間在〇v偏壓時具有倒u 型價帶。在一實施例中’此多層穿隧層包括第一層稱為電洞穿 隧層’第二層稱為能帶補償層及第三層稱為隔離層。在此實施 例中，電洞穿隧層97包括二氧化矽層形成於長條半導體材 料的側表面’其可利用如現場条汽產生（in_situ steam generation，ISSG)之方法形成，並選擇性地利用沉積後一氧 化氮退火或於沉積過程中加入一氧化氮之方式來進行氮化。第 15 201212168 一層中的二氧化矽之厚度係小於20埃’且最好是小於15埃， 在一代表性實施例中為10或12埃。 在此貫施例中’能帶補償層包含氮化石夕層係位於電洞穿隧 層之上，且其係利用像是低壓化學氣相沉積LPCVD之技術， 於680 C下使用二氣矽烷(dichlorosilane，DCS)與氨之前驅物來 形成。於其他製程中，能帶補償層包括氮氧化矽，其係利用類 似之製程及一氧化二氮前驅物來形成。能帶補償層中的氮化矽 層之厚度係小於30埃，且較佳為25埃或更小。 在此貫施例中，隔離層包含二氧化石夕層係位於能帶補償層 上，且其係利用像是LPCVD高溫氧化物HT0沉積之方式形 成。隔離層中的二氧化矽層厚度係小於35埃，且較佳為乃^ 或更小。如此的三層穿隧介電層產生了，，倒U”形狀之價帶能 階。 第一處之價帶能階係可使電場足以誘發電洞穿隧通過該第 一處與半導體主體(或長條半導體材料）介面間的薄區域，且 ^亦足以提升第-處後之價帶能階，以有效翁第—處後的複 5穿隨介電層内的電洞穿隨現象。此種結構，除了建立此三層 =隨介電層，，倒U”形狀之價帶’也可達成電場輔助之高速^ 其亦可在電場不存在或為了其他操作目的(像是從記憶 胞讀取資料或程式化鄰近之記憶胞)而鶴發小電場之情开^ 下有效的預防電荷流失通過經複合穿隧介電層結構。 、-代表性之裝置中，記憶材料層115包含能隙工程_) 牙随介電層，其包含第—層的二氧化奴厚度係小於2夺 層ϋ氮切層之厚度係小於3奈米及一第二層的二氧化ί 二4奈米。在—實施例中’此複合穿隨介電層包含 4氧化石夕層οι(例如小於等於15埃）、超帛氮化石夕層叫例 16 201212168 士】於卓於埃)以及超薄氧化梦層〇2(例如小於等於35埃) =組成，且其可在和半導體主體或長條半導體材料之介面起 ，的b—個15埃或更小之補償下，增加約2 6電子伏特的價帶 月巨階。藉由一低價帶能階區域(高電洞穿隧阻障)與高傳導帶能 階，2層可將N1層與電荷捕捉層分開一第二補償(例如從介 面起算約30埃至45埃）。由於第二處距離介面較遠，足以誘 發電洞穿隨之電場可提高第二處後的價帶能階，以使其有效地 消除電洞穿隧轉。@此’ 〇2層並不會嚴重干擾電場辅助之 電洞穿隧，同時又可增進經工程穿隧介電結構在低電 電荷流失的能力。 記憶材料層115中的電荷捕捉層在此實施例中包含氮化 矽層之厚度係大於50埃，包括舉例而言，厚度約7〇埃的氮化 f，且其係利用如LPCVD方式形成。本發明也可使用其他電 ，捕捉材料與結構，包括像是氮氧化矽(Six〇yNz)、高含矽量之 氮化物、高含矽量之氧化物，包括内嵌奈米粒子的捕捉層等等。 在此實施例中記憶材料層U5中的阻擋介電層是氧化 矽’其厚度係大於5〇埃’且包含在此實施例中式9〇埃，且可 以使用將氮化矽進行濕式轉換之濕爐管氧化製程。在其他實施 例中則可以使用高溫氧化物(HTO)或是LPCVD沉積方式形成 ，氧化碎。也可以使用其他的崎介電層㈣例如是氧化 高介電係數材料。 在一代表性實施例中’電洞穿隨層中的二氧化石夕之厚度係 ，13埃；能帶補償層之氮化矽層厚度係為2〇埃；隔離層之二 氧化石夕層層厚度係為25埃；電荷捕捉層之氮制^層厚度係為 70埃；及阻擋介電層可以是厚度9〇埃的氧化矽。導線u'6‘: 1Π的_材料可以是p+多晶石夕(其功函數為51電子伏特）。 第6圖顯示在導線116與長條半導體材料114交會處 201212168 形成之電荷捕捉記憶胞沿著記憶胞z-x平面的剖面 圖。主動區域125、126形成長條半導體材料114介於 導線116與長條半導體材料114之間的兩側。在第6圖 所描述的實施例中，每一個記憶胞是雙重閘極場效電晶 體具有兩個主動區域125、126形成長條半導體材料114 的兩侧。 第7圖顯示在導線116與長條半導體材料114交會處 形成之電荷捕捉記憶胞沿著記憶胞χ_γ平面的剖面 圖。圖中也顯示流至長條半導體材料114的電流路徑。 電子的流動如圖中虛線所示，是沿著p型長條半導體材 料流至感測放大器，其可以量測以指示所選取記憶胞的 狀態。介於作為字元線的導線116、117之間的源/汲極 區域128、129、130可以是"無接面”的，也就是源/汲極 的摻雜型態不需要與字元線底下的通道區域之摻雜型態不 同。在此’’無接面”的實施例中，電荷捕捉場效電晶^可 以具有P型通道結構。此外’在某些實施例中，源/及 極的摻雜可以在定義字元線之後利用自動對準佈植的 方式报ϊλί。 在替代實施例中，長條半導體材料111〜114可以在,, 無接面"的安排中使用淡摻雜η型半導體主體，導致形成 ff空乏模式下操作的埋藏通道場效電晶體，此電荷插 足δ己憶胞具有自然偏移至較低的臨界電壓分佈。 从第8圖顯示兩個記憶胞平面，每—個平面具有$ 4捕捉記憶胞安排成反及閘組態，其是—正方體的 = 括許多平面及許多字元線。此兩個記憶ΐ ^由作為子70線WLn•卜WLn和WLn =62,其分別為第-、第二和第三長條半導‘ 201212168 s己憶胞的第一平面包括記憶胞70、71和72於〜 閘串列中，且位於長條半導體材料堆疊之上， 73、74和75於-反及間串列中，且位於長條半導$ 料堆疊之上，以及記憶胞76、77和78於—反 = 中，且位於長條半導體材料堆疊之上。在此例示中， 憶胞的第二平面與立方體的底平面對應，且包括 (例如80、82 * 84)利用類似於第一平面的安= 反及閘串列中。 徘& 如圖中所*，作為字元線WLn❸導線161包括 延伸部分，其與第5圖中介於堆疊之間的溝渠12 料對應，以將導線161與所有平面中介於長條半導體 料間的溝渠内之介面區域的記憶胞（例如第一平面 憶胞的71、74和77)耦接。 位兀線與源極線係位於此記憶串列的相對端。位元 106、107和108藉由位元線信?虎心卜BLn和扯⑷ 的控制而連接至記憶串列巾的不同堆疊。在此安排中由 信號SLn㈣的源極、線86、終結上半平面的反及間串 列。類似地，在此安排巾由信號SLn+1控制的源極線 87終結下半平面的反及閘串列。 在此安排中，串列選擇電晶體85、88和89連接介於 各自的反及閘串列與位it綠BLnl、版* BLn+1之 間。串列選擇線83與字元線平行。 在此安排中，區塊選擇電晶體9〇〜95將反及閑串列 與源極線之接。在此範例巾，接地選擇線gsl與 區塊遠擇電晶體90〜95連接，且可以使用類似於導線 和162的方式實施。在某些實施例中，此串 包晶體及區塊選擇電晶體可以使用與記憶胞中 的間乳化層相_介電堆4。在其他的實施例中，可以 19 201212168 ::典;層來取代。此外，通道長度及寬度可以 y4的&要而調整以提供這些電晶體適當的切 月b ° 第9圖顯示一個類似於第5圖的替代 使用相同的參考標號，、:二^ 欠 圖不同的部分是絕緣層110的表面 ”導體材料113、114的側表面⑴Α、114Α 之、心31疋線之後在作為字元線的導線(例如16〇) 以，因此，記憶材料層115在字元線之間可 =王.或部分韻刻而不會影響到操作。然而，在某些結 需要如此處所描述的一般蝕刻通過記憶材料 層115來形成介電電荷捕捉結構。 第10圖顯示類似第6圖的記憶胞沿著Ζ-Χ平面的剖 f圖。第10圖與第6圖完全相同，顯示第9圖記憶胞 中的結構’在此剖面圖中與第5圖實施的結構之剖面圖 相同。第11圖顯示類似第7圖的記憶胞沿著χ_γ平面 白勺剖面圖。第11圖與第7圖不同的部分是沿著長條半 導體材料114的側表面（例如114Α)的區域ma、12% 和130a中的記憶材料被移除。 第12到16圖顯示實施如此處所描述的三維記憶陣列 的基本製私階段流程圖，其僅使用2個對陣列構成對準 =分關鍵影響的圖案化幕罩步驟。在第12圖中，顯示 父錯沈積絕緣層210、212、214及半導體層211、213 之後的結構，舉例而言半導體層可以使用全面沈積之摻 雜半導體形成於晶片的陣列區域。根據實施例的不同，半導 體層可以使用具有n型或p型摻雜的多晶矽或磊晶單晶 矽。層間絕緣層210、212、214可以舉例而言使用二氧 化矽、其他氧化矽或是氮化矽。這些層可以使用許多不 201212168 二ρΤϋ成’包括業界熟知的低壓化學氣相沈積 (LPCVD)等技術。 第13圖顯示第一微影圖案化步驟的結果，其用來定 義複數個山脊狀的長條半導體材料堆疊250，^中此長 條半導體材料是由半導體層2η、213構成且由絕緣層 210、M2、214分隔。具有很深及很高的深寬比的溝渠 可以形成於多層堆疊之間，其係使用微影為基礎的製程 及把加含破硬式幕罩和反應式離子钮刻。 第14Α和14Β圖分別顯示包括例如是反炫絲記憶胞 結構的可程式化電阻記憶結構及包括例如是矽氧氮氧 矽（SONOS)型態記憶胞結構的可程式化電荷捕捉記憶 結構實施例中下一個階段的剖面圖。 第14Α圖顯示包括如第丨圖所示的單層反熔絲記憶 胞結構的可程式化電阻記憶結構實施例全面沈積一記 憶材料215後的結果。替代地，可以進行氧化製程而不 使用全面沈積以形成氧化物於長條半導體材料裸露的 側面，其中氧化物係作為記憶材料。 第14B圖顯示包括如第4圖所示的多層電荷捕捉結 構的可私式化電阻記憶結構實施例全面沈積一記憶材 料315後的結果，此多層電荷捕捉結構包括一穿隧層 397、一電荷捕捉層398及一阻擋層399。如第14A和 14B圖所示’記憶材料層235、315是利用順形方式沈 積於山脊狀的長條半導體材料堆疊（第13圖中的250) 之上。 第15圖顯示導電材料填充高深寬比溝渠步驟後的結 果’此導電材料可以例如是具有η型或p型摻雜，用來 作為字元線的導線，被沈積以形成層225。此外，在使用多晶 石夕的實施例中，一層矽化物226形成於層225之上。如圖中所 21 201212168 比、、户^Μ屢化學氣相沈積(LPC VD)之多晶碎等高深寬 間技術在此實施例中使用以填充介於山脊狀堆疊 蓋退渠，即使是非常窄具有高深寬比的1〇奈米數量 、’ /再渠也可行。 =^6圖顯示第二微影圖案化步驟的結果，其用來定 第二i ί記憶陣列中作為字元線的複數條導線2 60。此 介ίif圖案化步驟使用單一幕罩定義此陣列中蝕刻 過山間尚深寬比溝渠的臨界尺寸，而不需要施刻通 ^大的堆4。多晶石夕可以使用具有對多晶石夕與氧化 替ϊ ϋ夕高度選擇性的蝕刻製程來進行蝕刻。因此， 蝕刻製程可以使用與蝕刻半導體及絕緣層相同 、一罩進行，此製程會停止於底部絕緣層210。 一選擇性的製程步驟包括形成硬式幕罩於複數條導 綠之f，這些導線包括字元線、接地選擇線及串列選擇 硬轉罩相制相對厚的纽物或其他可以阻 “，子佈植的材料形成。於硬式幕罩形成之後，可以進 二離子佈植以增加長條半導體材料中的摻雜濃度，及因 降低/t3著長條半導體材料電流路徑上的電阻。藉由使 用控制，植能量，佈植可以導致穿過底長條半導體材 料，及每一個在堆疊中的上方長條半導體材料。 之後，移除硬式幕罩將複數條導線上方的矽化物裸露 出來。於一層間介電層形成於陣列上方之後，介層孔被 形成且舉例而言使用鎢的栓塞填充於其中。作為位元線 BL的上方金屬線被圖案化且與解碼電路連接。一個三 維解碼電路被以圖中的方式建立，使用一字元線、一位 元線、及一源極線來存取一選取記憶胞。可參閱標題為 Plane Decoding Method and Device for ThreeTechnical Papers, pp. 14~15, June 12-14, 2007, described. In the structure described by Tanaka et al., including a multi-gate field-effect transistor structure, which has a vertical channel similar to the anti-gate operation, uses a SONOS type charge trapping memory cell structure to A storage location is created at a gate/vertical channel interface. The memory structure is based on a columnar semiconductor material arranged as a vertical channel to form a multi-gate memory cell, and a lower-selective gate is adjacent to the substrate, and a higher selection is extremely above. A plurality of leveling control gates are formed using the pillars. As a horizontal control _ plane electrode layer and ==: and! Each, the memory is still the ^ key 步骤 step. In addition, the multilayer structure of this method is still limited, and is determined by factors such as vertical channel & electrical, stylized and erase operation.因此 There is therefore a need to provide a three-dimensional construction with low manufacturing costs, including reliable, very small memory components. The invention is a memory device comprising an integrated circuit substrate 201212168 a plurality of strips of semiconductor material stack, a plurality of word lines, memory elements and diodes. The plurality of strips of semiconductor material stack extend out of the integrated circuit substrate, the plurality of stacks having a ridge shape and including at least two elongated semiconductor materials separated by a plurality of layers to form different planar positions in the plurality of planar positions. The plurality of word line lines are arranged orthogonal to the plurality of stacks, and are aligned with the plurality of stacks, such that a surface of the plurality of stacked lines and the plurality of character line intersections are established - a three-dimensional array Intersection area. The memory element is in the intersection area, the basin is accessible to the plurality of word lines via the strip of semiconductor material, and the three series are in the bit line structure and the source line is free (four) secret, and is older than the memory line Between the bit line structure and the source line. In some embodiments, the string is a reverse gate train. The plum 2 case towel 'touches the x-ray bursting — the deadweight element line, the source == complex = the cell of the specific character line in the meta line. Selecting to identify a particular memory in the memory cell of the two-dimensional array. In some embodiments, the diode is between the string and the bit line structure. The hybrid system is in the memory cell. In some embodiments, the diode is between the string and the source line. Some embodiments of the memory cell include a string of select lines and a line arrangement arranged to be orthogonal to the number of pieces of the tandem, such that the plurality of stacked surfaces are stacked with the string And above the summary, select a line intersection to establish a grounding surface and a plurality of stacked surfaces and the ground 201212168. In some embodiments, the diode is coupled to the string selection element. Between line structures. In some embodiments, the diode; the device is connected to the __. In some embodiments, the memory element tunneling layer, a charge trapping layer, and a barrier layer in the intersection region. Teeth In some embodiments, the elongated semiconductor material comprises an n-type slab and the body comprises a -p _ domain _ strip semi-conducting. Face (4) The strip of semiconductor material comprises η 财 and the diode comprises a strip of semiconductor material contact. Soil/Side Some embodiments include diodes that rely on the program to apply a reverse bias to the unselected series of memory cells. Another object of the present invention is to provide a memory device comprising an integrated circuit substrate and a three-dimensional array of memory cells in the integrated circuit substrate. The three arrays comprise a stack 4 of counter-serial memory cells; and a diode is coupled to the string between the memory cell string and one of the bit line structure and the source line. In some embodiments, the combination of a particular bit line in the bit line structure, the -specific line in the _, and the "specific word line" of the plurality of word lines can identify the three-dimensional A specific memory cell in the memory cell of the array. In some embodiments, the diode is coupled to the series and is between (5) of the memory cell string and the impurity line structure. In $(4), the diode is coupled to the column between the memory cell string and the source line. Some embodiments include - a serial selection between the bit line structure and the hidden string, and - a ground selection between the source line and the memory string. In some embodiments, the diode is coupled between the string selection device and the bit 7 201212168. The diode is coupled between the ground selection line structure. In some embodiments between the farm and the source line. A charge trapping structure for a portion of the intersection region includes a tunneling layer, a charge trapping layer and a barrier layer, respectively. It is still another object of the present invention to provide a method of operating a three-dimensional anti-gate flash memory. The step includes applying the three-dimensional anti-and-flash memory, and the three-dimensional body includes a diode and the string rib, so that the-pole system is interposed between the memory cell (four) and the bit line structure and The source line structure is between one of them.一条 One or more unselected serials are charged, and the unselected serials do not contain memory cells that are to be stylized by the _form. In various embodiments, this charging is performed from a source line structure or a self-bit line structure. In a different embodiment, this charging is carried out via a diode or not via a diode. The bit π line structure and the source line structure are lightly connected from the unselected string and the selected string containing the memory cells to be programmed by the programming adjustment bias. The stylized voltage is applied to the unselected string and the selected string 1 column by one or more word lines of the cell to be programmed by the stylized adjustment bias = the memory element is arranged in a series Between the bit line structure and the common source line, and including the diode and the series, which are in the memory string of the respective series and the bit line structure and the source line. between. The first selection gate is selected between the corresponding bit line structure and the cell string, and the second selection gate (eg, the ground selection gate GSL) can be connected to the corresponding common The source line is between the memory cell string. The diode can be connected between the first-selective gate and the corresponding bit line structure. The diode is coupled between the second selection gate and the corresponding common source line. The three-dimensional memory device comprises a plurality of ridge-shaped stacks 4, which are formed by separating a plurality of long 201212168 semiconductor materials by an insulating layer, arranged in a series in the example described herein, which can be sensed by a decoding circuit. The amp is coupled. The plurality of elongated semiconductor materials have side surfaces on the sides of the plurality of stacks. In this example, the multiple strips as the line of the word line can be arranged with the column decoder, and the parent is arranged on top of the flap 4. The wire has a surface (e.g., a silk surface) that is superposed with the plurality. 'The surface group of such a lion is established at the intersection with the side surface of the long conductor material and the plurality of wires. A multi-layered intersection area ^ Memory element An. The father of the woven and the radiant of the long semiconductor lion In the conference area. The log is programmable, similar to the one described in the following examples: a programmable resistor structure or a charge trapping structure. In the specific intersection area 1!! The alignment line, the memory element and the array of the elongated semiconductor material. The result of this array structure can provide the three-dimensional plurality of ridge-like stacks and a plurality of wires that are formed by automatic alignment to form memory cells. For example, 'a plurality of ridge-shaped stacks can be defined using a single--mask, resulting in the formation of staggered difficulties = deep and stacked long strips of semiconductor material _ surface is vertical or = forming grooved ridge slope _ surface alignment. This memory element can be used with two or more layers of full-thickness cake stacked on top of the 戦 ^ alignment step _ touch shaft. In addition, the outline of the wire can be used on the material, and then two early days - the etched mask 疋 出 导线 导线 导线 氮化 氮化 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The anti-gate flash structure of the surface of the polycrystalline stone-oxidized stone eve · Shi Xi - yttria-yttria (BE-SONOS) technology. 201212168 The present invention provides a very efficient array decoding method for three-dimensional vertical gate and gate flash design. Its die size can be applied to current floating gate and gate flash designs while extending the density to one megabit. The present invention also provides a viable circuit design architecture for ultra-high density three-dimensional anti-gate flash design. The objects, features, and embodiments of the present invention will be described in conjunction with the drawings in the following embodiments. [Embodiment] The following description of the embodiments of the present invention will be described with reference to Figs. Figure 1 shows a schematic diagram of a memory cell portion of a three-dimensional programmable resistive memory array in which the fill material is omitted to clearly represent the stacked and orthogonal conductors of the elongated semiconductor material that make up the three dimensional array. In this illustration, only two planes are shown. However, the number of planes can be extended to a very large number. As shown in the figure, the memory array is formed over an integrated circuit substrate having a semiconductor or other structure (not shown) underlying an insulating layer 1. The memory array includes a plurality of stacks of strips of semiconductor material n, 12, 13, 14 which are separated by an insulating material 21, 22, 23, 24. The stack is ridge-shaped and extends along the Y-axis direction in the drawing, so the elongated semiconductor materials 11 to 14 can be configured as bit lines and extend out of the substrate. The elongated semiconductor material 11, 13 can be used as a bitit line on the first memory plane, and the elongated semiconductor material 12, 14 can be used as a bit f on the second memory plane. A layer of memory material 15, such as a counter-filament material, is exemplified herein overlying the elongated semiconductor material, and in other examples, is > formed on the side of the elongated semiconductor material. A plurality of wires Μ, 10 201212168 semiconductor materials stacked orthogonally. A plurality of strips: 隹,, a strip of semi-conductive material stacked on a smooth surface: and filled with a deletion (for example, 2°), and between the intersection of the intersection point and the plurality of conductors 16, 17 The side surface (for example, the interface region of the bismuth bismuth multilayer array. A layer of metal bismuth line 16, knot, Shi Xihuaqin) 18, 19 is formed in a plurality of strips, and the f15 ' may contain, for example, a dioxide.矽 'Nitrogen Oxidation ^ The ruthenium of Taixue Xi's, for example, has a thickness of material, for example: t, grade. Other anti-drawing wires can also be used - guide = Erxi. The long strip of semiconductor materials n to 14 may be a semiconductor material having a first electrode (e.g., a P type). The wires 16, 17 can be a semiconductor material having a second conductivity type (e.g., n-type). For example, the long strip semiconductor materials 11 to 14 can be formed using a p-type polysilicon. A heavily doped n+ type polysilicon can be used. The strip of semiconductor, width, and width must be sufficient to provide the depletion region required for diode operation. Therefore, the memory cell includes a PN junction formed between the strip polysilicon and the wire rectifier formed in an array of three-dimensional intersection points, the PN junction having a programmable antifuse layer between the cathode and the anode. In other embodiments, different programmable resistive memory materials can be used, including converting metal oxides, such as tungsten oxide over tungsten or elongated semiconductor materials doped with metal telluride. Such materials can be programmed and erased and can be used in operational applications where multiple bits are stored in a memory cell. #第二图 shows a cross-sectional view along the Z-X plane of the memory cell at the intersection of the conductor 16 and the elongated semiconductor material 14. The active regions 25, 26 form the sides of the elongated semiconductor material 14 and are interposed between the wires 16 and the elongated semiconductor material 14. In the natural state, after the anti-fuse memory material layer 15 has high resistance to long-length, the anti-solvent memory material collapses, causing one or both of the active regions 25, 26 in the anti-201212168 fuse memory material to return to one. Low resistance state. In the embodiment described herein, each of the memory cells has two active regions 25, 26 forming the sides of the elongated semiconductor material 14. Figure 3 shows a cross-sectional view of the intersection of the wires 16, 17 and the elongated semiconductor material 14 at the σ 忆 χ χ γ γ plane. The figure shows the current path of the free conductor line 16 word line passing through the anti-fuse memory material layer 15 to the elongated semiconductor material 14. The flow of electrons is shown by the dashed line in Figure 3, from the η+ wire 16 into the 长-type elongated semiconductor material 14, and along the elongated semiconductor material 14 (, line arrow) to the sense amplifier, in the sense amplifier The state can be measured to indicate the state of the selected s. In an exemplary embodiment, about 1 nm thick yttrium oxide is used as the antifuse material, and a pulse of 5 to 7 volts and a pulse width of about 1 microsecond are applied by the in-wafer control circuit of the ρth. Stylized pulses. The read pulse is applied by the on-wafer control circuit in the factory diagram to apply the pulse width associated with the 2 volt pulse and the disk. This read pulse can be much shorter than the ^^^^ Fig. 4 shows two memory cell planes, each of which has a memory cell. These memory cells are represented by a diode with a ^: , a dotted line between the cathode and the anode. The two =, = are derived from the first word line WLn and the second word line state and the _ is the bit line BLn, BLn+1 * BLn+2, the first and third strips The intersection of the semiconductor material stacks 51, 52, 54 and 55, 56 defines the first plane of the array and the first plane of the memory cell is included in the strip of semiconductor material (4) # 5 ° ^ Recalling cells 30, 31' in the strip semiconductor The memory cell 3 on the material stack 54 and the memory cell 3 in the long semiconductor material stack 5 6 _L: The second plane of the memory cell is included on the stack of long semiconductor materials 12 201212168 • City cell 4 ( The memory cells 42 43 on the elongated semiconductor material stack 53 and the memory cells 44, 45 on the elongated semiconductor material stack 55. As shown in the figure, the wire 6 is used as the word line WLn, which includes vertically extending 6G_1, 6G-2, and 6G-3 corresponding to the material in the trench between the stacks in FIG. 1 to connect the wire 6G with Three exemplified strips of semiconductor material stacking in each plane are coupled. An array can be implemented with as many layers as described herein to form a very high density memory that approaches or reaches megabits per wafer. Figure 5 shows a schematic representation of a =2 memory cell portion of a three-dimensional programmable resistive memory array with a fill material in the figure to be clear, f not opposite the stack and turns of the long strip of semiconductor material that make up the three-dimensional array. relationship. In this illustration, only two layers are shown. However, the number of layers can be extended to a very large number. As shown in Fig. 5, the memory array is formed on a semiconductor circuit having an insulating layer 110 under it, or an integrated circuit substrate above a structure (not shown). The memory array includes a plurality of stacked strips of semiconductor material 121, 122, 123, 124 separated by a plurality of strips of semiconductor material. This stack extends in the γ-axis direction, so the long f-conductor (10) ui~114 can be configured as a bit line and extends out of its strip; the conductor material out, 113 can be used as the first-memory flat: 4 兀 line And the strip of semiconductor material 112 has a bit line on the memory plane. 117 as the first between the long semiconductor material ηι*112 and the insulating material i 2 3 between the elongated semiconductor material and 114 in the second stack has a thickness greater than the oxide layer (10), The thickness of the equivalent oxide layer (EOT) material f is multiplied by the dielectric constant of the oxidized (four) insulating layer and the thickness of the oxide layer. The term 'about 40 nal 201212168 m' used herein is the result of considering about 10% of the variation in the typical process of such a device. The thickness of this insulating layer has an important influence on reducing the interference between adjacent memory cells in this structure. In some embodiments, the equivalent oxide thickness (EOT) of the insulating material can be as small as 3 nanometers and still have sufficient isolation between adjacent layers. A layer of memory material 115' is, for example, a dielectric charge trapping structure. Wrapped over the elongated semiconductor material in this example, a plurality of wires 116, 117 are orthogonal to the stack of elongated semiconductor materials. The plurality of wires 116, 117 have a smooth surface that is stacked with the elongated semiconductor material. And filling in the trench defined by the stacks (for example, 12 〇), and defining the interface of the multilayer array at the intersection of the side surface of the strip of semiconductor material 111-114 and the plurality of wires 116, 117 A layer of metal telluride (such as tungsten telluride, cobalt telluride, titanium telluride) 118, 119 is formed on the upper surface of the plurality of wires 116, 117. The gold oxide half of the nanowire The effect transistor pattern is also configured in such a way by providing a channel region over the wires 111-114 of the nanowire or nanotube structure 'as in Pau丨 et al.' "linpact of a Pr〇 Cess Variation on Nanowire and Nanotube Device Performance " IEEE Transactions on Electron Device, Vol. 54, No. 9, September 11-13, 2007 'herein referenced. Therefore, it can be configured as a reverse gate. The three-dimensional array of the flash array is a SONOS-type cancer. The source, the wave, and the channel are formed in the stellite semiconductor material 111-114, and the memory material layer 115 includes the tunneling dielectric of yttrium oxide. The layer 97, the charge storage layer of tantalum nitride (N), the barrier dielectric layer 99 of germanium oxide, and the wires 116, in of the polysilicon (S). The elongated semiconductor materials 111 to 114 may be p-type semiconductor materials. The wires 116, 117 may use the same or different semiconductor materials (for example, p+ type). For example, the long strip semiconductor materials 111 to 114 may be p 201212168 • polycrystalline germanium or p-type epitaxial single crystal germanium, and Wires 116, 117 are used to make relatively thick P+ polycrystalline. Alternatively, the 'long strip semiconductor materials U1 to 114 may be semiconductor materials and the wires 116, 117 may use semiconductor materials of the same or different conductivity types (for example, P+ type). This n-type semiconductor material arrangement leads to burial. - Channel depletion type charge trapping memory cells. For example, the strip semiconductor materials 111 to 114 may be n-type polycrystalline germanium or n-type epitaxial single crystal germanium, and the wires 116, 117 may be relatively densely doped. Polycrystalline germanium. The doping concentration of a typical n-type elongated semiconductor material is about 1018/cm3, and the range of embodiments can be used to be between about 1 〇 n/cm 3 and 10 19 /cm 3 . The use of n-type strip semiconductor materials is a preferred choice for junctionless embodiments because the conductivity along the anti-gate string and thus the higher read current can be improved. Thus, this memory cell containing a field effect transistor has a charge storage structure formed in a three dimensional array structure at this intersection. A strip of semiconductor material and wire thickness on the order of about 25 nanometers is used, and the pitch of the ridge-shaped stack is also on the order of about 25 nanometers, and devices having tens of layers (for example, thirty layers) can reach megahertz in a single wafer (1) 〇 12) The capacity of the bit. This memory material layer 5 can contain other charge storage structures. For example, a gap-engineered (BE) SONOS charge storage structure can be used that includes a dielectric tunneling layer 97 with an inverted u-type valence band between 层次v biases. In one embodiment, the multilayer tunneling layer includes a first layer called a tunneling layer. The second layer is referred to as an energy band compensation layer and the third layer is referred to as an isolation layer. In this embodiment, the tunneling layer 97 includes a ruthenium dioxide layer formed on the side surface of the elongated semiconductor material. It can be formed by in-situ steam generation (ISSG) and selectively utilized. Nitriding is performed by annealing nitric oxide after deposition or by adding nitric oxide during deposition. The thickness of the cerium oxide in the first layer of 201212168 is less than 20 angstroms and preferably less than 15 angstroms, and in a representative embodiment is 10 or 12 angstroms. In this embodiment, the band-compensation layer comprises a layer of nitride layer on the tunnel layer, and the system uses a technique such as low-pressure chemical vapor deposition LPCVD to use dichlorosilane at 680 C. , DCS) is formed with ammonia precursors. In other processes, the bandgap compensation layer includes niobium oxynitride, which is formed using a similar process and a nitrous oxide precursor. The thickness of the tantalum nitride layer in the energy compensation layer is less than 30 angstroms, and preferably 25 angstroms or less. In this embodiment, the spacer layer comprises a layer of dioxide dioxide on the band compensation layer and is formed by means of LPCVD high temperature oxide HT0 deposition. The thickness of the ruthenium dioxide layer in the spacer layer is less than 35 angstroms, and is preferably or less. Such a three-layer tunneling dielectric layer produces a valence band energy level of the inverted U" shape. The first valence band energy system enables the electric field to be sufficient to induce tunneling through the first portion to the semiconductor body (or The thin semiconductor region) is a thin region between the interfaces, and is also sufficient to increase the valence band energy level after the first-position, so as to effectively penetrate the hole in the dielectric layer. Structure, in addition to the establishment of the three layers = with the dielectric layer, the inverted U" shape of the valence band 'can also achieve the electric field-assisted high speed ^ can also be in the absence of the electric field or for other operational purposes (such as reading from the memory cell Data or stylized neighboring memory cells) and the small electric field of the cranes are effective to prevent charge loss through the composite tunneling dielectric layer structure. In a representative device, the memory material layer 115 comprises an energy gap engineering _) a dentate dielectric layer comprising a first layer of cerium oxide thickness of less than 2 nitrite layers and a thickness of less than 3 nm. And a second layer of dioxide 245 nm. In the embodiment, the composite wear-through dielectric layer comprises 4 oxidized stone layer οι (for example, 15 angstroms or less), a super bismuth nitride layer (referred to as example 16 201212168), Yu Zhuo, and an ultra-thin oxidized dream. Layer 2 (for example, 35 angstroms or less) = composition, and it can increase the price of about 26 electron volts under the compensation of b - 15 angstroms or less from the interface of the semiconductor body or the strip of semiconductor material. With a huge month. With a low-cost band energy region (high hole tunneling barrier) and a high conduction band energy level, the two layers can separate the N1 layer from the charge trapping layer by a second compensation (eg, from about 30 angstroms to 45 angstroms from the interface). ). Because the second distance interface is far enough, it is enough to induce the power generation hole to penetrate and the electric field can increase the valence band energy level after the second place, so as to effectively eliminate the hole tunneling. The @此' layer 2 does not seriously interfere with the electric field-assisted hole tunneling, and at the same time enhances the ability of the engineered tunneling dielectric structure to lose low charge. The charge trapping layer in the memory material layer 115 in this embodiment comprises a tantalum nitride layer having a thickness greater than 50 angstroms, including, for example, nitridation f having a thickness of about 7 angstroms, and which is formed by, for example, LPCVD. Other energies can be used in the present invention to capture materials and structures, including, for example, bismuth oxynitride (Six〇yNz), high cerium-containing nitrides, high cerium oxides, including trapping layers embedded with nanoparticles. and many more. In this embodiment, the barrier dielectric layer in the memory material layer U5 is yttria' having a thickness greater than 5 angstroms' and is included in the embodiment 9 〇, and the tantalum nitride can be wet-converted. Wet furnace tube oxidation process. In other embodiments, high temperature oxide (HTO) or LPCVD deposition may be used to form and oxidize. Other sacrificial dielectric layers (4) may also be used, such as oxidized high dielectric constant materials. In a representative embodiment, the thickness of the dioxide in the layer is 13 angstroms; the thickness of the tantalum nitride layer with the compensation layer is 2 angstroms; the layer of the oxidized layer of the barrier layer The thickness is 25 angstroms; the thickness of the nitrogen layer of the charge trap layer is 70 angstroms; and the barrier dielectric layer can be yttrium oxide having a thickness of 9 angstroms. The wire u'6': 1Π's material may be p+ polycrystalline (the work function is 51 eV). Figure 6 shows a cross section of the charge trapping memory cell formed along the z-x plane of the memory cell at the intersection of the conductor 116 and the elongated semiconductor material 114. The active regions 125, 126 form a strip of semiconductor material 114 on either side of the conductor 116 and the elongated semiconductor material 114. In the embodiment depicted in Figure 6, each of the memory cells is a double gate field effect transistor having two active regions 125, 126 forming the sides of the elongated semiconductor material 114. Figure 7 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the conductor 116 and the elongated semiconductor material 114 along the memory cell χ γ plane. The current path to the elongated semiconductor material 114 is also shown. The flow of electrons, as indicated by the dashed lines in the figure, flows along the p-type elongated semiconductor material to a sense amplifier that can be measured to indicate the state of the selected memory cell. The source/drain regions 128, 129, 130 between the wires 116, 117 as word lines may be "no junction", that is, the source/drain doping type does not need to be with characters The doping profile of the channel region underneath the wire is different. In this "no junction" embodiment, the charge trapping field effect transistor may have a P-type channel structure. Further, in some embodiments, the source/pole doping may be reported by means of auto-alignment after the word line is defined. In an alternate embodiment, the elongated semiconductor materials 111-114 may use a lightly doped n-type semiconductor body in the arrangement of no junctions, resulting in the formation of buried channel field effect transistors operating in the ff deficient mode, The charge insertion δ has a natural shift to a lower threshold voltage distribution. Figure 8 shows two memory cell planes, each with a $4 capture memory cell arranged in a reverse gate configuration, which is - a square of = including many planes and many word lines. The two memories ΐ ^ are taken as the sub-70 lines WLn•Bu WLn and WLn=62, which are the first, second and third strips semi-conducting respectively. The first plane of the 201212168 s memory cell includes the memory cell 70, 71 and 72 are in the ~-lister column and are on top of the strip of semiconductor material, 73, 74 and 75 in the - and reverse series, and on the strip of semi-conducting material, and the memory cell 76 , 77 and 78 are in - and are located above the stack of elongated semiconductor materials. In this illustration, the second plane of the memory cell corresponds to the bottom plane of the cube and includes (e.g., 80, 82 * 84) in an array of amps and gates similar to the first plane.徘& as shown in the figure, as the word line WLn❸ wire 161 includes an extension portion corresponding to the trench 12 between the stacks in FIG. 5 to connect the wire 161 with all the planes between the long semiconductor materials The memory cells of the interface region within the trench (eg, the first planar memory cells 71, 74, and 77) are coupled. The bit line and source line are located at opposite ends of this memory string. Bits 106, 107, and 108 are connected to different stacks of memory strings by the control of bit line signals, BLn and pull (4). In this arrangement, the source, line 86, and the upper half of the signal SLn (4) are inverted and interleaved. Similarly, the source line 87 controlled by the signal SLn+1 is arranged to terminate the inverse gate sequence of the lower half plane. In this arrangement, the series selection transistors 85, 88 and 89 are connected between the respective AND gate series and the bit it green BLnl, version * BLn+1. The string selection line 83 is parallel to the word line. In this arrangement, the block selection transistors 9〇~95 will connect the reverse and the serial strings to the source lines. In this example, the ground selection line gsl is connected to the block remote selection transistors 90 to 95 and can be implemented in a manner similar to the wires and 162. In some embodiments, the packaged crystal and block selective transistor can be used with the interpolymer layer 4 in the memory cell. In other embodiments, it may be replaced by a layer: 201212168::. In addition, the length and width of the channel can be adjusted to provide the appropriate cut-off b ° for these transistors. Figure 9 shows an alternative reference to Figure 5 instead of using the same reference number, : The portion is the surface of the insulating layer 110. The side surfaces (1) Α, 114 Α of the conductor materials 113, 114, and the wires 31 (疋 16 〇) after the line 31 are drawn, so that the memory material layer 115 is in the character Between the lines can be = king or part of the rhyme without affecting the operation. However, at some junctions, a general dielectric etch is required to form a dielectric charge trapping structure through the memory material layer 115 as shown herein. Figure 10 shows a similar Figure 6 is a cross-sectional view of the memory cell along the Ζ-Χ plane. Figure 10 is identical to Figure 6, showing the structure of the memory cell in Figure 9 and the profile of the structure implemented in Figure 5 and Figure 5. The figure is the same. Fig. 11 shows a cross-sectional view of the memory cell similar to Fig. 7 along the χ γ plane. The difference between the 11th and 7th is the area along the side surface of the elongated semiconductor material 114 (e.g., 114 Α). Memory materials in ma, 12% and 130a are moved Figures 12 through 16 show a basic privacy stage flow diagram for implementing a three-dimensional memory array as described herein, using only two patterned mask steps that form alignment = sub-critical effects on the array. In Figure 12, The structure after the father is deposited with the insulating layers 210, 212, 214 and the semiconductor layers 211, 213 is shown. For example, the semiconductor layer can be formed on the array region of the wafer using the fully deposited doped semiconductor. Depending on the embodiment, the semiconductor layer can be Polycrystalline germanium or epitaxial single crystal germanium having n-type or p-type doping is used. The interlayer insulating layers 210, 212, 214 may be, for example, germanium dioxide, other antimony oxide or tantalum nitride. These layers may use many 201212168 Τϋ Τϋ ' 'includes the industry well-known low pressure chemical vapor deposition (LPCVD) and other technologies. Figure 13 shows the results of the first lithography patterning step, which is used to define a plurality of ridge-like strips of semiconductor material stack 250, The strip of semiconductor material is composed of semiconductor layers 2n, 213 and is separated by insulating layers 210, M2, 214. Ditches having a deep and high aspect ratio can be formed. Between the multi-layer stacks, the lithography-based process is used, and the hard-masked mask and reactive ion button are added. Figures 14 and 14 respectively show the stylization including, for example, the anti-shock memory cell structure. A cross-sectional view of a resistive memory structure and a next stage of an embodiment of a programmable charge trap memory structure comprising, for example, a SONOS type memory cell structure. Figure 14 is shown as shown in Figure 的A programmable resistive memory structure embodiment of a single layer anti-fuse memory cell structure results in the overall deposition of a memory material 215. Alternatively, an oxidation process can be performed without the use of full deposition to form oxides exposed to the elongated semiconductor material. Side, where the oxide is used as a memory material. Figure 14B shows the result of a fully-deposited memory material 315 comprising a multilayered charge trapping structure as shown in Figure 4, the multilayer charge trapping structure comprising a tunneling layer 397, a charge The capture layer 398 and a barrier layer 399. As shown in Figures 14A and 14B, the memory material layers 235, 315 are deposited in a ridged manner over a ridge-like strip of elongated semiconductor material (250 in Figure 13). Fig. 15 shows the result of the step of filling the high aspect ratio trench by the conductive material. This conductive material may be, for example, a wire having an n-type or p-type doping, used as a word line, to be deposited to form a layer 225. Moreover, in the embodiment using polysilicon, a layer of germanide 226 is formed over layer 225. As shown in the figure, the 2012-12168 ratio, the household chemical vapor deposition (LPC VD) polycrystalline crushing height and width technology is used in this embodiment to fill the ridge-like stacked cover retreat, even if it is very A narrow number of 1 nanometers with a high aspect ratio, ' / re-canal is also feasible. The Fig. 6 shows the result of the second lithography patterning step, which is used to define a plurality of wires 2 60 as word lines in the second memory array. This 395 step is a single mask that defines the critical dimension of the etched cross-mountain gap in the array without the need to apply a large stack. Polycrystalline can be etched using an etching process that is highly selective for polycrystalline litres and oxidized iridium. Therefore, the etching process can be performed using the same mask as etching the semiconductor and the insulating layer, and the process stops at the bottom insulating layer 210. An optional process step includes forming a hard mask on a plurality of green guides f, the conductors including the word line, the ground selection line, and the series selection of the hard cover, the relatively thick button or the other can block The material of the implant is formed. After the hard mask is formed, the second ion implantation can be performed to increase the doping concentration in the long semiconductor material, and the resistance on the current path of the long semiconductor material is reduced by /t3. Control, implant energy, implantation can result in a long strip of semiconductor material passing through the bottom, and each of the elongated semiconductor material in the stack. After that, the hard mask is removed to expose the germanium over the plurality of wires. After the interlayer dielectric layer is formed over the array, via holes are formed and filled therein, for example, using a plug of tungsten. The upper metal line as the bit line BL is patterned and connected to the decoding circuit. A three-dimensional decoding circuit is Created in the manner of the figure, a word line, a bit line, and a source line are used to access a selected memory cell. See the title of Plane Decoding Method and Dev. Ice for three
Dimensional Memories”的美國專利第 6906940 號。 22 201212168 為了程式化一所選取反熔絲型態記憶胞’在此實施例 中所選取字元線被偏壓至-7V，未選取字元線可以設定 為0V，所選取位元線也可以設定為0V，未選取位元線 可以設定為0V，所選取源極線可以設定為-3.3V，而未 選取源極線可以設定為0V。為了讀取一所選取記憶 胞，在此實施例中所選取字元線被偏壓至-1.5V，未選 取字元線可以設定為0V，所選取位元線也可以設定為 0V ’未選取位元線可以設定為〇v，所選取源極線SL 可以設定為-3_3V，而未選取源極線可以設定為〇v。 第17圖顯示根據本發明一實施例之積體電路的簡化示意 圖。其中積體電路875包括使用具有此處所描述的三維可程式 電阻唯讀記憶體(RRAM)陣列860於一半導體基板之上。一列 解碼器861與沿著記憶陣列860列方向安排之複數條字元線 862耦接且電性溝通。行解碼器863與沿著記憶陣列86〇行方 向女排之複數條位元線864(或之前所描述的串列選擇線)電 性溝通以對自陣列860的記憶胞進行讀取及程式化資料操 作平面解器858與此陣列860平面上的之前所描述的源 串列選擇線859(或之前所描述的位元線)耦接。位址係由匯 流排865提供給行解碼器863、列解碼$ 861與平面解碼器 =°方塊—866中的感測放大器與資料輸人結構經由資料匯流 =67與行解碼器863搞接。資料由積體電路8乃上的輸入/ 料輸入線Μ，或者由積體電路875其他内部 輸入至方塊嶋中物•結構。其他電 殊目的庫積體電路875之内，例如泛用目的處理器或特 列所或是模她合喷供由可程式餘記憶胞陣 器功能。資料由方塊866中的_放大 2 ’提供至積體電路875，或提供至# 篮电路875内部/外部的其他資料终端。 積 23 201212168 在本實施例中所使用的控制器係使用了偏壓調整狀態 ，，並控制了由電壓供應源或是方塊868 i生或提供^ 調整供應賴的應用，例如讀取和程式化電壓。該控制器 用特殊目的邏輯電路而細’如熟f該項技藝者職知 代實施例中，該控制器包括了通用目的處理器，其可使於同一 積體電路’以執行一電腦程式而控制裝置的操作。在又一實施 例中’該控制器係由特殊目的邏輯電路與通用目的處理器組合 而成。 第18圖顯示根據本發明—實闕之碰電路的簡化示音 圖。其中積體電路97S包括使用具有此處所描述的三維三維^ 及閘快閃記憶辦辦列960於-半導縣板之上。一列 器961與沿著記憶陣列960歹方向安排之複數條字元線％ 接且電性溝通。行解碼器963與沿著記憶陣列％〇行方向安排 之複數條位το線964(或之前所描述的串列選擇線)電性 以對自陣列960的記憶胞進行讀取及程式化資料操作。 解碼器958與此陣列960平面上的之前所描述的串列選擇線 959(或之前所描述的位元線迦妾。位址係由匯流排％ 給行解碼器963、列解碼器961與平面解碼器958。方塊966 中的感測放大器與資料輸人結構經由㈣匯流排％7與行解 碼器963雛。資料由積體電路975上的輸入/輸出^供給 資料輸入線97：1 ’或者由積體電路975其他内部/外部的資& 源，輸入至方塊966 +的資料輸入結構。在此例示實施例中， ，他電路974係包含於積體電路975之内，例如泛用目的處理 裔或特殊目的躺f路，或是模池合以提供由反及閘快 憶體，列所支援的系統單；功能。㈣由方塊％6中的感測 放大器，經由資料輸出線972，提供至積體電路975，或提供 至積體電路975内部/外部的其他資料終端。 、 在本實施例中所使用的控制器係使用了偏壓調整狀態機構 24 201212168 • 969，並控制了由賴供應源或是方塊868產生或提供之偏壓 調整供應電壓的應用，例如讀取、程式化、抹除、抹除驗^ 以及程式化驗證電壓。該控制器可利用特殊目的邏輯電路^應 用，如熟習該項技藝者所熟知。在替代實施例中，該控制器包 括了通用目的處理器，其可使於同一積體電路，以執行一電腦 程式而控制裝置的操作。在又一實施例中，該控制器係 目的邏輯電路與通用目的處理器組合而成。 、 "第19圖為8層垂直通道薄膜電晶體能隙工程多晶矽_ 氧化矽-氮化矽-氧化矽-氧化矽(BE_s〇N〇s)電荷捕捉反 置一部份之穿隧電子顯微鏡的剖面圖，其係以成第8圖^ 第23圖的方式被製造、測試及安排解碼。此裝置係利 用75奈米的半間距形成。其通道為大約18奈米厚的^ 型多晶矽。沒有進行額外的接面佈植而形成無接面結 構。在半導體長條間用來隔離通道的絕緣材料是在乙軸 方向，且其是厚度約為40奈米的氧化矽。所提供的閘 極為Ρ+多晶矽線。此串列選擇及接地選擇裝置具有較 記憶胞更長的通道長度。此測試裝置具有32個字元 線、無接面的反及閘串列。因為形成所示結構所使用的 溝渠蝕刻具有傾斜的形狀，在溝渠的底部具有距寬的矽 線，而且在細線間的絕緣材料距多晶矽被蝕刻得更多， 所以第19圖中下方細線的寬度係比上方細線的寬度 寬。 第20圖顯不一實施例中具有二極體（例如二極體 1492)於此反及閘串列半導體主體内的記憶胞剖面圖。 此結構包括複數個山脊狀堆疊，其包括長條半導體材料 Ml4、Ml3、Ml2於各自山脊狀堆疊平面的基板上。 複數條作為字元線的導線1425-1到1425-n(為簡化起見 圖中僅顯示兩條）與堆疊正交且延伸穿越，及如之前所 25 201212168 描述的順形地形成於記憶層之上。作為串列選擇線ssl 的導線1427及作為整體源極線GSL的導線1428 他的如此線安排成與作為子元線的複數條導線平行二 些導線可以利用例如是具有η型或p型摻雜多晶的^ 電材料1491形成，以供用來作為字元線的導線使用。 矽化物層1426可以形成於作為字元線、串 及整體源極線GSL的複數條導線之上。 '' 在區域1415中，長條半導體材料1414、1413、1412 經由整體源極線内連線而與相同平面中的苴他長條半 導體材料連接，及與一平面解碼器（未示）連/接。長條半 導體材料係使用之前所描述的階梯接觸區域而在整體 源極線内連線中延伸。 二極體(例如1492)放置於與導線1425_丨到1425 n連 接的δ己憶胞及將位元線BLn和BLn+1與長條半導體材 料1414、1413、1412連接的拴塞145〇、1451之間。在 此例示範例中，二極體是由長條半導體材料中的p+佈 植區域(例如1449)形成。栓塞145〇、1451可以包括摻 雜多晶矽、鎢或是其他垂直内連接技術。上方位元線 BLn和BLn+Ι連接介於栓塞145〇、1451與行解碼電路 (未示）之間。 在第20圖所示的結構中，並不需要在陣列中的串列 選擇閘極與共同源極選擇閘極上形成接觸。 第21圖顯示兩個記憶胞平面，每一個平面具有6個 電荷捕捉記憶胞安排成反及閘組態，其是一正方體的代 表例不’可以包括許多平面及許多字元線。此兩個記憶 胞平面由作為字元線\VLn-l、WLn和WLn+Ι的導線 1160、1161和1162，其分別為第―、第二和第三長條 半導體材料堆疊。 26 201212168 記憶胞的第一平面包括記憶胞1170、1171和1172於 -反及閘串列中’且位於長條半導體材料' 記憶胞㈣、1174和1175於一反及間串列巾，且位= 長條半導體材料堆疊之上。在此例示中，記憶胞的第二 平面與立方體的底平面對應，且包括記憶胞(例如 ^。1184)利用類似於第一平面的方式安排於反及間串列 如圖中所示’作為字元線WLn的導線1161包括垂直 ，伸部分’其與第5时介於堆疊之_溝渠12〇内材 料對應，以將導'線1161肖所有平面中介於長條半導體 材料間的溝渠内之介面區域的記憶胞（例如第一平面中 記憶胞的1171、1174)叙接。 串列選擇電晶體1196、1197連接介於各自的反及閉 串列與位7L線BL1和BL2之間。類似地，在此安排中， ，正方體底平面中的類似串列選擇電晶體連接介於各 的反及閘串列與位元線BL1和BL2之間，使得行解 馬施加於這些位元線。串列選擇線1與串列選擇電 曰曰體1196、1197連接，且與字元線平行，如第2〇圖中 所示。 在此範例中，二極體111〇、nn、1112、ni3連接 在此串列與對應的位元線之間。 接地選擇電晶體119〇、1191安排在此反及閘串列中 的相對側且用來將在一選取層中的此反及閘串列與一 共同源極茶考線耦接。此共同源極參考線由此結構中的 平面解碼器解碼。接地選擇線GSL可以使用類似於導 線1160、1161和1162的方式實施。在某些實施例中， 此串列選擇電晶體及接地選擇電晶體可以使用與記憶 胞中的閘氧化層相同的介電堆疊。在其他的實施例中， 27 201212168U.S. Patent No. 6,069,940 to Dimensional Memories. 22 201212168 To program a selected anti-fuse memory cell', the word line selected in this embodiment is biased to -7V, and the unselected word line can be set. For 0V, the selected bit line can also be set to 0V, the unselected bit line can be set to 0V, the selected source line can be set to -3.3V, and the unselected source line can be set to 0V. In a selected memory cell, the word line selected in this embodiment is biased to -1.5V, the unselected word line can be set to 0V, and the selected bit line can also be set to 0V 'Unselected bit line It can be set to 〇v, the selected source line SL can be set to -3_3V, and the unselected source line can be set to 〇v. Figure 17 shows a simplified schematic diagram of the integrated circuit according to an embodiment of the present invention. The body circuit 875 includes using a three-dimensional programmable resistive read only memory (RRAM) array 860 as described herein over a semiconductor substrate. A column of decoders 861 and a plurality of word lines 862 arranged along the column direction of the memory array 860. Coupled and electrically The row decoder 863 electrically communicates with a plurality of bit lines 864 (or the tandem selection lines previously described) along the row of the memory array 86 to read and program the memory cells from the array 860. The data manipulation plane solver 858 is coupled to the previously described source string select line 859 (or the previously described bit line) on the array 860 plane. The address is provided by the bus 865 to the row decoder 863. The column decoder $ 861 and the plane decoder = ° block - 866 sense amplifier and data input structure is connected to the row decoder 863 via data sink = 67. The data is input/output input by the integrated circuit 8 Μ, or other internal input into the block • • 结构 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 875 The program memory cell function. The data is provided by the _amplification 2' in block 866 to the integrated circuit 875, or to other data terminals inside/out of the # rim circuit 875. Product 23 201212168 Used in this embodiment Controller uses bias The entire state, and controls the application of the voltage supply or the supply of the adjustment, such as reading and staging the voltage. The controller uses a special purpose logic circuit to be as fine as the skill In another embodiment, the controller includes a general purpose processor that can control the operation of the device by executing a computer program on the same integrated circuit. In yet another embodiment, the controller is The purpose logic circuit is combined with a general purpose processor. Figure 18 shows a simplified diagram of the circuit according to the present invention. The integrated circuit 97S includes the use of the three-dimensional three-dimensional and gate flash memory array 960 described above on the semi-lead board. A column 961 is electrically coupled to a plurality of word lines arranged along the direction of the memory array 960. The row decoder 963 is electrically coupled to the memory cells of the array 960 for reading and stylizing data operations with a plurality of bit positions το line 964 (or the previously described string selection lines) arranged along the memory array % 〇 direction. . Decoder 958 and the previously described tandem select line 959 on the array 960 plane (or the previously described bit line 妾. The address is from bus % % to row decoder 963, column decoder 961 and plane Decoder 958. The sense amplifier and data input structure in block 966 is via (4) bus row %7 and row decoder 963. The data is supplied to the data input line 97:1 by input/output on integrated circuit 975. The other internal/external resources of the integrated circuit 975 are input to the data input structure of block 966 +. In this exemplary embodiment, the other circuit 974 is included in the integrated circuit 975, for example, for general purposes. Handling or special purpose lying, or the model pool to provide a system list supported by the reverse gate and the memory; (4) by the sense amplifier in block %6, via the data output line 972, Provided to the integrated circuit 975, or to other data terminals inside/outside the integrated circuit 975. The controller used in this embodiment uses a bias adjustment state mechanism 24 201212168 • 969 and is controlled by Lai source or party The 868 generates or provides a bias to adjust the supply voltage, such as reading, programming, erasing, erasing, and stylizing verification voltage. The controller can utilize special purpose logic circuits, such as familiarity with the art. As is well known, in an alternative embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller The logic circuit of the system is combined with the general purpose processor. [19] is an 8-layer vertical channel thin film transistor energy gap engineering polysilicon 矽 矽 矽 矽 矽 矽 矽 矽 BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE A cross-sectional view of a tunneling electron microscope with a portion of the charge trapping reversed, which was fabricated, tested, and arranged for decoding in the manner of Figure 8 and Figure 23. The device was formed using a half pitch of 75 nm. The channel is a polycrystalline germanium of about 18 nm thick. There is no additional junction implant to form a jointless structure. The insulating material used to isolate the channel between the semiconductor strips is in the direction of the biaxial axis, and it is the thickness. It is a 40 nm yttrium oxide. The gate is provided with a Ρ+ polysilicon line. This series selection and ground selection device has a longer channel length than the memory cell. This test device has 32 word lines and no junction. In contrast, the gate series is used because the trench etching used to form the structure has a slanted shape, and has a wide ridge line at the bottom of the trench, and the insulating material between the thin lines is etched more from the polysilicon, so the 19th The width of the lower thin line in the figure is wider than the width of the upper thin line. Fig. 20 shows a cross-sectional view of a memory cell having a diode (e.g., diode 1492) in the semiconductor body of the gate series. The structure includes a plurality of ridge-like stacks including elongated semiconductor materials M14, M13, M12 on a substrate of respective ridge-like stacked planes. The plurality of conductors 1425-1 through 1425-n (shown only as two in the figure for simplicity) are orthogonal to the stack and extend through, and are formed in a memory layer as described previously in the 2012 201212168. Above. The wire 1427 as the tandem selection line ss1 and the wire 1428 as the integral source line GSL are arranged such that they are parallel to the plurality of wires as the sub-line, and the wires may be, for example, have n-type or p-type doping. A polycrystalline material 1491 is formed for use as a wire for the word line. A telluride layer 1426 can be formed over the plurality of wires as the word line, the string, and the overall source line GSL. In region 1415, the elongated semiconductor material 1414, 1413, 1412 is connected to the other strip of semiconductor material in the same plane via an integral source interconnect, and is coupled to a planar decoder (not shown). Pick up. The elongated semiconductor material extends in the overall source line interconnect using the step contact regions previously described. A diode (e.g., 1492) is placed in the δ cell memory connected to the wires 1425_丨 to 1425 n and the cesium 145 连接 connecting the bit lines BLn and BLn+1 to the elongated semiconductor materials 1414, 1413, 1412, Between 1451. In this exemplary embodiment, the diode is formed from a p+ implant region (e.g., 1449) in the elongated semiconductor material. The plugs 145A, 1451 can include doped polysilicon, tungsten or other vertical interconnect techniques. The upper azimuth lines BLn and BLn+Ι are connected between the plugs 145A, 1451 and a row decoding circuit (not shown). In the structure shown in Fig. 20, it is not necessary to form a contact between the serial selection gates in the array and the common source selection gate. Figure 21 shows two memory cell planes, each having six charge trapping memory cells arranged in a reverse gate configuration, which is a representative of a cube that can include many planes and many word lines. The two memory planes are composed of conductors 1160, 1161, and 1162 as word lines \VLn-1, WLn, and WLn+1, which are stacks of the first, second, and third strips of semiconductor material, respectively. 26 201212168 The first plane of the memory cell consists of memory cells 1170, 1171, and 1172 in the - and gate series 'and located in the strip of semiconductor material ' memory cells (4), 1174, and 1175 in a reverse series, and = Long strip of semiconductor material stacked on top. In this illustration, the second plane of the memory cell corresponds to the bottom plane of the cube, and includes a memory cell (eg, ^1184) arranged in a reverse-to-intermediate manner as shown in the figure as a first plane. The wire 1161 of the word line WLn includes a vertical portion, which corresponds to the material in the stacked trench 12 第 at the 5th time, so that the conductive line 1161 is in the trench between the long semiconductor materials in all planes. The memory cells of the interface region (for example, 1171, 1174 of the memory cells in the first plane) are connected. Tandem select transistors 1196, 1197 are connected between respective inverted and closed columns and between bit 7L lines BL1 and BL2. Similarly, in this arrangement, a similar series-selective transistor connection in the bottom plane of the cube is interposed between each of the opposite gate series and the bit lines BL1 and BL2 such that the line is applied to the bit lines. . The string selection line 1 is connected to the string selection electrodes 1196, 1197 and is parallel to the word lines as shown in Fig. 2. In this example, diodes 111, nn, 1112, and ni3 are connected between the string and the corresponding bit line. Ground select transistors 119, 1191 are arranged on opposite sides of the gate train and are used to couple the reverse gate train in a selected layer to a common source tea line. This common source reference line is decoded by the planar decoder in this structure. The ground select line GSL can be implemented in a manner similar to the wires 1160, 1161, and 1162. In some embodiments, the tandem selection transistor and ground selection transistor can use the same dielectric stack as the gate oxide layer in the memory cell. In other embodiments, 27 201212168
且分別會對代表與目標記憶胞A ^列/字元線，但是不同行/位元線的記 Μ同τ叼圯惕脃A，And the representative and target memory cell A ^ column / word line, but the different row / bit line record is the same as τ 叼圯惕脃 A,
對在與目& 5己憶胞A在相同行/位元線及相同列/字 = 疋不同平面/源極線的記憶胞c，對在與目標記憶胞 :同列/字兀線，但是不同行/位元線及不同平面/源極線的 D ’對在與目標記憶胞a在相同平面/源極線及相同 行/位το線，但是不同列/字元線的記憶胞E慮記憶胞的干 擾條件。 根據此安排，此串列選擇線及共同源極選擇線可以在 一立方體中以立方體為基礎的方式解碼。此字元線可以 在一列中以列為基礎的方式解碼。此共同源極線可以在 一平面中以平面為基礎的方式解碼。此位元線可以在一 行中以行為基礎的方式解碼。 第22圖顯示類似於第20圖中的陣列之程式化操作的 時序示意圖。此程式化區間分割成標示為T1、丁2和T3 的三個主要區段。在T1的第一部分時，此立方體中的 接地選擇線GSL和未選取的共同源極線csl(顯示於圖 中標示為SL)被設疋為VCC ’其大約是3 3V而選取的 共同源極線CSL則保留在約〇v。此外，此_列選擇線 SSL也保留在約0V。如此可以達到將所選取的平面與 ον之耦合效應且未選取的平面是浮接的，造成介於未 選取的共同源極線與共同源極選擇線之間的差值不足 以開啟共同源極選擇線的閘極。於一小段轉換時間之 後’此電路中的未選取字元線及其他的導通間極（例如 假字元線及選擇閘極)被耦接至一約為1 的導通電壓 28 201212168 值。類似地，此選取字元線被耦接至相同或接近的電焊 值，而接地選擇線GSL和未選取的共同源極線cSLj二 保留在VCC。如此會造成此正方體未選取平面中的主 體區域之自我壓升效應。請參閱第21圖，記憶胞c和 D在區間T1中因為此操作的結果而具有麗升區域。 在T2區段中，接地選擇線GSL和未選取的共同源極 線CSL轉變回到0V，而字元線及導通閘極保留在/導通 電壓。於接地選擇線GSL和未選取的共同源極線cSl 轉變回到0V的一小段時間之後，此立方體中的串列選 擇線SSL轉變至VCC，其可以是如之前所描述的約 3·3ν。類似地，未選取的位元線也轉變至vcc。T2時 間中的偏壓結果會造成在相同平面/源極線及相同列/字元 線Μ旦是不同行/位元線的記憶胞(如記憶胞Β)之通道以及在相 同列/字元線，但是不同行/位元線及不同平面/源極線的記憶胞 (如5己憶胞D)之通道藉由自我壓升而被升壓。記憶胞c的升壓 通道電壓因會此二極體而不會由位元線BL洩漏。於Τ2段落 之後，串列選擇線SSL和未選取的位元線轉變回到〇ν。 在Τ3區段中，於接地選擇線GSL和未選取的共同源 極線C S L轉變回到〇 v之後，選取字元線的電壓被提升 至一例如是20V的程式化電位，而串列選擇線SSl、接 地選擇線GSL、選取位元線、未選取位元線、選取的共 同源極線CSL和未選取的共同源極線CSL保持在〇v。 於T1和T2的時間區段中所選取記憶胞中會形成一反 轉的通道，且因此即使是在串列選擇閘極和選擇共同源 ，閘極皆_的情況下也可以達成程式化。必須注意的 是，與目標記憶胞A在相同平面/源極線及相同行/位元線， 但1不同列/字元線的記憶胞E，僅會因為導通電壓施加在 未达取子元線而受到干擾。所以所施加的導通電壓必須 29 201212168 足夠低(例如小於iOV)以防止儲存在這些記憶胞中的資 料受到干擾。 於程式化區間之後，所有的電壓皆回到約0V。 第20圖中結構的不同實施例使用汲極端（位元線)正 向感測。在不同的實施例中，此二極體於讀取及程式化 抑制操作時抑制散失的電流路徑。 第23圖顯示類似於第20圖中的陣列之讀取操作的偏 壓條件示意圖。根據第23圖顯示施加於基板410上結 構的偏壓條件，一立方體中一平面上的記憶胞之讀取偏 壓為施加導通電壓呈未選取字元線，及一讀取參考電壓 施加至一選取字元線。選取的共同源極線C SL與約 耗接’未選取的共同源極線CSL與約VCC搞接，而此 立方體中的接地選擇線GSL和串列選擇線SSL皆與約 3.3V耦接。此立方體中的位元線BLn和BLn+Ι則與約 為1.5V的預充電階级耦接。 在此範例中的頁面解碼可以藉由使用共同源極線的 平面解碼而達成。因此，對一給定偏壓條件，因為立方 體中母一選取的共同源極線或平面具有可以被讀取的 位元線具有相同位元數目的一頁面。選取的共同源極線 CSL與約〇v耦接或是設定為參考電壓，而其他的共同 源極線CSL則設定為約3.3V。在此情況下，未選取的 共同源極線是浮接的。對未選取平面上位元線路徑之二 極體防止電流發散。 ，頁面讀取操作中，一立方體中之每一平面上的每一 條字元線被讀取一次。類似地，於一個以頁面為基 耘式化刼作中，此裎式化抑制條 卜 頁面程式化所需的程式化次數，即每-個平 此對個包含8個記憶胞的立方體而言，未選取記情 30 201212168 胞的程式化抑制條件必須足以承受8個程式化循環。 必須注意的是，此位元線串列中的二極體需要將位元 線上的偏壓略為提升約0.7V以補償二極體之典型壓 降。 第24圖顯示一立方體之抹除操作的偏壓條件示意 圖。根據第24圖顯示的偏壓條件’字元線與一例如是 -5V的負電壓搞接，共同源極線CSL及位元線與一例如 是+8V的正電壓耦接，及接地選擇線GSL與一例如是 +8V之合適的高導通電壓耦接。如此可以抑制源極線偏 壓的擊穿尺度。其他區塊的接地選擇線GSL和串列選 擇線SSL則是關閉。位元線所需的高電壓則可由位元 線驅動is a又δ十來滿足。替代地，子元線及串列選擇線可 以接地而共同源極線CSL及接地選擇線GSL則與一例 如是+ 13V的高電壓轉接。 第25圖顯示一替代實施例，其中二極體1492係應用 由使用在形成拴塞時的同位p+摻雜形成之多晶矽^ 1550、1551形成。在此情況下’二極體是自動對準的 而可以減少製程步驟。其他的結構則與第2〇囷中 4〇 於自我壓升時 以一桠體必須在數十毫秒内承受 一約8V的升壓通道電位。在8V反^「 電流應該小於100PA以承受此升壓電位,：的估5:: 電位應該遠咼於8 V。一個較低開啟| 田；、、;、朋/貝 幫助防止感測的困難。 叫約小於0, 極體是放置在記 在區域1515中， 雜而耦接在一起， 第26圖顯示一替代實施例，其中二 憶胞串列的共同源極線CSL端。因此， 每一個平面中的源極線藉由ρ+線或穆 31 201212168 3;:串㈣共同源極線解碼器與接地選擇線⑽L 的相同。一極體。其他的結構則與第20圖中所示 向m中結構的不同實施例使用源極端(源極線)反 抑二二不同的實施例中，此二極體於讀取及程式化 抑^呆作時抑制散失的電流路徑。 憶胞的2:::: 一 的示意圖，在此圖示中顯示記 CSL1 十面，對應共同源極線CSL0和共同源極線 节产晌Ϊ憶胞的兩行，對應位元線BL〇和位元線BL1， 擇線GSL i^^ SSL與串列選擇閘極耦接，而接地選 自我^接地選擇閘極耦接。類似於之前所描述的 式化式化操作用來進行程式化，其具有兩階段程 述。二極，加至所選取字元線會於以下更詳細地描 CST ~ "耦接至對應的記憶胞串列與共同源極線 bL〇或共同源極線CSL1之間。 個了 ::^_位元線是表示-串列中的另- 成低準位時當選取的共同源極線CSL變 ^ 〇〇 匕織位疋線的高電壓不會變成低準位。頁 線ΐ壓Ϊ ^那1固記憶胞應該被程式化。當位元 雷ϊγ反及閉快閃記憶胞而言，可以使用富勒-諾德漢 •V陪6隨對所選取記憶胞進行程式化。為了抑制非選取 。- Ξ?!程式化，應該施加高電壓至此記憶胞的區域位 岡1 ^通道。為了達成程式化抑制，可以施加如第 28圖和第妁圖的程式化序列。 弟 32 201212168 此程式化操作包含施加高電壓至未選取的共同源 線，且施加VCC(約3.3V)至未選取位元線。當字元’綠冲 g:CC=高電壓的導通電壓時，未選取位元線的 广、同源極線強迫拉至高電壓或是由位元線被強】 m ^共同源極線。當所選取記憶胞的字元線改變至 =化電位時’所有的區域位元料浮接。在程 加Γ能必須足以使得由—未選取位元線： 的電壓階級導致的任何電流(自vcj； 问電壓至地）不會對程式化造成 c/ 擾情況發生。 及疋導致耘式化干 第28圖顯示一個五階段的程式化 接地選擇線開啟接地選擇閘極，而串‘ 卜 選取平面中的區域位元線充電至言=„未 字元線電壓被升高至一第一字；。戶二，兀線的 妾地選擇雜襲❿施加供 =及將 將選取位讀接地。在步驟3 位元線和 】通電壓而串列選擇間極保持開啟及 ==-個 巧=此導致未選取區域位元線中 回電壓耦接。在步驟4，分享 U位7C線與 同源極線的區域位元線充電至高=選取共 選擇線關閉而接地選擇線開啟。在步 ^奴，串列 被偏壓至程式化電壓而串 只A ，字元線電壓 關閉。 甲〜擇線及接地選擇線保持 第29®顯示-轉代的五階段 1，所有的區域位元線經由偏壓 C序列。在步驟 Μ中的共同源極線 33 201212168 2電壓而被充電至高電壓，·此立方射的接地選 :極’且關閉串列選擇閘極。之後，關閉此立方體中 「地選擇閘極’且開料列選擇閘極，其會驅動選取 品域位元線中的區域位元線至地電壓。 2驟3 ’字元線被偏壓至一導通電壓而_列選擇閘 =呆持開啟及接地選擇閘極保持_。如此導致選取區 ^ 7L線中的區域位元線保持接地而未選取區域位元 由^區域位7C線浮接且由？元線升壓。在步驟4，藉 極二喜^立方體中的接地選擇閘極，且關閉串列選擇閘 ^未選取共同源極線偏壓，將選取位元線及-未選取 ^源極線的區域位元線充電至高電壓。在步驟5，選 =凡線接收程式化電壓而串列選擇閘極及接地選擇 =保持關閉129圖中的演算法相較於第28圖可以 二有較，的提升抑制特性而消耗更多的功率。自提升區 =tl線LBL3自高電壓可収善提升抑制結果，如此 更Γ改良了抑制。由共同源極線改 支至问t壓及放電至地的結果會增加功率消耗。 因此，在此操作技術中，自源極線所施加的高電壓可 以抑制程式化。當程式化電壓被施加所選取位元線=未 選取源極線被拉下至地時，此被程式化的位元線是浮 的。此外，此偏壓電壓序列是以維持正確升壓來抑制程 式化的方式施加。在程式化時，係以二極體的電流 以防止電流回到共同源極。 王 因為共同源極線是整體的，共同源極線可以斜整個陣 列解碼一次即可。相對的，解碼串列選擇線則需要 的串列選擇線驅動器及接觸區域。 在不同的實施例中，此二極體解碼之記憶陣列減少 列選擇線閘極的數目至每一個區塊只有一個串列選擇 34 201212168 線結構，或是每一個反及閘串列只有一個串列選擇線閘 極:如此結構大幅降低製程困難度，且具有高度對稱性 及微縮性。此架構在增加三維記憶陣列中的記憶胞層數 目時並不需要大量的_列選擇線。類似地，—個區塊中 也僅需要一條接地選擇線。 =匕二維垂直閘極裝置最好是使用薄膜電晶體能隙工 程多晶矽·氧化矽-氮化矽·氧化矽_氧化矽田E_s〇N〇s)裝置。另 方面’也可以開發使用反炫絲或是其他記憶技術的類似裝置 (例如使用其他的具有高介電係數介電層之電荷捕捉裝置）。 第3 0圖顯示類似於第21圖中的陣列之另—範例程式 化操作的時序示意圖。 在T1相位時’此源極線藉由接地選擇線GSL及未 取源極線上的vcc而被自我升壓。 及m相/立時’此未選取位元線藉由串列選擇線视 HV ? I·立Γ疋線上的高電屋HV❿才皮升壓至高電屢 之通道賴糾也被提升。記憶胞C被提升 在T3 t J 士為此位元線BL上的二極體而不會攻漏。 位時就已經形日i \記憶胞A被程式化。其反轉通道在T1相 ^ ΐ Ϊ' t ； Γ A 牡此圖不中顯不此串列中包;k 體形成於源極線結構鱼 匕栝一極 置可以用來支持程串列之間。這些二極體的位 的^^=^=胞八，且會考慮以下記憶胞 極線及相同列/字元線，標記憶f A在相同平面％ C代表與目標記憶胞Α—=同雜元線的記憶胞’記憶胞 但是不同平面/源極線 目同饤7位兀線及相同列/字元線， 凜的心fe胞，記憶胞D代表與目標記憶 35 201212168 月^ A在相同列/子元線，但是不同行/位元線及不同平面/源極 線的記憶胞’記憶胞E代表與目標記憶胞A在_平面/源 極線及相同行/位元線，但是不_字元線的記憶胞。記憶胞 E被導通錢Vpass干擾且在許乡實施射可减略。‘心 第32圖顯示類似於第31圖中的陣列之一範 操作的時序示意圖。 在Τ1相位時，此未選取位元線（記憶胞Β和D)藉由 串列選擇線SSL及未選取位元線上的錢Vee而被自 我升壓_。 在T2相位時，此未選取源極線藉由接地選擇線 及未選取源極線上的高電壓HV而被升壓至高電壓 HV。例如記憶胞c之未選取源極線的通道電壓也被直 接提升。當源極線SL的電壓為〇v及接地選擇線GSL開啟 時，例如記憶胞B之已經被提升的通道電壓Vch因為此源極 線SL上反向偏壓的二極體之較小漏電而不會洩漏。 在T3相位時’雖然串列選擇線SSL被關閉記憶胞a 仍是被程式化。其反轉通道在T1相位時就已經形成。 第33A和33B圖為三維反及閘快閃記憶陣列一部份之 穿隧電子顯微鏡的相片。 顯示於圖中的是75奈米半間距(4F2)之虛擬接地裝置的穿隧 電子顯微鏡相片。其通道寬度和長度分別是30和40奈米， 而通道高度是30奈米。每一個裝置是雙閘極(垂直閘極)的垂 直通道裝置，其中通道(埋藏通道裝置)是淡摻雜的η型以增 加讀取電流。此位元線BL的輪廓是適合使用平面〇Ν〇 的形狀。藉由適當調配此製程以獲取較小的側壁凹陷。 而在此位元線BL的側壁形成一非常平坦的ΟΝΟ。 第33Α圖為此陣列在X軸方向上的剖面圖。圖中顯 示兩個電荷捕捉能隙工程多晶矽-氧化矽_氮化;5夕_氧化石夕_氣 36 201212168 : 化矽(ΒΕ-SONOS)裝置形成於每一個通道的側壁。每一個裝置 是雙閘極裝置。通道電流是水平地流動，而閘極是垂直地排 列。具有最小的ΟΝΟ侧壁凹陷。 第33Β圖為此陣列在Υ軸方向上的刹面圖。由於較 緊縮的間距及較小的位元線寬度，聚焦離子束之穿隧電 子顯微鏡相片顯不包括多晶梦-閑極於位元線(水平半導體 長條)上及間距的雙重影像。圖示中的裝置其通道長度大 約是40奈来。 第34圖為實驗量測之多晶矽二極體的電流電壓（Ιν) 特性圖。 多晶石夕ΡΝ二極體的正向及反向電流電壓（ιν)特性係 直接自與虛擬接地反及閘垂直閘極三維反及閘陣列連 接之ΡΝ二極體量測。此多晶矽的高度/寬度尺寸為3〇/3〇 奈米。在-8的漏電流遠低於ι〇ρΑ，其已經符合自我升 壓及幫助消除程式化干擾的需求。施加源極偏壓vs， 及7V的導通電壓Vpass於所有的字元線上。此p+_N 二極體(30奈米寬度及30奈米高度)顯示超過6個數量及以上 的成功開啟/關閉比例。此正向電流由反及閘串列串聯電阻所 钳制。For the memory cell c in the same row/bit line and the same column/word = 疋 different plane/source line in the target & 5 memory cell, the pair is in the same column/word line as the target memory cell, but The D' pairs of different row/bit lines and different plane/source lines are in the same plane/source line and the same row/bit το line as the target memory cell a, but the memory cells of different column/character lines are considered The interference condition of the memory cell. According to this arrangement, the serial selection line and the common source selection line can be decoded in a cube in a cube. This character line can be decoded in a column-based manner in one column. This common source line can be decoded in a plane-based manner in a plane. This bit line can be decoded in a behavior-based manner in one line. Figure 22 shows a timing diagram similar to the stylized operation of the array in Figure 20. This stylized interval is divided into three main sections labeled T1, D2, and T3. In the first part of T1, the ground select line GSL and the unselected common source line csl (shown as SL in the figure) are set to VCC 'which is approximately 3 3V and the common source selected Line CSL is retained at approximately 〇v. In addition, this _ column select line SSL also remains at approximately 0V. In this way, the coupling effect between the selected plane and ον can be achieved, and the unselected plane is floating, so that the difference between the unselected common source line and the common source selection line is insufficient to open the common source. Select the gate of the line. After a short transition time, the unselected word lines and other conduction interpoles (e.g., dummy word lines and select gates) in the circuit are coupled to a turn-on voltage of approximately 20121212. Similarly, the selected word line is coupled to the same or close weld value, while the ground select line GSL and the unselected common source line cSLj remain at VCC. This will cause the self-pressure effect of the main body region in the plane not selected. Referring to Fig. 21, memory cells c and D have a rise region in the interval T1 because of the result of this operation. In the T2 sector, the ground select line GSL and the unselected common source line CSL transition back to 0V, while the word line and the turn-on gate remain at the /on voltage. After a short period of time after the ground select line GSL and the unselected common source line cS1 transition back to 0V, the tandem select line SSL in this cube transitions to VCC, which may be about 3·3 ν as previously described. Similarly, the unselected bit lines also transition to vcc. The bias voltage in T2 time results in channels of memory cells (such as memory cells) with the same plane/source line and the same column/word line being different rows/bit lines and in the same column/character Line, but the channels of different row/bit lines and memory cells of different plane/source lines (such as 5 cells) are boosted by self-pressure rise. The boosting channel voltage of the memory cell c is not leaked by the bit line BL due to the diode. After the 2 paragraphs, the tandem selection line SSL and the unselected bit lines are converted back to 〇ν. In the Τ3 section, after the ground selection line GSL and the unselected common source line CSL are switched back to 〇v, the voltage of the selected word line is raised to a stylized potential of, for example, 20V, and the string selection line SS1, ground selection line GSL, selected bit line, unselected bit line, selected common source line CSL, and unselected common source line CSL remain at 〇v. A reversed channel is formed in the selected memory cells in the time segments of T1 and T2, and thus stylization can be achieved even in the case where the gate selects the gate and selects the common source, and the gates are both _. It must be noted that the memory cell E of the same plane/source line and the same row/bit line as the target memory cell A, but only the different column/character line, is only applied to the unreachable sub-element due to the turn-on voltage. The line is disturbed. Therefore, the applied turn-on voltage must be 29 201212168 low enough (for example, less than iOV) to prevent the data stored in these memory cells from being disturbed. After the stylized interval, all voltages return to approximately 0V. Different embodiments of the structure in Fig. 20 use 汲 extreme (bit line) forward sensing. In various embodiments, the diode suppresses the lost current path during read and program inhibit operations. Fig. 23 is a view showing a bias condition similar to the reading operation of the array in Fig. 20. According to FIG. 23, the bias conditions applied to the structure on the substrate 410 are shown. The read bias of the memory cell on a plane in a cube is an applied turn-on voltage as an unselected word line, and a read reference voltage is applied to the Select the word line. The selected common source line C SL is coupled to the approximately common source line CSL and about VCC, and the ground select line GSL and the serial select line SSL in the cube are coupled to about 3.3V. The bit lines BLn and BLn+Ι in this cube are coupled to a precharge stage of about 1.5V. Page decoding in this example can be achieved by using planar decoding of a common source line. Thus, for a given bias condition, because the common source line or plane selected by the parent in the cube has a page with the same number of bits that the bit line can be read. The selected common source line CSL is coupled to about 〇v or set to the reference voltage, while the other common source line CSL is set to be about 3.3V. In this case, the unselected common source lines are floating. The diode of the bit line path on the unselected plane prevents current from diverging. In the page read operation, each character line on each plane in a cube is read once. Similarly, in a page-based simplification, this simplification suppresses the number of stylizations required to program a page, that is, for each cube that contains eight memory cells. , did not select the quotation 30 201212168 The stylization suppression condition of the cell must be sufficient to withstand 8 stylized cycles. It must be noted that the diode in this bit string series needs to slightly increase the bias voltage on the bit line by about 0.7V to compensate for the typical voltage drop of the diode. Figure 24 shows a schematic diagram of the bias conditions for a cube erase operation. According to the bias condition shown in Fig. 24, the word line is connected to a negative voltage of, for example, -5V, and the common source line CSL and the bit line are coupled to a positive voltage of, for example, +8V, and the ground selection line. The GSL is coupled to a suitable high turn-on voltage such as +8V. This suppresses the breakdown scale of the source line bias. The ground selection line GSL and the serial selection line SSL of other blocks are turned off. The high voltage required for the bit line can be satisfied by the bit line driving is a and δ ten. Alternatively, the sub-line and the string selection line may be grounded, and the common source line CSL and the ground selection line GSL are switched to a high voltage such as +13V. Fig. 25 shows an alternative embodiment in which the diode 1492 is formed by using polycrystalline germanium 1550, 1551 formed using in-situ p+ doping at the time of forming a dam. In this case, the 'diode is self-aligned and the process steps can be reduced. The other structure is the same as the second step. When the self-pressure rises, a body must withstand a booster channel potential of about 8V in tens of milliseconds. In 8V anti-"" current should be less than 100PA to withstand this boosting potential, the estimated 5:: potential should be farther than 8 V. A lower opening | field;,,;, Peng / Bei help to prevent the difficulty of sensing The call is less than 0, the polar bodies are placed in the area 1515, and are coupled together. Figure 26 shows an alternative embodiment in which the two source cells are connected to the common source line CSL end. Therefore, each The source line in one plane is the same as the ground selection line (10) L by the ρ+ line or the mu 31 201212168 3;: string (4) common source line decoder. The other structure is shown in Fig. 20. The different embodiments of the structure in m use the source terminal (source line) to suppress the two different embodiments. This diode suppresses the lost current path during reading and stylization. 2:::: A schematic diagram showing the two sides of the CSL1, which correspond to the common source line CSL0 and the common source line, and the corresponding bit line BL〇 and the bit element. Line BL1, select line GSL i^^ SSL is coupled to the serial selection gate, and the ground is selected from the ground connection gate coupling. Similar to before The described modularization operation is used for stylization, which has a two-stage description. The two poles, added to the selected word line, will be described in more detail below. CST ~ " coupled to the corresponding memory cell string Between the common source line bL〇 or the common source line CSL1. The ::^_bit line is the representation--the other common source line CSL becomes 低 when the other is in the low level. The high voltage of the 〇匕 疋 疋 不会 不会 不会 。 。 。 。 。 页 页 页 页 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 那 固 固 固 固 固 固 固 固Le-Nordham V is accompanied by a programmatic programming of the selected memory cells. In order to suppress non-selection. - Ξ?! Stylized, a high voltage should be applied to the region of the memory cell 1 ^ channel. To achieve stylization For suppression, a stylized sequence such as Figure 28 and Figure 可以 can be applied. Brother 32 201212168 This stylization involves applying a high voltage to the unselected common source line and applying VCC (about 3.3V) to the unselected bit line. When the character 'green rushing g:CC=high voltage turn-on voltage, the wide and homologous poles of the bit line are not selected. The line is forced to pull to a high voltage or is strongly stronger by the bit line. m ^ common source line. When the word line of the selected memory cell changes to the = potential, all the area bits are floated. Any current that can be caused by the voltage class of the unselected bit line: (from vcj; ask voltage to ground) does not cause c/disturbance to stylize. A five-stage stylized ground selection line is shown to turn on the ground selection gate, and the string in the string 'selection plane is charged to the word = „the unword line voltage is raised to a first word; Household 2, the squatting line selects the smashing ❿ ❿ 供 and will read the selected bit to ground. In step 3, the bit line and 】 pass voltage and the series selects the pole to remain on and ==- 巧 = this causes the return voltage connection in the unselected area bit line. In step 4, the U-bit 7C line and the region line of the homopolar line are charged to the high level = the selected common line is turned off and the ground selection line is turned on. In step ^ slave, the string is biased to the stylized voltage and the string is only A, and the word line voltage is turned off. A ~ select line and ground select line to maintain the 29th display - five stages of the transition 1, all the area bit lines via the bias C sequence. The common source line in step Μ 33 201212168 2 is charged to a high voltage, and the grounding of this cube selects the pole and closes the series selection gate. After that, the "ground select gate" in the cube is turned off and the gate select gate is selected, which drives the bit line of the region in the selected bit line to the ground voltage. 2Step 3 'The word line is biased to A turn-on voltage and _ column select gate = hold open and ground select gate hold _. This causes the bit line in the area of the selected area to remain grounded and the unselected area bit is floated by the line 7C line Boost by the ? element line. In step 4, the gate is selected by the ground in the pole two hi cubes, and the series selection gate is turned off. The common source line bias is not selected, and the bit line is selected and - not selected ^ The bit line of the source line is charged to a high voltage. In step 5, the selected line of the line receives the stylized voltage and the serial selection gate and the ground selection = keeps off. The algorithm in the figure 129 can be compared to the figure 28 Compared with the lifting suppression characteristic, it consumes more power. The self-lifting zone = tl line LBL3 can improve the suppression result from the high voltage, so that the suppression is improved. The common source line is changed to the t-voltage and discharge. The result of the ground will increase the power consumption. Therefore, in this operation technology The high voltage applied from the source line can suppress stylization. When the programmed voltage is applied to the selected bit line = the unselected source line is pulled down to ground, the stylized bit line is floating. In addition, the bias voltage sequence is applied in such a way as to maintain correct boosting to suppress stylization. In stylization, the current of the diode is used to prevent current from returning to the common source. Wang because of the common source line. Integral, the common source line can be decoded once in the entire array. In contrast, the tandem select line driver and the contact area are required to decode the serial select line. In different embodiments, the diode is decoded. The memory array reduces the number of column select line gates to only one string selection for each block. 34 201212168 line structure, or each reverse gate series has only one series select line gate: this structure greatly reduces process difficulty And it has high symmetry and miniaturization. This architecture does not require a large number of _ column selection lines when increasing the number of memory cell layers in a three-dimensional memory array. Similarly, only one block needs Strip grounding selection line. = 匕 Two-dimensional vertical gate device is preferably a thin film transistor energy gap engineering polysilicon 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 矽 E 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Similar devices using anti-drawing or other memory technologies can be developed (eg, using other charge trapping devices with high-k dielectric layers). Figure 30 shows another example similar to the array in Figure 21. Schematic diagram of the stylization operation. In the T1 phase, 'this source line is self-boosted by the ground selection line GSL and the vcc on the source line not taken. And m phase/set time' this unselected bit line The serial selection line depends on the high-voltage house HV❿ on the HV?I·立Γ疋线, and the battery is boosted to the high-powered channel. The memory cell C is promoted on the bit line BL of T3 t J. The diode does not leak. At the time of the bit, it has been stylized. The inversion channel is in the T1 phase ^ Ϊ t't; Γ A 此 This picture is not in the series; k body is formed in the source line structure, the pole is set to support the string between. The bits of these diodes are ^^=^=cell eight, and the following memory cell lines and the same column/character line are considered. The standard memory f A is in the same plane % C represents the same memory cell as the target memory cell. The memory cell of the meta-line is a memory cell but the different plane/source line is the same as the 7-bit line and the same column/character line. The heart of the cell, the memory cell D represents the same as the target memory 35 201212168 month ^ A Column/sub-element, but different row/bit lines and different plane/source lines of memory cell 'memory cell E represent and target cell A in _plane/source line and same row/bit line, but not The memory cell of the _ character line. The memory cell E is interfered by the money Vpass and can be reduced in Xuxiang. ‘Heart Figure 32 shows a timing diagram similar to one of the array operations in Figure 31. In the case of Τ1 phase, the unselected bit line (memory cell and D) is boosted by _ by the serial selection line SSL and the money Vee on the unselected bit line. In the T2 phase, the unselected source line is boosted to a high voltage HV by a ground selection line and a high voltage HV on the unselected source line. For example, the channel voltage of the unselected source line of the memory cell c is also directly boosted. When the voltage of the source line SL is 〇v and the ground selection line GSL is turned on, for example, the channel voltage Vch of the memory cell B has been boosted due to the small leakage of the reverse biased diode on the source line SL. Will not leak. At the T3 phase, although the serial selection line SSL is turned off, the memory cell a is still stylized. Its inversion channel is already formed at the T1 phase. Figures 33A and 33B are photographs of a tunneling electron microscope of a portion of a three-dimensional inverse gate flash memory array. Shown in the figure is a tunneling electron micrograph of a virtual grounding device with a 75 nm half-pitch (4F2). The channel width and length are 30 and 40 nm, respectively, and the channel height is 30 nm. Each device is a vertical gate device with a double gate (vertical gate) in which the channel (buried channel device) is a lightly doped n-type to increase the read current. The outline of this bit line BL is a shape suitable for using the plane 〇Ν〇. This process is suitably adapted to obtain smaller sidewall depressions. On the side wall of this bit line BL, a very flat crucible is formed. Figure 33 is a cross-sectional view of the array in the X-axis direction. The figure shows two charge trapping energy gap polycrystalline germanium-yttria-nitriding; 5 eve_oxidized oxide __ gas 36 201212168: A 矽-SONOS device is formed on the sidewall of each channel. Each device is a dual gate device. The channel current flows horizontally and the gates are arranged vertically. Has the smallest sidewall recess. Figure 33 is a diagram of the brake surface of the array in the direction of the x-axis. Due to the tighter pitch and the smaller bit line width, the tunneling electron microscope photo of the focused ion beam does not include a dual image of polycrystalline dream-and-slip on the bit line (horizontal semiconductor strip) and spacing. The device in the illustration has a channel length of about 40 nanometers. Figure 34 is a graph showing the current-voltage (Ιν) characteristics of the experimentally measured polycrystalline germanium diode. The forward and reverse current-voltage (ιν) characteristics of the polycrystalline quartz ΡΝ diode are directly measured from the 接地 diode of the virtual ground and the vertical gate of the sluice gate. The height/width dimension of this polysilicon is 3〇/3〇 nanometer. The leakage current at -8 is much lower than ι〇ρΑ, which is already in line with self-voltage and helps eliminate stylized interference. A source bias vs, and a turn-on voltage Vpass of 7V are applied to all of the word lines. This p+_N diode (30 nm width and 30 nm height) shows a successful on/off ratio of more than 6 quantities and above. This forward current is clamped by the series resistors of the anti-gate series.
第35圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的讀取電流特性圖。 M 此二維反及閘記憶體具有32條字元線。字元線的Vpass 和Vread兩者電壓皆為7V。源極線電壓Vsl則在以下數值中 變動：2.5V、2.0V、l.0V、〇.5V和aiv。在此圖示中，源極 線電壓Vsl超過l.ov時導致合適的感測電流。施加在源極端 的讀取電壓(源極端感測技術），在此情況下是一正電壓。'所兩 的偏壓由此ΡΝβ體提升，其需要足夠的開啟電壓，使得^ 過1.5V的源極偏壓才可以產生足夠的讀取電流。 ° 37 201212168 第36圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的程式化抑制特性圖。 Ba 圖中顯示記憶胞A、B、C、D的典型地程式化抑制 特性。在此情況下，Vcc=3.3V、HV=8V、vpass=9v。 在記憶胞A係施加遞增步進脈衝ISSp方法。此圖式顯 示出超過5V的無干擾區間。如此是由二極體隔離特性 所造成。 第37圖為實驗量測之與三維反及閘記憶體連接之多晶 石夕二極體的源極偏壓效應對於程式化干擾影響。 源極線抑制偏壓（HV)對於程式化干擾區間具有影 響。藉由HV>7V可以將記憶胞c的干擾降至最>小。’ 第38圖為實驗量測之與三維反及閘記憶體連接之多晶 石夕一極體的導通閘極電壓效應對於程式化干擾影響。 導通閘極電壓對於程式化干擾具有影響。藉由 Vpass>6V可以減少記憶胞c的干擾。 第39圖為實驗量測之與三維反及間記憶體連接之多晶 矽二極體的區塊抹除轉換電流示意圖。 源極，S L上不同的偏壓會改變區塊抹除轉換特性。 抹除係藉由施加一正源極線偏壓及將所有的字元線w L 接地而達成。如此表不將此三維反及閘陣列的主體浮接。 源極選擇線SSL/接地選擇線GSL施加合適的正電壓以 避免干擾。在第10圖中亦顯示此抹除轉變。在某些實 施例中此陣列並未使用電場增強效應（因為平坦0N0的 ，故），使得此抹除主要由能隙工程多晶石夕_氧化砂-氮化石夕· 祕矽-氧切(BE-SONOS)電洞穿隨注入支持。 第40圖為實驗罝測之與三維反及閘記憶體連接之多晶 石一極體的程式化及抹除狀態電流電壓特性示意圖，此 記憶體具有不同數目的程式化/抹除循環。 38 201212168 此，流電壓曲線顯示進行低於一萬次抹除操作内的 二^劣化，特別是在1 〇〇〇次及一次時。耐力的劣化通 书疋因為介面狀態（Dit)產生的緣故使得次臨界斜率變 ，，而，憶區間並不會改變。藉由調整能隙工程多晶矽_ 氧^[匕石夕·氮化石夕-氧化石夕-氧化石夕(BE-SONOS)堆疊此裝置顯示出 進行—萬次抹除操作之後與巨大裝置相較的合理較小 劣化。 第41圖為實驗量測之與三維反及閘記憶體連接之多晶 矽一極體的臨界電壓分佈示意圖，此記憶體具有檢查表分 佈之程式化/抹除記憶胞。 ^ 單一階級記憶胞的檢查表分佈在此與三維反及閘 =憶體連接之PN多晶石夕二極體中使用。（在此三維感測 中）最接近的記憶胞被程式化至相反狀態以代表最差的 干擾情况。在每一層中係使用傳統的頁面程式化及程式 化抑制方法，且然後將其他未選取源極線（記憶胞c和 )抑制依次在其他層進行頁面程式化。在一三維陣列 中未，取記憶胞受到許多次的列應力及行應力的傷害。 ，許夕不同的實施例中，替代實施例的二極體是與汲 極端（位TL線）或是源極端（源極線)連接，且具有將 選擇，SSL/接地選擇線GSL與位元線/源極線的角色互 f這些替代操作係在裝置階級中驗證。然而，在電路 設計中，源極線具有很小的電容負載，如此在施加高 壓HV&於源極線時可以在速度及功耗上的表現更佳。 、—本發明之較佳實施例與範例詳細揭露如上，惟應瞭解為上 述=例僅作為範例，非用以限制專利之範圍。就熟知技藝之人 自可輕易依據下列申請專利範圍對相關技術進行修改與 39 201212168 【圖式簡單說明】 第1圖顯示此處所描述之一個三維記憶結構的示意Figure 35 is a graph showing the read current characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. M This two-dimensional inverse gate memory has 32 word lines. The voltage of both Vpass and Vread of the word line is 7V. The source line voltage Vsl varies among the following values: 2.5V, 2.0V, 1.00V, 〇.5V, and aiv. In this illustration, the source line voltage Vsl exceeds 1.0 volts resulting in a suitable sense current. The read voltage applied to the source terminal (source extreme sensing technique), in this case a positive voltage. The bias voltage of the two is boosted by the ΡΝβ body, which requires a sufficient turn-on voltage so that a source bias of 1.5V can generate sufficient read current. ° 37 201212168 Figure 36 is a diagram showing the stylized suppression characteristics of the polycrystalline ruthenium diode connected to the three-dimensional inverse gate memory. The Ba diagram shows the typical stylized suppression characteristics of memory cells A, B, C, and D. In this case, Vcc = 3.3V, HV = 8V, and vpass = 9v. An incremental stepping pulse ISSp method is applied to the memory cell A system. This pattern shows an interference-free interval of more than 5V. This is caused by the isolation characteristics of the diode. Figure 37 shows the effect of the source bias effect of the polycrystalline quartz diode connected to the three-dimensional inverse gate memory on the stylized interference. The source line rejection bias (HV) has an effect on the stylized interference interval. The interference of the memory cell c can be reduced to the most > small by HV > 7V. Figure 38 shows the effect of the turn-on gate voltage effect of the polycrystalline celestial body connected to the three-dimensional anti-gate memory on the stylized interference. The turn-on gate voltage has an effect on stylized interference. The interference of memory cell c can be reduced by Vpass > 6V. Figure 39 is a schematic diagram showing the block erase conversion current of the polycrystalline germanium diode connected to the three-dimensional inverse and the inter-memory. The source, different bias voltages on S L will change the block erase conversion characteristics. Wiping is achieved by applying a positive source line bias and grounding all of the word lines w L . In this way, the three-dimensional anti-gate body of the gate array is not floated. The source select line SSL/ground select line GSL applies a suitable positive voltage to avoid interference. This erase transition is also shown in Figure 10. In some embodiments, this array does not use the electric field enhancement effect (because of the flat 0N0), so that this erase is mainly performed by the energy gap engineering polycrystalline stone _ oxidized sand - nitride 夕 · secret - oxygen cut ( BE-SONOS) hole penetration with injection support. Figure 40 is a schematic diagram showing the stylized and erased state current-voltage characteristics of the polycrystalline monolith connected to the three-dimensional inverse gate memory. The memory has a different number of stylized/erase cycles. 38 201212168 Therefore, the flow voltage curve shows the degradation of less than 10,000 erase operations, especially at 1 time and once. The deterioration of endurance is caused by the interface state (Dit), which causes the subcritical slope to change, and the recall interval does not change. By adjusting the energy gap engineering polycrystalline 矽 _ oxygen ^ [匕石夕· 氮化 夕 氧化 氧化 氧化 - 氧化 氧化 氧化 氧化 氧化 BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE BE 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此Reasonably less deteriorated. Figure 41 is a schematic diagram showing the critical voltage distribution of the polycrystalline 矽-polar body connected to the three-dimensional inverse gate memory. The memory has a stylized/erased memory cell with a checklist distribution. ^ The checklist distribution of single-class memory cells is used here in conjunction with the three-dimensional inverse gate-remembered PN polycrystalline liturgical diode. The closest memory cell (in this three-dimensional sense) is programmed to the opposite state to represent the worst interference situation. In each layer, the traditional page stylization and stylization suppression methods are used, and then the other unselected source lines (memory cells c and ) are suppressed and sequentially paged at other layers. In a three-dimensional array, the memory cells are subjected to many times of column stress and line stress. In a different embodiment of the present embodiment, the diode of the alternative embodiment is connected to the 汲 terminal (bit TL line) or the source terminal (source line), and has a selection, SSL/ground selection line GSL and bit The role of the line/source line mutual f is verified in the device class. However, in circuit design, the source line has a small capacitive load, which allows for better performance in terms of speed and power consumption when applying high voltage HV& to the source line. The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above description is only an example and is not intended to limit the scope of the patent. Those who are familiar with the art can easily modify the related technology according to the following patent application scope. 39 201212168 [Simple description of the diagram] Figure 1 shows the schematic of a three-dimensional memory structure described here.
圖’其包括複數個長條半導體材料平面與Y轴平行I 安排成複數個山脊狀堆疊，一記憶層於長條半導體材料 的側面’及複數條具有與其下的複數個山脊狀堆蟲 之底表面的導線。 且 y 第2圖顯示第1圖的記憶胞結構在沿著ζ_χ平面的 剖面圖。 第3圖顯示第！圖的記憶胞結構在沿著γ_χ平面的 剖面圖。 第4圖顯示具有第1圖結構的反熔絲為基礎記憶體 不意圖。 第5 —圖顯示此處所描述之一個三維反及閘快閃記憶 結構的示意圖，其包括複數個長條半導體材料平面與^ 軸平行且安排成複數個山脊狀堆疊，一電荷捕捉記憶層 於長條半導體材料的側面，及複數條具有與其下的 個山脊狀堆疊順型之底表面的導線。 第6圖顯示第5圖的記憶胞結構在沿著ζ_χ 剖面圖。Figure 2, which includes a plurality of strips of semiconductor material plane parallel to the Y-axis I arranged in a plurality of ridge-like stacks, a memory layer on the side of the strip of semiconductor material and a plurality of strips having a plurality of ridge-like piles underneath The wire of the surface. And y Fig. 2 shows a cross-sectional view of the memory cell structure of Fig. 1 along the ζ_χ plane. Figure 3 shows the first! The memory cell structure of the figure is a cross-sectional view along the γ_χ plane. Fig. 4 shows an antifuse having the structure of Fig. 1 as a base memory. Figure 5 - shows a schematic diagram of a three-dimensional inverse gate flash memory structure as described herein, comprising a plurality of strips of semiconductor material plane parallel to the axis and arranged in a plurality of ridge-like stacks, a charge trapping memory layer being long The sides of the strip of semiconductor material, and the plurality of strips having the bottom surface of the ridge-shaped stack of the lower ridge. Figure 6 shows the memory cell structure of Figure 5 along the ζ_χ profile.
第7圖顯示第5圖的記憶胞結構在沿著γ_χ平 剖面圖。 J 圖顯示具有第5圖和第23圖結構的反 記憶體之示意圖。 、門 顯Ϊ 一個類似於第5圖的三維反及閘快閃記憶 ί除，代貫施例的示意圖’其中記憶材料層自導線間 第10圖顯示第9圖的記憶胞結構在沿著Z-X平面的 201212168 剖面圖。 f 11 ®顯7F第9 ®的記憶胞結構在沿著γ·χ平面的 alj面圖。 、9圖中的記憶裝置的 、9圖中的記憶裝置的 第12顯示實施製造如第] 製程第一階段之剖面示意圖 第丨3顯示實施製造如第] 製程第二階段之剖面示意圖 第第jlA顯示實施製造如第1圖中的記憶裝置的製程 第二階段之剖面示意圖。 第5圖中的記憶裝置的製程 弟二階段之剖面示意圖。 9圖中的記憶裝置的 9圖中的記憶裝置的 5 第顯示實施製造如第] 製程第三階段之剖面示意圖 第顯示實施製造如第i 製程第四階段之剖面示意圖 —^ 17圖顯示根據本發明—實施例之積體電路的簡化方快 = 巾積體電路包括具有行、列及平面解碼電路之：唯 可程式電阻唯讀記健㈣。 _之一維 第18，顯示根據本發明另—實施例 =，其中積體電路包括具有行、列及平 == 反及閘快閃記憶體陣列。 电 <一維 子iLL圖為三維反及閑快閃記憶體陣列一部份之穿隨電 第20圖顯示一三維反及間快閃 體==位元線結構與記憶串列之間二面有， 顯示兩個記憶胞平面，每-個平面二 41 201212168 憶胞安排成反及閘組態。 第一2 2圖顯示類似於第2 〇圖中的陣列之程式化操作的 時序不意圖。 第23圖顯示一三維反及閘快閃記憶結構中具有二極 體於此串列的位元線結構與記憶串列之間在^ &取 操作時的剖面圖。 ^ 24圖顯示—三維反及閘快閃記憶結構中具有二極 體於此串列的位兀線結構與記憶串 化操作時的剖面圖。 你延仃私式 體3二一三維反及閘快閃記憶結構中具有二極 孫伯田ί列的位70線結構與記憶串列之間的示意圖，其 係使用多晶石夕栓塞作為二極體。 ϋ圖顯示—三維反及閘快閃記憶結射具有二極 體^此串列的源極線結構與記憶串列之間的剖面圖。 體於此2i歹 記‘_^有二極 顯示兩個結構與記憶串列之間的示意圖，其 範:^^。21圖中的陣列之程式化操作的第-範« μ陣㈣綱作的第二 ..® ^^ ^ ^ ^b# ^ ^ 纪示—個類似於第27圖中之三維反及閑快閃 二η示意圖’在此圖示中顯示此串列中包括二極 體升第=極線結構與記憶串列之間。 範例之時序!^圖第。31圖中的陣列之程式化操作的一個 42 201212168 第33A和33B圖為三維反及閘快閃記憶陣列一部份之 穿隧電子顯微鏡的相片。 第34圖為實驗量測之多晶矽二極體的電流電壓（IV) 特性圖。 第35圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的讀取電流特性圖。 第36圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的程式化抑制特性圖。 第37圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的源極偏壓效應對於程式化干擾影響。 第38圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的導通閘極電壓效應對於程式化干擾影響。 第39圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的區塊抹除轉換電流示意圖。 第40圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的程式化及抹除狀態電流電壓特性示意圖，此 記憶體具有不同數目的程式化/抹除循環。 第41圖為實驗量測之與三維反及閘記憶體連接之多晶 矽二極體的臨界電壓分佈示意圖，此記憶體具有檢查表分 佈之程式化/抹除記憶胞。 【主要元件符號說明】 10、110 :絕緣層 11〜14、111〜114 :長條半導體材料 15、 115 :記憶材料 16、 17、116、117 :導線 18、19、118、119 :金屬矽化物 43 201212168 20、120 :溝渠 21〜24、121〜124 :絕緣材料 25、26、125、126 :主動區域 30〜35、40〜45、70〜78、80、82、84 :記憶胞 51〜56 :長條半導體材料堆疊 60(60-1、60-2、60-3)、61、160〜162 :字元線 86、87 :源極線 90〜95 :區塊選擇電晶體 97、 397 :穿隧介電層 98、 398 :電荷儲存層 99、 399 :阻擋介電層 83 :串列選擇線 85、88、89 :串列選擇電晶體 106、107、108 :位元線 128、129、130 :源/汲極區域 210、 212、214 :絕緣層 211、 213 :半導體 215 .記憶材料層 250 :山脊狀堆疊 315 :電荷捕捉層 225 :導線 226、1426 :金屬矽化物 875、975 :積體電路 860 :具有二極體於記憶串列中的三維可程式電阻唯讀記憶體 陣列 960 :有二極體於記憶串列中的三維反及閘快閃記憶體陣列 858、 958 :平面解碼器 859、 959 :串列選擇線 201212168 861、 961 :列解碼器 862、 962 :字元線 863、 963 :行解碼器 864、 964 :位元線 865、 965、867、967 :匯流排 866、 966 :感測放大器/資料輸入結構 874、974 :其他電路 869、969 :狀態機構 868、968 :偏壓調整供應電壓 871、 971 :資料輸入線 872、 972 :資料輸出線 410、1410 :基板 1412〜1414 :長條半導體材料 1415、1515 :區域 1425-1 到 1425-n :導線Fig. 7 is a cross-sectional view showing the memory cell structure of Fig. 5 along the γ_χ plane. The J diagram shows a schematic diagram of the inverse memory having the structures of Figs. 5 and 23. A door similar to Figure 5 is a three-dimensional anti-gate flash memory ί, a schematic diagram of a generational example. The memory material layer from the wire between the 10th figure shows the memory cell structure of Figure 9 along the ZX Plane 201212168 section view. The f 11 ® display 7F 9th memory cell structure is shown in the alj plane along the γ·χ plane. The 12th display of the memory device of the memory device of FIG. 9 and the manufacturing process of the memory device of FIG. 9 is a cross-sectional view of the first stage of the process. The third embodiment shows the cross-sectional view of the second stage of the manufacturing process. A schematic cross-sectional view showing the second stage of the process of manufacturing the memory device as shown in Fig. 1 is shown. Fig. 5 is a schematic cross-sectional view of the second stage of the process of the memory device. 9 shows the memory device in the figure 9 of the memory device. The first embodiment shows the manufacturing process as shown in the third stage of the process. The figure shows the cross-sectional view of the fourth stage of the i-th process. The simplified embodiment of the integrated circuit of the invention-invention is as follows: The integrated circuit of the towel includes a row, a column and a plane decoding circuit: the only programmable resistance is only (4). _ One dimension No. 18, showing another embodiment according to the present invention, wherein the integrated circuit includes an array of rows, columns, and flats == anti-gate flash memory. The electric < one-dimensional sub-iLL diagram is a part of the three-dimensional anti-free flash memory array. Figure 20 shows a three-dimensional inverse and inter-flash body == bit line structure and memory series between two sides Yes, two memory cell planes are displayed, and each of the planes is two 41 201212168. The first 2 2 figure shows the timing intent of the stylized operation similar to the array in Figure 2. Fig. 23 is a cross-sectional view showing the operation of the bit line structure having the dipole in the series and the memory string in the three-dimensional inverse gate flash memory structure. ^ 24 Figure shows a cross-sectional view of a three-dimensional anti-gate flash memory structure with a bit line structure and a memory serialization operation of the diode. You have a schematic diagram between the 70-line structure and the memory string of the two-pole Sun Botian 列 column in the private body 3 2D three-dimensional anti-gate flash memory structure, which uses the polycrystalline stone embolism as the diode. . The figure shows that the three-dimensional inverse gate flash memory junction has a cross-sectional view between the source line structure and the memory string of the diode. In this case, 2i歹 ‘_^ has two poles showing a schematic diagram between two structures and a memory string, which is: ^^. In the figure 21, the stylized operation of the array is the second.. ^ ^ ^ ^ ^b# ^ ^ of the program outline - a similar to the three-dimensional anti-free flash in Figure 27 The two η schematic 'shows in this illustration that the string includes a diode 第 = = pole line structure and a memory string. The timing of the example! ^ Figure. A stylized operation of the array in Figure 31 201212168 Figures 33A and 33B are photographs of a tunneling electron microscope of a portion of a three-dimensional inverse gate flash memory array. Figure 34 is a graph showing the current-voltage (IV) characteristics of the experimentally measured polycrystalline germanium diode. Figure 35 is a graph showing the read current characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. Figure 36 is a diagram showing the stylized suppression characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. Figure 37 shows the effect of the source bias effect of the polycrystalline ruthenium diode connected to the three-dimensional inverse gate memory on the stylized interference. Figure 38 shows the effect of the on-gate voltage effect of the polysilicon 矽 diode connected to the three-dimensional inverse gate memory on the stylized interference. Figure 39 is a schematic diagram showing the block erase conversion current of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. Figure 40 is a schematic diagram showing the stylized and erased state current-voltage characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a different number of stylized/erase cycles. Figure 41 is a schematic diagram showing the critical voltage distribution of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a stylized/erased memory cell with a checklist distribution. [Description of main component symbols] 10, 110: insulating layers 11 to 14, 111 to 114: elongated semiconductor materials 15, 115: memory materials 16, 17, 116, 117: wires 18, 19, 118, 119: metal telluride 43 201212168 20,120: trenches 21 to 24, 121 to 124: insulating materials 25, 26, 125, 126: active regions 30 to 35, 40 to 45, 70 to 78, 80, 82, 84: memory cells 51 to 56 : Long strip of semiconductor material stack 60 (60-1, 60-2, 60-3), 61, 160~162: word line 86, 87: source line 90~95: block selection transistor 97, 397: Tunneling dielectric layers 98, 398: charge storage layer 99, 399: blocking dielectric layer 83: series select lines 85, 88, 89: tandem selection transistors 106, 107, 108: bit lines 128, 129, 130: source/drain regions 210, 212, 214: insulating layers 211, 213: semiconductor 215. memory material layer 250: ridge-like stack 315: charge trapping layer 225: wires 226, 1426: metal telluride 875, 975: product Body circuit 860: a three-dimensional programmable resistance read-only memory array 960 having a diode in a memory string: a three-dimensional inverse gate flash memory with a diode in the memory string Arrays 858, 958: Planar Decoders 859, 959: Tandem Select Lines 201212168 861, 961: Column Decoders 862, 962: Word Lines 863, 963: Row Decoders 864, 964: Bit Lines 865, 965, 867 967: Busbars 866, 966: sense amplifier/data input structure 874, 974: other circuits 869, 969: state mechanisms 868, 968: bias adjustment supply voltage 871, 971: data input lines 872, 972: data output Lines 410, 1410: Substrates 1412-1414: elongated semiconductor material 1415, 1515: regions 1425-1 through 1425-n: wires
1427 :串列選擇線SSL 1428 :整體源極線GSL 1449 : P+佈植區域 1450、1451、1550、1551 :栓塞 1491 :導電材料 1492、1592 :二極體 1106 :串列選擇線 1110〜1113 :二極體 1160〜1162 :導線 1170〜1175、1180、1182 :記憶胞 1190、1191 :接地選擇電晶體 1196、1197 :串列選擇電晶體 451427: Tandem selection line SSL 1428: integral source line GSL 1449: P+ implant area 1450, 1451, 1550, 1551: plug 1491: conductive material 1492, 1592: diode 1106: tandem select line 1110~1113: Dipoles 1160 to 1162: wires 1170 to 1175, 1180, 1182: memory cells 1190, 1191: ground selection transistors 1196, 1197: tandem selection transistor 45
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| Application Number | Priority Date | Filing Date | Title |
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| US37929710P | 2010-09-01 | 2010-09-01 | |
| US13/011,717 US8659944B2 (en) | 2010-09-01 | 2011-01-21 | Memory architecture of 3D array with diode in memory string |
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| TWI427744B TWI427744B (en) | 2014-02-21 |
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| JP (1) | JP5977003B2 (en) |
| KR (1) | KR20120022676A (en) |
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Also Published As
| Publication number | Publication date |
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| KR20120022676A (en) | 2012-03-12 |
| TWI427744B (en) | 2014-02-21 |
| CN102386188B (en) | 2014-01-22 |
| JP2012054550A (en) | 2012-03-15 |
| CN102386188A (en) | 2012-03-21 |
| JP5977003B2 (en) | 2016-08-24 |
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