CN104576595B - Integrated circuit and its operating method - Google Patents
Integrated circuit and its operating method Download PDFInfo
- Publication number
- CN104576595B CN104576595B CN201310482109.9A CN201310482109A CN104576595B CN 104576595 B CN104576595 B CN 104576595B CN 201310482109 A CN201310482109 A CN 201310482109A CN 104576595 B CN104576595 B CN 104576595B
- Authority
- CN
- China
- Prior art keywords
- conductive
- laminated construction
- integrated circuit
- stripe
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of integrated circuit and its operating method, the integrated circuit includes a laminated construction and a conductive structure；Laminated construction includes a conductive stripe；Conductive structure is located above laminated construction, and is electrically connected to conductive stripe；Conductive structure has different clearance distances between different groups of corresponding points from conductive stripe according to standard shaft.
Description
Technical field
There is conductive structure the invention relates to a kind of integrated circuit and its operating method, and in particular to one kind
Integrated circuit and its operating method.
Background technology
When critical dimension to the limit for being commonly stored monotechnics of the device in integrated circuit, designer then turns
And seek the multiple layer stack planar technique of memory cell to reach higher storage density, and each bit it is relatively low into
This.For example, thin-film transistor technologies are had been applied among charge capturing memory.In addition, plotted point array technique
Have been applied among antifuse memory.
In a cubical array, the structure electrical characteristic in different estate (1evel) can cause to program, wipe and
The dynamic of electric charge storage is different, is included in the change that different estate asks these memory cell critical voltage corresponding with storage state
It is dynamic.Therefore, in order to reach the optimization that memory cell in each layer reads and writes quality, programming and erase process to some extent must
The variation of the different interlayers of Destination Storage Unit must be adapted to.These variations also result in endurance problem and the generation of memory cell
Other challenges.
In a cubical array, the e.g. access line of main bit line is arranged to the not same order for accessing this array
Layer, it is necessary to enable its be, for example, the characteristic of electric capacity or inductance with the circuit coupled because variation between different layers
It is different and and then change.For example, main bit line be typically extend to for read and write storage unit sensing circuit.
The perpendicular connectors of different interlayers and other different qualities can cause the capacitance between main bit line to produce variation.These electric capacity
The difference of value can influence status of a sovereign line voltage when reading, programming or erasing operation, and can influence the demand of specification, be, for example,
Larger reading is interval between programming and erase status.
Therefore need to provide a kind of integrated circuit, it is wrapped to reduce because the complexity caused by the difference of different interlayers is asked
Topic.
The content of the invention
The invention relates to a kind of integrated circuit and its operating method, with average inductance capacitance.
According to an embodiment, a kind of integrated circuit, including a laminated construction and a conductive structure are proposed；Laminated construction includes
One conductive stripe；Conductive structure is located above laminated construction, and is electrically connected to conductive stripe；Conductive structure exists with conductive stripe
There are different clearance distances according to standard shaft between the corresponding points of difference group.
According to another embodiment, a kind of operating method of integrated circuit is proposed, integrated circuit is folded including a three-dimensional storage
Layer and a conductive structure；Three-dimensional storage lamination include a neighbouring dummy part and a memory portion, the dummy part and
The memory portion includes a laminated construction, a dielectric layer, one first conductive layer and one second conductive layer；Laminated construction includes
One conductive stripe；First conductive layer is electrically insulated from conductive stripe by dielectric layer；The opposing end portions of conductive stripe are by electricity respectively
Property is connected to the second conductive layer and conductive structure；First conductive layer is configured between the opposing end portions of conductive stripe；Operation side
Method comprises the following steps：A first voltage is provided to the conductive structure of dummy part；A second voltage is provided to dummy part
Second conductive layer；First voltage is equal to second voltage.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, are described in detail below：
Brief description of the drawings
Fig. 1 is the schematic diagram of the integrated circuit according to an embodiment.
Fig. 2 is the schematic diagram of the integrated circuit according to an embodiment.
Fig. 3 is the top view of the integrated circuit according to an embodiment.
Fig. 4 is the top view of the integrated circuit according to an embodiment.
Fig. 5 is the schematic diagram of the integrated circuit according to a comparative example.
【Symbol description]
102：Laminated construction
104：Dielectric layer
106、106A、106B、106C、106D：First conductive layer
108：Second conductive layer
110、210：Conductive structure
112：Substrate
114：Conductive stripe
116：Dielectric striped
118：Conductive ladder
119：Conductive plunger
120、220：Conductor wire
122：Conductive plate
124：Dummy part
126：Memory portion
D1、D2、D3、D4：Distance
Embodiment
Fig. 1 is the schematic diagram of the integrated circuit according to an embodiment, and integrated circuit includes three-dimensional (3D) memory stacks, its
Including laminated construction 102, dielectric layer 104, first conductive layer 106A, 106B, 106C, 106D and the second conductive layer 108；Integrated electricity
Road also includes conductive structure 110.
Fig. 1 is refer to, the laminated construction 102 of difference row (for example extending toward Z-direction) is configured separately of each other in substrate
On 112.Laminated construction 102 respectively includes multiple cross laminates and conductive stripe 114 and dielectric striped 116 for vertical bar shape.Dielectric
Striped 116 is similar to conductive stripe 114, is the structure that vertical bar shape continuously extends, and in order to clearly show that the integrated electricity of embodiment
The structure on road, it is conductive between first conductive layer 106A, 106B, 106C, 106D and second that Fig. 1 does not show dielectric striped 116
Part between layer 108.
The opposing end portions of conductive stripe 114 are to be respectively and electrically connected to the conductive layer 108 of conductive structure 110 and second.It is conductive
First conductive layer 106A, 106B, 106C, 106D between the opposing end portions of striped 114 is electrically insulated from by dielectric layer 104
Conductive stripe 114.First conductive layer 106A of bearing of trend (such as X-direction) not same page (page) parallel to each other, 106B,
106C, 106D can be separated from each other with the second conductive layer 108 by dielectric structure (not shown).
Conductive structure 110 is located at the top of laminated construction 102, and electrical with conductive plunger (plug) 119 by conductive ladder 118
It is connected to conductive stripe 114.In this example, conductive structure 110 includes conductor wire 120 separated from each other, and it is electrically connected to not
With the conductive stripe 114 of the identical stratum of laminated construction 102 of row.Conductive stripe 114 has zigzag or ladder as shown in Figure 1
Shape, or other suitable shapes.
In one embodiment, the conductive stripe 114 of laminated construction 102 is used as bit line (BL).Configuration is in laminated construction 102
On the wall of side and the first conductive layer 106A of neighbouring conductive ladder 118 is used as concatenation selection line (SSL), wherein can be by providing to the
One conductive layer 106A voltages, to control neighbouring conductive stripe 114 to be selection (selected) state (or opening) or be
Non-selected (unselected) state (or closed mode).The second conductive layer 108 away from conductive ladder 118 is used as common source
Line (common source line, CSL), is electrically connected to the conductive stripe 114 of the laminated construction 102 of different rows.Neighbouring the
First conductive layer 106D of two conductive layers 108 is used as ground connection selection line (GSL).First conductive layer 106A and the first conductive layer
First conductive layer 106B, 106C between 106D is used as wordline (WL).
First conductive layer 106B, 106C (WL) of embodiment number of pages, the row of laminated construction 102, conductive stripe 114
Stratum's number, conductor wire 120 etc. are not limited to number as shown in Figure 1, and visual actual state is respectively designed to more or less
Number.In embodiment, conductive material may include metal, polysilicon, metal silicide or other suitable materials.Dielectric material
It may include oxide or silicide, such as silica, silicon nitride or silicon oxynitride, or other suitable materials.
Fig. 2 illustrates the schematic diagram of the integrated circuit according to an embodiment, and its Discrepancy Description with Fig. 1 is as follows.Conductive structure
110 include conductive plate 122, and the bearing of trend of its major axis is not parallel to the extension of each laminated construction 102 (or conductive stripe 114)
Direction.Conductive plate 122 is electrically connected to the conductive stripe 114 of the identical stratum of different laminated construction 102, and electrically connects simultaneously
It is connected to these conductive stripes 114 of the different estate of each laminated construction 102.
Fig. 3 is refer to, it is the top view of the integrated circuit according to an embodiment, wherein, for the sake of clarity, only show and lead
Electric striped 114, the first conductive layer 106 and conductive structure 110.Conductive structure 110 includes conductive plate 122 separated from each other and conduction
Line 120, it is configured in same stratum（Such as the 3rd rank metal level (M3)).First conductive layer 106 and the (figure of the second conductive layer 108
1) bearing of trend (such as X-direction) is the bearing of trend (such as Z-direction) with the conductive stripe 114 of laminated construction 102 (Fig. 1)
It is interlaced with each other.
Three-dimensional storage lamination includes neighbouring dummy part 124 and memory portion 126.In one embodiment, citing comes
Say, dummy part 124 is disposed between memory portion 126.Memory portion 126 is led with neighbouring dummy part 124
Electric striped 114 is electrically connected to the conductor wire 120 of conductive structure 110, and the three-dimensional storage lamination of this part is similar to Figure 1
Structure.Leading for conductive structure 110 is electrically connected to away from its conductive stripe 114 of the dummy part 124 of memory portion 126
Electroplax 122, the three-dimensional storage lamination of this part structure similar to Figure 2.In one embodiment, dummy part 124 and storage
Device part 126 is shared single the second conductive layer 108 (or common source line) (Fig. 1, Fig. 2).
In embodiment, conductive structure 110 and the bearing of trend of conductive stripe 114 are not parallel to each other, or integrated circuit configuration
There is dummy part 124, thereby compensate (compensate) different bit architecture (upper surface face of such as Fig. 1 conduction ladder 118
Product) capacitance difference that causes, and cause integrated circuit that there is average inductance capacitance.For example, regarded from shown in Fig. 3
From the point of view of figure, conductor wire 120 is the conductive stripe 114 that its electric connection is gradually distance from from end section toward center section.Conductive plate
122 long edge is the conductive stripe 114 for the most edge row that its electric connection is gradually distance from from end section toward center section.Or
Person, conductive structure 110 has different clearance distances between different groups of corresponding points from conductive stripe 114 according to standard shaft.Lift
For example, conductive plate 122 and conductive stripe 114 are between different groups of corresponding points according to standard shaft（Such as Z axis) with different
Clearance distance（For example it is more than apart from D1 apart from D2).Or, conductor wire 120 and conductive stripe 114 different groups corresponding points it
Between different clearance distances (being for example more than apart from D3 apart from D4) are had according to standard shaft (such as Z axis).
In embodiment, the operating method of integrated circuit includes programming, reads and wipe the memory of three-dimensional storage lamination
Part 126 (Fig. 3).During memory portion 126 is operated, it is to provide first voltage to the conduction knot of dummy part 124
Structure 110, and second voltage is provided to the second conductive layer 108 (Fig. 1) of dummy part 124, wherein first voltage is equal to the second electricity
Pressure.
Referring to Fig. 1 to Fig. 3.For example, the method for programmable memory part 126 comprises the following steps：There is provided
One voltage（Such as 0V) to conductor wire 120；A voltage to the first conductive layer 106A (concatenation selection line) is provided, to select (or to open
Open) conductive stripe 114；There is provided one by the first conductive layer 106B of voltage (Vpass) or program voltage (Vpgm) to not same page,
106C (wordline)；A voltage to the first conductive layer 106D (ground connection selection line) is provided, to close conductive stripe 114；One electricity is provided
Pressure（Such as power source voltage Vcc) to the second conductive layer 108 (common source line).
It is dummy part 124 not to be programmed, method is said while step is programmed to memory portion 126
It is bright as follows：Identical (first) voltage is provided（Such as power source voltage Vcc) to dummy part 124 the first conductive layer 106A with leading
Electric structure 110 (conductor wire 120 or conductive plate 122).In one embodiment, for example, the first conductive layer of dummy part 124
106A is by a conducting element adjacent to the part of conductive structure 110 with conductive stripe 114（Such as metal level, does not show) it is short
Connect, therefore shared (first) voltage can simultaneously be provided to the first conductive layer 106A and conduction (from conductive structure 110)
Striped 114.First conductive layer 106B, 106C (wordline) of dummy part 124 is shared with memory portion 126, therefore is provided
Voltage be same as memory portion 126.Identical (second) voltage is provided（Such as power source voltage Vcc) to dummy part 124
The first conductive layer 106D and the second conductive layer 108.In one embodiment, for example, the first conductive layer of dummy part 124
106D and the second conductive layer 108 are by a conducting element（Such as metal level, does not show) short circuit, therefore can be with one shared (the
Two) voltage is provided to the first conductive layer 106D and the second conductive layer 108 simultaneously.
The method for reading memory portion 126 comprises the following steps：One voltage is provided（Such as 1V) to conductor wire 120；Carry
For a voltage (such as power source voltage Vcc) to the first conductive layer 106A (concatenation selection line), to open conductive stripe 114；There is provided
One passes through voltage (Vpass) to first conductive layer 106B, 106C (wordline)；A voltage (such as power source voltage Vcc) is provided to
One conductive layer 106D (ground connection selection line), to open conductive stripe 114；A voltage (being for example grounded) is provided to the second conductive layer
108 (common source lines).
It is dummy part 124 not to be sensed, method is said while step is read out to memory portion 126
It is bright as follows：Identical (first) voltage (such as 0V) is provided to the first conductive layer 106A and conductive structure 110 of dummy part 124
(conductor wire 120 or conductive plate 122)；Identical (second) voltage (such as 0V, or ground connection) is provided to the first of dummy part 124
Conductive layer 106D and the second conductive layer 108.
The method of erasing memory portion 126 comprises the following steps：A voltage (such as 14V) is provided to conductor wire 120；Carry
For a voltage to the first conductive layer 106A (concatenation selection line), to open conductive stripe 114；A voltage (such as 0V) is provided to
One conductive layer 106B, 106C (wordline)；A voltage to the first conductive layer 106D (ground connection selection line) is provided, to open conductive stripe
114；A voltage (such as 14V) is provided to the second conductive layer 108 (common source line).
It is that dummy part 124 is wiped while erasing step is carried out to memory portion 126, method explanation
It is as follows：There is provided identical erasing bias (erasing bias) (such as 14V) to dummy part 124 first conductive layer 106A with
Conductive structure 110 (conductor wire 120 or conductive plate 122)；There is provided identical (second) voltage (such as 14V, or ground connection) extremely dummy
The the first conductive layer 106D and the second conductive layer 108 of part 124.
Fig. 4 is the top view of the integrated circuit according to an embodiment, and its Fig. 3 Discrepancy Description is as follows：First conductive layer 106
Bearing of trend（Such as X-direction) it is bearing of trend with conductor wire 120（Such as Z-direction) it is interlaced with each other；Laminated construction 102
Conductive stripe 114 has zigzag or stepped, and bearing of trend is not parallel to conductor wire 120.
Fig. 5 illustrates the integrated circuit of a comparative example, and the difference of itself and the integrated circuit of embodiment is, conductive structure 210
For conductor wire 220 of the bearing of trend parallel to conductive stripe 114.Compared to comparative example, embodiments of the invention (conductive structure
110 are not parallel to each other with the bearing of trend of conductive stripe 114) there is average inductance capacitance.
In summary, although the present invention is disclosed above with embodiment, so it is not limited to the present invention.Institute of the present invention
Has usually intellectual in category technical field, without departing from the spirit and scope of the present invention, when various change and profit can be made
Decorations.Therefore, protection scope of the present invention is when depending on being defined that appended claims scope is defined.
Claims (9)
1. a kind of integrated circuit, including a three-dimensional storage lamination, the three-dimensional storage lamination are deposited including a dummy part with one
Reservoir portion, the dummy part respectively includes with the memory portion：
One laminated construction, including multiple conductive stripes；And
One conductive structure, above the laminated construction, and is electrically connected to the plurality of conductive stripe, wherein the conductive structure bag
Multiple conductor wires and a conductive plate are included, the plurality of conductive stripe system of the laminated construction of the memory portion is electrically connected to this
A part for multiple conductor wires, the plurality of conductive stripe system of the laminated construction of the dummy part is electrically connected to the conductive plate
Or another part of the plurality of conductor wire, the conductive structure and the plurality of conductive stripe are between different groups of corresponding points according to base
Axle has different clearance distances, and the conductive structure and the bearing of trend of the plurality of conductive stripe are not parallel to each other.
2. integrated circuit according to claim 1, the wherein conductive plate are configured between these conductor wires, wherein the conduction
Plate and these conductor wires are separated from each other and all configure in same stratum.
3. integrated circuit according to claim 1, the wherein conductive plate and the conductive stripe different groups corresponding points it
Between there are different clearance distances according to standard shaft.
4. multiple conductive stripes in integrated circuit according to claim 1, the wherein laminated construction are separated from each other, this is led
Conductive plate in electric structure, is electrically connected to these conductive stripes of the identical stratum of each laminated construction, and is electrically connected with simultaneously
To these conductive stripes of the different estate of each laminated construction.
5. integrated circuit according to claim 1, the wherein conductor wire and the conductive stripe different groups corresponding points it
Between there are different clearance distances according to standard shaft.
6. multiple conductive stripes in integrated circuit according to claim 1, the wherein laminated construction are separated from each other, this is led
Conductor wire in electric structure, is electrically connected to these conductive stripes of the identical stratum of each laminated construction.
7. integrated circuit according to claim 1, wherein the three-dimensional storage lamination also include：
One dielectric layer；
One ground connection selection line (GSL)；
One common source line (common source line, CSL)；And
Connect selection line for a string, configure on the side wall of the laminated construction, and by the dielectric layer be divided in the laminated construction should
Conductive stripe,
Wherein the ground connection selection line is electrically insulated from the conductive stripe of the laminated construction by the dielectric layer, and the wherein ground connection is selected
Select line and the conductive stripe is interlaced with each other, the ground connection selection line and the mutual short circuit of the common source line, the concatenation selection line is with being somebody's turn to do
The mutual short circuit of conductive stripe.
8. a kind of operating method of integrated circuit, the wherein integrated circuit include：
One three-dimensional storage lamination, including a neighbouring dummy part and a memory portion, the dummy part and the memory
Part includes：
One laminated construction, including a conductive stripe；
One dielectric layer；
One first conductive layer, the conductive stripe is electrically insulated from by the dielectric layer；And
One second conductive layer；And
The opposing end portions of one conductive structure, the wherein conductive stripe are respectively and electrically connected to second conductive layer and tied with the conduction
Structure, first conductive layer is configured between these opposing end portions of the conductive stripe；
The operating method includes：
A first voltage is provided to the conductive structure of the dummy part；And
A second voltage is provided to second conductive layer of the dummy part, the wherein first voltage is equal to the second voltage.
9. the operating method of integrated circuit according to claim 8, further includes programming, reads and wipes the three-dimensional storage
Memory portion of lamination, wherein during the programming, the reading and the erasing, the first voltage is equal to second electricity
Pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310482109.9A CN104576595B (en) | 2013-10-16 | 2013-10-16 | Integrated circuit and its operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310482109.9A CN104576595B (en) | 2013-10-16 | 2013-10-16 | Integrated circuit and its operating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104576595A CN104576595A (en) | 2015-04-29 |
| CN104576595B true CN104576595B (en) | 2017-08-15 |
Family
ID=53092293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310482109.9A Active CN104576595B (en) | 2013-10-16 | 2013-10-16 | Integrated circuit and its operating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104576595B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3827461B1 (en) * | 2018-10-18 | 2023-08-02 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device having zigzag slit structures and method for forming the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6643159B2 (en) * | 2002-04-02 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Cubic memory array |
| US6831854B2 (en) * | 2002-08-02 | 2004-12-14 | Unity Semiconductor Corporation | Cross point memory array using distinct voltages |
| TWI427744B (en) * | 2010-09-01 | 2014-02-21 | Macronix Int Co Ltd | Memory architecture of 3d array with diode in memory string |
| CN102623457B (en) * | 2011-01-26 | 2015-04-15 | 旺宏电子股份有限公司 | Semiconductor structure, manufacturing method thereof and operating method |
-
2013
- 2013-10-16 CN CN201310482109.9A patent/CN104576595B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104576595A (en) | 2015-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9595566B2 (en) | Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines | |
| CN105374395B (en) | Memory component and its operating method | |
| CN104364849B (en) | Reduce the weak erasing type reading interference in 3D NAND non-volatile memories | |
| US10615173B2 (en) | Three dimensional semiconductor memory devices | |
| US8933516B1 (en) | High capacity select switches for three-dimensional structures | |
| CN103038882B (en) | Three-dimensional storage and the method forming described three-dimensional storage | |
| CN109524408A (en) | Semiconductor memory | |
| US9703719B2 (en) | Fast read for non-volatile storage | |
| CN106601745A (en) | A memory device | |
| KR20150035787A (en) | Method for forming staircase word lines in a 3d non-volatile memory having vertical bit lines | |
| CN107767911A (en) | Non-volatile memory device and data manipulation method | |
| CN102800361A (en) | 3-dimensional non-volatile memory device and method of manufacturing the same | |
| CN102610260A (en) | Integrated circuit device | |
| CN107358973A (en) | Include the non-volatile memory device of sub- common source | |
| TW202006933A (en) | Semiconductor memory | |
| CN205282476U (en) | Nonvolatile memory on semiconductor substrate | |
| CN105938836A (en) | Semiconductor device | |
| CN105304669A (en) | Non-volatile resistance-variable storage circuit and control method thereof | |
| CN104576595B (en) | Integrated circuit and its operating method | |
| CN107154273A (en) | Semiconductor storage | |
| CN104241521A (en) | Memory array and operation method and manufacturing method thereof | |
| US9177964B2 (en) | Methods of forming sidewall gates | |
| TWI515745B (en) | Three-dimensional memory device | |
| US9245603B2 (en) | Integrated circuit and operating method for the same | |
| CN104751890B (en) | Apply to the control method of the non-volatility memorizer of orthogonal array structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |