CN104112745B - 3 D semiconductor structure and its manufacture method - Google Patents

Abstract

The invention discloses a kind of semiconductor structure and its manufacture method, the structure includes multiple laminated tapes on a substrate and multiple conductor wires on the multiple laminated tape.The multiple laminated tape and the multiple conductor wire are configured orthogonally with respect to one another and a conductive gasket is formed between it.The space between two neighbouring laminated tapes is filled and under the conductor wire in one first space, wherein the conductor wire is positioned at the upper of described two neighbouring laminated tapes；And a Second gap is located between two neighbouring conductor wires.The material of the conductive gasket is different from the material of the multiple conductor wire.The distance between described two neighbouring laminated tapes are in below 200nm, and the depth-width ratio of the laminated tape is at least 1.

Description

3 D semiconductor structure and its manufacture method

Technical field

The present invention is on semiconductor structure, especially with regard to 3-dimensional (3D) semiconductor structure and its manufacture method.

Background technology

Due to in semiconductor industry high-density storage (for example, floating gate memory, charge capturing memory, Nonvolatile memory and in-line memory) tight demand, the framework of memory cell is changed into 3-dimensional from planar structure Structure, 3-dimensional structure helps to increase the storage volume in limited chip area.Crosspoint array (cross-point arrays) It is a form of the 3D memory constructions for including multiple wordline, multiple bit lines and sandwiching accumulation layer between wordline and bit line.

Under the continuous downward trend of component size, not only bit line (and wordline) dimensional contraction of itself, between it away from From also shrinking.For crosspoint array, by producing multiple memory cell in the footprint area in crosspoint, the height of bit line is wide Than being constantly increasing in order to pursue higher storage density.The problem of structure on being formed compared with large ratio of height to width is produced in process Also wordline is betided, this makes so for the laminated construction of 3D memories.It is for example anisotropic that strip pattern (bit line or wordline) defines program Property etching can be because face the test more sternly completed compared with the narrow space between large ratio of height to width and bit line (wordline).Above-mentioned pattern circle There is flaw to cause bridge effect (bridging effect) and cause storage arrangement not operate if determining program.

In known crosspoint 3D memory constructions, when the space between wordline reduces, the coupling between wordline and wordline Effect (word-line to word-line coupling) becomes serious problems.Wordline coupling is attributable to longer wordline And narrower interval between wordline, and certainly, it is known that 3D memory constructions form high overlapping area between adjacent word line, can therefore Increase coupled capacitor.

Therefore, 3D memory constructions need the generation efficiently against bridge joint and coupling effect.If however, fabrication schedule is simple List and cost is controlled, the structure is by with bigger demand.

The content of the invention

It is a goal of the present invention to provide 3-dimensional (3D) organization of semiconductor memory and its manufacture method.

One embodiment demonstration semiconductor structure, it includes：One substrate；Multiple laminated tapes, it is configured in parallel with each other, and It is positioned on the substrate；And multiple conductor wires, it is configured in parallel with each other, and is orthogonally positioned on these laminated tapes.Because Not all basal surfaces of the conductor wire with the laminated tape conformal (conformal), so one first space fill two neighbours Space between nearly laminated tape and below the conductor wire, the conductor wire is positioned on this two neighbouring laminated tapes；And one Two spaces are between two neighbouring conductor wires.The distance between two neighbouring laminated tapes are in below 200nm, and the height of laminated tape is wide Than being at least 1.

Above-mentioned semiconductor structure can be manufactured by least two methods.The example of the present invention is to form multiple on a substrate Laminated tape, and then meet a conductive gasket of the pattern of these laminated tapes by conformal deposit formation.Deposit and pass through this A little lower stacks bands support a non-conformal conductive membrane layer, are followed by a non-conformal conductive thin of the pattern for defining these conductor wires Etched film step.

Another example of the present invention meets this to form multiple laminated tapes on a substrate by conformal deposit formation One conductive gasket of the pattern of a little laminated tapes.One planarization program continue with can ashing material fill and lead up to the top table of the laminated tape Face, and then etch-back this can ashing material with exposure the conformal conductive pad.Multiple conductor wires are formed parallel to each other in this Can ashing material layer it is upper and contacted with the conductive gasket that this is exposed through.In this example, removed after these conductor wires are formed This can ashing material layer.

As used herein, "or" be inclusive inclusive-OR operation son and be equivalent to " and/or ", unless context is clear in addition Indicate clearly.In addition, throughout this specification, the meaning of " one " and "the" includes multiple reference substances." coupling " represents that element can be straight Connect or can be connected via one or more intermediates in succession.

The technical characteristic and advantage of the present invention are quite widely summarized above, so that the present invention hereafter is described in detail To obtain better understanding.Constituting the other technical characteristics and advantage of the claim of the present invention will be described below.Institute of the present invention State in technical field and have usually intellectual it will be appreciated that can comparatively easy can using the concept and specific embodiment that are disclosed below Realized and identical purpose of the present invention as changing or designing other structures or manufacture craft.In technical field of the present invention Has usually intellectual it should also be understood that this kind of equivalent construction can not depart from spirit of the invention and the model that claim is defined Enclose.

Brief description of the drawings

Fig. 1 is the perspective view of 3-dimensional (3D) organization of semiconductor memory of one embodiment of the invention；

Fig. 2 to Fig. 7 for one embodiment of the invention 3-dimensional (3D) organization of semiconductor memory manufacture method the step of bow View and cross section taken in correspondence figure；And

Fig. 8 to Figure 15 is the step of another manufacture method of 3-dimensional (3D) organization of semiconductor memory of one embodiment of the invention Rapid top view and cross section taken in correspondence figure.

【Main element symbol description】

10 3D memory constructions

11 substrates

12A laminated tapes

12B laminated tapes

13A conductor wires

13B conductor wires

14 accumulation layers

15 conductive gaskets

16 insulating barriers/interlayer dielectric (ILD)

21 substrates

22 laminated tapes

34 conductive gaskets

35 accumulation layers

42 laminated tapes

43 conductive films

46 side walls

53 conductive films

54 conductive gaskets

57 photoresists

63 conductive films

64 conductive gaskets

65 accumulation layers

67 photoetching agent patterns

72 laminated tapes

73 conductor wires

76 first spaces

77 insulating barriers

78 Second gaps

84 conductive gaskets

86 can ashing material

87 accumulation layers

94 conductive gaskets

96 TOPAZ

103 conductive films

104 conductive gaskets

106 TOPAZ

113 conductive films

115 photoresists

121 conductive strips

122 insulating tapes

123 conductive strips

123 ' conductor wires

124 insulating tapes

124 ' conductive gaskets

125 photoresists

126 TOPAZ

133 conductor wires

134 conductive gaskets

135 photoresists

136 TOPAZ

137 accumulation layers

142A laminated tapes

142B laminated tapes

143 conductor wires

151 first spaces

152 laminated tapes

153 conductor wires

156 Second gaps

158 insulating barriers

159 side walls

D distances

H height

W width

Embodiment

The present invention will be described according to institute's accompanying drawings.

Fig. 1 illustrates a part for the 3D memory constructions 10 according to one embodiment of the invention.Two laminated tapes (12A, 12B) it is positioned in parallel with each other on substrate 11 along x-axis comprising conductive strips (121,123) and insulating tape (122,124).Two Individual conductor wire (13A, 13B) is parallel to each other and be positioned on two laminated tapes along y-axis.In the present embodiment, laminated tape is determined To the orientation (y-axis) of (x-axis) relative to conductor wire to be orthogonal.However, the configuration of scope of the invention not limited to this and any angle It can all be covered by scope of the invention.In the present embodiment, the distance between two laminated tapes (12A, 12B) D is 150nm, And the depth-width ratio (that is, height H with width W) of laminated tape is 10.However, below 200nm any appointing apart from D and more than 1 What depth-width ratio (H/W) all can be applied to memory construction 10.

At least two spaces are present in memory construction 10.One of space person fills two laminated tapes (12A, 12B) Between space and below conductor wire 13A.In other words, conductor wire 13A is propped up in structure by lower stacks band (12A, 12B) Support.Another space is between two conductor wires (13A, 13B) and below insulating barrier 16.In one embodiment, laminated tape (12A, Can be 12B) bit line and conductor wire (13A, 13B) can be wordline.The presence at least two spaces has separated neighbouring conductor wire and neighbour Nearly laminated tape.In one embodiment, two spaces form a connectivity structure.

For brevity, description concentrates on a laminated tape or a conductor wire, and described material and structural configuration below It is applicable to all laminated tape/conductor wires in memory construction.Laminated tape 12A in the present embodiment is handed over by two kinds of different materials Constituted for multiple insulating tapes/conductive strips 121 to 124 of configuration.For example, insulating tape 122 and 124 can be insulating materials, all Such as silica, other silica or silicon nitride；And conductive strips 121 and 123 can be conductive material, do not have doping such as or have There are the polysilicon or monocrystalline silicon of n-type or p-type doping.Insulating tape 122 and 124 be by low-pressure chemical vapor deposition LPCVD (not with Restrictive one describe) prepare silica.The explanation in a unlimited number in the present invention of insulating tape/conductive strips, and a pair of insulation The combination of band-conductive strips can implement the function of memory construction of the present invention.Figure in describing below does not show the thin of laminated tape Portion's structure, but be applicable to according to the laminate tape structure of foregoing description in following description.

Accumulation layer 14 is formed to conformal with laminated tape 12A surface.The material of accumulation layer 14 is designed via energy gap Composite tunnel dielectric substance layer, it includes a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer.Per monoxide or nitridation The thickness of nitride layer in nano-scale, and other embodiments can by five alternate thin dielectric substance layers (that is, silica, nitridation Silicon, silica, silicon nitride, silica) it is used as accumulation layer 14.In one embodiment, LPCVD is to form nitride or oxide Thin dielectric substance layer.

The surface that 1nm to 5nm conductive gasket 15 is formed to the accumulation layer 14 with previously depositing is conformal.Accumulation layer 14 is pressed from both sides It is placed between conductive gasket 15 and laminated tape 12A.Conductive gasket 15 is deposited to provide laminated tape 12A smooth interfaces and in lamination Formed and be electrically coupled between band 12A and conductor wire (13A, 13B).The conformality of conductive gasket 15 can be avoided in conductive gasket 15 with covering There is any space between the laminated tape 12A for covering deficiency.The material of conductive gasket 15 may be selected from TiN, TaN, p-type or n-type polycrystalline Silicon, TANOS (TaN/WN/N, Al₂O₃、SiN、SiO₂, Si), WN, W, or its combination, its available technology include CVD programs. In the preferred embodiment, conductive gasket 15 and conductor wire 13A are different in terms of etch-rate.For example, its can be relative to Special etch program has the different materials of different etch-rate.

Conductor wire (13A, 13B) is positioned on laminated tape (12A, 12B), and is electrically connected to form in conductor wire (13A, 13B) Basal surface and laminated tape (12A, 12B) conductive gasket 15 between.Conductor wire can be by such as tungsten silicide, aluminium or TiN/TaN Conductive material is made.Insulating barrier or interlayer dielectric (ILD) 16 are positioned at conduction online, and deposit to be formed with non-conformal manner Continuous film.According to a kind of fabrication schedule applied to the memory construction 10, the program can make a part of side wall of laminated tape Material with micro composition conductor wire, and the section that the part can be covered for laminated tape by conductor wire.More particularly, fold The thick of these conductive wiring materials on the side wall of layer band is at most 1/10th of the thickness of conductor wire.Other manufacture journeys Sequence may not make conductive wiring material on the specific part of laminated tape.Another fabrication schedule can make the side of a part for laminated tape Wall has insulating barrier or ILD materials, and the part includes the section that laminated tape is not covered by conductor wire.

Fig. 2 to Fig. 7 is the step of the manufacture method of 3-dimensional (3D) organization of semiconductor memory according to one embodiment of the invention Rapid top view and cross section taken in correspondence figure.As shown in FIG. 2,20A is the top view of the memory construction in manufacture, and 20B For along 20A dotted line AA cross section.Multiple laminated tapes 22 are formed parallel to each other on substrate 21.Retouched in previous paragraph The laminated construction inside laminated tape has been stated, therefore this section will not describe the detailed fabrication schedule of the laminated construction.In figure 3,30A For the top view of the memory construction in a fabrication schedule, and 30B is along 30A dotted line AA cross section.30B display storages The blanket-deposited of layer 35, continues with another blanket-deposited of conductive gasket 34.The table of two blanket-depositeds and laminated tape Face pattern is conformal, and the pattern of laminated tape has at least 1 depth-width ratio (H/W), and the distance between two proximity band D is preferably 150nm.In one embodiment, deposition procedure can be implemented by LPCVD, and the deposition of wherein accumulation layer 35 may include thin dielectric substance layer Multiple depositions, such as ONO structure (that is, silica (1.5nm)-silicon nitride (3.0nm)-silica (3.5nm)) or ONONO knots Structure.The material of conductive gasket 34 may be selected from TiN, TaN, p-type or n-type polysilicon, TANOS (TaN/WN/N, Al₂O₃、SiN、SiO₂、 Si), WN, W, or its combination.30A shows the top view of the blanket-deposited of conductive gasket 34.

As demonstrated in Figure 4,40A is the top view of the memory construction in manufacture, and 40B is along 40A dotted line AA's Cross section, and 40C is illustrated in the structure of the 40B after chemically mechanical polishing (CMP) program.In this step, first is performed non- Conformal deposit.Continuous conduction film layer is formed via the deposition of non-conformal film.For example, CVD can be used to sink for tungsten silicide Product, and PVD can be used to be formed for aluminium, TiN/TaN.Although PVD is often used as producing the instrument of non-conformal film, in the present invention In, the electric wire bed of material might not must use PVD to be formed.The CVD deposition conductive material of such as tungsten silicide can also achieve institute Want non-conformal film.Also the technique using PVD and CVD can be interacted.As shown in Figure 40 B, non-conformal deposition passes through in lamination Form conductive film 43 on band 42 to start, due to the bad conformality of conductive film, film plane protrusion on the top of laminated tape 42 And laterally grow to meet with accumulating on the film on neighbouring laminated tape 42.To be formed the meeting of film 43 continuous conduction film and Ensure the continuous electric channel on laminated tape 42.However, micro conductive wiring material is possible to be deposited on the side wall of laminated tape 42 On 46.In one embodiment, the thick for the conductive wiring material being deposited on the side wall 46 of laminated tape 42 up to laminated tape On conductive film 43 thickness 1/10th.Therefore, the first space is formed because of the non-conformal deposition of conductive film 43. First space is between two neighbouring laminated tapes 42 and under 43 layers of conductive film.In 40C, the conductive film 43 met Polished by CMP programs with more uniform thickness and flat surfaces.

As shown in figure 5, top views of the 50A for the memory construction in manufacture, 50B is along the transversal of 50A dotted line AA Face, and 50C is along 50A dotted line BB cross section.The pattern of photoresist 57 is formed on conductive film 53, first is followed by Anisotropic etching, preferably reactive ion etching (RIE), remove conductive film 53 the region do not protected by photoresist and Etch stop is at conductive gasket 54.In other words, for the first etchant used in for RIE programs, conductive film Etching selectivity between 53 and conductive gasket 54 is sufficiently high (for example, more than 10).In one embodiment, conductive film 53 Material is tungsten (W), and the material of conductive gasket is TiN.In another embodiment, the material of conductive film 53 is Al, and conductive The material of pad is TiN.In the region that 50A displaying conductive gaskets 54 are protected exposed to unglazed photoresist.Maintain conductive wiring material with High etching selectivity between electroconductive gasket material will ensure that over etching (over-etch) process does not damage laminated tape.Because The higher depth-width ratio (more than 10) of laminated tape (or wordline) in typical 3D memory constructions, in order to remove the remnants in raceway groove Thing, is common means using over etching.

As illustrated in figure 6,60A is the top view of the memory construction in manufacture, and 60B is along 60A dotted line AA's Cross section, and 60C is along 60A dotted line BB cross section.In this step, the second anisotropic etching is performed to remove not The conductive gasket 64 covered by photoetching agent pattern 67.Because the selection of the material as conductive gasket 64 and as conductive film 63 It is the etching selectivity out of the ordinary based on it relative to special etch process, so in order to remove conductive gasket 64, for RIE programs In the second etchant should have and the chemicals different for the first etchant in the first anisotropic etching.Remain conductive High etching selectivity between wire material and electroconductive gasket material will ensure that the second anisotropic etching does not damage conductor wire.60A Show in the region that accumulation layer 65 is protected exposed to unglazed photoresist.If etching selectivity is not high enough to, the side wall of conductor wire can It can be attacked by the second etchant and form narrower conductor wire.The sheet resistance (sheet resistance) of narrower conductor wire will Increase.Therefore, it is preferable etching selectivity to be remained into high system in present treatment step.

As shown in fig. 7,70A is the top view of the memory construction in manufacture, and 70B is along 70A dotted line AA's Cross section, 70C be along 70A dotted line BB cross section, and 70D be along 70A dotted line CC cross section.Dotted line AA is cut in On conductor wire 73；Dotted line BB is parallel with dotted line AA, but is not cut on conductor wire 73；Dotted line CC is vertical with dotted line AA and BB, but not It is cut on laminated tape 72.After the photoresist removal to define conductor wire, perform the second non-conformal deposition to deposit insulation 77 (such as IDL) of layer.Second non-conformal deposition can utilize available oxide deposition technique in this area.However, such as 70C institutes Show, micro insulating materials has an opportunity to be deposited on the side wall of a part for laminated tape 72, the part is not covered by conductor wire Section.

As shown in 70D, the first space 76 between two neighbouring laminated tapes 72 and below the shielded area of conductor wire 73 Defined when conductor wire is formed, and the Second gap 78 between two neighbouring conductor wires 73 is then aoxidized in this non-conformal Thing deposition step is defined when completing.

Fig. 8 to Figure 15 is another manufacturer of 3-dimensional (3D) organization of semiconductor memory according to one embodiment of the invention The top view and cross section taken in correspondence figure of the step of method.Form multiple parallel laminated tapes and take to form conformal conductive pad at these The step of the step of layer can be with described in previous manufacture method (refer to Fig. 2 and Fig. 3) is same or like, and explanation in Fig. 8 Subsequent step.As demonstrated in Figure 8,80A is the top view of the memory construction in manufacture, and 80B is the dotted line AA along 80A Cross section.According to this manufacture method, two can be less than 200nm adjacent to the distance between laminated tape D.Using can be ashed (ashable) material 86 performs planarization program to fill and lead up the laminated tape for being coated with accumulation layer 87 and conductive gasket 84.Can be in response to Difference can ashing material and use with the appropriate speed of rotation spin coating technique, to be suitably filled with the raceway groove between laminated tape. Can ashing material can pass through Oxygen plasma ashing comprising organic dielectric material (ODL), TOPAZ, SHB and BARC etc. Material.In one embodiment, TOPAZ be used as can ashing material because TOPAZ can bear what conductor wire deposition step thereafter was used Depositing temperature, substantially (degradation) is degraded without producing.Among an embodiment, TOPAZ does not produce the temperature substantially degraded Degree can be 500 degree Celsius.

Fig. 9 90A is the top view of the memory construction in manufacture, and 90B is along 90A dotted line AA cross section. TOPAZ96 in this step etch-back (etch back) this structure is to expose a part for conductive gasket 94, and particularly this is sudden and violent The part of dew is the part on laminated tape.Etched using code-pattern（For example, waiting tropism oxygen plasma etch) to hold This etch-back step of row.Figure 10 100A is the top view of the memory construction in manufacture, and 100B is the dotted line along 100A AA cross section.Conductive film 103 is deposited on the conductive gasket 104 of TOPAZ106 and exposure, and wherein conductive film 103 can be P+ or n+ polysilicons, aluminium, tungsten or its combination.In one embodiment, above-mentioned material selection depositing temperature 400 degree Celsius with Under, and selected TOPAZ does not have obvious degradation during conductive film 103 is deposited.On the other hand, the conductive film Derivative of 103 deposition procedures without any oxygen or oxygen is produced, because the derivative of oxygen or oxygen easily reacts with TOPAZ and damages ODL Structural intergrity.The thickness of conductive film 103 can be more than the thickness for the conductive gasket 104 being exposed through.

As shown in fig. 11,110A is the top view of the memory construction in manufacture, and 110B is the dotted line along 110A AA cross section, and 110C is along 110A dotted line BB cross section.This step forms photoresist figure on conductive film 113 Case 115 simultaneously defines conductor wire 123 after anisotropic etching as shown in figure 12.As shown in Figure 12,120A is manufacture In memory construction top view, 120B be along 120A dotted line AA cross section, and 120C be along 120A dotted line BB cross section.Anisotropic etching（For example, RIE) to remove conductive film 113 it is not photo-etched glue using the 3rd etchant The part that pattern 115 is protected, and this can be exposed as shown in 120C, after RIE be not photo-etched the part that glue pattern 125 is protected Underlying conductive pad 124 '.Conductor wire 123 ' is able to define in this step and is orthogonally formed on laminated tape, so as to contact The conductive gasket 124 ' being exposed through.

As shown in figure 13, follow-up anisotropic etching further removes in Figure 12 conductive gasket 124 ' and the exposure of exposure TOPAZ126.As shown in figure 13,130A is the top view of the memory construction in manufacture, and 130B is along 130A dotted line AA's Cross section, and 130C is along 130A dotted line BB cross section.Anisotropic etching (such as RIE) using the 4th etchant with The TOPAZ136 being exposed through and the conductive gasket 134 being exposed through are removed, and is stopped at accumulation layer 137.Because two neighbouring Deep trench configuration between laminated tape, should have between conductor wire 133 and ODL136/ conductive gaskets 134 relative to the 4th etchant High etching selectivity（For example, 5: 1), because the structure majority of deep trench configuration needs over etching.If this of the 4th etchant Etching selectivity is more than 10: 1, then the issuable lateral degradation of conductor wire 133 during can lowering over etching.Implement one It is different for the 3rd etchant in this manufacture method and the 4th etchant in example.

In fig. 14,140A is the top view of the memory construction in manufacture, and 140B is the horizontal stroke along 140A dotted line AA Section, and 140C is along 140A dotted line BB cross section.As shown in figure 13, photoresist is removed by stripping/ash process 135 and TOPAZ136.It can be used to peel off the TOPAZ below conductor wire 143 etc. tropism oxygen plasma etch.It is subsequently formed positioning The first space between two neighbouring laminated tapes (142A, 142B) and below the shielded area of conductor wire 143.By conductor wire The conductive gasket 144 of 143 maskings can be retained in this stripping/ash process.Residue cleaning procedure is optionally implemented To ensure that removal completely can ashing material layer.

In fig .15,150A is the top view of the memory construction in manufacture, and 150B is the horizontal stroke along 150A dotted line AA Section, 150C be along 150A dotted line BB cross section, and 150D be along 150A dotted line CC cross section.Dotted line AA is cut In on conductor wire 153；Dotted line BB is parallel with dotted line AA, but is not cut on conductor wire 153；Dotted line CC is vertical with dotted line AA and BB, But it is not cut on laminated tape 152.Insulating barrier 158（For example, interlayer dielectric) conductor wire 153 is then deposited on non-conformal manner On.150C displayings complete two Second gaps 156 between conductor wires 153 after non-conformal oxide deposition procedure. Deposition procedure can be PVD, CVD or its combination.However, as shown in 150C, micro insulating materials has an opportunity to be deposited on laminated tape On the side wall 159 of 152 part, the part can be the section not covered by conductor wire 153.

As shown in 150D, the first space between two neighbouring laminated tapes 152 and below the shielded area of conductor wire 153 151 are defined when conductor wire is formed, and the Second gap 156 between two neighbouring conductor wires 153 is then in Ben Feibao Shape oxide deposition step is defined when completing.

The technology contents and technical characterstic of the present invention have revealed that as above, but have in the technical field of the invention usual Skill is it will be appreciated that in the spirit and scope of the invention defined without departing substantially from claim, teachings of the present invention and announcement can Make a variety of replacements and modification.For example, many manufacture crafts being disclosed above can in a variety of ways be implemented or be made with other Technique is replaced, or using the combination of above-mentioned two kinds of modes.

In addition, the interest field of this case is not limited to manufacture craft, board, the system for the specific embodiment being disclosed above Make, the composition of material, device, method or step.Persond having ordinary knowledge in the technical field of the present invention is it will be appreciated that based on this Invention teaching and disclose manufacture craft, board, manufacture, the composition of material, device, method or step, no matter it is now existing or Developer in the future, it, to perform substantially identical function in substantially the same manner, and reaches reality with this case embodiment announcement person Matter identical result, also can be used in the present invention.Therefore, following claim is used to such manufacture craft, machine to cover Platform, manufacture, the composition of material, device, method or step.

Claims (5)

1. a kind of method for manufacturing semiconductor structure, it is included：

The multiple laminated tapes configured in parallel with each other are formed on a substrate；

A conductive gasket of the pattern for meeting the multiple laminated tape is formed by one conformal deposit of implementation；And

Formed by carrying out one first non-conformal deposition and configure and be orthogonally positioned at the multiple laminated tape in parallel with each other On multiple conductor wires；

Wherein, there is space between conductive gasket and conductor wire, the sky between two neighbouring laminated tapes is filled in one first space Between and below the conductor wire, the conductor wire is positioned on this two neighbouring laminated tapes；One Second gap neighbouring is led at two Between electric wire；The distance between two neighbouring laminated tapes are in below 200nm, and the depth-width ratio of laminated tape is at least 1.

2. according to the method described in claim 1, it is further included by one second non-conformal deposition on the conductor wire Form a step of an insulating barrier.

3. according to the method described in claim 1, it is further contained between the multiple laminated tape and the conductive gasket Form a step of an accumulation layer.

4. a kind of method for manufacturing semiconductor structure, it is included：

The multiple laminated tapes configured in parallel with each other are formed on a substrate；

A conductive gasket of the pattern for meeting the multiple laminated tape is formed by one conformal deposit of implementation；

Can the multiple laminated tape of ashing material planarizing layers by one；

By described in etch-back can ashing material layer and the exposure conductive gasket a part；And

Form the multiple conductor wires for configuring and being orthogonally positioned on the laminated tape in parallel with each other, and the conductive linear contact lay The conductive gasket of the exposure；

Wherein, there is space between conductive gasket and conductor wire, the sky between two neighbouring laminated tapes is filled in one first space Between and below the conductor wire, the conductor wire is positioned on this two neighbouring laminated tapes；One Second gap neighbouring is led at two Between electric wire；The distance between two neighbouring laminated tapes are in below 200nm, and the depth-width ratio of laminated tape is at least 1.

5. method according to claim 4, it is further contained between the multiple laminated tape and the conductive gasket Form a step of an accumulation layer.