201145578 六、發明說明： 【發明所屬之技術領域】 [0001]本發明涉及一發光二極體，尤其涉及一具有三維奈米結 構陣列之發光二極體。 【先前技術】 [0002]由氮化鎵半導體材料製成之高效藍光、綠光及白光發光 二極體具有#命長、節能、綠色環保等顯著特點，已被 廣泛應用於大螢幕彩色顯示、汽車照明、交通信號、複 數媒體顯示及光通訊等領域，特別暴在照明領域具有廣 D 闊之發展潛力。 [〇〇〇3]傳統發光二極體通常包括N型半導體層、P型半導體層、 設置於N型半導體層與P型半導體層之間之活性層、設置 於P型半導體層上之P型電極（通常為透明電極）及設置於N 型半導體層上之N型電極。發光二極體處於工作狀態時， 在P型半導體層與N型半導體層上分別施加正 '負電壓， 這樣，存在於P型半導體層中之空穴與存在半導體 〇 層中之電子在活姓層中發生複+而產生光子’且光子從 發光二極體中射出。 1 [0004]然而，先則技術之發光二極體的光取出效率（光取出效率 通常指活性層中所產生之光從發光二極體内部釋放出之 效率）較低，其主要原因是由於半導體（通常為氮化鎵） 之折射率大於空氣之折射率，來自活性層之大角度光在 半導體與空氣之介面處發生全反射，從而大部份大角度 光被限制在發光二極體之内部，直至以熱等方式耗散。 這對發光二極體而言非常不利。 0992034318-0 099119362 表單編號A0101 第3頁/共25頁 201145578 [0005] 為了解決上述問題，先前技術中通過控制氤化鎵生長方 式提高發光二極體之出光率。然該方法工藝複雜，成本 較高。先前技術中也有採用表面粗縫化或表面圖形化發 光二極體之出光面等方法改變光線之入射角度從而提高 發光二極體之出光率的報導。然這種方法只能在較小程 度上改變光線之入射角，對於入射角較大之大角度光仍 無法有效地提取，影響了發光二極體之出光率。 【發明内容】 [0006] [0008] 099119362 光取出效率較高之發光二極體實為必 有鑒於此，提供一 要。 [0007] — 發光一極體丨包括：—基底；-第-半導體層、-活性層及-第二铸體層依:欠層#設置於所述基底之一 •’且所述第铸體層靠近基底設置；-第-電極與 所述第一半導體層Φ 電連接；一第二電極與所述第二半導 體層電連接；其中，& 、 進一步包括複數三維奈米結構以陣 列形式設置於第-生播 一 、—丰導體層之遠離基底的表面，且所述 二維奈米結構為_狀_。 發光二極體，其包括：—基底；—第―半導體層、一 曰及帛—半導體層依次層疊設置於所述基底之一 •、所述第+導體層靠近基底設置；-第-電極與 所述第-半導體層電連接；H㈣所述第二半導 I電連接’其中’進—步包括複數三維奈米結構以陣 導體層與基底接觸之表面且所述 二維奈米結構為階梯狀結構。 發光—極體，其句虹. 表單編號麵基底；一第—半導體層、一 第4頁/共25頁 09 [0009] 201145578 [0010]BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light-emitting diode, and more particularly to a light-emitting diode having a three-dimensional array of nanostructures. [Prior Art] [0002] High-efficiency blue, green, and white light-emitting diodes made of gallium nitride semiconductor materials have remarkable features such as length, energy saving, and environmental protection, and have been widely used in large-screen color display. In the fields of automotive lighting, traffic signals, complex media display and optical communications, there is a wide potential for development in the field of lighting. [〇〇〇3] A conventional light-emitting diode generally includes an N-type semiconductor layer, a P-type semiconductor layer, an active layer disposed between the N-type semiconductor layer and the P-type semiconductor layer, and a P-type disposed on the P-type semiconductor layer. An electrode (usually a transparent electrode) and an N-type electrode disposed on the N-type semiconductor layer. When the light-emitting diode is in operation, a positive 'negative voltage is applied to the P-type semiconductor layer and the N-type semiconductor layer, respectively, so that the holes existing in the P-type semiconductor layer and the electrons present in the semiconductor germanium layer are in the live surname A complex + occurs in the layer to generate a photon 'and a photon is emitted from the light emitting diode. [0004] However, the light extraction efficiency of the light-emitting diode of the prior art (the light extraction efficiency generally means that the efficiency of light generated in the active layer is released from the inside of the light-emitting diode) is low, mainly due to The refractive index of the semiconductor (usually gallium nitride) is greater than the refractive index of air, and the large angle light from the active layer is totally reflected at the interface between the semiconductor and the air, so that most of the large angle light is confined to the light emitting diode. Internal, until dissipated by heat, etc. This is very disadvantageous for the light-emitting diode. 0992034318-0 099119362 Form No. A0101 Page 3 of 25 201145578 [0005] In order to solve the above problem, the prior art improves the light-emitting rate of the light-emitting diode by controlling the growth of gallium antimonide. However, this method is complicated in process and high in cost. In the prior art, there is also a method of changing the incident angle of light by using a rough surface of a surface or a light-emitting surface of a surface patterned light-emitting diode to improve the light-emitting rate of the light-emitting diode. However, this method can only change the incident angle of the light to a small extent, and the large-angle light with a large incident angle cannot be effectively extracted, which affects the light-emitting rate of the light-emitting diode. SUMMARY OF THE INVENTION [0006] [0008] 099119362 Light-emitting diodes with higher light extraction efficiency are indispensable for this reason. [0007] - the light-emitting body includes: - a substrate; - a first semiconductor layer, - an active layer, and - a second cast layer: a lower layer # is disposed on one of the substrates - and the first casting layer is adjacent a substrate disposed; the first electrode is electrically connected to the first semiconductor layer Φ; a second electrode is electrically connected to the second semiconductor layer; wherein, &, further comprising a plurality of three-dimensional nanostructures arranged in an array - a broadcast of the surface of the conductor layer away from the substrate, and the two-dimensional nanostructure is _-like. a light-emitting diode comprising: a substrate; a first semiconductor layer, a germanium and a germanium-semiconductor layer are sequentially stacked on one of the substrates; and the ++ conductor layer is disposed adjacent to the substrate; - the first electrode and The first semiconductor layer is electrically connected; H (four) the second semiconductor I electrically connected 'in which the step comprises a plurality of three-dimensional nanostructures with a surface of the array of conductor layers in contact with the substrate and the two-dimensional nanostructure is a step Structure. Luminous-polar body, its sentence rainbow. Form number surface base; a first-semiconductor layer, a 4th page/total 25 pages 09 [0009] 201145578 [0010]
D ❹ [0011] [0012] [0013] 活性層及一第二半導體層依次層疊設置於所述基底之一 側，且所述第一半導體層靠近基底設置；一第一電極與 所述第一半導體層電連接；一第二電極與所述第二半導 體層電連接；其中，進一步包括複數三維奈米結構以陣 列形式設置於基底與第一半導體層接觸之表面，且所述 三維奈米結構為階梯狀結構。 與先前技術相比較，本發明之發光二極體中，複數三維 奈米結構以陣列形式設置形成三維奈米結構陣列。由於 本發明之三維奈米結構為階梯狀結構，相當於包括至少 二層三維奈米結構或二層光子晶體結構，故可以更加有 效提高發光二極體之大角度光的取出效率。或者，當大 角度光向基底傳播過程中遇到三維奈米結構陣列，會經 三維奈米結構陣列反射而變成小角度光。一方面，大角 度光變成小角度光可以提高發光二極體之出光效率，另 一方面，大角度光變成小角度光可以減小光線在發光二 極體内部之傳播路徑，從而減小光線在傳播過程中之損 耗。 【實施方式】 為了對本發明作更進一步之說明，舉以下具體實施例並 配合附圖詳細描述如下。 請參閱圖1，本發明第一實施例提供一發光二極體10，其 包括：一基底12、一第一半導體層14、一活性層16、一 第二半導體層18、一第一電極13、一第二電極11及一三 維奈米結構陣列17。 所述第一半導體層14、活性層16及第二半導體層18依次 099119362 表單編號A0101 第5頁/共25頁 0992034318-0 201145578 層疊設置於基底12之-侧。所述第—電_與所述第一 半導體層14電連接。所”二電極η與所述第二半導體 層18電連接。所述二維奈米結構陣列口可以設置於第二 半導體層18之遠離基底12之表面，或/及第-半導體層14 與基㈣接觸之表面’或/及基底12與第—半導體層難 觸之表面。本實施例中，所述三維奈米結構陣列17設置 於所述第二半導體層18之遠離基底12之表面。 [0014] [0015] [0016] 099119362 所述基底12具有支推之作用。所述基底12之厚度為綱至 _微米’其㈣為藍寶石、坤化鎵、献銦、偏誠裡 、嫁酸經、氮她1、碳_聽獅等材料中之- 或其混合物。本實施例中，所述基底12之厚度為4〇0微米 ，其材料為藍寶石。 可選擇地’一緩衝層（圖未示）可以設置於基底12及第 一半導體層14之間，並與基底12及第一半導體層14分別 接觸，此時第一半導體層14靠埤綦底12之表面與緩衝層 接觸。所述緩衝層有利於提高材料之外延生長品質，減 少晶格失配。所述緩衝層之厚度為1〇奈米至3〇〇奈米，其 材料可以為氮化鎵或氮化鋁等。 所述第一半導體層14為一台階結構。所述第一半導體層 14包括一第一表面、—第二表面及一第三表面◊該三個 表面相互平行。第二表面及第三表面均與第一表面相對 设置。該第一半導體層14之第二表面與第三表面具有不 同之高度，從而使第一半導體層14具有一台階。第二表 面是該台階之高度較低的表面，第三表面是該台階之高 度較高的表面。相比於第三表面，第二表面與第一表面 表單編號Α0Η11 第6頁/共25頁 0992034318-0 201145578 Ο [0017] 之距離較小。將第一半導體層14設置於基底12之ζ侧時 ，第—半導體層14之第一表面靠近基底12設置。活性層 16及第二半導體層18依次設置於第一半導體層14之第一* 表面。優選地，活性層16及第一半導體層14之第彡表面 之接觸面積與第一半導體層14之第三表面之面積相專 第二半導體層18完全覆蓋活性層16之遠離基底12的表面 。可選擇地，所述第一半導體層14之第三表面與第二表 面可位於一平面即第二表面及第三表面高度相同，此時 ’所述活性層16與第二半導體層18依次層疊設置於所述 第一半導體層14之部份表面，從而形成台階結構。所述 第一電極13設置於第一半導體層14之第二表面。 ❹ 所述第—半導體層14、第二半導趑層18分別為Ν型半導體 層及Ρ型半導體層二類型中之一。具體地，當該第一半導 體層14為Ν型半導體層時，第二半導體層18為ρ型半導體 層；當該第一半導體層14為Ρ型韦導體層時，第二半導體 層18為Ν型半導體層。所述ν型半導體層起到提供電子之 作用，所述ρ型半導趙層起到提供空穴之作用。Ν型半導 體層之材料為Ν型氮化鎵、ν型砷化鎵及N型磷化銅等材料 中之或其混合物。Ρ型半導體層之材料為ρ型氮化鎵、ρ 型砷化鎵及Ρ型磷化銅等材料中之一或其混合物。所述第 一半導體層14之厚度為1微米至5微米。所述第二半導體 層18之厚度為〇· 1微米至3微米。本實施例中，所述第一 半導體層14為Ν型半導體層，該第一半導體層14之第一表 面及第三表面的距離為0.3微米，第一表面及第二表面之 距離為0· 1微米。第一半導體層14之材料為N型氮化鎵。 099119362 表單編號Α0101 第7頁/共25頁 0992034318-0 201145578 所述第二半導體層18gp型半導體層’該第二半導體層18 之厚度為0.3微米，材料為P型氤化鎵。 [0018] [0019] 活性層16設置於第一半導體層14之第三表面。所述活性 層16為包含一層或複數層量子牌層之量子畔結構 (Quantum Well)。所述活性層16用於提供光子。所述 活性層16之材料為氮化鎵、氮化麵鎵、氮化銦鎵銘、砷 化稼、砷化鋁稼、磷化銦鎵、磷化銦砷或砷化銦鎵中之 或其犯合物，其厚度為〇. 〇1微米至〇. 6微米。本實施例 中’所述活性層16為二層結構，包括—氮化銦鎵層及一 鼠化鎵層，其厚度為〇..· 〇3微米_。所述第一半導體層14之 第二表面與第二半導體層18遠離基底12之表面的距離是 〇 · 8微米。 所述第一電極13、第二電極η可以為n型電極或p型電極 二類型中之一。所述第二電極丨丨之類型與第二半導體層 18之類型相同。第一電極13與第一半導體層14之類型相 同。所述第二電極11、第一電極13至少為一層結構其 厚度為0.01微米至2微米。所述第一電極13、第二電極 11之材料包括鈦、鋁、鎳及金中之一或其任意組合。優 選地，所述第二電極11為N型電極，該第二電極n為二層 結構，包括一厚度為150埃之鈦層及一厚度為2〇〇〇埃之金 層。所述第一電極13為P型電極，該帛一電極13為二層結 構，包括一厚度為150埃之鎳層及一厚度為1〇〇〇埃之金層 。本實施例中，第一電極丨3設置於所述第一半導體層14 之第二表面，第二電極11設置於所述第二半導體層18之 遠離基底12的部份表面。 099119362 表單編號A0101 第8頁/共25頁 0992034318-0 201145578 [0020] ❹ 所述三維奈米結構陣列17包括複數三維奈米結構15。所 述三維奈米結構15之材料或定義該三維奈米結構15之材 料可以與第二半導體層18之材料相同以形成一體結構， 或與第二半導體層18之材料不同。所述複數三維奈米結 構15在第二半導體層18表面以陣列形式設置。所述陣列 形式設置指所述複數三維奈米結構1 5可以按照等間距行 列式排布、同心圓環排布或六角形密堆排布等方式排列 。而且，所述以陣列形式設置之複數三維奈米結構15可 形成一單一圖案或複數圖案。所述單一圖案可以為三角 形、平行四邊形、體形、菱形、方形、矩形或圓形等。 所述複數圖案可以包括複數相同或不同上述單一圖案所 形成之圖案化的陣列。所述相鄰之二個三維奈米結構15 之間的距離相等，即相鄰之二第一圓台152之間的距離相 等，為10奈米~ 1 000奈米，優選為10奈米〜30奈米。本實 施例中，所述複數三維奈米結構15呈六角形密堆排布形 成一單一正方形圖案，且相鄰二個三維奈杀結構15之間 之距離約為30奈米。 Ο [0021] 所述三維奈米結構15為一階梯狀結構。所述三維奈米結 構15可以為一階梯狀凸起結構或階梯狀凹陷結構。所述 階梯狀凸起結構為從所述第二半導體層18表面向外延伸 出之階梯狀突起之實體。所述階梯狀凹陷結構為從第二 半導體層18表面向第二半導體層18内凹陷形成之階梯狀 凹陷之空間。所述階梯狀凸起結構或階梯狀凹陷結構可 以為一複數層台狀結構，如複數層三棱台、複數層四棱 台、複數層六棱台或複數層圓台等。優選地，所述階梯 099119362 表單編號Α0101 第9頁/共25頁 0992034318-0 201145578 [0022] [0023] 狀凸起結構或階梯狀凹陷結構為複數層圓台結構。所謂 階梯狀凹陷結構為複數層圓台結構是指所述階梯狀凹陷 之空間為複數層圓台形狀。所述階梯狀凸起結構或階梯 狀凹陷結構之最大尺度為小於等於1〇〇〇奈米，即其長度 、寬度及高度均小於等於1 000奈米。優選地，所述階梯 狀凸起結構或階梯狀凹陷結構長度、寬度及高度範圍為 10奈米~500奈米。 請參閱圖2及圖3，本實施例中，所述三維奈米結構叫 一階梯狀凸起之雙層圓台結構。具體地，所述三維奈米 結構15包括一第一圓台152及一設置於該第—圓台a〗表 面之第二圓台154。所述第一圓台152靠近第二半導體層 又置所述第一圓台152之侧面垂直於第二半導體層μ 表面所述第一圓台1 54之側面垂直於第一圓台1 μ之 低面。所述第-圓台152與第二圓台154形成一階梯狀凸 起結構，所述第二圓台154設置在所述第一圓台152之範 圍内。優選地，所述第-圓台152與第二圓台154同轴設 置。所述第—圓台152與第二圓台154為一體結構，即所 述第二圓台154為第一圓台152之頂面延伸出之圓台狀结 構。 。 所述第—圓台152之底面直徑大於第二圓台154之底面直 ^。所述第—圓台152之底面直徑為30奈米]000奈米， 门度為50奈米〜1000奈求。優選地，所述第-圓台152之 底面直植為50奈米』00奈米，高度為100奈米〜500奈米 。所述第二圓台154之底面直徑為10奈米〜500奈来，高 度為20奈米〜5QQ奈米。優選地，所述第二圓台154之底 099119362 表單編號A0101 第1〇頁/共25頁 0992034318-0 201145578 面直徑為20奈米〜200奈米，高度為100奈米〜300奈米。 本實施例中，所述第一圓台152與第二圓台154同軸設置 。所述第一圓台152之底面直徑為380奈米，高度為105 奈米。所述第二圓台154之底面直徑為280奈米，高度為 55奈米。 [0024] 可以理解，所述三維奈米結構1 5還可以包括一設置於該 第二圓台154表面之第三圓台（圖未示）。優選地，所述 第三圓台與第一圓台152，第二圓台154同軸設置。 〇 障5] 當由第二半導體層18發出之大角度光在出射過程中遇到 三維奈米結構陣列17，會經三維奈米結構陣列17繞射而 改變光子之出射方向，從而實現了發光二極體10之大角 度光的取出，提高了發光二極體10之光取出效率。由於 本發明之三維奈米結構陣列17之三維奈米結構15為階梯 狀結構，相當於包括至少二層三維奈米結構或二層光子 晶體結構，可以更加有效之提高發光二極體10之光取出 效率。請參閱圖4，本發明提供之發光二極體10之光取出 G 效率為先前技術中沒有設置三維奈米結構陣列之發光二 極體的光取出效率的5倍。 [0026] 請參閱圖5，本發明第二實施例提供一發光二極體20，其 包括：一基底22、一第一半導體層24、一活性層26、一 第二半導體層28、一第一電極23、一第二電極21及一三 維奈米結構陣列27。本發明第二實施例中之發光二極體 20的結構同第一實施例中之發光二極體10的結構相似， 其區別在於，所述三維奈米結構陣列27設置於第一半導 體層24與基底22接觸之表面。 099119362 表單編號A0101 第11頁/共25頁 0992034318-0 201145578 [0027] 請參閱圖6，本發明第三實施例提供一發光二極體30，其 包括：一基底32、一第一半導體層34、一活性層36、一 第二半導體層38、一第一電極33、一第二電極31及一三 維奈米結構陣列37。本發明第三實施例中之發光二極體 30之結構同第一實施例中之發光二極體10的結構相似， 其區別在於，所述三維奈米結構陣列37設置於基底32與 第一半導體層34接觸之表面。 [0028] 可以理解，由於本發明第二實施例與第三實施例中分別 將三維奈米結構陣列37，47設置於第一半導體層24與基 底22接觸之表面或基底32與第一半導體層34接觸之表面 ，所以當大角度光向基底22，32傳播過程中遇到三維奈 米結構陣列37，47,會經三維奈米結構陣列37，47反射 而變成小角度光。一方面，大角度光變成小角度光可以 提高發光二極體20，30之出光效率，另一方面，大角度 光變成小角度光可以減小光線在發光二極體20，30内部 之傳播路徑，從而減小光線在傳播過程中之損耗。當緩 衝層設置於第一半導體層24，34與基底22，32之間時， 本發明第二實施例與第三實施例中可以分別將三維奈米 結構陣列37，47設置於第一半導體層24與緩衝層接觸之 表面或基底32與缓衝層接觸之表面。 [0029] 請參閱圖7及圖8，本發明第四實施例提供一發光二極體 4〇，其包括：一基底42、一第一半導體層44 ' 一活性層 46、一第二半導體層48、一第一電極43、一第二電極41 及一三維奈米結構陣列47。本發明第四實施例中之發光 二極體40的結構同第一實施例中之發光二極體10的結構 099119362 表單編號A0101 第12頁/共25頁 0992034318-0 201145578 ❹ 相似，其區別在於，所述三維奈米結構陣列47包括複數 三維奈米結構45，且該三維奈米結構45為一階梯狀凹陷 結構，即由第二半導體層48定義之凹陷空間。所述三維 奈米結構45之形狀為一雙層圓台狀空間，具體包括一第 一圓台狀空間452，及一與第一圓台狀空間452連通之第 二圓台狀空間454。所述第一圓台狀空間452與第二圓台 狀空間454同軸設置。所述第一圓台狀空間452與第二圓 台狀空間454同軸設置。所述第二圓台狀空間454靠近第 二半導體層48表面設置。所述第二圓台狀空間454之直徑 大於第一圓台狀空間452的直徑。 [0030] 综上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施例 ，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 ❹ _1] 【圖式簡單說明】 圖1為本發明第一實施例提供之發光二極體的結構示意圖 0 [0032] 圖2為圖1之發光二極體沿II-II線的剖視圖。 [0033] 圖3為本發明第一實施例提供之發光二極體的三維奈米結 構陣列之掃描電鏡照片。 [0034] 圖4為本發明第一實施例提供之發光二極體的光取出效率 測試結果。 [0035] 圖5為本發明第二實施例提供之發光二極體的結構示意圖 099119362 表單編號A0101 第13頁/共25頁 0992034318-0 201145578 [0036] 圖6為本發明第三實施例提供之發光二極體的結構示意圖 〇 [0037] 圖7為本發明第四實施例提供之發光二極體的結構示意圖 〇 [0038] 圖8為圖7之發光二極體沿VI II-VII I線的剖視圖。 【主要元件符號說明】 [0039] 發光二極體：10，20, 30，40 [0040] 第二電極：11，21，31，41 [0041] 基底：12，22，32，42 [0042] 第一電極：13，23，33，43 [0043] 第一半導體層：14，24，34，44 [0044] 三維奈米結構：15，45 [0045] 第一圓台：152 [0046] 第二圓台：154 [0047] 活性層：1 6，2 6，3 6，4 6 [0048] 三維奈米結構陣列：17，27, 37, 47 [0049] 第二半導體層：18，28，38，48 [0050] 第一圓台狀空間：4 5 2 [0051] 第二圓台狀空間：454 099119362 表單編號A0101 第14頁/共25頁 0992034318-0[0012] [0013] The active layer and a second semiconductor layer are sequentially stacked on one side of the substrate, and the first semiconductor layer is disposed adjacent to the substrate; a first electrode and the first The semiconductor layer is electrically connected; a second electrode is electrically connected to the second semiconductor layer; and further comprising a plurality of three-dimensional nanostructures disposed in an array on a surface of the substrate in contact with the first semiconductor layer, and the three-dimensional nanostructure It is a stepped structure. In comparison with the prior art, in the light-emitting diode of the present invention, a plurality of three-dimensional nanostructures are arranged in an array to form a three-dimensional nanostructure array. Since the three-dimensional nanostructure of the present invention has a stepped structure, which corresponds to at least two layers of a three-dimensional nanostructure or a two-layer photonic crystal structure, the extraction efficiency of the large-angle light of the light-emitting diode can be more effectively improved. Alternatively, when a large-angle light encounters a three-dimensional nanostructure array during propagation to the substrate, it is reflected by the three-dimensional nanostructure array to become a small angle of light. On the one hand, the large angle light becomes a small angle light to improve the light extraction efficiency of the light emitting diode. On the other hand, the large angle light becomes a small angle light, which can reduce the propagation path of the light inside the light emitting diode, thereby reducing the light in the light. Loss during the propagation process. [Embodiment] In order to further clarify the present invention, the following specific embodiments are described in detail below with reference to the accompanying drawings. Referring to FIG. 1 , a first embodiment of the present invention provides a light emitting diode 10 including a substrate 12 , a first semiconductor layer 14 , an active layer 16 , a second semiconductor layer 18 , and a first electrode 13 . a second electrode 11 and a three-dimensional nanostructure array 17. The first semiconductor layer 14, the active layer 16, and the second semiconductor layer 18 are sequentially stacked in the form of 099119362 Form No. A0101, Page 5 of 25, 0992034318-0, 201145578. The first electric_ is electrically connected to the first semiconductor layer 14. The two electrodes η are electrically connected to the second semiconductor layer 18. The two-dimensional nanostructure array opening may be disposed on a surface of the second semiconductor layer 18 away from the substrate 12, or/and the first semiconductor layer 14 and the base (4) The surface of the contact 'or/ and the surface of the substrate 12 and the first semiconductor layer are difficult to touch. In the embodiment, the three-dimensional nanostructure array 17 is disposed on the surface of the second semiconductor layer 18 away from the substrate 12. [0016] [0016] 099119362 The substrate 12 has a pushing effect. The thickness of the substrate 12 is from the order of _micron' (4) is sapphire, kung gallium, indium, eccentric, marry acid In the present embodiment, the substrate 12 has a thickness of 4 〇 0 μm and the material thereof is sapphire. Optionally, a buffer layer (not shown) The first semiconductor layer 14 is in contact with the substrate 12 and the first semiconductor layer 14, and the first semiconductor layer 14 is in contact with the buffer layer by the surface of the substrate 12 at the time. The buffer layer is beneficial to improve the growth quality of the material and reduce the lattice mismatch. The buffer layer has a thickness of 1 nanometer to 3 nanometers, and the material thereof may be gallium nitride or aluminum nitride, etc. The first semiconductor layer 14 is a stepped structure. The first surface, the second surface, and the third surface are parallel to each other. The second surface and the third surface are disposed opposite to the first surface. The second surface of the first semiconductor layer 14 is The third surface has a different height such that the first semiconductor layer 14 has a step. The second surface is a lower height surface of the step, and the third surface is a higher height surface of the step. Surface, second surface and first surface form number Α0Η11 page 6/total 25 page 0992034318-0 201145578 Ο [0017] The distance is small. When the first semiconductor layer 14 is disposed on the ζ side of the substrate 12, the first semiconductor The first surface of the layer 14 is disposed adjacent to the substrate 12. The active layer 16 and the second semiconductor layer 18 are sequentially disposed on the first surface of the first semiconductor layer 14. Preferably, the active layer 16 and the second surface of the first semiconductor layer 14 Contact area and first semiconductor The area of the third surface of the second semiconductor layer 18 completely covers the surface of the active layer 16 away from the substrate 12. Alternatively, the third surface and the second surface of the first semiconductor layer 14 may be located on a plane The second surface and the third surface have the same height, and the active layer 16 and the second semiconductor layer 18 are sequentially stacked on a portion of the surface of the first semiconductor layer 14 to form a stepped structure. 13 is disposed on the second surface of the first semiconductor layer 14. The first semiconductor layer 14 and the second semi-conductive layer 18 are respectively one of two types of a germanium semiconductor layer and a germanium semiconductor layer. When the first semiconductor layer 14 is a Ν-type semiconductor layer, the second semiconductor layer 18 is a p-type semiconductor layer; when the first semiconductor layer 14 is a 韦-type Wei conductor layer, the second semiconductor layer 18 is a Ν-type semiconductor layer. The ν-type semiconductor layer functions to provide electrons, and the p-type semi-conductive layer functions to provide holes. The material of the bismuth-type semiconductor layer is a material of bismuth gallium nitride, ν-type gallium arsenide and N-type phosphide copper or a mixture thereof. The material of the germanium-type semiconductor layer is one of a material such as p-type gallium nitride, p-type gallium arsenide and germanium-type copper phosphide or a mixture thereof. The first semiconductor layer 14 has a thickness of from 1 micrometer to 5 micrometers. The second semiconductor layer 18 has a thickness of from 1 μm to 3 μm. In this embodiment, the first semiconductor layer 14 is a Ν-type semiconductor layer, and the distance between the first surface and the third surface of the first semiconductor layer 14 is 0.3 μm, and the distance between the first surface and the second surface is 0· 1 micron. The material of the first semiconductor layer 14 is N-type gallium nitride. 099119362 Form No. Α0101 Page 7 of 25 0992034318-0 201145578 The second semiconductor layer 18gp-type semiconductor layer The second semiconductor layer 18 has a thickness of 0.3 μm and the material is P-type gallium antimonide. [0019] The active layer 16 is disposed on the third surface of the first semiconductor layer 14. The active layer 16 is a Quantum Well comprising one or a plurality of quantum card layers. The active layer 16 is used to provide photons. The material of the active layer 16 is gallium nitride, gallium nitride, indium gallium nitride, arsenic trioxide, aluminum arsenide, indium gallium phosphide, indium phosphide or indium gallium arsenide or The compound has a thickness of 〇. 〇 1 μm to 〇. 6 μm. In the present embodiment, the active layer 16 has a two-layer structure including an indium gallium nitride layer and a gallium germanium layer having a thickness of 〇..·〇3 μm. The distance between the second surface of the first semiconductor layer 14 and the surface of the second semiconductor layer 18 away from the substrate 12 is 〇 8 μm. The first electrode 13 and the second electrode η may be one of two types of an n-type electrode or a p-type electrode. The second electrode is of the same type as the second semiconductor layer 18. The first electrode 13 is of the same type as the first semiconductor layer 14. The second electrode 11 and the first electrode 13 are at least one layer structure having a thickness of 0.01 μm to 2 μm. The material of the first electrode 13 and the second electrode 11 includes one of titanium, aluminum, nickel and gold or any combination thereof. Preferably, the second electrode 11 is an N-type electrode, and the second electrode n has a two-layer structure comprising a titanium layer having a thickness of 150 angstroms and a gold layer having a thickness of 2 angstroms. The first electrode 13 is a P-type electrode, and the first electrode 13 has a two-layer structure including a nickel layer having a thickness of 150 angstroms and a gold layer having a thickness of 1 angstrom. In this embodiment, the first electrode 丨3 is disposed on the second surface of the first semiconductor layer 14, and the second electrode 11 is disposed on a portion of the surface of the second semiconductor layer 18 away from the substrate 12. 099119362 Form No. A0101 Page 8 of 25 0992034318-0 201145578 [0020] The three-dimensional nanostructure array 17 comprises a plurality of three-dimensional nanostructures 15. The material of the three-dimensional nanostructure 15 or the material defining the three-dimensional nanostructure 15 may be the same as the material of the second semiconductor layer 18 to form a unitary structure or different from the material of the second semiconductor layer 18. The plurality of three-dimensional nanostructures 15 are disposed in an array on the surface of the second semiconductor layer 18. The array form arrangement means that the plurality of three-dimensional nanostructures 15 can be arranged in an equidistant arranging arrangement, a concentric annular arrangement or a hexagonal dense arrangement. Moreover, the plurality of three-dimensional nanostructures 15 arranged in an array form a single pattern or a plurality of patterns. The single pattern may be a triangle, a parallelogram, a body, a diamond, a square, a rectangle, or a circle. The plurality of patterns may include a patterned array of a plurality of identical or different single patterns. The distance between the two adjacent three-dimensional nanostructures 15 is equal, that is, the distance between the adjacent two first circular tables 152 is equal, ranging from 10 nm to 1 000 nm, preferably 10 nm~ 30 nm. In this embodiment, the plurality of three-dimensional nanostructures 15 are formed in a hexagonal densely packed arrangement into a single square pattern, and the distance between two adjacent three-dimensional nanostructures 15 is about 30 nm. [0021] The three-dimensional nanostructure 15 is a stepped structure. The three-dimensional nanostructure 15 may be a stepped convex structure or a stepped concave structure. The stepped protrusion structure is an entity of a stepped protrusion extending outward from the surface of the second semiconductor layer 18. The stepped recessed structure is a space in which a stepped recess formed in the second semiconductor layer 18 is recessed from the surface of the second semiconductor layer 18. The stepped protrusion structure or the stepped recess structure may be a plurality of layered structures, such as a plurality of layers of triangular prisms, a plurality of layers of quadrangular prisms, a plurality of layers of hexagonal prisms or a plurality of layers of circular tables. Preferably, the step 099119362 Form No. 101 0101 Page 9 / Total 25 Page 0992034318-0 201145578 [0023] The raised structure or the stepped recessed structure is a plurality of layered truncated cone structures. The fact that the stepped recessed structure is a plurality of layers of the truncated cone structure means that the space of the stepped recess is a plurality of truncated cone shapes. The maximum dimension of the stepped convex structure or the stepped concave structure is less than or equal to 1 nanometer, that is, its length, width and height are less than or equal to 1,000 nanometers. Preferably, the stepped protrusion structure or the stepped recess structure has a length, a width and a height ranging from 10 nm to 500 nm. Referring to FIG. 2 and FIG. 3, in the embodiment, the three-dimensional nanostructure is called a stepped protrusion double-layered truncated cone structure. Specifically, the three-dimensional nanostructure 15 includes a first circular table 152 and a second circular table 154 disposed on the surface of the first circular table. The first circular stage 152 is adjacent to the second semiconductor layer, and the side of the first circular stage 152 is perpendicular to the second semiconductor layer μ. The side of the first circular stage 154 is perpendicular to the first circular stage 1 μ. Low face. The first-circular table 152 and the second circular table 154 form a stepped convex structure, and the second circular table 154 is disposed within the range of the first circular table 152. Preferably, the first truncated cone 152 is disposed coaxially with the second truncated cone 154. The first truncated cone 152 and the second truncated cone 154 are of a unitary structure, that is, the second truncated cone 154 is a truncated cone structure extending from the top surface of the first truncated cone 152. . The diameter of the bottom surface of the first truncated cone 152 is larger than the bottom surface of the second truncated cone 154. The diameter of the bottom surface of the first truncated cone 152 is 30 nm]000 nm, and the degree of the door is 50 nm to 1000 N. Preferably, the bottom surface of the first-round table 152 is directly implanted at 50 nm 00 nm and the height is 100 nm to 500 nm. The bottom surface of the second circular table 154 has a diameter of 10 nm to 500 N, and a height of 20 nm to 5 QQ N. Preferably, the bottom of the second round table 154 is 099119362 Form No. A0101 Page 1 of 25 0992034318-0 201145578 The surface diameter is 20 nm to 200 nm, and the height is 100 nm to 300 nm. In this embodiment, the first circular table 152 is coaxially disposed with the second circular table 154. The bottom surface of the first truncated cone 152 has a diameter of 380 nm and a height of 105 nm. The bottom surface of the second truncated cone 154 has a diameter of 280 nm and a height of 55 nm. [0024] It can be understood that the three-dimensional nanostructure 15 may further include a third circular table (not shown) disposed on the surface of the second circular table 154. Preferably, the third circular table is disposed coaxially with the first circular table 152 and the second circular table 154. 〇 5] When the large-angle light emitted by the second semiconductor layer 18 encounters the three-dimensional nanostructure array 17 during the exit, the three-dimensional nanostructure array 17 is diffracted to change the exit direction of the photons, thereby realizing illumination. The removal of the large-angle light of the diode 10 improves the light extraction efficiency of the light-emitting diode 10. Since the three-dimensional nanostructure 15 of the three-dimensional nanostructure array 17 of the present invention has a stepped structure, which is equivalent to including at least two layers of a three-dimensional nanostructure or a two-layer photonic crystal structure, the light of the light-emitting diode 10 can be more effectively improved. Take out the efficiency. Referring to Fig. 4, the light extraction G efficiency of the light-emitting diode 10 provided by the present invention is five times that of the light-emitting diode of the prior art in which the three-dimensional nanostructure array is not provided. Referring to FIG. 5, a second embodiment of the present invention provides a light emitting diode 20 including a substrate 22, a first semiconductor layer 24, an active layer 26, a second semiconductor layer 28, and a first An electrode 23, a second electrode 21 and a three-dimensional nanostructure array 27. The structure of the light-emitting diode 20 in the second embodiment of the present invention is similar to that of the light-emitting diode 10 in the first embodiment, except that the three-dimensional nanostructure array 27 is disposed on the first semiconductor layer 24. The surface in contact with the substrate 22. 099119362 Form No. A0101 Page 11 of 25 0992034318-0 201145578 [0027] Referring to FIG. 6, a third embodiment of the present invention provides a light emitting diode 30 including a substrate 32 and a first semiconductor layer 34. An active layer 36, a second semiconductor layer 38, a first electrode 33, a second electrode 31, and a three-dimensional nanostructure array 37. The structure of the light-emitting diode 30 in the third embodiment of the present invention is similar to that of the light-emitting diode 10 in the first embodiment, except that the three-dimensional nanostructure array 37 is disposed on the substrate 32 and the first The surface of the semiconductor layer 34 contacts. [0028] It can be understood that, in the second embodiment and the third embodiment of the present invention, the three-dimensional nanostructure arrays 37, 47 are respectively disposed on the surface of the first semiconductor layer 24 in contact with the substrate 22 or the substrate 32 and the first semiconductor layer. 34 contacts the surface, so when the large angle light encounters the three-dimensional nanostructure arrays 37, 47 during propagation to the substrates 22, 32, it will be reflected by the three-dimensional nanostructure arrays 37, 47 to become small angle light. On the one hand, the large angle light becomes a small angle light to improve the light extraction efficiency of the light emitting diodes 20, 30. On the other hand, the large angle light becomes a small angle light to reduce the propagation path of the light inside the light emitting diodes 20, 30. , thereby reducing the loss of light during the propagation process. When the buffer layer is disposed between the first semiconductor layers 24, 34 and the substrates 22, 32, the three-dimensional nanostructure arrays 37, 47 can be respectively disposed on the first semiconductor layer in the second embodiment and the third embodiment of the present invention. 24 a surface in contact with the buffer layer or a surface in contact with the buffer layer. Referring to FIG. 7 and FIG. 8 , a fourth embodiment of the present invention provides a light emitting diode 4A including a substrate 42 , a first semiconductor layer 44 ′, an active layer 46 , and a second semiconductor layer. 48. A first electrode 43, a second electrode 41 and a three-dimensional nanostructure array 47. The structure of the light-emitting diode 40 in the fourth embodiment of the present invention is similar to the structure of the light-emitting diode 10 in the first embodiment, 099119362, Form No. A0101, Page 12/25, 0992034318-0, 201145578 ,, and the difference is that The three-dimensional nanostructure array 47 includes a plurality of three-dimensional nanostructures 45, and the three-dimensional nanostructures 45 are a stepped recessed structure, that is, a recessed space defined by the second semiconductor layer 48. The shape of the three-dimensional nanostructure 45 is a double-decked space, specifically including a first circular-shaped space 452, and a second circular-shaped space 454 communicating with the first circular-shaped space 452. The first frustum-shaped space 452 is disposed coaxially with the second truncated-shaped space 454. The first truncated cone shaped space 452 is disposed coaxially with the second truncated cone shaped space 454. The second frustum-shaped space 454 is disposed near the surface of the second semiconductor layer 48. The diameter of the second truncated space 454 is larger than the diameter of the first truncated space 452. [0030] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by those skilled in the art to the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of the light-emitting diode of FIG. 1 taken along line II-II. FIG. 3 is a scanning electron micrograph of a three-dimensional nanostructure array of a light-emitting diode according to a first embodiment of the present invention. 4 is a test result of light extraction efficiency of a light-emitting diode according to a first embodiment of the present invention. 5 is a schematic structural view of a light-emitting diode according to a second embodiment of the present invention. 099119362 Form No. A0101 Page 13/25 pages 0992034318-0 201145578 FIG. 6 is a third embodiment of the present invention. [0037] FIG. 7 is a schematic structural view of a light-emitting diode according to a fourth embodiment of the present invention. [0038] FIG. 8 is a light-emitting diode of FIG. 7 along line VI II-VII I. Cutaway view. [Description of Main Component Symbols] [0039] Light Emitting Diode: 10, 20, 30, 40 [0040] Second Electrode: 11, 21, 31, 41 [0041] Substrate: 12, 22, 32, 42 [0042] First electrode: 13, 23, 33, 43 [0043] First semiconductor layer: 14, 24, 34, 44 [0044] Three-dimensional nanostructure: 15, 45 [0045] First round table: 152 [0046] Two round table: 154 [0047] Active layer: 1, 6, 2 6, 3 6, 4 6 [0048] Three-dimensional nanostructure array: 17, 27, 37, 47 [0049] Second semiconductor layer: 18, 28, 38,48 [0050] First truncated space: 4 5 2 [0051] Second truncated space: 454 099119362 Form No. A0101 Page 14 of 25 0992034318-0