TWI447963B - Light-emitting diode - Google Patents
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Description
本發明涉及一種發光二極體，尤其涉及一種具有金屬光柵之發光二極體。 The invention relates to a light-emitting diode, in particular to a light-emitting diode having a metal grating.
由氮化鎵半導體材料製成之高效藍光、綠光及白光發光二極體具有壽命長、節能、綠色環保等顯著特點，已被廣泛應用於大螢幕彩色顯示、汽車照明、交通訊號、多媒體顯示及光通訊等領域，特別於照明領域具有廣闊之發展潛力。 High-efficiency blue, green and white light-emitting diodes made of GaN semiconductor materials have longevity, energy saving, green environmental protection and other remarkable features, and have been widely used in large screen color display, automotive lighting, traffic signal, multimedia display In the field of optical communication, etc., it has broad development potential especially in the field of lighting.
傳統之發光二極體通常包括N型半導體層、P型半導體層、設置在N型半導體層與P型半導體層之間之活性層、設置在P型半導體層上之P型電極(通常為透明電極)及設置在N型半導體層上之N型電極。發光二極體處於工作狀態時，於P型半導體層與N型半導體層上分別施加正、負電壓，這樣，存在於P型半導體層中之空穴與存在於N型半導體層中之電子在活性層中發生複合而產生光，光從發光二極體中射出。 Conventional light-emitting diodes generally include an N-type semiconductor layer, a P-type semiconductor layer, an active layer disposed between the N-type semiconductor layer and the P-type semiconductor layer, and a P-type electrode (usually transparent) disposed on the P-type semiconductor layer An electrode) and an N-type electrode disposed on the N-type semiconductor layer. When the light-emitting diode is in operation, positive and negative voltages are respectively applied to the P-type semiconductor layer and the N-type semiconductor layer, so that holes existing in the P-type semiconductor layer and electrons existing in the N-type semiconductor layer are Recombination occurs in the active layer to generate light, and light is emitted from the light-emitting diode.
然而，先前技術發光二極體之光取出效率(光取出效率通常指活性層中所產生之光從發光二極體內部釋放出之效率)較低，其主要原因係由於半導體之折射率大於空氣之折射率，來自活性層之大角度光在半導體與空氣之介面處發生全反射，從而大部分大角度光被限制在發光二極體之內部，直至被發光二極體內之材料完 全吸收。 However, the light extraction efficiency of the prior art light-emitting diode (the light extraction efficiency generally means that the light generated in the active layer is released from the inside of the light-emitting diode) is low, mainly because the refractive index of the semiconductor is larger than that of the air. The refractive index, the large angle light from the active layer is totally reflected at the interface between the semiconductor and the air, so that most of the large angle light is confined inside the light emitting diode until the material in the light emitting diode is finished. Full absorption.
為了解決上述問題，先前技術中採用表面粗糙化或表面圖形化發光二極體之出光面之方法改變光線之入射角度從而提高發光二極體之出光率。惟這種方法只能在較小程度上改變光線之入射角，對於入射角較大之大角度光仍無法有效地提取，影響了發光二極體之出光率。 In order to solve the above problem, in the prior art, the method of surface roughening or surface patterning of the light-emitting surface of the light-emitting diode is used to change the incident angle of the light to improve the light-emitting rate of the light-emitting diode. However, this method can only change the incident angle of the light to a small extent, and the large-angle light with a large incident angle cannot be effectively extracted, which affects the light-emitting rate of the light-emitting diode.
有鑒於此，提供一種光取出效率較高之發光二極體，以解決上述技術問題實為必要。 In view of the above, it is necessary to provide a light-emitting diode having a high light extraction efficiency to solve the above technical problems.
一種發光二極體，其包括：一基底；一第一半導體層、一活性層及一第二半導體層依次層疊設置於所述基底之一側；一第一電極與所述第一半導體層電連接；一導電層設置於第二半導體層遠離第二半導體層之表面；一第二電極與所述導電層電連接；其中，一金屬光柵設置於所述導電層之遠離基底之表面，該金屬光柵為複數金屬微結構排列成具有多行及多列之二維陣列。 A light emitting diode comprising: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer are sequentially stacked on one side of the substrate; a first electrode and the first semiconductor layer are electrically a conductive layer is disposed on the surface of the second semiconductor layer away from the second semiconductor layer; a second electrode is electrically connected to the conductive layer; wherein a metal grating is disposed on a surface of the conductive layer away from the substrate, the metal The grating is a plurality of metal microstructures arranged in a two-dimensional array having a plurality of rows and columns.
與先前技術相比，由第二半導體層發出之大角度光在出射過程中遇到金屬光柵激發了表面電漿電磁耦子之共振，從而改變了光子之出射方向，實現了發光二極體之大角度光之取出，提高了發光二極體之光取出效率。進一步地，所述金屬光柵為陣列狀，故，該金屬光柵提高了發光二極體之出光均勻性。 Compared with the prior art, the large-angle light emitted by the second semiconductor layer encounters the metal grating to excite the resonance of the surface plasma electromagnetic coupler during the exiting process, thereby changing the exit direction of the photon and realizing the light-emitting diode. The removal of the large-angle light improves the light extraction efficiency of the light-emitting diode. Further, the metal grating is in an array shape, so the metal grating improves the light uniformity of the light emitting diode.
10‧‧‧發光二極體 10‧‧‧Lighting diode
11‧‧‧基底 11‧‧‧Base
12‧‧‧緩衝層 12‧‧‧ Buffer layer
13‧‧‧第一半導體層 13‧‧‧First semiconductor layer
14‧‧‧活性層 14‧‧‧Active layer
15‧‧‧第二半導體層 15‧‧‧Second semiconductor layer
16‧‧‧第一電極 16‧‧‧First electrode
17‧‧‧導電層 17‧‧‧ Conductive layer
18‧‧‧第二電極 18‧‧‧second electrode
19‧‧‧金屬光柵 19‧‧‧Metal grating
圖1係本發明第一實施例之發光二極體之結構示意圖。 1 is a schematic structural view of a light-emitting diode according to a first embodiment of the present invention.
圖2係圖1所示發光二極體之俯視圖。 2 is a top plan view of the light emitting diode shown in FIG. 1.
以下將結合附圖詳細說明本發明實施例的發光二極體。 Hereinafter, a light-emitting diode of an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
請參閱圖1，本發明第一實施例提供一種發光二極體10。所述發光二極體10包括一基底11、一第一半導體層13、一活性層14、一第二半導體層15、一第一電極16、一導電層17、一第二電極18及一金屬光柵19。所述第一半導體層13、活性層14及第二半導體層15依次層疊設置於基底11之一側。所述第一電極16與所述第一半導體層13電連接。所述導電層17設置於所述第二半導體層15之遠離基底11之表面。所述金屬光柵19設置於所述導電層17之遠離基底11之表面。該金屬光柵19為複數金屬微結構排列而成之二維陣列。一第二電極18與所述導電層17電連接。 Referring to FIG. 1, a first embodiment of the present invention provides a light emitting diode 10. The light emitting diode 10 includes a substrate 11, a first semiconductor layer 13, an active layer 14, a second semiconductor layer 15, a first electrode 16, a conductive layer 17, a second electrode 18, and a metal. Grating 19. The first semiconductor layer 13, the active layer 14, and the second semiconductor layer 15 are sequentially stacked on one side of the substrate 11. The first electrode 16 is electrically connected to the first semiconductor layer 13. The conductive layer 17 is disposed on a surface of the second semiconductor layer 15 away from the substrate 11. The metal grating 19 is disposed on a surface of the conductive layer 17 remote from the substrate 11. The metal grating 19 is a two-dimensional array in which a plurality of metal microstructures are arranged. A second electrode 18 is electrically connected to the conductive layer 17.
所述基底11具有支撐之作用。所述基底11之厚度為300至500微米，其材料包括藍寶石、砷化鎵、磷化銦、偏鋁酸鋰、鎵酸鋰、氮化鋁、矽、碳化矽及氮化矽等材料中之一種或幾種。本實施例中，所述基底11之厚度為400微米，其材料為藍寶石。 The substrate 11 has a supporting role. The substrate 11 has a thickness of 300 to 500 micrometers, and the material thereof comprises materials such as sapphire, gallium arsenide, indium phosphide, lithium metaaluminate, lithium gallate, aluminum nitride, tantalum, tantalum carbide and tantalum nitride. One or several. In this embodiment, the substrate 11 has a thickness of 400 micrometers and the material thereof is sapphire.
可選擇地，一緩衝層12設置於基底11及第一半導體層13之間，並與基底11及第一半導體層13分別接觸，此時第一半導體層13靠近基底11之表面與緩衝層12接觸。可以理解，當沒有緩衝層12存在時，第一半導體層13直接設置於基底11之表面。所述緩衝層12有利於提高材料之磊晶生長品質，減少晶格失配。所述緩衝層12之厚度為10奈米至300奈米，其材料為氮化鎵或氮化鋁等。本實施例中，所述緩衝層12之厚度為20奈米至50奈米，材料為氮化鎵。所述第一半導體層13設置於基底11之一側。 Optionally, a buffer layer 12 is disposed between the substrate 11 and the first semiconductor layer 13 and is in contact with the substrate 11 and the first semiconductor layer 13, respectively, and the first semiconductor layer 13 is adjacent to the surface of the substrate 11 and the buffer layer 12 contact. It can be understood that the first semiconductor layer 13 is directly disposed on the surface of the substrate 11 when no buffer layer 12 is present. The buffer layer 12 is advantageous for improving the epitaxial growth quality of the material and reducing lattice mismatch. The buffer layer 12 has a thickness of 10 nm to 300 nm, and the material thereof is gallium nitride or aluminum nitride. In this embodiment, the buffer layer 12 has a thickness of 20 nm to 50 nm, and the material is gallium nitride. The first semiconductor layer 13 is disposed on one side of the substrate 11.
所述第一半導體層13具有台階結構。所述第一半導體層13包括一 第一表面、一第二表面及一第三表面。該三個表面相互平行。第二表面及第三表面均與第一表面相對設置。該第一半導體層13之第二表面與第三表面具有不同之高度，從而使第一半導體層13具有一台階。第二表面係該台階之高度較低之表面，第三表面係該台階之高度較高之表面。相比於第三表面，第二表面與第一表面之距離較小。將第一半導體層13設置於基底11之一側時，第一半導體層13之第一表面靠近基底11設置。所述活性層14及第二半導體層15依次設置於第一半導體層13之第三表面。優選地，活性層14及第一半導體層13之第三表面之接觸面積與第一半導體層13之第三表面之面積相等。第二半導體層15完全覆蓋活性層14之遠離基底11之表面。可選擇地，所述第一半導體層13之第三表面與第二表面可位於一個平面即第二表面及第三表面高度相同，此時，所述活性層14與第二半導體層15依次層疊設置於所述第一半導體層13之部分表面，從而形成台階結構。第一電極16設置於第一半導體層13之第二表面。 The first semiconductor layer 13 has a stepped structure. The first semiconductor layer 13 includes a first a first surface, a second surface, and a third surface. The three surfaces are parallel to each other. The second surface and the third surface are both disposed opposite to the first surface. The second surface of the first semiconductor layer 13 has a different height from the third surface, so that the first semiconductor layer 13 has a step. The second surface is the lower surface of the step, and the third surface is the surface of the step having a higher height. The distance between the second surface and the first surface is smaller than the third surface. When the first semiconductor layer 13 is disposed on one side of the substrate 11, the first surface of the first semiconductor layer 13 is disposed adjacent to the substrate 11. The active layer 14 and the second semiconductor layer 15 are sequentially disposed on the third surface of the first semiconductor layer 13 . Preferably, the contact area of the active layer 14 and the third surface of the first semiconductor layer 13 is equal to the area of the third surface of the first semiconductor layer 13. The second semiconductor layer 15 completely covers the surface of the active layer 14 away from the substrate 11. Optionally, the third surface and the second surface of the first semiconductor layer 13 may be located at one plane, that is, the second surface and the third surface have the same height. At this time, the active layer 14 and the second semiconductor layer 15 are sequentially stacked. A portion of the surface of the first semiconductor layer 13 is disposed to form a stepped structure. The first electrode 16 is disposed on the second surface of the first semiconductor layer 13.
所述第一半導體層13、第二半導體層15分別為N型半導體層及P型半導體層兩種類型中之一種。具體地，當該第一半導體層13為N型半導體層時，第二半導體層15為P型半導體層；當該第一半導體層13為P型半導體層時，第二半導體層15為N型半導體層。所述N型半導體層起到提供電子之作用，所述P型半導體層起到提供空穴之作用。N型半導體層之材料包括N型氮化鎵、N型砷化鎵及N型磷化銅等材料中之一種或幾種。P型半導體層之材料包括P型氮化鎵、P型砷化鎵及P型磷化銅等材料中之一種或幾種。所述第一半導體層13之厚度為1微米至5微米。所述第二半導體層15之厚度為0.1微米至3微米。本實施例中，所述第一半導體層13為N型半導 體層，該第一半導體層13之第一表面及第三表面之距離為0.3微米，第一表面及第二表面之距離為0.1微米。第一半導體層13之材料為N型氮化鎵。所述第二半導體層15為P型半導體層，該第二半導體層15之厚度為0.3微米，材料為P型氮化鎵。 The first semiconductor layer 13 and the second semiconductor layer 15 are respectively one of two types of an N-type semiconductor layer and a P-type semiconductor layer. Specifically, when the first semiconductor layer 13 is an N-type semiconductor layer, the second semiconductor layer 15 is a P-type semiconductor layer; when the first semiconductor layer 13 is a P-type semiconductor layer, the second semiconductor layer 15 is an N-type Semiconductor layer. The N-type semiconductor layer functions to provide electrons, and the P-type semiconductor layer functions to provide holes. The material of the N-type semiconductor layer includes one or more of materials such as N-type gallium nitride, N-type gallium arsenide, and N-type copper phosphide. The material of the P-type semiconductor layer includes one or more of materials such as P-type gallium nitride, P-type gallium arsenide, and P-type copper phosphide. The first semiconductor layer 13 has a thickness of 1 micrometer to 5 micrometers. The second semiconductor layer 15 has a thickness of 0.1 μm to 3 μm. In this embodiment, the first semiconductor layer 13 is an N-type semiconductor The body layer has a distance between the first surface and the third surface of the first semiconductor layer 13 of 0.3 μm, and the distance between the first surface and the second surface is 0.1 μm. The material of the first semiconductor layer 13 is N-type gallium nitride. The second semiconductor layer 15 is a P-type semiconductor layer, the second semiconductor layer 15 has a thickness of 0.3 μm, and the material is P-type gallium nitride.
活性層14設置於第一半導體層13之第三表面。所述活性層14為一量子井(Quantum Well)結構，包含一層或多層量子井層。所述活性層14用於提供光子。所述活性層14之材料為氮化鎵、氮化銦鎵、氮化銦鎵鋁、砷化稼、砷化鋁稼、磷化銦鎵、磷化銦砷或砷化銦鎵中之一種或幾種，其厚度為0.01微米至0.6微米。本實施例中，所述活性層14為二層結構，包括一氮化銦鎵層及一氮化鎵層，其厚度為0.3微米。所述第一半導體層13之第二表面與第二半導體層15之遠離基底11的表面之間的距離係0.8微米。 The active layer 14 is disposed on the third surface of the first semiconductor layer 13. The active layer 14 is a Quantum Well structure comprising one or more layers of quantum well layers. The active layer 14 is used to provide photons. The material of the active layer 14 is one of gallium nitride, indium gallium nitride, indium gallium aluminum nitride, arsenic trioxide, aluminum arsenide, indium gallium phosphide, indium phosphide, or indium gallium arsenide. Several, having a thickness of from 0.01 micron to 0.6 micron. In this embodiment, the active layer 14 has a two-layer structure including an indium gallium nitride layer and a gallium nitride layer having a thickness of 0.3 μm. The distance between the second surface of the first semiconductor layer 13 and the surface of the second semiconductor layer 15 remote from the substrate 11 is 0.8 micrometers.
所述導電層17至少包括一金層、一氧化銦錫層或一銀層。當所述導電層17僅為金層時，所述導電層17之厚度範圍為1奈米至10奈米。當所述導電層17包括一金層，可於所述金層及第二半導體層15之間設置一鎳層。所述鎳層之作用為增加金層及第二半導體層15之間之結合力，此時所述導電層17之厚度範圍為1奈米至10奈米。當所述導電層17為氧化銦錫時，所述導電層17之厚度範圍10奈米至200奈米。本實施例中，所述導電層17為二層結構，其包括一層厚度為5奈米之鎳層及一層厚度為5奈米之金層，並且鎳層直接鋪設於第二半導體層15之表面，金層鋪設於鎳層之表面。所述導電層17之作用為提供均勻之電流給第一半導體層16。 The conductive layer 17 includes at least a gold layer, an indium tin oxide layer or a silver layer. When the conductive layer 17 is only a gold layer, the conductive layer 17 has a thickness ranging from 1 nm to 10 nm. When the conductive layer 17 includes a gold layer, a nickel layer may be disposed between the gold layer and the second semiconductor layer 15. The function of the nickel layer is to increase the bonding force between the gold layer and the second semiconductor layer 15, and the thickness of the conductive layer 17 ranges from 1 nm to 10 nm. When the conductive layer 17 is indium tin oxide, the conductive layer 17 has a thickness ranging from 10 nm to 200 nm. In this embodiment, the conductive layer 17 is a two-layer structure including a nickel layer having a thickness of 5 nm and a gold layer having a thickness of 5 nm, and the nickel layer is directly laid on the surface of the second semiconductor layer 15. The gold layer is laid on the surface of the nickel layer. The conductive layer 17 functions to provide a uniform current to the first semiconductor layer 16.
請參閱圖2，所述金屬光柵19為複數金屬微結構排列形成之二維陣列。所述複數金屬微結構排列成多行及多列之二維陣列結構。 沿所述二維陣列之行及列方向，所述複數金屬微結構相互間隔設置，且沿所述二維陣列之行及列方向週期性排列。沿所述二維陣列之行方向上相鄰二微結構之間的間距相等。沿所述二維陣列之列方向上相鄰二微結構之間的間距相等。該金屬微結構之形狀為錐形、楔形或柱形。所述柱形可為圓柱或棱柱。本實施例中，所述金屬微結構為方柱。複數金屬方柱形成週期性之金屬方柱陣列。所述金屬方柱陣列中之金屬方柱之高度範圍為20奈米至1020奈米，金屬方柱之長及寬之範圍為60奈米至120奈米。優選地，相鄰二金屬方柱之高度範圍為20奈米至100奈米。相鄰二金屬方柱之中心線之間的距離為200奈米至1000奈米。所述相鄰二金屬方柱之含義為沿金屬方柱陣列之行或列方向上相鄰二金屬方柱。本實施例中，請參閱圖2，相鄰二金屬方柱為沿A方向或B方向相鄰之二金屬方柱。所述金屬光柵19之材料為金或銀，優選地，採用銀作為金屬光柵19之材料。銀作為金屬光柵19之材料可以更有效地提高發光二極體之出光率。本實施例中所述複數金屬方柱之材料為銀，金屬方柱中之每一金屬方柱之高度均為50奈米，長及寬均為85奈米。相鄰二金屬方柱之中心線之間的距離為680奈米。可在金屬方柱之暴露於外界之表面進一步地覆蓋一層厚度為2奈米至20奈米之二氧化矽膜。金屬方柱與導光層17相接觸之表面未覆蓋二氧化矽膜。本實施例中，該二氧化矽膜之厚度為3奈米至5奈米。該二氧化矽膜可以有效地防止銀氧化，且不影響發光二極體之出光率。所述金屬光柵19可通過一佔空比描述。所述金屬光柵19之佔空比為沿所述金屬微結構形成之二維陣列之行或列方向上分別計算之佔空比。所述佔空比之計算方法為沿二維陣列之行或列方向上，金屬微結構之邊長與相鄰之二金屬方柱之中心線之 間的距離之比。本實施例中，請參閱圖2，金屬光柵19沿行方向上即A方向上之佔空比為0.06：1至0.6：1，金屬光柵19沿列方向上即B方向上之佔空比為0.06：1至0.6：1，通過控制金屬光柵19之佔空比可以提高發光二極體10之出光率。 Referring to FIG. 2, the metal grating 19 is a two-dimensional array formed by a plurality of metal microstructures. The plurality of metal microstructures are arranged in a two-dimensional array structure of a plurality of rows and a plurality of columns. The plurality of metal microstructures are spaced apart from each other along the row and column directions of the two-dimensional array, and are periodically arranged along the row and column directions of the two-dimensional array. The spacing between adjacent two microstructures in the row direction of the two-dimensional array is equal. The spacing between adjacent two microstructures in the direction of the two-dimensional array is equal. The metal microstructure has a shape of a cone, a wedge or a cylinder. The cylindrical shape may be a cylinder or a prism. In this embodiment, the metal microstructure is a square column. A plurality of metal square columns form a periodic array of metal square columns. The height of the metal square column in the metal square column array ranges from 20 nm to 1020 nm, and the length and width of the metal square column ranges from 60 nm to 120 nm. Preferably, the height of the adjacent two metal square columns ranges from 20 nanometers to 100 nanometers. The distance between the centerlines of adjacent two metal square columns is from 200 nm to 1000 nm. The adjacent two metal square pillars mean adjacent two metal square pillars in the row or column direction of the metal square pillar array. In this embodiment, referring to FIG. 2, the adjacent two metal square columns are two metal square columns adjacent in the A direction or the B direction. The material of the metal grating 19 is gold or silver, and preferably silver is used as the material of the metal grating 19. Silver as the material of the metal grating 19 can more effectively improve the light-emitting rate of the light-emitting diode. In the embodiment, the material of the plurality of metal square columns is silver, and the height of each metal square column in the metal square column is 50 nm, and the length and width are both 85 nm. The distance between the centerlines of adjacent two metal square columns is 680 nm. The surface of the metal square pillar exposed to the outside may be further covered with a layer of cerium oxide having a thickness of 2 nm to 20 nm. The surface of the metal square pillar in contact with the light guiding layer 17 is not covered with the cerium oxide film. In this embodiment, the thickness of the cerium oxide film is from 3 nm to 5 nm. The ruthenium dioxide film can effectively prevent silver oxidation and does not affect the light-emitting rate of the light-emitting diode. The metal grating 19 can be described by a duty cycle. The duty cycle of the metal grating 19 is the duty cycle calculated in the row or column direction of the two-dimensional array formed by the metal microstructure. The duty ratio is calculated by the side length of the metal microstructure and the center line of the adjacent two metal square columns along the row or column direction of the two-dimensional array. The ratio of the distance between. In this embodiment, referring to FIG. 2, the duty ratio of the metal grating 19 in the row direction, that is, in the A direction is 0.06:1 to 0.6:1, and the duty ratio of the metal grating 19 in the column direction, that is, in the B direction is 0.06. From 1:1 to 0.6:1, the light extraction rate of the light-emitting diode 10 can be improved by controlling the duty ratio of the metal grating 19.
所述第一電極16、第二電極18可為N型電極或P型電極兩種類型中之一種。所述第二電極18之類型與第二半導體層15之類型相同。第一電極16與第一半導體層13之類型相同。所述第二電極18、第一電極16至少為一層結構，他們之厚度為0.01微米至2微米。所述第一電極16、第二電極18之材料包括鈦、鋁、鎳及金中之一種或其任意組合。優選地，所述第二電極18為N型電極，該第二電極18為兩層結構，包括一厚度為150埃之鈦層及一厚度為2000埃之金層。所述第一電極16為P型電極，該第一電極16為二層結構，包括一厚度為150埃之鎳層及一厚度為1000埃之金層。本實施例中，第一電極16設置於所述第一半導體層13之第二表面，第二電極18及金屬光柵19均設置於所述導電層17之遠離基底11之表面。週期性排列之金屬微結構及第二電極18覆蓋導電層17之遠離基底11之表面。 The first electrode 16 and the second electrode 18 may be one of two types of an N-type electrode or a P-type electrode. The second electrode 18 is of the same type as the second semiconductor layer 15. The first electrode 16 is of the same type as the first semiconductor layer 13. The second electrode 18 and the first electrode 16 are at least one layer structure, and their thickness is 0.01 micrometer to 2 micrometers. The material of the first electrode 16 and the second electrode 18 includes one of titanium, aluminum, nickel and gold or any combination thereof. Preferably, the second electrode 18 is an N-type electrode, and the second electrode 18 has a two-layer structure including a titanium layer having a thickness of 150 angstroms and a gold layer having a thickness of 2000 angstroms. The first electrode 16 is a P-type electrode, and the first electrode 16 has a two-layer structure including a nickel layer having a thickness of 150 angstroms and a gold layer having a thickness of 1000 angstroms. In this embodiment, the first electrode 16 is disposed on the second surface of the first semiconductor layer 13 , and the second electrode 18 and the metal grating 19 are disposed on the surface of the conductive layer 17 away from the substrate 11 . The periodically arranged metal microstructures and the second electrode 18 cover the surface of the conductive layer 17 remote from the substrate 11.
本發明第二實施例提供一種發光二極體。第二實施例中的發光二極體之結構同第一實施例中的發光二極體之結構相似，其區別在於，所述金屬光柵中金屬方柱之高度為45奈米，相鄰二金屬方柱之中心線之間的距離為270奈米，金屬方柱之長度及寬度均為85奈米，導電層為二結構，其包括一層厚度為5奈米之鎳層及一層厚度為5奈米之金層，並且鎳層直接鋪設於第二半導體層15的遠離基底11之表面，金層鋪設於鎳層的遠離基底11之表面。所述金 屬方柱之材料為銀。第二實施例中金屬光柵之沿行及列方向上之佔空比均為0.3148：1。 A second embodiment of the present invention provides a light emitting diode. The structure of the light-emitting diode in the second embodiment is similar to that of the light-emitting diode in the first embodiment, except that the height of the metal square column in the metal grating is 45 nm, and the adjacent two metal The distance between the center line of the square column is 270 nm, the length and width of the metal square column are 85 nm, and the conductive layer is a two-layer structure, which includes a nickel layer with a thickness of 5 nm and a thickness of 5 nm. The gold layer of rice, and the nickel layer is directly laid on the surface of the second semiconductor layer 15 away from the substrate 11, and the gold layer is laid on the surface of the nickel layer away from the substrate 11. The gold The material belonging to the square column is silver. In the second embodiment, the duty ratio of the metal grating in the row and column directions is 0.3148:1.
本發明第三實施例提供一種發光二極體。第三實施例中之發光二極體之結構同第一實施例中之發光二極體之結構相似，其區別在於，所述導電層為單層結構，所述導電層為一氧化銦錫層，該氧化銦錫層之厚度為200奈米，所述金屬光柵為方柱結構，相鄰方柱之中心線之間的距離為260奈米，金屬方柱之高度為55奈米，長及寬均為85奈米，所述金屬方柱之材料為銀。第三實施例中金屬光柵之沿著行及列之方向上之佔空比均為0.3269：1。 A third embodiment of the present invention provides a light emitting diode. The structure of the light-emitting diode in the third embodiment is similar to that of the light-emitting diode in the first embodiment, except that the conductive layer is a single-layer structure, and the conductive layer is an indium tin oxide layer. The thickness of the indium tin oxide layer is 200 nm, the metal grating is a square column structure, the distance between the center lines of adjacent square columns is 260 nm, and the height of the metal square column is 55 nm, and the length is The width is 85 nm, and the material of the metal square column is silver. In the third embodiment, the duty ratio of the metal grating in the direction of rows and columns is 0.3269:1.
本發明第四實施例提供一種發光二極體。第四實施例中之發光二極體之結構同第三實施例中之發光二極體之結構相似，其區別在於，所述金屬光柵為方柱結構，相鄰方柱之中心線之間的距離為680奈米，所述金屬方柱之材料為銀。所述導電層為單層結構，所述導電層為一氧化銦錫層，該氧化銦錫層之厚度為200奈米，金屬方柱之高度為50奈米，長及寬均為85奈米。第四實施例中金屬光柵之沿著行及列之方向上之佔空比均為0.125：1。 A fourth embodiment of the present invention provides a light emitting diode. The structure of the light-emitting diode in the fourth embodiment is similar to that of the light-emitting diode in the third embodiment, except that the metal grating is a square column structure between the center lines of adjacent square columns. The distance is 680 nm, and the material of the metal square column is silver. The conductive layer is a single layer structure, the conductive layer is an indium tin oxide layer, the thickness of the indium tin oxide layer is 200 nm, the height of the metal square column is 50 nm, and the length and width are 85 nm. . In the fourth embodiment, the duty ratio of the metal grating in the direction of the row and the column is 0.125:1.
由第二半導體層發出之大角度光在出射過程中遇到金屬光柵激發了表面電漿電磁耦子共振，從而改變了光子之出射方向，提高了大角度光之出光率。表面電漿子(surface plasmon)係沿金屬表面傳播之波，其本質係光子與導體中之自由電子相互作用而被表面俘獲之光波。表面電漿子可以通過亞波長結構來彙聚及導引光波，從而起到增強透射之作用。因此，於發光二極體之第二半導體層之表面設置週期性金屬微結構陣列可以提高發光二極體之大角度光之取出率。進一步地，陣列狀之金屬光柵可以提高出光 之均勻性。由於銀係產生表面電漿電磁耦子之最佳介質，故本發明採用銀作為金屬微結構之材料可以較好地提高發光二極體之出光率。 The large-angle light emitted by the second semiconductor layer encounters the metal grating during the exiting process to excite the surface plasma electromagnetic coupler resonance, thereby changing the exit direction of the photon and improving the light-emitting rate of the large-angle light. A surface plasmon is a wave propagating along a metal surface, which is essentially a light wave that is captured by a surface by photons interacting with free electrons in the conductor. Surface plasmons can converge and direct light waves through sub-wavelength structures to enhance transmission. Therefore, providing a periodic metal microstructure array on the surface of the second semiconductor layer of the light-emitting diode can improve the extraction rate of the large-angle light of the light-emitting diode. Further, the array of metal gratings can enhance the light output Uniformity. Since silver is the best medium for generating surface plasma electromagnetic couplers, the present invention can use silver as a material of metal microstructure to improve the light-emitting rate of the light-emitting diode.
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
10‧‧‧發光二極體 10‧‧‧Lighting diode
11‧‧‧基底 11‧‧‧Base
12‧‧‧緩衝層 12‧‧‧ Buffer layer
13‧‧‧第一半導體層 13‧‧‧First semiconductor layer
14‧‧‧活性層 14‧‧‧Active layer
15‧‧‧第二半導體層 15‧‧‧Second semiconductor layer
16‧‧‧第一電極 16‧‧‧First electrode
17‧‧‧導電層 17‧‧‧ Conductive layer
18‧‧‧第二電極 18‧‧‧second electrode
19‧‧‧金屬光柵 19‧‧‧Metal grating
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| US20050199895A1 (en) * | 2004-03-12 | 2005-09-15 | Samsung Electronics Co., Ltd. | Nitride-based light-emitting device and method of manufacturing the same |
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| US20050199895A1 (en) * | 2004-03-12 | 2005-09-15 | Samsung Electronics Co., Ltd. | Nitride-based light-emitting device and method of manufacturing the same |
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