201140545 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種準位移位器以及液晶顯示器 料驅動器。 【先前技術】 傳先上負料驅動器僅能單獨用於產生交流共電壓或直 流共電壓。當資料驅動器用於產生交流共電壓時會有兩種 〃有不同電壓的電源在資料驅動器之中。當資料驅動器用 於產生直流共電壓時，有兩個具有相同變壓的電源在資料 驅動器之中。通常，有兩種不同型態的準位移位器在資料 f動器用以產生交流共電壓以及兩個相同型態的準位移位 器在資料驅動器中用以產生直流共電壓。 第1A圖顯示用於產生液晶顯示器的交流共電壓的傳 統貝料驅動器之電路圖。在資料驅動器1〇〇之中有的 ，源VDDA以及-5V的電源VDDAN。也有第一準位移位 益110與第二準位移位器120在資料驅動器1〇〇。第一準 位移位器110偏移介於〇與1.8V之間的電壓到介於〇到 5V之間的電壓。第二準位移位器12()移動介於g與 之間的電壓到介於〇到_5V之間的電壓。 第1B圖顯示用於產生液晶顯示器的直流共電壓的傳 統資料驅動器之電路圖。在資料驅動器1〇1之中有的 電源VDDA以及別#電源似她也有第一準位移位器 130與第二準位移位器⑽在資料驅動器ΐ()ι。第—準位移 位器130偏移介於〇與！ ·8ν之間的電壓到介於〇到5v之 間的電壓。第二準位移位器14〇移動介於〇與i8v之間的 201140545 電壓到介於〇到5V之間的電壓。 通常’用於偏移介於〇與i.8伏特之間的信號到介於〇 與5伏特之間的信號之移位器無法用於偏移介於〇與i 8 伏特之間的信號到介於0與_5伏特之間的信號。目前，義 :硬體架構’用於產生交流共電壓的資料驅動器以及用ς ΐ生直流共電壓的資料驅動时因為準位移位H而不能相 電壓範圍到兩電201140545 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a quasi-positioner and a liquid crystal display device driver. [Prior Art] The pre-loading driver can only be used alone to generate an AC common voltage or a DC common voltage. When the data driver is used to generate the AC common voltage, there are two power supplies with different voltages in the data driver. When the data driver is used to generate a DC common voltage, there are two power supplies with the same voltage transformation in the data drive. Typically, there are two different types of quasi-displacers used to generate AC common voltage and two identical types of quasi-displacers for generating a DC common voltage in a data driver. Figure 1A shows a circuit diagram of a conventional batten driver for generating an alternating current common voltage of a liquid crystal display. Among the data drivers, there are source VDDA and -5V power supply VDDAN. There is also a first quasi-displacement bit 110 and a second quasi-positioner 120 in the data drive 1〇〇. The first level shifter 110 shifts the voltage between 〇 and 1.8V to a voltage between 〇 and 5V. The second quasi-positioner 12() moves the voltage between g and 至 to a voltage between 〇5 volts. Fig. 1B is a circuit diagram showing a conventional data driver for generating a DC common voltage of a liquid crystal display. In the data driver 1〇1, there are power supply VDDA and other # power supply. She also has the first quasi-positioner 130 and the second quasi-positioner (10) in the data drive ΐ(). The first-quasi-positioner 130 offset is between 〇 and ! • The voltage between 8 ν is between 〇 and 5 volts. The second quasi-positioner 14 〇 moves the voltage of 201140545 between 〇 and i8v to a voltage between 〇 and 5V. Usually a 'shifter for shifting the signal between 〇 and i.8 volts to a signal between 〇 and 5 volts cannot be used to offset the signal between 〇 and i 8 volts to A signal between 0 and _5 volts. At present, the term "hardware architecture" is used to generate the AC common voltage data driver and the data used to generate the DC common voltage is driven by the quasi-displacement bit H and cannot be phased to two voltages.
此，有必要提供一種可用於偏移一 壓範圍的資料驅動器。 【發明内容】 料驅動=·了位移位器’適用於液晶顯示器的資 號，，根據—輸入邏輯用於產生一信 壓之f;二：、介於一正輸入電源電壓與-負輸入電源電 H二ϋί，—中間級，根據該信號產生—第一邏輯 盥該第-iSMh ^ —輸出根據該第—邏輯信號 邏，號在—第—輸出端點產生—第-輸出信號 二右：一雨出端點產生一第二輸出信號，該第-輸幻: 唬具有介於一筮一 η：认L由 糊 壓之門的Φ「輸出電源電壓與—第—負輸出電源電 壓之間的-電麼’該第二輸 二： 本揭露_ —=日:，之間的-電壓。 -準位移位器，用於 第二參考源產生—第-第-參考源與- 位類比轉換器，用於根:第二輸出信號；一數 號以及該第—參考源與：第:=或該第二輸出信 罘一參考源產生一第一類比信號 201140545 t二;截波裝置’用於根據該第-炎 相是零時，產生該第一輸出信參 疋零且该第二參考源是負電壓時，產生該第^源 本揭露更提供一種移位一信號準位的方法，包= 一輸入級根據-輸人邏輯產生—信號，該信號具有介 正輸入電源電壓與-負輸人電源電壓的―電壓；二 間級根據該信號產生H輯錢與—第二‘ 以及猎由一輸出級根據該第一邏輯信號與該第二邏輯信號 在第-輸出端點產生一第一輸出信號且在一第 > 產生-第二輸出信號，該第—輸出信號具有介於:第 輸出電源電Μ與-第-負輸出電源電壓之間的—電壓 第二輸出信號具有介於一第二正輸出電源電壓與一第二負" 輸出電源電壓之間的電壓。 、 —、 上述液晶顯示器的資料驅動器的準位移位器及其方法 可偏移-電壓範圍的-個信號分別成為具有各自電壓範圍 的二個信號。因此，具有上述準位移位器的資料驅動器可 用於產生AC共電壓與DC共電壓。 【實施方式】 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下: 第2圖係顯示發明的液晶顯示器的資料驅動器的準位 移位Ιι之電路圖。準位移位器2〇〇包括一輸入級21〇、一 中間級220、一輸出級230、一第一開關24〇與一第二開關 201140545 250 ° 輸入級210用於根據輪入邏輯(IN與INB)產生介於正 輸入電源電壓VDDD與負輸人電源電壓VDDDN之間的一 個信號。中間級220用於根據這個信號產生第_邏輯信參Therefore, it is necessary to provide a data driver that can be used to offset the voltage range. [Summary of the invention] material drive = · shifter 'applicable to the liquid crystal display's capital number, according to - input logic is used to generate a signal f; two: between a positive input power supply voltage and - negative input The power supply H ϋ ί, the intermediate stage, according to the signal generated - the first logic 盥 the -iSMh ^ - output according to the first - logic signal logic, the number is generated at the - first output terminal - the first output signal two right : a rain output terminal produces a second output signal, the first-transition illusion: 唬 has a 介于 η: recognizes L by the paste pressure gate Φ "output supply voltage and - first - negative output supply voltage Between the two - the second two: the disclosure _ - = day:, between the - voltage. - Quasi-bit shifter for the second reference source generation - the first - reference source and - bit An analog converter for root: a second output signal; a number and the first reference source and: the:: or the second output signal and a reference source generate a first analog signal 201140545 t two; 'Used to generate the first output reference 疋 zero according to the first-inflammation phase and the second reference source is negative When the pressure is applied, the source device further provides a method for shifting a signal level, and the package = an input stage generates a signal according to the input logic, and the signal has a positive input power supply voltage and a negative input power supply. Voltage-voltage; the two-stage generates H-series and -second' according to the signal, and the hunter produces an output signal from the first logic signal and the second logic signal at the first-output end according to the first logic signal and the second logic signal. And generating a second output signal having a second output signal having a voltage between the first output power supply and the -first negative output power supply voltage. The voltage between the positive output power supply voltage and a second negative " output power supply voltage., -, the above-mentioned liquid crystal display data driver's quasi-displacer and its method can be offset - the voltage range - the signals become Two signals of respective voltage ranges. Therefore, a data driver having the above quasi-displacer can be used to generate an AC common voltage and a DC common voltage. [Embodiment] To achieve the above objects, features and advantages of the present invention The following is a detailed description of the preferred embodiment, and the following is a detailed description of the following: Figure 2 is a circuit diagram showing the quasi-displacement bit of the data driver of the inventive liquid crystal display. The bit device 2〇〇 includes an input stage 21〇, an intermediate stage 220, an output stage 230, a first switch 24〇 and a second switch 201140545 250° input stage 210 for logic according to wheeling (IN and INB) Generating a signal between the positive input supply voltage VDDD and the negative input supply voltage VDDDN. The intermediate stage 220 is configured to generate a _ logical reference according to the signal
以及第t邏輯信號。輸出級230用於根據第一邏輯信號與U 第二邏輯信號在第-輸出端點〇UT1產生介於第—正出、 電源電壓與第一負輸出電源電壓之間的第一輸出_號 及在第二輸出端點0UT2產生介於第二正輸出電源㈣盘 第二負輸出電源電壓之間的第二輸出信號。當 出信號時，第一開關240導通，且當產生第二輸出信號時| 第二開關250導通。 中間級220更包括第一上準位電路260與第一下準位 電路270。第-上準位電路與第一下準位電路別分 別有兩個緩衝器串聯一起。緩衝器可能是非反相器，作不 限於此。輸出級230更包括第二上準位電路與第 =位電路290。第二上準位電路的第一輸 =Τ;:Γ4°’且第二下準位電路的第二輸出 〜化OUT2連接到第二開關250。 第二上準位電路更包括第一 ^電晶體如 Ρ型電晶體282、第一 η刑雷曰锕杜 * 4電曰曰體283、第二η型電晶體挪、 二n 3L電晶體285與第四η型電晶體挪。第 f包括第三ρ型電晶體291、第四ρ型電晶— 體说、 P5L電晶體293、第六ρ型電晶體294、第五η型電晶 體295與第六^型電晶體。 第一 Ρ型電晶體281與第二卩型電晶體加㈣第一 201140545 電壓源VSSAN。第一 η型電晶體283耦接第一 p型電晶體 281，且第二η型電晶體284耦接第二p型電晶體282。第 一 ρ型電晶體281的閘極連接第一 η型電晶體283的閘極 且第二Ρ型電晶體282的閘極連接第二η型電晶體284的 閘極。第三η型電晶體285耦接第一 η型電晶體283與第 二電壓源VDDAN。第四η型電晶體286耦接第二η型電 晶體284與第二電壓源VDDAN。第三η型電晶體285的 閘極與第二ρ型電晶體282的汲極連接到第一輸出終端 OUT1。 第五η型電晶體295與第六η型電晶體296耦接第三 電壓源VDDA。第五ρ型電晶體293耦接第五η型電晶體 295且第六ρ型電晶體294耦接第六η型電晶體296。第五 η型電晶體295的閘極連接第五ρ型電晶體293的閘極。 第六η型電晶體296的閘極連接第六ρ型電晶體294的閘 極。第三ρ型電晶體291耦接第五ρ型電晶體293與第四 電壓源VSSA。第四ρ型電晶體292耦接第六ρ型電晶體 294與第四電壓電源VSSA。第三ρ型電晶291的閘極與第 六ρ型電晶體294的汲極連接到第二輸出端點OUT2。 第3圖係顯示第2圖的移位器的實施例的示意圖。於 實施例中，在輸入級210之中，正輸入電源電壓VDDD是 1.8伏特，且負輸入電源電壓VDDDN是正輸入電源電壓 VDDD的負數，亦即-1.8伏特。輸入級210的輸出電壓介 於1.8伏特與-1.8伏特之間。在中間級220，第一上準位電 路260輸出電壓介於0與-1.8伏特之間的邏輯信號，且第 一下準位電路270輸出電壓介於0與1.8伏特之間的邏輯 201140545 信號。在輸出級230之中，第一電壓源VSSAN與第四電壓 源VSSA是接地，亦即〇伏特。第二電壓源VDDAN與第 三電壓源VDDA是-5伏特。以此方式，第二下準位電路290 將在第二輸出端點OUT2輸出零電壓信號且第二開關250 相對應地導通。同時，第二上準位電路280將在第一輸出 端點OUT1輸出電壓介於〇與-5伏特之間的信號且第一開 關240相對應地導通。因此，跨越第二開關250的電位被 限制於5伏特。And the tth logic signal. The output stage 230 is configured to generate a first output_number between the first positive output, the power supply voltage and the first negative output power supply voltage at the first output terminal 〇UT1 according to the first logic signal and the U second logic signal. A second output signal is generated between the second positive output terminal (UT) and the second negative output supply voltage at the second output terminal OUT2. When the signal is output, the first switch 240 is turned on, and when the second output signal is generated | the second switch 250 is turned on. The intermediate stage 220 further includes a first upper level circuit 260 and a first lower level circuit 270. The first-up level circuit and the first lower level circuit have two buffers connected in series. The buffer may be a non-inverter, and is not limited thereto. The output stage 230 further includes a second upper level circuit and a first bit circuit 290. The first output of the second upper level circuit = Τ; Γ 4°' and the second output of the second lower level circuit is connected to the second switch 250. The second upper level circuit further includes a first transistor such as a 电-type transistor 282, a first η 刑 曰锕 * * * * * 283 283, a second η-type transistor, and a second n 3L transistor 285 Moved with the fourth n-type transistor. The fth includes a third p-type transistor 291, a fourth p-type electromorph, a P5L transistor 293, a sixth p-type transistor 294, a fifth n-type transistor 295, and a sixth transistor. The first 电-type transistor 281 and the second 卩-type transistor are added (IV) the first 201140545 voltage source VSSAN. The first n-type transistor 283 is coupled to the first p-type transistor 281, and the second n-type transistor 284 is coupled to the second p-type transistor 282. The gate of the first p-type transistor 281 is connected to the gate of the first n-type transistor 283 and the gate of the second germanium transistor 282 is connected to the gate of the second n-type transistor 284. The third n-type transistor 285 is coupled to the first n-type transistor 283 and the second voltage source VDDAN. The fourth n-type transistor 286 is coupled to the second n-type transistor 284 and the second voltage source VDDAN. The gate of the third n-type transistor 285 and the drain of the second p-type transistor 282 are connected to the first output terminal OUT1. The fifth n-type transistor 295 and the sixth n-type transistor 296 are coupled to the third voltage source VDDA. The fifth p-type transistor 293 is coupled to the fifth n-type transistor 295 and the sixth p-type transistor 294 is coupled to the sixth n-type transistor 296. The gate of the fifth n-type transistor 295 is connected to the gate of the fifth p-type transistor 293. The gate of the sixth n-type transistor 296 is connected to the gate of the sixth p-type transistor 294. The third p-type transistor 291 is coupled to the fifth p-type transistor 293 and the fourth voltage source VSSA. The fourth p-type transistor 292 is coupled to the sixth p-type transistor 294 and the fourth voltage source VSSA. The gate of the third p-type transistor 291 and the drain of the sixth p-type transistor 294 are connected to the second output terminal OUT2. Fig. 3 is a schematic view showing an embodiment of the shifter of Fig. 2. In an embodiment, among input stages 210, the positive input supply voltage VDDD is 1.8 volts and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, i.e., -1.8 volts. The output voltage of input stage 210 is between 1.8 volts and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage between 0 and -1.8 volts, and the first level level circuit 270 outputs a logic 201140545 signal having a voltage between 0 and 1.8 volts. Among the output stages 230, the first voltage source VSSAN and the fourth voltage source VSSA are grounded, that is, volts. The second voltage source VDDAN and the third voltage source VDDA are -5 volts. In this manner, the second lower level circuit 290 will output a zero voltage signal at the second output terminal OUT2 and the second switch 250 will be turned on correspondingly. At the same time, the second upper level circuit 280 will output a signal having a voltage between 〇 and -5 volts at the first output terminal OUT1 and the first switch 240 is turned on correspondingly. Therefore, the potential across the second switch 250 is limited to 5 volts.
第4圖係顯示第2圖的移位器的另一實施例的示意 圖。於實施例中’在輸入級210中，正輸入電源電壓VDDD 是1.8伏特，且負輸入電源電壓VDDDN是正輸入電源電 壓VDDD的負數，亦即-1.8伏特。輸入級210的輸出電壓 將介於1.8與-1.8伏特之間。在中間級220，第一上準位電 路260輸出具有電壓0伏特的邏輯信號，且第一下準位電 路270輸出電壓介於0與1.8伏特之間的邏輯信號。在輸 出級230，第一電壓源VSSAN，第二電壓源VDDAN與第 二電壓源VDDA是接地’亦即〇伏特。第四電壓源VSSA 是5伏特。以此方式，第二上準位電路28〇將在第一輸出 端點ουτι輸出零電壓信號以關閉第一開關24〇。同時’ 第二下準位電路290將在第二輸出端點〇υΤ2輸出電壓介 於〇與5伏特的信號以導通第二開關25〇。因此，跨越第 —開關240的電位將被限制於5伏特以下。 例 器 第5圖係顯示發明的液晶顯示器的資料驅動器的實施 資料·5〇〇包括準位移位器別、數位類比轉換 520以及戴波裝置530。 201140545 準位移位器510如上述，用於根據輸入邏輯一參 考參考源¥_產生第一輸出信號或第 一輸幻5唬。於一貫施例中，當輸入電壓是I 其邏輯準位是高準位，當輸入電壓是零伏 Μ輯 位是低準位。第-參考源VSSAN是零伏特且第 壓當資料驅動器5°°操作為產μ 。、電壓時產生第—輸出信號。第-參考源vSSAN是交伏 = 原_颜是5伏特且當資料驅動器500操 作成產生DC共電壓時產生第二輸出信號 是負電壓信號，且第二輸出信號是正電壓戶號。輸幻5號 數位類比轉換器別用於根據第一輸出信號或第 「參考源V_與第二參考 據第一東去k。號或第一類比信號。截波裝置530用於根 2第-參考源VSSAN與第：參考源VdDan限制第一輸出 5號或第二輸出信號的電壓準位。 位琴：W圖^兄明藉由發明的液晶顯示器的資料驅動器的移 移位㈣的方法流程圖。在步驟⑽，準位移位器^ 據輸入邏輯產生電麗介於正輸入電源 輸入電源電壓之間的一個信號。 生第接著㈣Γ驟620準位移位器藉由中間級根據信號產 生第二邏輯信號。藉由第-上準位電路產 源第一邏輯信號之電虔介於負輸入電 信號，曰、間。藉由第一下準位電路產生第二邏輯 之間。5亥第—邏輯信號之電麗介於零與正輸入電源電壓 201140545 最後’準位移位器根攄筮 藉由耠楚认 據第一邏軻信號與第二 位介於第一正輸出 第輪出⑷其電壓準 或在第一於,、電U 一負輸出電源電壓之間， 出端點產生第二輸出信號，其辦位介於第 -輸出電源電壓與第二負輸出電源電壓之間。、 藉由第:上準位電路根據第—邏輯信號產生第一輸出 ，以及藉由第二下準位電路根據第二邏輯電路產生第 二輸出信號。 J最後’熟此技藝者可體認到他們可以輕易地使用揭露 的觀念以及敎實施例為基礎而 變更及設計可以實施同樣 的之其他結構且不脫離本發明以及申請專利範圍。 201140545 【圖式簡單說明】 第1A圖顯示用於產生液晶顯 ^ 曰貝不态的父流共電壓的傳 統貝枓驅動器之電路圖； 吁 第1B圖顯示用於產生液晶顯 統資料驅動器之電路圖； 第2圖係顯示發明的液晶顯^ ^ ^ ^ ^ ^ ^ ^ ^ 移位器之電路圖； 盗的貝枓驅動益的準位 =3圖係顯示第2圖的移位器的實施例的示意圖； 例 =圖係顯示第2圖的移位器的另—實施例的示意圖； 圖係顯示發明的液晶顯示器的資料驅動器的實施 器的資料驅動器的移 第6圖說明藉由發明的液晶顯 位器移位信號的方法流程圖。 【主要元件符號說明】 100〜資料驅動器 120〜第二準位移位器 130〜第一準位移位器 200〜準位移位器 220〜中間級 240〜第一開關 260〜第一上準位電路 280〜第二上準位電路 281〜第一 P型電晶體 283〜第一 η型電晶體 110〜第一準位移位器 101〜資料驅動器 140〜第二準位移位器 210〜輪入級 230〜輪出級 25〇〜第二開關 270〜第一下準位電路 290〜第二下準位電路 282〜第二Ρ型電晶體 284〜第二η型電晶體Fig. 4 is a schematic view showing another embodiment of the shifter of Fig. 2. In the embodiment, in the input stage 210, the positive input supply voltage VDDD is 1.8 volts, and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, i.e., -1.8 volts. The output voltage of input stage 210 will be between 1.8 and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage of 0 volts, and the first lower level circuit 270 outputs a logic signal having a voltage between 0 and 1.8 volts. In the output stage 230, the first voltage source VSSAN, the second voltage source VDDAN and the second voltage source VDDA are grounded, i.e., volts. The fourth voltage source VSSA is 5 volts. In this manner, the second upper level circuit 28A will output a zero voltage signal at the first output terminal ουτι to turn off the first switch 24A. At the same time, the second lower level circuit 290 will output a signal at a second output terminal 〇υΤ2 with a voltage of 〇 and 5 volts to turn on the second switch 25A. Therefore, the potential across the first switch 240 will be limited to less than 5 volts. Example Fig. 5 shows the implementation of the data driver of the liquid crystal display of the invention. The data includes a quasi-bit shifter, a digital analog conversion 520, and a wearer device 530. The 201140545 quasi-positioner 510 is as described above for generating a first output signal or a first illusion 5 根据 based on the input logic a reference source ¥. In a consistent example, when the input voltage is I, its logic level is high, and when the input voltage is zero volts, the bit is low. The first reference source VSSAN is zero volts and the first voltage is operated as a data drive at 5°. The first output signal is generated when the voltage is applied. The first reference source vSSAN is the intersection = the original is 5 volts and the second output signal is a negative voltage signal when the data driver 500 is operated to generate a DC common voltage, and the second output signal is a positive voltage account number. The imaginary 5th digital analog converter is not used for the first output signal or the first reference source V_ and the second reference data to the first east to k. or the first analog signal. The chopper device 530 is used for the root 2 - reference source VSSAN and reference: reference source VdDan limits the voltage level of the first output No. 5 or the second output signal. Position: W figure ^ brother Ming by the invention of the liquid crystal display data drive shift (four) method Flowchart. In step (10), the quasi-displacer data input logic generates a signal between the positive input power supply input power supply voltage. The second (step) 620 quasi-displacer according to the intermediate stage according to the signal Generating a second logic signal. The first logic signal is generated by the first-up level circuit, and the second logic signal is generated by the first lower level circuit. 5 Haidi - the logic signal is connected to the zero and positive input power supply voltage 201140545. The last 'quasi-bit shifter' is based on the first logic signal and the second bit is in the first positive output first round. Out (4) its voltage level or in the first,, U, a negative output Between the voltages, the output terminal generates a second output signal, which is between the first output power supply voltage and the second negative output power supply voltage. The first: the upper level circuit generates the first according to the first logic signal. Outputting, and generating a second output signal according to the second logic circuit by the second lower level circuit. J. Finally, those skilled in the art can recognize that they can easily use the concept of disclosure and change based on the embodiment. The design can implement the same other structure without departing from the scope of the invention and the patent application. 201140545 [Simple description of the drawing] FIG. 1A shows a conventional Bellow drive for generating a parent-current common voltage of a liquid crystal display. Circuit diagram; FIG. 1B shows a circuit diagram for generating a liquid crystal display data driver; FIG. 2 is a circuit diagram showing the liquid crystal display of the invention ^ ^ ^ ^ ^ ^ ^ ^ shifter; Bit = 3 shows a schematic diagram of an embodiment of the shifter of Fig. 2; Example = Fig. shows a schematic view of another embodiment of the shifter of Fig. 2; the figure shows the liquid crystal display of the invention FIG. 6 is a flow chart showing a method of shifting a signal by the liquid crystal display device of the invention. [Main element symbol description] 100 to data driver 120 to second quasi-bit shifter 130 The first quasi-bit shifter 200 to the quasi-displacer 220 to the intermediate stage 240 to the first switch 260 to the first upper level circuit 280 to the second upper level circuit 281 to the first P-type transistor 283~ The first n-type transistor 110 to the first quasi-displacer 101 to the data driver 140 to the second quasi-displacer 210 to the in-stage 230 to the round-out stage 25〇 to the second switch 270 to the first Bit circuit 290 to second lower level circuit 282 to second 电 type transistor 284 to second n type transistor
12 201140545 285〜第三η型電晶體 291〜第三ρ型電晶體 293〜第五ρ型電晶體 295〜第五η型電晶體 500資料驅動器 5 2 0〜數位類比轉換器 610-630〜步驟方法 286〜第四η型電晶體 292〜第四ρ型電晶體 294〜第六ρ型電晶體 296〜第六η型電晶體 510〜準位移位器 530〜截波裝置12 201140545 285~3rd n-type transistor 291~3rd p-type transistor 293~5th p-type transistor 295~5th n-type transistor 500 data driver 5 2 0~digital analog converter 610-630~step Method 286 to fourth n-type transistor 292 to fourth p-type transistor 294 to sixth p-type transistor 296 to sixth n-type transistor 510 to quasi-displacer 530 to chopping device
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