TWI462083B - Level shifter devices and methods and source driver for liquid crystal display - Google Patents
Level shifter devices and methods and source driver for liquid crystal display Download PDFInfo
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Description
本發明係有關於一種準位移位器以及液晶顯示器的資料驅動器。The present invention relates to a quasi-positioner and a data driver for a liquid crystal display.
傳統上資料驅動器僅能單獨用於產生交流共電壓或直流共電壓。當資料驅動器用於產生交流共電壓時會有兩種具有不同電壓的電源在資料驅動器之中。當資料驅動器用於產生直流共電壓時,有兩個具有相同變壓的電源在資料驅動器之中。通常,有兩種不同型態的準位移位器在資料驅動器用以產生交流共電壓以及兩個相同型態的準位移位器在資料驅動器中用以產生直流共電壓。Traditionally, data drivers can only be used alone to generate AC common voltage or DC common voltage. When the data driver is used to generate the AC common voltage, there are two power supplies with different voltages in the data driver. When the data driver is used to generate a DC common voltage, there are two power supplies with the same voltage transformation in the data driver. Generally, there are two different types of quasi-displacers used in the data driver to generate the AC common voltage and two quasi-displacers of the same type to generate a DC common voltage in the data driver.
第1A圖顯示用於產生液晶顯示器的交流共電壓的傳統資料驅動器之電路圖。在資料驅動器100之中有5V的電源VDDA以及-5V的電源VDDAN。也有第一準位移位器110與第二準位移位器120在資料驅動器100。第一準位移位器110偏移介於0與1.8V之間的電壓到介於0到5V之間的電壓。第二準位移位器120移動介於0與1.8V之間的電壓到介於0到-5V之間的電壓。Figure 1A shows a circuit diagram of a conventional data driver for generating an alternating current common voltage of a liquid crystal display. Among the data drivers 100, there are a 5V power supply VDDA and a -5V power supply VDDAN. There is also a first quasi-positioner 110 and a second quasi-positioner 120 in the data drive 100. The first quasi-positioner 110 offsets a voltage between 0 and 1.8V to a voltage between 0 and 5V. The second quasi-positioner 120 moves the voltage between 0 and 1.8V to a voltage between 0 and -5V.
第1B圖顯示用於產生液晶顯示器的直流共電壓的傳統資料驅動器之電路圖。在資料驅動器101之中有5V的電源VDDA以及5V的電源VSSAN。也有第一準位移位器130與第二準位移位器140在資料驅動器101。第一準位移位器130偏移介於0與1.8V之間的電壓到介於0到5V之間的電壓。第二準位移位器140移動介於0與1.8V之間的電壓到介於0到5V之間的電壓。Figure 1B shows a circuit diagram of a conventional data driver for generating a DC common voltage of a liquid crystal display. Among the data drivers 101, there are a 5V power supply VDDA and a 5V power supply VSSAN. There is also a first quasi-positioner 130 and a second quasi-positioner 140 in the data drive 101. The first quasi-positioner 130 offsets a voltage between 0 and 1.8V to a voltage between 0 and 5V. The second quasi-positioner 140 moves the voltage between 0 and 1.8V to a voltage between 0 and 5V.
通常,用於偏移介於0與1.8伏特之間的信號到介於0與5伏特之間的信號之移位器無法用於偏移介於0與1.8伏特之間的信號到介於0與-5伏特之間的信號。目前,基於硬體架構,用於產生交流共電壓的資料驅動器以及用於產生直流共電壓的資料驅動器會因為準位移位器而不能相容。In general, a shifter for shifting a signal between 0 and 1.8 volts to a signal between 0 and 5 volts cannot be used to offset a signal between 0 and 1.8 volts to 0. Signal with -5 volts. Currently, based on the hardware architecture, the data drivers used to generate the AC common voltage and the data drivers used to generate the DC common voltage are not compatible due to the quasi-displacer.
因此,有必要提供一種可用於偏移一電壓範圍到兩電壓範圍的資料驅動器。Therefore, it is necessary to provide a data driver that can be used to offset a voltage range to two voltage ranges.
本揭露提供一種準位移位器,適用於液晶顯示器的資料驅動器,包括:一輸入級,根據一輸入邏輯用於產生一信號,該信號具有介於一正輸入電源電壓與一負輸入電源電壓之間的一電壓;一中間級,根據該信號產生一第一邏輯信號與一第二邏輯信號;一輸出級,根據該第一邏輯信號與該第二邏輯信號在一第一輸出端點產生一第一輸出信號或在一第二輸出端點產生一第二輸出信號,該第一輸出信號具有介於一第一正輸出電源電壓與一第一負輸出電源電壓之間的一電壓,該第二輸出信號具有介於一第二正輸出電源電壓與一第二負輸出電源電壓之間的一電壓。The present disclosure provides a quasi-displacement device for a data driver of a liquid crystal display, comprising: an input stage for generating a signal according to an input logic, the signal having a positive input supply voltage and a negative input supply voltage a voltage between the first stage, according to the signal to generate a first logic signal and a second logic signal; an output stage, according to the first logic signal and the second logic signal generated at a first output end a first output signal or a second output signal at a second output end, the first output signal having a voltage between a first positive output supply voltage and a first negative output supply voltage, The second output signal has a voltage between a second positive output supply voltage and a second negative output supply voltage.
本揭露另提供一種液晶顯示裝置的資料驅動器,包括:一準位移位器,用於根據一輸入邏輯、一第一參考源與一第二參考源產生一第一輸出信號或一第二輸出信號;一數位類比轉換器,用於根據該第一輸出信號或該第二輸出信號以及該第一參考源與該第二參考源產生一第一類比信號或一第二類比信號;以及一截波裝置,用於根據該第一參考源與該第二參考源限制該第一輸出信號或該第二輸出信號的該電壓準位;其中當第一參考源是正電壓且該第二參考源是零時,產生該第一輸出信號,以及當該第一參考源是零且該第二參考源是負電壓時,產生該第二輸出信號。The present disclosure further provides a data driver for a liquid crystal display device, comprising: a quasi-positioner for generating a first output signal or a second output according to an input logic, a first reference source and a second reference source a signal; a digital analog converter for generating a first analog signal or a second analog signal according to the first output signal or the second output signal and the first reference source and the second reference source; a wave device configured to limit the voltage level of the first output signal or the second output signal according to the first reference source and the second reference source; wherein when the first reference source is a positive voltage and the second reference source is Zero time, the first output signal is generated, and when the first reference source is zero and the second reference source is a negative voltage, the second output signal is generated.
本揭露更提供一種移位一信號準位的方法,包括:藉由一輸入級根據一輸入邏輯產生一信號,該信號具有介於一正輸入電源電壓與一負輸入電源電壓的一電壓;藉由一中間級根據該信號產生一第一邏輯信號與一第二邏輯信號;以及藉由一輸出級根據該第一邏輯信號與該第二邏輯信號在第一輸出端點產生一第一輸出信號且在一第二輸出端點產生一第二輸出信號,該第一輸出信號具有介於一第一正輸出電源電壓與一第一負輸出電源電壓之間的一電壓,該第二輸出信號具有介於一第二正輸出電源電壓與一第二負輸出電源電壓之間的電壓。The disclosure further provides a method for shifting a signal level, comprising: generating, by an input stage, a signal according to an input logic, the signal having a voltage between a positive input power supply voltage and a negative input power supply voltage; Generating a first logic signal and a second logic signal according to the signal by an intermediate stage; and generating a first output signal at the first output end according to the first logic signal and the second logic signal by an output stage And generating a second output signal at a second output end, the first output signal having a voltage between a first positive output power voltage and a first negative output power voltage, the second output signal having A voltage between a second positive output supply voltage and a second negative output supply voltage.
上述液晶顯示器的資料驅動器的準位移位器及其方法可偏移一電壓範圍的一個信號分別成為具有各自電壓範圍的二個信號。因此,具有上述準位移位器的資料驅動器可用於產生AC共電壓與DC共電壓。The quasi-displacer of the data driver of the above liquid crystal display and the method thereof can shift one signal of a voltage range into two signals having respective voltage ranges. Therefore, a data driver having the above quasi-displacer can be used to generate an AC common voltage and a DC common voltage.
為使本發明之上述目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:第2圖係顯示發明的液晶顯示器的資料驅動器的準位移位器之電路圖。準位移位器200包括一輸入級210、一中間級220、一輸出級230、一第一開關240與一第二開關250。The above described objects, features and advantages of the present invention will become more apparent from the following description of the preferred embodiments of the invention. Circuit diagram of the quasi-displacer. The quasi-displacer 200 includes an input stage 210, an intermediate stage 220, an output stage 230, a first switch 240 and a second switch 250.
輸入級210用於根據輸入邏輯(IN與INB)產生介於正輸入電源電壓VDDD與負輸入電源電壓VDDDN之間的一個信號。中間級220用於根據這個信號產生第一邏輯信號以及第二邏輯信號。輸出級230用於根據第一邏輯信號與第二邏輯信號在第一輸出端點OUT1產生介於第一正輸出電源電壓與第一負輸出電源電壓之間的第一輸出信號,以及在第二輸出端點OUT2產生介於第二正輸出電源電壓與第二負輸出電源電壓之間的第二輸出信號。當產生第一輸出信號時,第一開關240導通,且當產生第二輸出信號時,第二開關250導通。Input stage 210 is operative to generate a signal between positive input supply voltage VDDD and negative input supply voltage VDDDN based on input logic (IN and INB). The intermediate stage 220 is configured to generate a first logic signal and a second logic signal based on the signal. The output stage 230 is configured to generate a first output signal between the first positive output power voltage and the first negative output power voltage at the first output terminal OUT1 according to the first logic signal and the second logic signal, and in the second Output terminal OUT2 produces a second output signal between the second positive output supply voltage and the second negative output supply voltage. When the first output signal is generated, the first switch 240 is turned on, and when the second output signal is generated, the second switch 250 is turned on.
中間級220更包括第一上準位電路260與第一下準位電路270。第一上準位電路260與第一下準位電路270分別有兩個緩衝器串聯一起。緩衝器可能是非反相器,但不限於此。輸出級230更包括第二上準位電路280與第二下準位電路290。第二上準位電路280的第一輸出終端OUT1連接到第一開關240,且第二下準位電路290的第二輸出終端OUT2連接到第二開關250。The intermediate stage 220 further includes a first upper level circuit 260 and a first lower level circuit 270. The first upper level circuit 260 and the first lower level circuit 270 have two buffers connected in series. The buffer may be a non-inverting device, but is not limited thereto. The output stage 230 further includes a second upper level circuit 280 and a second lower level circuit 290. The first output terminal OUT1 of the second upper level circuit 280 is connected to the first switch 240, and the second output terminal OUT2 of the second lower level circuit 290 is connected to the second switch 250.
第二上準位電路280更包括第一p型電晶體281、第二p型電晶體282、第一n型電晶體283、第二n型電晶體284、第三n型電晶體285與第四n型電晶體286。第二下準位電路290包括第三p型電晶體291、第四p型電晶體292、第五p型電晶體293、第六p型電晶體294、第五n型電晶體295與第六n型電晶體。The second upper level circuit 280 further includes a first p-type transistor 281, a second p-type transistor 282, a first n-type transistor 283, a second n-type transistor 284, a third n-type transistor 285 and a Four n-type transistors 286. The second lower level circuit 290 includes a third p-type transistor 291, a fourth p-type transistor 292, a fifth p-type transistor 293, a sixth p-type transistor 294, a fifth n-type transistor 295 and a sixth N-type transistor.
第一p型電晶體281與第二p型電晶體282耦接第一電壓源VSSAN。第一n型電晶體283耦接第一p型電晶體281,且第二n型電晶體284耦接第二p型電晶體282。第一p型電晶體281的閘極連接第一n型電晶體283的閘極且第二p型電晶體282的閘極連接第二n型電晶體284的閘極。第三n型電晶體285耦接第一n型電晶體283與第二電壓源VDDAN。第四n型電晶體286耦接第二n型電晶體284與第二電壓源VDDAN。第三n型電晶體285的閘極與第二p型電晶體282的汲極連接到第一輸出終端OUT1。The first p-type transistor 281 and the second p-type transistor 282 are coupled to the first voltage source VSSAN. The first n-type transistor 283 is coupled to the first p-type transistor 281, and the second n-type transistor 284 is coupled to the second p-type transistor 282. The gate of the first p-type transistor 281 is connected to the gate of the first n-type transistor 283 and the gate of the second p-type transistor 282 is connected to the gate of the second n-type transistor 284. The third n-type transistor 285 is coupled to the first n-type transistor 283 and the second voltage source VDDAN. The fourth n-type transistor 286 is coupled to the second n-type transistor 284 and the second voltage source VDDAN. The gate of the third n-type transistor 285 and the drain of the second p-type transistor 282 are connected to the first output terminal OUT1.
第五n型電晶體295與第六n型電晶體296耦接第三電壓源VDDA。第五p型電晶體293耦接第五n型電晶體295且第六p型電晶體294耦接第六n型電晶體296。第五n型電晶體295的閘極連接第五p型電晶體293的閘極。第六n型電晶體296的閘極連接第六p型電晶體294的閘極。第三p型電晶體291耦接第五p型電晶體293與第四電壓源VSSA。第四p型電晶體292耦接第六p型電晶體294與第四電壓電源VSSA。第三p型電晶291的閘極與第六p型電晶體294的汲極連接到第二輸出端點OUT2。The fifth n-type transistor 295 and the sixth n-type transistor 296 are coupled to the third voltage source VDDA. The fifth p-type transistor 293 is coupled to the fifth n-type transistor 295 and the sixth p-type transistor 294 is coupled to the sixth n-type transistor 296. The gate of the fifth n-type transistor 295 is connected to the gate of the fifth p-type transistor 293. The gate of the sixth n-type transistor 296 is connected to the gate of the sixth p-type transistor 294. The third p-type transistor 291 is coupled to the fifth p-type transistor 293 and the fourth voltage source VSSA. The fourth p-type transistor 292 is coupled to the sixth p-type transistor 294 and the fourth voltage source VSSA. The gate of the third p-type transistor 291 and the drain of the sixth p-type transistor 294 are connected to the second output terminal OUT2.
第3圖係顯示第2圖的移位器的實施例的示意圖。於實施例中,在輸入級210之中,正輸入電源電壓VDDD是1.8伏特,且負輸入電源電壓VDDDN是正輸入電源電壓VDDD的負數,亦即-1.8伏特。輸入級210的輸出電壓介於1.8伏特與-1.8伏特之間。在中間級220,第一上準位電路260輸出電壓介於0與-1.8伏特之間的邏輯信號,且第一下準位電路270輸出電壓介於0與1.8伏特之間的邏輯信號。在輸出級230之中,第一電壓源VSSAN與第四電壓源VSSA是接地,亦即0伏特。第二電壓源VDDAN與第三電壓源VDDA是-5伏特。以此方式,第二下準位電路290將在第二輸出端點OUT2輸出零電壓信號且第二開關250相對應地不導通。同時,第二上準位電路280將在第一輸出端點OUT1輸出電壓介於0與-5伏特之間的信號且第一開關240相對應地導通。因此,跨越第二開關250的電位被限制於5伏特。Fig. 3 is a schematic view showing an embodiment of the shifter of Fig. 2. In an embodiment, among input stages 210, the positive input supply voltage VDDD is 1.8 volts and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, ie -1.8 volts. The output voltage of input stage 210 is between 1.8 volts and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage between 0 and -1.8 volts, and the first lower level circuit 270 outputs a logic signal having a voltage between 0 and 1.8 volts. Among the output stages 230, the first voltage source VSSAN and the fourth voltage source VSSA are grounded, that is, 0 volts. The second voltage source VDDAN and the third voltage source VDDA are -5 volts. In this manner, the second lower level circuit 290 will output a zero voltage signal at the second output terminal OUT2 and the second switch 250 will not be conductively corresponding. At the same time, the second upper level circuit 280 will output a signal having a voltage between 0 and -5 volts at the first output terminal OUT1 and the first switch 240 is turned on correspondingly. Therefore, the potential across the second switch 250 is limited to 5 volts.
第4圖係顯示第2圖的移位器的另一實施例的示意圖。於實施例中,在輸入級210中,正輸入電源電壓VDDD是1.8伏特,且負輸入電源電壓VDDDN是正輸入電源電壓VDDD的負數,亦即-1.8伏特。輸入級210的輸出電壓將介於1.8與-1.8伏特之間。在中間級220,第一上準位電路260輸出具有電壓0伏特的邏輯信號,且第一下準位電路270輸出電壓介於0與1.8伏特之間的邏輯信號。在輸出級230,第一電壓源VSSAN,第二電壓源VDDAN與第三電壓源VDDA是接地,亦即0伏特。第四電壓源VSSA是5伏特。以此方式,第二上準位電路280將在第一輸出端點OUT1輸出零電壓信號以關閉第一開關240。同時,第二下準位電路290將在第二輸出端點OUT2輸出電壓介於0與5伏特的信號以導通第二開關250。因此,跨越第一開關240的電位將被限制於5伏特以下。Fig. 4 is a schematic view showing another embodiment of the shifter of Fig. 2. In an embodiment, in input stage 210, the positive input supply voltage VDDD is 1.8 volts and the negative input supply voltage VDDDN is the negative of the positive input supply voltage VDDD, ie -1.8 volts. The output voltage of input stage 210 will be between 1.8 and -1.8 volts. In the intermediate stage 220, the first upper level circuit 260 outputs a logic signal having a voltage of 0 volts, and the first lower level circuit 270 outputs a logic signal having a voltage between 0 and 1.8 volts. In the output stage 230, the first voltage source VSSAN, the second voltage source VDDAN and the third voltage source VDDA are grounded, that is, 0 volts. The fourth voltage source VSSA is 5 volts. In this manner, the second upper level circuit 280 will output a zero voltage signal at the first output terminal OUT1 to turn off the first switch 240. At the same time, the second lower level circuit 290 will output a signal having a voltage between 0 and 5 volts at the second output terminal OUT2 to turn on the second switch 250. Therefore, the potential across the first switch 240 will be limited to less than 5 volts.
第5圖係顯示發明的液晶顯示器的資料驅動器的實施例。資料驅動器500包括準位移位器510、數位類比轉換器520以及截波裝置530。Fig. 5 is a view showing an embodiment of a data drive of the inventive liquid crystal display. The data driver 500 includes a quasi-bit shifter 510, a digital analog converter 520, and a clipping device 530.
準位移位器510如上述,用於根據輸入邏輯、第一參考源VSSAN與第二參考源VDDAN產生第一輸出信號或第二輸出信號。於一實施例中,當輸入電壓是1.8伏特時,其邏輯準位是高準位,當輸入電壓是零伏特時,其邏輯準位是低準位。第一參考源VSSAN是零伏特且第二參考源VDDAN是-5伏特,並且當資料驅動器500操作為產生交流共電壓時產生第一輸出信號。第一參考源VSSAN是零伏特且第二參考源VDDAN是5伏特且當資料驅動器500操作成產生DC共電壓時產生第二輸出信號。第一輸出信號是負電壓信號,且第二輸出信號是正電壓信號。The quasi-bit shifter 510 is configured to generate a first output signal or a second output signal according to the input logic, the first reference source VSSAN and the second reference source VDDAN, as described above. In one embodiment, when the input voltage is 1.8 volts, its logic level is a high level, and when the input voltage is zero volts, its logic level is a low level. The first reference source VSSAN is zero volts and the second reference source VDDAN is -5 volts and produces a first output signal when the data driver 500 is operative to generate an alternating current common voltage. The first reference source VSSAN is zero volts and the second reference source VDDAN is 5 volts and produces a second output signal when the data driver 500 is operative to generate a DC common voltage. The first output signal is a negative voltage signal and the second output signal is a positive voltage signal.
數位類比轉換器520用於根據第一輸出信號或第二輸出信號,以及第一參考源VSSAN與第二參考源VDDAN產生第一類比信號或第二類比信號。截波裝置530用於根據第一參考源VSSAN與第二參考源VDDAN限制第一輸出信號或第二輸出信號的電壓準位。The digital analog converter 520 is configured to generate a first analog signal or a second analog signal according to the first output signal or the second output signal, and the first reference source VSSAN and the second reference source VDDAN. The chopper device 530 is configured to limit the voltage level of the first output signal or the second output signal according to the first reference source VSSAN and the second reference source VDDAN.
第6圖說明藉由發明的液晶顯示器的資料驅動器的移位器移位信號的方法流程圖。在步驟610,準位移位器藉由輸入級根據輸入邏輯產生電壓介於正輸入電源電壓與負輸入電源電壓之間的一個信號。Figure 6 is a flow chart showing the method of shifting the signal by the shifter of the data driver of the liquid crystal display of the invention. At step 610, the quasi-displacer generates a signal between the positive input supply voltage and the negative input supply voltage based on the input logic by the input stage.
接著,在步驟620準位移位器藉由中間級根據信號產生第一邏輯信號與第二邏輯信號。藉由第一上準位電路產生第一邏輯信號,且該第一邏輯信號之電壓介於負輸入電源電壓與零伏特之間。藉由第一下準位電路產生第二邏輯信號,且該第二邏輯信號之電壓介於零與正輸入電源電壓之間。Next, in step 620, the quasi-bit shifter generates a first logic signal and a second logic signal according to the signal by the intermediate stage. The first logic signal is generated by the first upper level circuit, and the voltage of the first logic signal is between the negative input power supply voltage and zero volts. The second logic signal is generated by the first lower level circuit, and the voltage of the second logic signal is between zero and the positive input power source voltage.
最後,準位移位器根據第一邏輯信號與第二邏輯信號藉由輸出級在第一輸出端點產生第一輸出信號,其電壓準位介於第一正輸出電源電壓與第一負輸出電源電壓之間,或在第二輸出端點產生第二輸出信號,其電壓準位介於第二正輸出電源電壓與第二負輸出電源電壓之間。Finally, the quasi-displacer generates a first output signal at the first output end by the output stage according to the first logic signal and the second logic signal, and the voltage level is between the first positive output power supply voltage and the first negative output A second output signal is generated between the supply voltages or at the second output terminal, the voltage level being between the second positive output supply voltage and the second negative output supply voltage.
藉由第二上準位電路根據第一邏輯信號產生第一輸出信號,以及藉由第二下準位電路根據第二邏輯電路產生第二輸出信號。The first output signal is generated according to the first logic signal by the second upper level circuit, and the second output signal is generated according to the second logic circuit by the second lower level circuit.
最後,熟此技藝者可體認到他們可以輕易地使用揭露的觀念以及特定實施例為基礎而變更及設計可以實施同樣目的之其他結構且不脫離本發明以及申請專利範圍。In the end, it is obvious to those skilled in the art that they can easily use the disclosed concept and the specific embodiments to change and design other structures that can perform the same purpose without departing from the invention and the scope of the claims.
100...資料驅動器100. . . Data driver
110...第一準位移位器110. . . First quasi-positioner
120...第二準位移位器120. . . Second quasi-positioner
101...資料驅動器101. . . Data driver
130...第一準位移位器130. . . First quasi-positioner
140...第二準位移位器140. . . Second quasi-positioner
200...準位移位器200. . . Quasi-displacer
210...輸入級210. . . Input stage
220...中間級220. . . Intermediate level
230...輸出級230. . . Output stage
240...第一開關240. . . First switch
250...第二開關250. . . Second switch
260...第一上準位電路260. . . First upper level circuit
270...第一下準位電路270. . . First lower level circuit
280...第二上準位電路280. . . Second upper level circuit
290...第二下準位電路290. . . Second lower level circuit
281...第一p型電晶體281. . . First p-type transistor
282...第二p型電晶體282. . . Second p-type transistor
283...第一n型電晶體283. . . First n-type transistor
284...第二n型電晶體284. . . Second n-type transistor
285...第三n型電晶體285. . . Third n-type transistor
286...第四n型電晶體286. . . Fourth n-type transistor
291...第三p型電晶體291. . . Third p-type transistor
292...第四p型電晶體292. . . Fourth p-type transistor
293...第五p型電晶體293. . . Fifth p-type transistor
294...第六p型電晶體294. . . Sixth p-type transistor
295...第五n型電晶體295. . . Fifth n-type transistor
296...第六n型電晶體296. . . Sixth n-type transistor
500...資料驅動器500. . . Data driver
510...準位移位器510. . . Quasi-displacer
520...數位類比轉換器520. . . Digital analog converter
530...截波裝置530. . . Chopping device
610-630...步驟方法610-630. . . Step method
第1A圖顯示用於產生液晶顯示器的交流共電壓的傳統資料驅動器之電路圖;Figure 1A is a circuit diagram showing a conventional data driver for generating an alternating current common voltage of a liquid crystal display;
第1B圖顯示用於產生液晶顯示器的直流共電壓的傳統資料驅動器之電路圖;Figure 1B is a circuit diagram showing a conventional data driver for generating a DC common voltage of a liquid crystal display;
第2圖係顯示發明的液晶顯示器的資料驅動器的準位移位器之電路圖;Figure 2 is a circuit diagram showing a quasi-displacer of a data driver of the inventive liquid crystal display;
第3圖係顯示第2圖的移位器的實施例的示意圖;Figure 3 is a schematic view showing an embodiment of the shifter of Figure 2;
第4圖係顯示第2圖的移位器的另一實施例的示意圖;Figure 4 is a schematic view showing another embodiment of the shifter of Figure 2;
第5圖係顯示發明的液晶顯示器的資料驅動器的實施例;以及Figure 5 is a diagram showing an embodiment of a data drive of the inventive liquid crystal display;
第6圖說明藉由發明的液晶顯示器的資料驅動器的移位器移位信號的方法流程圖。Figure 6 is a flow chart showing the method of shifting the signal by the shifter of the data driver of the liquid crystal display of the invention.
200...準位移位器200. . . Quasi-displacer
210...輸入級210. . . Input stage
220...中間級220. . . Intermediate level
230...輸出級230. . . Output stage
240...第一開關240. . . First switch
250...第二開關250. . . Second switch
260...第一上準位電路260. . . First upper level circuit
270...第一下準位電路270. . . First lower level circuit
280...第二上準位電路280. . . Second upper level circuit
290...第二下準位電路290. . . Second lower level circuit
281...第一p型電晶體281. . . First p-type transistor
282...第二p型電晶體282. . . Second p-type transistor
283...第一n型電晶體283. . . First n-type transistor
284...第二n型電晶體284. . . Second n-type transistor
285...第三n型電晶體285. . . Third n-type transistor
286...第四n型電晶體286. . . Fourth n-type transistor
291...第三p型電晶體291. . . Third p-type transistor
292...第四p型電晶體292. . . Fourth p-type transistor
293...第五p型電晶體293. . . Fifth p-type transistor
294...第六p型電晶體294. . . Sixth p-type transistor
295...第五n型電晶體295. . . Fifth n-type transistor
296...第六n型電晶體296. . . Sixth n-type transistor
Claims (12)
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US20070096965A1 (en) * | 2005-11-03 | 2007-05-03 | Analog Devices, Inc. | Digital to analog converter and a ground offset compensation circuit |
US20070139351A1 (en) * | 2005-12-20 | 2007-06-21 | Tpo Hong Kong Holding Limited | Circuit devices |
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TW200832918A (en) * | 2007-01-16 | 2008-08-01 | Tpo Displays Corp | Voltage level shifter and image display system with the voltage level shifter |
US20080225036A1 (en) * | 2007-03-16 | 2008-09-18 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display |
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US20070096965A1 (en) * | 2005-11-03 | 2007-05-03 | Analog Devices, Inc. | Digital to analog converter and a ground offset compensation circuit |
US20070139351A1 (en) * | 2005-12-20 | 2007-06-21 | Tpo Hong Kong Holding Limited | Circuit devices |
US20080111611A1 (en) * | 2006-11-13 | 2008-05-15 | Texas Instruments Deutschland Gmbh | Cmos power switching circuit usable in dc-dc converter |
TW200832918A (en) * | 2007-01-16 | 2008-08-01 | Tpo Displays Corp | Voltage level shifter and image display system with the voltage level shifter |
US20080225036A1 (en) * | 2007-03-16 | 2008-09-18 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display |
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