TWI567785B - Method for fabricating patterned structure of semiconductor device - Google Patents
Method for fabricating patterned structure of semiconductor device Download PDFInfo
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本發明係關於一種圖案化結構之領域，特別是關於一種半導體裝置圖案化結構之製作方法。 The present invention relates to the field of patterned structures, and more particularly to a method of fabricating a patterned structure of a semiconductor device.
積體電路(integrated circuit,IC)建構之方式包含在基板或不同膜層中形成圖案化特徵(feature)以構成元件裝置和內連線結構。在IC的製作過程中，微影(photolithography)製程係為一不可或缺之技術，其主要是將所設計的圖案形成於一個或多個光罩上，然後再藉由曝光(exposure)與顯影(development)步驟將光罩上的圖案轉移至一膜層上之光阻層內。伴隨著後續的蝕刻製程、離子佈植製程以及沉積製程等半導體製程步驟，係可完成複雜的IC結構。 The integrated circuit (IC) is constructed in such a manner as to form patterned features in the substrate or in different layers to form the component device and the interconnect structure. In the production process of IC, photolithography is an indispensable technology, which is mainly to form the designed pattern on one or more masks, and then by exposure and development. The development step transfers the pattern on the reticle to the photoresist layer on a film layer. Complicated IC structures can be completed with subsequent semiconductor processing steps such as etching processes, ion implantation processes, and deposition processes.
隨著半導體元件的持續微型化及半導體製作技術的進步，目前業界常採用雙重圖案化技術(DPT)作為32奈米(nanometer,nm)與22 nm的主要線寬技術。常見的雙重圖案化技術包含顯影-蝕刻-顯影-蝕刻(photolithography-etch-photolithography-etch,2P2E)的方式。舉例而言，在一2P2E的製程方式中，首先會在目標層，例如多晶矽層，上方覆蓋有一蝕刻遮罩層，用以定義出圖案欲形成的區域。然後藉由第一次的微影-蝕刻以形成複數條彼此平行之條狀目標層圖案，且兩相鄰之條狀目標層間會被定義出一關鍵尺寸(critical dimension,CD)。最後再利用第二次的微影-蝕刻以斷開各個條狀目標層圖案。然而，即便採用2P2E的製程方式，其仍具有諸多缺失。例如，在經過第二次微影-蝕刻製程之後，兩相鄰平行條狀目標層間的關鍵尺寸通常會被進一步蝕刻擴大，而導致其尺寸產生變異。由於關鍵尺寸與半導體元件之電性密切相關，因而關鍵尺寸之變異實不利於後續半導體元件之電性控制與表現。 With the continued miniaturization of semiconductor components and advances in semiconductor fabrication technology, double patterning (DPT) is often used in the industry as the main linewidth technology for 32 nanometers (nm) and 22 nm. A common double patterning technique involves a photolithography-etch-photolithography-etch (2P2E) approach. For example, in a 2P2E process, an etch mask layer is first overlaid on a target layer, such as a polysilicon layer, to define the area where the pattern is to be formed. Then, by the first lithography-etching to form a plurality of strip-shaped target layer patterns parallel to each other, and a critical dimension is defined between the two adjacent strip target layers (critical Dimension, CD). Finally, a second lithography-etch is used to break the individual strip target layer patterns. However, even with the 2P2E process, it still has many drawbacks. For example, after a second lithography-etch process, the critical dimensions between two adjacent parallel strip target layers are typically further etched and enlarged, resulting in variations in their size. Since the critical dimensions are closely related to the electrical properties of the semiconductor components, variations in critical dimensions are not conducive to the electrical control and performance of subsequent semiconductor components.
因此，為了克服習知技藝中的諸多缺失及提升製程良率，有必要提出一種改良式的圖案化技術以獲得所需的圖案化結構。 Therefore, in order to overcome many of the shortcomings in the prior art and to improve process yield, it is necessary to propose an improved patterning technique to obtain the desired patterned structure.
本發明之目的在於提供一種圖案化結構之製作方法，以解決習知技術中關鍵尺寸會受到後續蝕刻步驟而增大的問題。 It is an object of the present invention to provide a method of fabricating a patterned structure that addresses the problem of the critical dimensions of the prior art being increased by subsequent etching steps.
根據本發明之一較佳實施例，係提供一種半導體裝置圖案化結構之製作方法，其包含有下列步驟。首先，提供一基板，其具有一第一區域以及一第二區域。依序形成一目標層、一硬遮罩層以及一第一圖案化遮罩層於基板上，並進行一第一蝕刻製程，以第一圖案化遮罩層作為一蝕刻遮罩，蝕刻第一區域內之硬遮罩層，以形成一圖案化硬遮罩層。繼以分別形成一間隙壁於圖案化硬遮罩層之各側壁上，並形成一第二圖案化遮罩層於基板上，其中第二圖案化遮罩會直接接觸各間隙壁。接著，進行一第二蝕刻製程，以第二圖案化遮罩層作為一蝕刻遮罩，蝕刻第二區域內之圖案化硬遮罩層，且同時暴露出各間隙壁。在暴露各間隙壁後，再以圖案化硬遮罩層作為一蝕刻遮罩，去除目標層直至暴露出基板。 According to a preferred embodiment of the present invention, a method of fabricating a patterned structure of a semiconductor device is provided, which includes the following steps. First, a substrate is provided having a first area and a second area. Forming a target layer, a hard mask layer and a first patterned mask layer on the substrate, and performing a first etching process, using the first patterned mask layer as an etch mask, etching first A hard mask layer within the area to form a patterned hard mask layer. Subsequently, a spacer is formed on each sidewall of the patterned hard mask layer, and a second patterned mask layer is formed on the substrate, wherein the second patterned mask directly contacts the spacers. Next, a second etching process is performed to etch the patterned hard mask layer in the second region with the second patterned mask layer as an etch mask, and simultaneously expose the spacers. After exposing the spacers, the patterned hard mask layer is used as an etch mask to remove the target layer until the substrate is exposed.
1‧‧‧基板 1‧‧‧Substrate
3‧‧‧介電層 3‧‧‧ dielectric layer
3’‧‧‧圖案化介電層 3'‧‧‧ patterned dielectric layer
5‧‧‧目標層 5‧‧‧Target layer
5’‧‧‧圖案化目標層 5’‧‧‧ patterned target layer
7‧‧‧硬遮罩層 7‧‧‧hard mask layer
7’‧‧‧圖案化硬遮罩層 7'‧‧‧ patterned hard mask
10‧‧‧第一佈局圖案 10‧‧‧First layout pattern
11‧‧‧底部遮罩層 11‧‧‧Bottom mask layer
11’‧‧‧圖案化底部遮罩層 11’‧‧‧ patterned bottom mask
13‧‧‧中間遮罩層 13‧‧‧Intermediate mask layer
15‧‧‧頂部遮罩層 15‧‧‧Top mask layer
19‧‧‧第一圖案化遮罩層 19‧‧‧First patterned mask layer
20‧‧‧薄介電層 20‧‧‧thin dielectric layer
20’‧‧‧間隙壁 20’‧‧‧
21‧‧‧第一蝕刻製程 21‧‧‧First etching process
41‧‧‧底部遮罩層 41‧‧‧Bottom mask layer
43‧‧‧中間遮罩層 43‧‧‧Intermediate mask layer
45‧‧‧頂部遮罩層 45‧‧‧Top mask layer
47‧‧‧第二圖案化遮罩層 47‧‧‧Second patterned mask layer
50‧‧‧第二佈局圖案 50‧‧‧Second layout pattern
51‧‧‧第二蝕刻製程 51‧‧‧Second etching process
61‧‧‧第三蝕刻製程 61‧‧‧ Third etching process
70’‧‧‧間隙壁 70’‧‧‧
71‧‧‧蝕刻製程 71‧‧‧ etching process
80‧‧‧溝渠 80‧‧‧ Ditch
82‧‧‧絕緣層 82‧‧‧Insulation
84‧‧‧鰭狀結構 84‧‧‧Fin structure
D1‧‧‧第一深度 D1‧‧‧first depth
D2‧‧‧第二深度 D2‧‧‧second depth
D3‧‧‧第三深度 D3‧‧‧ third depth
R1‧‧‧第一區域 R1‧‧‧ first area
R2‧‧‧第二區域 R2‧‧‧ second area
X‧‧‧第一方向 X‧‧‧ first direction
Y‧‧‧第二方向 Y‧‧‧second direction
第1圖至第12圖繪示了本發明之一較佳實施例之製作半導體裝置圖案化結構之製作方法示意圖，其中：第1圖繪示了基板上依序堆疊有目標層、硬遮罩層以及第一圖案化遮罩層之俯視圖；第2圖為沿著第1圖剖線A-A’所繪示的剖面示意圖；第3圖至第5圖繪示了製作間隙壁的剖面示意圖；第6圖至第9圖繪示了去除第二區域內圖案化目標層的示意圖；第10圖至第11圖繪示了在基板內形成溝渠的示意圖；以及第12圖繪示了形成淺溝渠絕緣結構的示意圖。 1 to 12 are schematic views showing a method of fabricating a patterned structure of a semiconductor device according to a preferred embodiment of the present invention, wherein: FIG. 1 is a view showing a target layer and a hard mask stacked on a substrate in sequence. a top view of the layer and the first patterned mask layer; FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1; and FIGS. 3 to 5 are schematic cross-sectional views of the spacer layer. 6 to 9 are schematic views showing removal of the patterned target layer in the second region; FIGS. 10 to 11 are schematic views showing the formation of trenches in the substrate; and FIG. 12 is a view showing shallow formation Schematic diagram of the trench insulation structure.
第13圖至第14圖繪示了本發明之一較佳實施例之形成圖案化目標層的示意圖。 13 through 14 illustrate schematic views of forming a patterned target layer in accordance with a preferred embodiment of the present invention.
第15圖繪示了本發明之一較佳實施例之製作間隙壁的剖面示意圖。 Figure 15 is a cross-sectional view showing the fabrication of a spacer in accordance with a preferred embodiment of the present invention.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。 The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .
第1圖至第12圖繪示了本發明之一較佳實施例之製作半導體裝置圖案化結構之製作方法示意圖。其中，本實施例所述之半導體裝置圖案化結構較佳係為一淺溝渠絕緣結構，因此，下文先就雙重圖案化技術(DPT)應用在淺溝渠絕緣結構之情形做詳細的解說。首先如第1圖及第2圖所示，第1圖繪示了在製程初始之結構剖面圖，第2圖為沿著第1圖剖線A-A’所繪示的剖面示意圖。在此階段，係提供一基板1，其上依序堆疊有一介電層3、一 目標層5、一硬遮罩層7以及一第一圖案化遮罩層19。基板1上定義有第一區域R1和第二區域R2，其中，第一區域R1包括複數條沿著一第一方向X平行排列之區域，而第二區域R2則包括複數條沿著一第二方向Y交錯排列(或視為非連續排列)之區域。根據本實施例，第一方向X與第二方向Y間的夾角較佳是90度，但不限於此，其也可以介於0度至180度之間。因此，基板1上之第一區域R1與第二區域R2會部份交錯重疊。設置於基板1上之第一圖案化遮罩層19較佳係為多層堆疊結構，例如是由下至上依序包含一底部遮罩層11、中間遮罩層13及頂部遮罩層15的三層堆疊結構，但不限於此，其層數也可以增添或刪減。第一圖案化遮罩層19較佳具有一第一佈局圖案10，其可以透過光微影的方式被定義於頂部遮罩層15中，但不限於此。較佳來說，第一佈局圖案10是根據第一區域R1而設計，亦即原本位於第一區域R1的頂部遮罩層15會在光微影過程中被去除，而使頂部遮罩層15呈現如第1圖所示之條狀佈局圖案。 1 to 12 are schematic views showing a method of fabricating a patterned structure of a semiconductor device in accordance with a preferred embodiment of the present invention. The patterned structure of the semiconductor device described in this embodiment is preferably a shallow trench isolation structure. Therefore, the following is a detailed explanation of the application of the double patterning technology (DPT) in the shallow trench isolation structure. First, as shown in Figs. 1 and 2, Fig. 1 is a cross-sectional view showing the structure at the beginning of the process, and Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1. At this stage, a substrate 1 is provided, on which a dielectric layer 3 and a layer are sequentially stacked. The target layer 5, a hard mask layer 7, and a first patterned mask layer 19. A first region R1 and a second region R2 are defined on the substrate 1, wherein the first region R1 includes a plurality of regions arranged in parallel along a first direction X, and the second region R2 includes a plurality of stripes along a second region. The area where the directions Y are staggered (or treated as non-continuously arranged). According to the embodiment, the angle between the first direction X and the second direction Y is preferably 90 degrees, but is not limited thereto, and may be between 0 degrees and 180 degrees. Therefore, the first region R1 and the second region R2 on the substrate 1 are partially overlapped. The first patterned mask layer 19 disposed on the substrate 1 is preferably a multi-layer stack structure, for example, three layers including a bottom mask layer 11, an intermediate mask layer 13 and a top mask layer 15 from bottom to top. The layer stack structure, but is not limited thereto, and the number of layers may be added or deleted. The first patterned mask layer 19 preferably has a first layout pattern 10 that can be defined in the top mask layer 15 by means of photolithography, but is not limited thereto. Preferably, the first layout pattern 10 is designed according to the first region R1, that is, the top mask layer 15 originally located in the first region R1 is removed during the photolithography process, and the top mask layer 15 is removed. A strip layout pattern as shown in Fig. 1 is presented.
上述之基板1較佳是半導體基板，例如矽基板、矽鍺(SiGe)基板以及矽覆絕緣(silicon-on-insulator,SOI)基板等等。介電層3係為氧化層，例如二氧化矽或其他適合氧化物墊層，其可以利用熱氧化法、高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)或次常壓化學氣相沉積(sub-atmosphere CVD,SACVD)等製程而製得。目標層5係為氮化層，例如氮化矽墊層，而硬遮罩層7係為氧化層，例如氧化矽層。此外，底部遮罩層11/中間遮罩層13/頂部遮罩層15可分別對應下層光阻層/抗反射層/上層光阻層，或分別對應非晶碳層(amorphous carbon layer)/抗反射層/光阻層，但不限於此。 The substrate 1 described above is preferably a semiconductor substrate such as a germanium substrate, a germanium (SiGe) substrate, and a silicon-on-insulator (SOI) substrate. The dielectric layer 3 is an oxide layer, such as cerium oxide or other suitable oxide underlayer, which may utilize thermal oxidation, high density plasma CVD (HDPCVD) or sub-atmospheric chemistry. It is produced by processes such as sub-atmosphere CVD (SACVD). The target layer 5 is a nitride layer such as a tantalum nitride layer, and the hard mask layer 7 is an oxide layer such as a hafnium oxide layer. In addition, the bottom mask layer 11 / the intermediate mask layer 13 / the top mask layer 15 may correspond to the lower photoresist layer / anti-reflection layer / upper photoresist layer, respectively, or respectively correspond to an amorphous carbon layer / anti-resistance Reflective layer / photoresist layer, but is not limited thereto.
具體來說，下層光阻層/抗反射層/上層光阻層之細部組成可以例如是ODL層/SHB層/193 nm光阻之結構，其中ODL層為有機介電層(organic dielectric layer)之簡稱，而SHB層是含矽硬遮罩及抗反射(silicon-containing hard-mask bottom anti-reflection coating,SHB)層之簡稱，而193 nm光阻是指在波長為193奈米(nm)的光源照射下會產生裂解的特定光阻。其製程方式可以是先利用一般光阻塗佈程序，將下層光阻層，例如ODL層，塗佈在基板之上，然後選擇性再加以烘烤固化。接著，形成一抗反射層，例如SHB層，其成分為含矽之有機高分子聚合物(organosilicon polymer)或聚矽物(polysilane)，至少具有一發色基團(chromophore group)、一交聯基團(crosslinkable group)及交聯劑(crosslinking agent)，使SHB層在照光後可產生交聯反應。最後，於SHB層上塗佈一上層光阻層，例如193 nm光阻。因為上層光阻層之主要功能是作為一乾蝕刻遮罩，以轉移其圖案至下方之抗反射層，因此其的厚度不需要太厚。另一方面，非晶碳層/抗反射層/光阻層之細部組成可以例如是先進圖案化材料層(advanced patterning film,APF)/SHB層/193 nm光阻之結構。在此需注意的是，由於非晶碳層具有良好的準直性(high aspect ratio,HAR)、低邊緣粗糙度(lower line edge roughness,LER)及可灰化性(PR-like ashability)，因此常被使用於小線寬的製程中。 Specifically, the composition of the lower photoresist layer/antireflection layer/upper photoresist layer may be, for example, an ODL layer/SHB layer/193 nm photoresist structure, wherein the ODL layer is an organic dielectric layer (organic) Abbreviation for the dielectric layer, and the SHB layer is an abbreviation for the silicon-containing hard-mask bottom anti-reflection coating (SHB) layer, and the 193 nm photoresist is at a wavelength of 193 nm. The specific photoresist of the cleavage is generated by the light source of (nm). The process may be that a lower photoresist layer, such as an ODL layer, is first coated on the substrate by a general photoresist coating process, and then selectively baked and cured. Next, an anti-reflective layer, such as an SHB layer, is formed, which is composed of an organosilicon polymer or a polysilane having at least one chromophore group and a crosslink. A crosslinkable group and a crosslinking agent cause the SHB layer to generate a crosslinking reaction after illumination. Finally, an upper photoresist layer, such as a 193 nm photoresist, is applied over the SHB layer. Since the primary function of the upper photoresist layer is to act as a dry etch mask to transfer its pattern to the underlying anti-reflective layer, its thickness does not need to be too thick. On the other hand, the detailed composition of the amorphous carbon layer/antireflection layer/photoresist layer may be, for example, an advanced patterning film (APF)/SHB layer/193 nm photoresist structure. It should be noted here that since the amorphous carbon layer has good high aspect ratio (HAR), low edge line roughness (LER) and PR-like ashability, Therefore, it is often used in processes with small line widths.
接著，請參照第2圖及第3圖。在第一圖案化遮罩層19覆蓋基板1之情況下進行一第一蝕刻製程21，以利用第一圖案化遮罩層19作為一蝕刻遮罩，至少將第一佈局圖案10轉移至硬遮罩層7中，而形成一圖案化硬遮罩層7’。較佳來說，更可以將第一佈局圖案10轉移至目標層5中，而形成如第3圖所示具有圖案化目標層5’之結構，並暴露出位於第一區域R1內之介電層3。此時，由於基板1之表面被介電層3覆蓋，因此可以避免基板1受到第一蝕刻製程21中蝕刻成份之破壞。根據本實施例，在經過第一蝕刻製程21後，第3圖所示之圖案化硬遮罩層7’的上方會殘留有圖案化底部遮罩層11’，但不限於此。根據其他實施例，在施行第一蝕刻製程21的過程中，當第一佈局圖案10被轉移至圖案化硬遮罩層7’時，底部遮罩層11有可能已被消耗殆盡。 在此情況下，若進一步將第一佈局圖案10轉移至圖案化目標層5’時，則是以圖案化硬遮罩層7’作為蝕刻遮罩。因此，第一蝕刻製程21不僅限於一種蝕刻程式(etch recipe)，其可以包括多種蝕刻程式，以在不同的蝕刻條件下轉移第一佈局圖案10。 Next, please refer to Figures 2 and 3. Performing a first etching process 21 in the case where the first patterned mask layer 19 covers the substrate 1 to utilize the first patterned mask layer 19 as an etch mask, at least transferring the first layout pattern 10 to the hard mask In the cover layer 7, a patterned hard mask layer 7' is formed. Preferably, the first layout pattern 10 can be transferred to the target layer 5 to form a structure having the patterned target layer 5' as shown in FIG. 3, and the dielectric in the first region R1 is exposed. Layer 3. At this time, since the surface of the substrate 1 is covered by the dielectric layer 3, the substrate 1 can be prevented from being damaged by the etching component in the first etching process 21. According to the present embodiment, after the first etching process 21 is passed, the patterned bottom mask layer 11' remains on the patterned hard mask layer 7' shown in Fig. 3, but is not limited thereto. According to other embodiments, during the execution of the first etching process 21, when the first layout pattern 10 is transferred to the patterned hard mask layer 7', the bottom mask layer 11 may have been exhausted. In this case, if the first layout pattern 10 is further transferred to the patterning target layer 5', the patterned hard mask layer 7' is used as an etching mask. Thus, the first etch process 21 is not limited to an etch recipe, which may include multiple etch recipes to transfer the first layout pattern 10 under different etch conditions.
接著，請參照第4圖至第5圖。第4圖至第5圖分別繪示了製作間隙壁的剖面示意圖。如第4圖所示，在形成圖案化硬遮罩層7’之後，全面形成一厚度均勻之薄介電層20，順向性地覆蓋並直接接觸圖案化硬遮罩層7’、圖案化目標層5’以及介電層3。其中，薄介電層20之厚度較佳小於圖案化硬遮罩層7’之厚度。接著，進行一蝕刻製程，去除圖案化硬遮罩層7’正上方之薄介電層20，以形成間隙壁20’。各間隙壁20’會暴露出第一區域R1內之部份介電層3，且各間隙壁20’可以覆蓋圖案化硬遮罩層7’之相對應各側壁，並延伸覆蓋於圖案化目標層5’之相對應各側壁。上述薄介電層20之材質可以是氮化物、氧化物或氮氧化物，且其材質可以與圖案化硬遮罩層7’相同或不同。 Next, please refer to Figures 4 to 5. 4 to 5 are schematic cross-sectional views showing the fabrication of the spacers, respectively. As shown in FIG. 4, after the patterned hard mask layer 7' is formed, a thin dielectric layer 20 of uniform thickness is formed integrally, and the patterned hard mask layer 7' is smoothly covered and directly contacted, and patterned. The target layer 5' and the dielectric layer 3. The thickness of the thin dielectric layer 20 is preferably less than the thickness of the patterned hard mask layer 7'. Next, an etching process is performed to remove the thin dielectric layer 20 directly over the patterned hard mask layer 7' to form the spacers 20'. Each of the spacers 20 ′ exposes a portion of the dielectric layer 3 in the first region R1 , and each of the spacers 20 ′ can cover the corresponding sidewalls of the patterned hard mask layer 7 ′ and extend over the patterned target The layers 5' correspond to the respective side walls. The material of the thin dielectric layer 20 may be a nitride, an oxide or an oxynitride, and the material thereof may be the same as or different from the patterned hard mask layer 7'.
接著，請參照第6圖至第9圖。第6圖至第9圖繪示了去除第二區域內的圖案化目標層的製程示意圖。如第6圖所示，形成一第二圖案化遮罩層47於基板1上，以完全覆蓋住圖案化硬遮罩層7’以及各間隙壁20’。類似上述第一圖案化遮罩層之結構，第二圖案化遮罩層47較佳也是多層堆疊結構，例如是由下至上依序包含一底部遮罩層41、中間遮罩層43及頂部遮罩層45的三層堆疊結構，但不限於此，其層數也可以增添或刪減。第二圖案化遮罩層47較佳具有一第二佈局圖案50，其可以透過光微影的方式被定義於頂部遮罩層45中，但不限於此。較佳來說，第二佈局圖案50是根據第二區域R2而設計，使得原本位於第二區域R2的頂部遮罩層45會在施行光微影的過程中被去除。因此，本實施例之第一佈局圖案10與第二佈局圖案50彼 此延伸的方向會互相正交(orthogonal)，但不限於此。 Next, please refer to Figures 6 to 9. 6 to 9 are schematic views showing a process of removing the patterned target layer in the second region. As shown in Fig. 6, a second patterned mask layer 47 is formed on the substrate 1 to completely cover the patterned hard mask layer 7' and the spacers 20'. Similar to the structure of the first patterned mask layer, the second patterned mask layer 47 is preferably also a multi-layer stack structure, for example, including a bottom mask layer 41, an intermediate mask layer 43 and a top mask sequentially from bottom to top. The three-layer stack structure of the cover layer 45 is not limited thereto, and the number of layers thereof may be added or deleted. The second patterned mask layer 47 preferably has a second layout pattern 50 that can be defined in the top mask layer 45 by means of photolithography, but is not limited thereto. Preferably, the second layout pattern 50 is designed according to the second region R2 such that the top mask layer 45 originally located in the second region R2 is removed during the process of performing photolithography. Therefore, the first layout pattern 10 and the second layout pattern 50 of the embodiment are The directions of this extension will be orthogonal to each other, but are not limited thereto.
如第6圖至第8圖所示，其中第8圖是沿著第7圖中剖線A-A’所繪示的剖面示意圖。接著，進行一第二蝕刻製程51，利用第二圖案化遮罩層47作為一蝕刻遮罩，將第二佈局圖案50轉移至圖案化硬遮罩層7’中。根據本實施例，由於第二蝕刻製程51的蝕刻程式可以依據不同製程需求而被加以調整，而使得底部遮罩層41、中間遮罩層43及頂部遮罩層45的蝕刻移除速率大於圖案化硬遮罩層7’的蝕刻移除速率，因此當第二佈局圖案50被轉移至圖案化硬遮罩層7’時，第一區域R1內之底部遮罩層41可以被蝕刻至一第一深度D1，使得各間隙壁20’部份被暴露出於底部遮罩層41，但不限於此。根據其他實施例，第二蝕刻製程51也可完全移除第一區域R1內的底部遮罩層41，而暴露出位於第一區域R1內的介電層3。在此需注意的是，根據本實施例，第一區域R1之寬度較佳會小於第二區域R2之寬度，但不限於此。根據其他實施例，第一區域R1之寬度也可大於第二區域R2之寬度。 As shown in Figs. 6 to 8, wherein Fig. 8 is a schematic cross-sectional view taken along line A-A' in Fig. 7. Next, a second etching process 51 is performed to transfer the second layout pattern 50 into the patterned hard mask layer 7' by using the second patterned mask layer 47 as an etch mask. According to the embodiment, since the etching process of the second etching process 51 can be adjusted according to different process requirements, the etching removal rate of the bottom mask layer 41, the intermediate mask layer 43 and the top mask layer 45 is greater than the pattern. The etching removal rate of the hard mask layer 7' is reduced, so that when the second layout pattern 50 is transferred to the patterned hard mask layer 7', the bottom mask layer 41 in the first region R1 can be etched to a first A depth D1 is such that each of the spacers 20' is partially exposed to the bottom mask layer 41, but is not limited thereto. According to other embodiments, the second etching process 51 can also completely remove the bottom mask layer 41 in the first region R1 to expose the dielectric layer 3 located in the first region R1. It should be noted here that, according to the embodiment, the width of the first region R1 is preferably smaller than the width of the second region R2, but is not limited thereto. According to other embodiments, the width of the first region R1 may also be greater than the width of the second region R2.
接著，如第9圖所示，繼續進行第二蝕刻製程51，利用圖案化硬遮罩層7’作為蝕刻遮罩，蝕穿圖案化目標層5’直至暴露出介電層3，因而將第二佈局圖案轉移至圖案化目標層5’內。在此需注意的是，由於第一區域R1內的圖案化硬遮罩層7’及圖案化目標層5’的側壁均被間隙壁20’覆蓋，所以在蝕刻去除位於第二區域R2內之圖案化目標層5’時，蝕刻劑不會接觸到第一區域R1內之圖案化硬遮罩層7’以及圖案化目標層5’，而使得第一區域R1內圖案化目標層5’的相對側壁可以維持原先定義於第一區域R1內之第一佈局圖案之尺寸。換句話說，間隙壁20’可以避免定義於第一區域R1內第一佈局圖案之臨界尺寸受到第二蝕刻製程51的影響。根據本實施例，第二蝕刻製程51較佳不會蝕刻間隙壁20’。然而，根據其他實施例，第二蝕刻製程51也可能會蝕刻間隙壁20’，使間隙壁20’被進一步減薄，或是使原本被間隙壁 20’覆蓋之圖案化硬遮罩層7’被暴露出。但即便如此，間隙壁20’仍展現了避免圖案化目標層5’被直接蝕刻的作用。另外，根據本實施例，第二蝕刻製程51可以包含多種蝕刻程式，使得在蝕刻第二區域R2內圖案化目標層5’所採用的蝕刻程式較佳會不同於蝕刻第二區域R2內圖案化硬遮罩層7’所採用的蝕刻程式。 Next, as shown in FIG. 9, the second etching process 51 is continued, and the patterned hard mask layer 7' is used as an etch mask to etch through the patterned target layer 5' until the dielectric layer 3 is exposed. The second layout pattern is transferred into the patterned target layer 5'. It should be noted that since the sidewalls of the patterned hard mask layer 7' and the patterned target layer 5' in the first region R1 are covered by the spacers 20', the etching is removed in the second region R2. When the target layer 5' is patterned, the etchant does not contact the patterned hard mask layer 7' and the patterned target layer 5' in the first region R1, so that the target region 5' is patterned in the first region R1. The opposite sidewalls can maintain the size of the first layout pattern originally defined in the first region R1. In other words, the spacer 20' can prevent the critical dimension of the first layout pattern defined in the first region R1 from being affected by the second etching process 51. According to this embodiment, the second etching process 51 preferably does not etch the spacers 20'. However, according to other embodiments, the second etching process 51 may also etch the spacers 20' such that the spacers 20' are further thinned or otherwise provided with spacers. The 20' covered patterned hard mask layer 7' is exposed. Even so, the spacers 20' exhibit the effect of avoiding direct etching of the patterned target layer 5'. In addition, according to the embodiment, the second etching process 51 may include various etching programs, so that the etching process used to pattern the target layer 5' in the etching second region R2 is preferably different from the etching in the etching second region R2. The etching procedure used for the hard mask layer 7'.
經由上述之第一蝕刻製程和第二蝕刻製程，第一佈局圖案以及第二佈局圖案便會分別被定義於圖案化目標層5’內。接著，參照第10圖至第12圖所示，其中第11圖是沿著第10圖中剖線A-A’所繪示的剖面示意圖。如第10圖及第11圖所示，可以繼續進行一第三蝕刻製程61，蝕穿介電層3，並進一步形成複數個溝渠80於基板1內，其中各溝渠80會具有一第二深度D2。此時，第一佈局圖案10以及第二佈局圖案50便會被轉移至基板1中。如第11圖及第12圖所示，在完全去除圖案化硬遮罩層7’之後，繼以進行一絕緣層沉積製程、平坦化製程以及回蝕刻製程，使絕緣層82之頂面位於一第三深度D3。最後，完全移除圖案化目標層5’以及介電層3，以暴露出部份之基板1。至此，便完成本實施例之淺溝渠絕緣結構。之後，可繼續施行離子佈植、形成閘極結構以及製作導電接觸結構等製程，使得突出於絕緣層82之基板1作為多閘極電晶體之鰭狀結構84。 Through the first etching process and the second etching process described above, the first layout pattern and the second layout pattern are respectively defined in the patterned target layer 5'. Next, reference is made to Figs. 10 to 12, wherein Fig. 11 is a schematic cross-sectional view taken along line A-A' in Fig. 10. As shown in FIGS. 10 and 11 , a third etching process 61 can be continued to etch through the dielectric layer 3 and further form a plurality of trenches 80 in the substrate 1 , wherein each trench 80 has a second depth. D2. At this time, the first layout pattern 10 and the second layout pattern 50 are transferred to the substrate 1. As shown in FIGS. 11 and 12, after the patterned hard mask layer 7' is completely removed, an insulating layer deposition process, a planarization process, and an etch back process are performed to place the top surface of the insulating layer 82 at a top. The third depth D3. Finally, the patterned target layer 5' and the dielectric layer 3 are completely removed to expose a portion of the substrate 1. So far, the shallow trench insulation structure of this embodiment is completed. Thereafter, the processes of ion implantation, formation of a gate structure, and fabrication of a conductive contact structure may be continued such that the substrate 1 protruding from the insulating layer 82 functions as a fin structure 84 of the multi-gate transistor.
本發明除了上述第一較佳實施例外，另可包括其他形成淺溝渠絕緣結構的實施例變化型。這些變化型之結構以及製程步驟大致類似於上述第一較佳實施例，以下僅就主要差異處加以描述，且相類似的元件與結構可以搭配參照。 In addition to the first preferred embodiment described above, the present invention may include other embodiment variations that form a shallow trench isolation structure. The structure and process steps of these variations are generally similar to the first preferred embodiment described above, and only the main differences will be described below, and similar components and structures may be referred to.
請參照第13圖及第14圖，第13圖及第14圖是根據本發明第一較佳實施例之一變化型形成圖案化目標層的示意圖。第13圖及第14圖之結 構、製程步驟和形成時點大致對應於上述第一較佳實施例的第3圖至第5圖，兩者的主要差異在於，根據此第一較佳實施例之變化型，形成間隙壁70’的時點優先於形成圖案化目標層之時點，因此間隙壁70’僅會覆蓋圖案化硬遮罩層7’之側壁，而形成如第13圖所示之結構。接著，如第14圖所示，利用圖案化硬遮罩層7’及各間隙壁70’作為蝕刻遮罩，進行一蝕刻製程71以蝕刻第一區域R1內之目標層，以形成圖案化目標層5’。此時，第一區域R1內圖案化目標層5’相對側壁間的距離會小於原先第一佈局圖案定義之尺寸。在後續轉移第二佈局圖案之製程中，位於各間隙壁70’正下方之圖案化目標層5’便可以作為蝕刻犧牲層，透過部份消耗之方式以避免圖案化硬遮罩層7’正下方之圖案化目標層5’被進一步蝕刻。因此，即便第一區域R1內圖案化目標層5’之側壁會在轉移第二佈局圖案至圖案化目標層5’之過程中被部份蝕刻，但是其尺寸仍會維持等於或略小於原先第一佈局圖案定義出的臨界尺寸。 Referring to Figures 13 and 14, Figures 13 and 14 are schematic views of forming a patterned target layer in accordance with a variation of the first preferred embodiment of the present invention. Figure 13 and Figure 14 The structure, the processing steps, and the forming time point substantially correspond to the third to fifth figures of the first preferred embodiment described above, and the main difference between the two is that the spacer 70' is formed according to the variation of the first preferred embodiment. The time point takes precedence over the time at which the patterned target layer is formed, so that the spacer 70' only covers the sidewall of the patterned hard mask layer 7' to form a structure as shown in FIG. Next, as shown in FIG. 14, using the patterned hard mask layer 7' and each of the spacers 70' as an etch mask, an etching process 71 is performed to etch the target layer in the first region R1 to form a patterned target. Layer 5'. At this time, the distance between the opposite sidewalls of the patterned target layer 5' in the first region R1 may be smaller than the size defined by the original first layout pattern. In the subsequent process of transferring the second layout pattern, the patterned target layer 5' located directly under each of the spacers 70' can serve as an etching sacrificial layer, and partially consumes the pattern to avoid patterning the hard mask layer 7'. The patterned target layer 5' below is further etched. Therefore, even if the sidewall of the patterned target layer 5' in the first region R1 is partially etched during the transfer of the second layout pattern to the patterned target layer 5', the size thereof remains equal to or slightly smaller than the original A layout pattern defines the critical dimension.
本發明第一較佳實施例更包括另一變化型。請參照第15圖，第15圖是根據本發明第一較佳實施例之一變化型形成圖案化介電層的示意圖。第15圖之結構、製程步驟和形成時點大致對應於上述第一較佳實施例的第5圖。兩者的主要差異在於，根據此第一較佳實施例之變化型，在第一蝕刻製程中，第一佈局圖案不僅被轉移至硬遮罩層和目標層，其也會被進一步轉移至介電層而形成一圖案化介電層3’，以暴露出位於第一區域R1內之基板1。因此，間隙壁70’不僅只覆蓋圖案化硬遮罩層7’及圖案化目標層5’之側壁，其也會進一步覆蓋圖案化介電層3’之側壁。 The first preferred embodiment of the present invention further includes another variation. Referring to Figure 15, Figure 15 is a schematic illustration of a patterned dielectric layer formed in accordance with a variation of the first preferred embodiment of the present invention. The structure, process steps and formation timing of Fig. 15 substantially correspond to Fig. 5 of the first preferred embodiment described above. The main difference between the two is that, according to the variation of the first preferred embodiment, in the first etching process, the first layout pattern is not only transferred to the hard mask layer and the target layer, but also is further transferred to the medium layer. The electrical layer forms a patterned dielectric layer 3' to expose the substrate 1 located in the first region R1. Therefore, the spacers 70' cover not only the sidewalls of the patterned hard mask layer 7' and the patterned target layer 5', but also the sidewalls of the patterned dielectric layer 3'.
在此需注意的是，根據本發明之第一較佳實施例之又一變化型，目標層以及基板之間也可以不設置介電層。因此，當蝕穿目標層後便會暴露出相對應區域之基板，使得後續形成之間隙壁可以直接接觸基板。除了沒有設置介電層之外，本變化型實施例之結構或製程實質上均類似於第一較佳實 施例及上述變化型之第1圖至第15圖所示之結構或製程，在此便不再贅述。 It should be noted that, according to still another variation of the first preferred embodiment of the present invention, a dielectric layer may not be disposed between the target layer and the substrate. Therefore, when the target layer is etched through, the substrate of the corresponding region is exposed, so that the subsequently formed spacer can directly contact the substrate. The structure or process of the present modified embodiment is substantially similar to the first preferred embodiment except that no dielectric layer is provided. The structures or processes shown in the first and fifth embodiments of the above-described variations are not described herein.
根據上述，半導體裝置圖案化結構之製作方法是針對淺溝渠絕緣結構之製作方法。然而，根據本發明之第二較佳實施例，其亦可以用以製作閘極圖案結構，由於第二較佳實施例之製程步驟及結構大致類似於上述第一較佳實施例，以下僅就主要差異處加以描述，且相類似的元件與結構可以搭配參照。類似於第1圖至第10圖以及第13圖至第15圖所示，本實施例與第一較佳實施例之主要差別在於，第二較佳實施例之目標層5係為一閘極導電層，其包括一單晶矽層、一多晶矽層或一非晶矽層，且介電層3係為一閘極氧化層，例如氧化矽層。此外，本較佳實施例間隙壁20’之組成可以與目標層5相同，使得在轉移第二佈局圖案至圖案化目標層5’時，可以連帶去除間隙壁20’，而不需額外施行去除間隙壁20’之製程。本較佳實施例之閘極結構除了不會在基板1內形成溝渠外，其俯視佈局設計大致會類似於第10圖所示之佈局設計。因此，本實施例利用第一佈局圖案定義出兩相鄰閘極結構之側邊(side-by-side)間距，而利用第二佈局圖案定義出兩相鄰閘極結構之頭對頭(head-to-head)間距。類似如第9圖所示，由於在轉移第二佈局圖案時，間隙壁20’會覆蓋住第一區域R1內之圖案化目標層5’，因此避免了原始第一佈局圖案的尺寸被蝕刻擴大。在此需注意的是，本第二較佳實施例之介電層3較佳在轉移第一佈局圖案時便會被蝕穿，而形成一圖案化介電層3’，並暴露出下方之基板1。此外，第二較佳實施例也可以先轉移第二佈局圖案至目標層，之後再轉移第一佈局圖案至圖案化目標層，以滿足製程之需求。 According to the above, the method of fabricating the patterned structure of the semiconductor device is directed to a method of fabricating a shallow trench insulating structure. However, according to the second preferred embodiment of the present invention, the gate pattern structure can also be used. Since the process steps and structure of the second preferred embodiment are substantially similar to the first preferred embodiment described above, the following is only The main differences are described, and similar components and structures can be referred to. Similar to FIGS. 1 to 10 and FIGS. 13 to 15, the main difference between this embodiment and the first preferred embodiment is that the target layer 5 of the second preferred embodiment is a gate. The conductive layer comprises a single crystal germanium layer, a poly germanium layer or an amorphous germanium layer, and the dielectric layer 3 is a gate oxide layer, such as a hafnium oxide layer. In addition, the composition of the spacer 20' of the preferred embodiment may be the same as that of the target layer 5, so that when the second layout pattern is transferred to the patterned target layer 5', the spacer 20' may be removed without additional removal. The process of the spacer 20'. The gate structure of the preferred embodiment does not form a trench in the substrate 1, and its top layout design is substantially similar to the layout design shown in FIG. Therefore, in this embodiment, the side-by-side spacing of two adjacent gate structures is defined by the first layout pattern, and the head-to-head of the two adjacent gate structures is defined by the second layout pattern (head- To-head) spacing. Similarly, as shown in FIG. 9, since the spacer 20' covers the patterned target layer 5' in the first region R1 when the second layout pattern is transferred, the size of the original first layout pattern is prevented from being etched and enlarged. . It should be noted that the dielectric layer 3 of the second preferred embodiment is preferably etched through the first layout pattern to form a patterned dielectric layer 3' and exposes the underlying layer. Substrate 1. In addition, the second preferred embodiment may also transfer the second layout pattern to the target layer, and then transfer the first layout pattern to the patterned target layer to meet the requirements of the process.
為了簡潔起見，上述各實施例僅以淺溝渠絕緣結構以及閘極圖案結構作為製作方法之應用標的，但本發明不限於此。進一步來說，本發明亦可應用於各式高密度與積集度的圖案化製程中，例如接觸洞(contact holes)、介層開孔(via holes)等半導體製程。 For the sake of brevity, the above embodiments use only the shallow trench isolation structure and the gate pattern structure as the application targets of the fabrication method, but the invention is not limited thereto. Further, the present invention can also be applied to various high density and accumulative patterning processes, such as semiconductor processes such as contact holes and via holes.
綜上所述，本發明在轉移第二佈局圖案至圖案化目標層之前，會先形成間隙壁，至少覆蓋於圖案化硬遮罩層之側壁或進一步延伸覆蓋於圖案化目標層之側壁，以保護第一佈局圖案所定義出之臨界尺寸。因此在後續轉移第二佈局圖案的蝕刻製程中，原先被定義在圖案化硬遮罩層或圖案化目標層的第一佈局圖案的尺寸便不會被蝕刻擴大，進而有利於後續半導體元件之電性控制與表現。 In summary, the present invention first forms a spacer before transferring the second layout pattern to the patterned target layer, at least covering the sidewall of the patterned hard mask layer or further extending over the sidewall of the patterned target layer to Protects the critical dimension defined by the first layout pattern. Therefore, in the etching process of subsequently transferring the second layout pattern, the size of the first layout pattern originally defined in the patterned hard mask layer or the patterned target layer is not etched and enlarged, thereby facilitating the subsequent semiconductor component. Sexual control and performance.
1‧‧‧基板 1‧‧‧Substrate
3‧‧‧介電層 3‧‧‧ dielectric layer
5’‧‧‧圖案化目標層 5’‧‧‧ patterned target layer
7’‧‧‧圖案化硬遮罩層 7'‧‧‧ patterned hard mask
20’‧‧‧間隙壁 20’‧‧‧
51‧‧‧第二蝕刻製程 51‧‧‧Second etching process
R1‧‧‧第一區域 R1‧‧‧ first area
R2‧‧‧第二區域 R2‧‧‧ second area
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