TW201104732A - Thin wafer structure and method - Google Patents

Thin wafer structure and method Download PDF

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TW201104732A
TW201104732A TW99121418A TW99121418A TW201104732A TW 201104732 A TW201104732 A TW 201104732A TW 99121418 A TW99121418 A TW 99121418A TW 99121418 A TW99121418 A TW 99121418A TW 201104732 A TW201104732 A TW 201104732A
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layer
carrier
wafer
peeling
adhesive layer
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TW99121418A
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TWI485756B (zh
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Chen-Hua Yu
Kuo-Ching Hsu
Chen-Shien Chen
Ching-Wen Hsiao
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1476—Release layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Description

201104732 六、發明說明： 【發明所屬之技術領域】 本發明係有關於晶圓處理’且特別是有關於一種薄 晶圓處理結構及便於接合及剝離的方法。 【先前技術】 在半導體晶圓處理製程中，薄晶圓背側製程需要暫 時接合及剝離技術。晶圓藉由黏著層接合在剛硬的載材 (carrier)上。經過研磨及/或其他後接合製程(post-bonding processes)後，自此剛硬的載材上將B日圓剝離。 傳統剝離方法之一為在一光熱轉換層（light-t0 heat conversion layer)上使用雷射以剝離載材’並接者剝除 (peel off)黏著層。黏著材料為紫外光（UV )固化材料， 例如不能由化學物剝除（stripped) ’但可以物理方式剝落 (peel off)的熱固性聚合物。此方法於晶圓剝離後會留有 化學殘餘物。因此’此雷射剝離層在背侧製程時的化學 抵抗性極低。 另一種傳統方法為使用化學剝離（chemical release)。此方法是以化學方式溶解黏著層以剝離載材。 此方法需要多孔的玻璃且容易導致交叉污染（cross contamination)。此方法之處理速度，例如每小時晶圓產 出率（wafers per hour，WPH)，相較於其他方法亦較緩慢。 另一種傳統方法為熱滑動（thermal sliding)。此方法 以熱處理晶圓及載材，接著使其滑動分開。此方法需要 較高的剝離溫度，且對内連線配置（interconnection 0503-A35003TWF/jeff 4 201104732 scheme )造成不利的影響。 因此，業界需要的是新穎的結構及方法，來穩固晶 圓接合以確保剝離後的表面清潔，且在後製程中有良好 的化學抵抗性。 【發明内容】 為解決上述問題，本發明提供一種薄晶圓處理結 構’包括.一半導體晶圓；一剝離層（release layer)， φ 其可由施加能量予以剝離；一黏著層，其可由一溶劑予 以移除；以及一載材；其中該剝離層以塗佈或壓合方式 至少其一施加至該載材，該黏著層係以塗佈或壓合方式 至少其一施加至該半導體晶圓，該半導體晶圓及該載材 相互接合，且該剝離層及該黏著層位於該半導體晶圓及 該載材之間。 本發明亦提供一種方法，包括：以塗佈或壓合至少 其一施加一剝離層於一載材上；以塗佈或壓合至少其一 鈀加。黏著層至一半導體晶圓上；接合該載材及該半導 ，晶圓，且該剝離層及該黏著層位於該載材及該半導體 日日圓之間；施予能量至該剝離層，以剝離該载材；以及 夕/合齊u綠该半導體晶圓之一表面，以移除該黏著層 之所有殘餘物。 明顯=本==其他目的、特徵'和優點能更 作實施例，並配合所附圖式， 0503-A35003TWF/jeff 5 201104732 【實施方式】 以下將詳細討論本發明各種實施例之製造及使用方 法。然而值得注意的是，本發明所提供之許多可行的發 明概念可實施在各種特定範圍中。這些特定實施例僅用 於舉例說明本發明之製造及使用方法，但非用於限定本 發明之範圍。 本發明提供一種薄晶圓處理結構及方法，以便於晶 圓製程中的接合及剝離。在本發明所揭示的各種圖示及 實施例中，相似的標號用於表示相似的元件。 第1圖顯示為依照本發明一實施例之薄晶圓處理結 構，用以便於接合及剝離。晶圓102藉由使用在其與載 材108之間的兩膜層（亦即剝離層106及黏著層104)接合 在載材108上。以塗佈或壓合製程施加剝離層106至載 材108上，接著以晶圓邊緣殘餘物移除法（edge bead removal，EBR)去除該剝離層相對於載材之外緣的0.1 mm 至 3 mm ° 晶圓邊緣殘餘物移除法（EBR)去除於晶圓邊緣處堆 積材料。在無任何其他處理下，過量的材料可堆積在晶 圓邊緣處，且達膜層名義上厚度（nominal thickness)的數 倍厚。這種情況會造成設備污染的風險。於化學晶圓邊 緣殘餘物移除（chemical EBR)中，塗佈後立即旋轉晶圓， 溶劑會分散至晶圓邊緣。 以塗佈或壓合製程施加黏著層104至晶圓102上， 且此黏著層104可由溶劑移除。例如在一較佳實施例中， 可使用熱塑性聚合物作為黏著層。載材108及晶圓102 0503-A35003TWF/jeff 6 201104732 為藉由uv光或熱能相互接合。 第2圖為顯示依照發明一實施例之便於薄晶圓接合 及剝離之方法。於步驟202，以塗佈或壓合方式施加剝離 層106至載材108上。在一實施例中，可使用旋轉塗佈。 於步驟204，以塗佈或壓合方式施加黏著層104至晶圓 102上。於步驟206，晶圓102及載材108相互接合，且 剝離層106及黏著層104位於其間，並以熱能或UV光 固化。黏著劑可在接合之前先作預烘烤。於步驟208，晶 φ 圓進行後接合製程，例如研磨、晶圓背側製程等。晶圓 背側製程可包含離子佈植、退火、蝕刻、濺鍍、蒸鍍及/ 或金屬化。 在進行後晶圓製程之後，對晶圓進行剝離製程，其 包含剝離載材及後清潔（post cleaning)。於步驟210，施 予能量（例如UV光或雷射光）於剝離層106上以剝離載材 108。在載材108剝離之前，薄晶圓102可掛載於切割框 上，以壓合切割膠帶（dicing tape lamination)。接著，以 • 浸泡在溶劑中的化學品清潔晶圓102表面，以移除黏著 層104之所有殘餘物。例如，使用熱塑性聚合物之黏著 層可被溶劑以化學方式清潔。本發明所屬領域具有通常 知識者可知本發明尚具有許多其他變化實施例。 本發明所揭示的優點包含晶圓在剝離後的清潔表 面，及在後結合製程中具有良好的化學抵抗性。 雖然本發明已以數個較佳實施例揭露如上，然其並 非用以限定本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 0503-A35003TWF/jeff 7 201104732 動與潤飾。此外，太旅 發展的特m / ㈣不限定於現有或未來所 j:特疋知式、機器、製造、物質之組合、功能、方 法或步驟，1實皙！b 方 /、貰買上進仃與依照本發明所述之實施例相 同的功能或達成相同的社果 的…果因此，本發明之保護範圍 後附之申請專利範圍所界定者為準。此外，每個申 请專利範圍建構成—獨立的實施例，且各種申請專利範 圍及實施例之組合皆介於本發明之範圍内。
0503-A35003TWF/jeflF 8 201104732 【圖式簡單說明】 第1圖顯示為依照本發明一實施例之薄晶圓處理結 構，用以便於接合及剝離。 第2圖為顯示依照發明一實施例之便於薄晶圓接合 及剝離之方法。 【主要元件符號說明】 102〜晶圓， φ 104〜黏著層； 106〜剝離層； 108〜載材。
0503-A35003TWF/jeff

Claims (1)

  1. 201104732 七、申請專利範圍： I一種薄晶圓處理結構，包括： 一半導體晶圓； 一剝離層（release layer)，其可由施加能量 剝 離； 一黏著層，其可由溶劑予以移除；以及 一载材； 其中該剝離層以塗佈或壓纟方式至少其一施加至該 載材’該黏著層係以塗佈或壓合方式至少其—施加至該 半導體晶圓’該半導體㈣及該載材相互接合，且該剝 離層及該黏著層位於該半導體晶圓及該載材之間。 2·如中請專利範圍第】項所述之薄晶圓處理結構，其 ，在以塗佈或壓合至少其—施加該剝離層至該載材上之 後，對該剝離層進行晶圓邊緣殘除物移除(ebr)。 3. 如中請專利範圍第2項所述之薄晶圓處理結構，复 中該晶圓邊緣殘除物移除（EBR)製程移除該剝離層相對 於該載材之外緣的0.1 mm至3 mm。 4. 如切專利範㈣丨項所述之以圓處理結構，龙 中該剝離層由UV光或雷射光至少其一予以剝離。、 5·如巾請專利範㈣i項所述之薄晶圓處理結構，发 中该黏著層為熱塑性聚合物__丨ρ1_ pQiymer)。、 6 ·種薄晶圓接合及剝離之方法，包括： 、塗佈或壓合至少其—施加—I彳離層於—載材上； U佈或屢合至少其—施加—黏著層至—半導體曰 0503.A35003TWF/jeff 10 201104732 材及該半導體晶圓，且該剝離層及該黏著 曰位於該载材及該半導體晶圓之間，· 轭予犯里至該剝離層，以剝離該载材；以及 以一溶劑清潔該半導體晶圓之 著層之所有殘餘物。 移除該黏 之方利範圍第6項所述之薄晶圓接合及剝離 8W該剝離層係由施予uv光或雷射光而剝離。 之方法甘t專利範圍第6項所述之薄晶圓接合及剝離 3法’ Μ料層材由㈣絲學㈣之熱塑性聚 之方專利範㈣6項所述之薄晶_合及剝離 剝離層至剝離層在以塗佈或壓合至少其-施加該 物移除(ΕΒ&/上之後，對該剝離層進行晶圓邊緣殘除 之方L°.二=利範圍第9項所述之薄晶圓接合及剝離 相對於邊緣殘除物移除(舰)製程移除該剝離層 ^胃㈣之外緣的G.l mm至3 mm。 〇503-A350〇3TWF/jeff
TW099121418A 2009-06-30 2010-06-30 薄晶圓處理結構及薄晶圓接合及剝離之方法 TWI485756B (zh)

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