201103384 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種蝕刻薄膜電阻電路板製作方法，尤指一種可 以形成正確的電阻尺寸之製法。 【先前技術】 月參閱第一圖為文獻薄膜嵌入式電阻(Thin Film Embedded 會ReS1St〇rs) ’作者為王建濤與席迪可勞斯(jiangtao Wang and Sid C1_r) ’為美國古爾德電子公司(GouldElectronicsIncOJS)所記載 之種姓刻薄膜電阻製作流程示意圖。如第三A至第三〇騎 不先域-有-電阻材料8及一金屬層c之基板A，再於該金 屬曰C上形成預疋形狀之第一光阻D，此第一光阻〇寬度^為 電阻的預定寬度，再以钱刻去除該第一光阻D涵蓋範圍以外之金 屬層C及電阻材料B，去除第一光阻D。於金屬層c上形成一具 •有-開窗E1之第二光阻E，該開窗m長度L為電阻的預定長度， =刻去除開窗E1以下所對應姻之金屬層c，以露出對應於開 屬E1位置之電阻材料B，去除第二光阻e，便形成具有電阻ρ之 電路板G。 製程中，當侧第-光阻D所涵蓋範圍以外之金屬層C及電 阻材料B時’由於絲刻相堆疊的金屬狀電阻材料，钮刻厚度 較厚’常造成下層的電阻材料_不盡，在電阻材料邊界盘基: 的接觸地方便產生殘足㈣問題，後續需多加一道糊製程，方 .201103384 能將該殘足盡力去除。 此外，請參閱第三E圖，由第二光阻俯視，底下金屬層的寬 度是介於開錢中央，金屬層時，除了將對應於開窗位 置的金屬層侧掉，爛液還會滲透至金制c鮮二光阻£及 電阻材料B之間關隙’造成被侧後的金屬層c其㈣位置的 各角落被侧成圓弧狀。以上兩種問題，會造成不易控制成型出 正確的電阻尺寸的缺點。 因此如何在進行侧薄膜電阻製作流程中，避免殘足問題以 及避免金屬層祕形雜，而制正麵電阻尺寸，實已成 爲目前業界亟待克服之課題。 【發明内容】 ，馨於習知技術的種種缺失’本發明主要目的在於提供—種钱刻 =膜電阻電路板製作方法’以解料知在進行㈣雜電阻製作 〜程中，所遇到的電阻殘足問題。 、為達上述目的’本發明提供一種餘刻薄膜電阻電路板製作方 法’係包括下列步驟： (1) 提供一堆疊有一金屬層及一電阻材料之基板； (2) 於該金屬層上形成-第—取圖樣之第一光阻； (3) 實行第一道餘刻，以圖樣化該今麗 水冗》金屬層，使電阻材料對應一 第一寬度露出； 〜 (4) 移除第一光阻； 201103384 ⑸形成-第二預定圖樣之第二光阻； ⑷實订第一道蝕刻’以圖樣化金屬層及電阻材料 道侧所露出之第—寬度電阻材料移除至第二寬度因第一 ⑺移除第二光阻；以形成具有電阻之電路板。 本案之製作方法她於習知的製程，由於第—道糊厚度未 匕3電阻層厚度，H知技術—開始將金屬層及電崎料一^ 刻的厚度還要薄，使得本_製作方法絲_職阻電路 板上未被金屬層覆蓋的電阻層邊緣持發生_不⑼ 材料殘足的問題。 此外’在本發明的較佳實施例下，實行第一道賴時，雖缺 钱刻液也會滲透至金屬層鮮—光阻及電阻材料之_間隙，造 成被侧後的金屬層各肖落被侧賴弧狀，但*於後續的第二 光阻是遮蔽在第-寬度電阻材料的中_分，因此第二道姓刻 時，餘刻液會沿著第二光阻之平整邊界，移除金屬層及電阻材 料’使第-寬度電阻材料在此卩皆段被移除至第二寬度，意即移除 了各圓弧狀角落，而得到具有完整邊界的電阻。 【實施方式】 以下配合圖式及元件符號對本發明之實施方式做更詳細的說 明’俾使熟習該項技藝者在研讀本說明書後能據以實施。 請參閱第一圖顯示本發明蝕刻薄膜電阻電路板製程100之具 體實施例說明流程圖。第二A至第二G圖，係顯示第一圖中各說 201103384 明流程之狀態圖。如步驟110及第二A圖所示，首先提供一基板 1 ;該基板1可為雙面皆可施作之雙面板，或_雙面板為核^並 在外部堆疊有介電層、線路、導電層等結構之多層板；本發明實 施例是在基板1的至少一面堆疊一電阻材料2以及一金屬層3。其 中該電阻材料2可為鎳鉻(NiCr)、錄鉻链石夕⑽以⑸）、錄^201103384 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating an etched thin film resistor circuit board, and more particularly to a method of forming a correct resistor size. [Prior Art] The first picture of the month is the literature film embedded resistor (Thin Film Embedded will ReS1St〇rs) 'The author is Jiangtao Wang and Sid C1_r' is the American Gould Electronics Company (GouldElectronicsIncOJS) The schematic diagram of the production process of the caste resistance recorded by Gould Electrics IncOJS. For example, the third A to the third cymbal do not have the first domain-there is a resistive material 8 and a substrate A of the metal layer c, and then the first photoresist D is formed on the metal 曰C in a pre-疋 shape, the first photoresist The width ^ is the predetermined width of the resistor, and the metal layer C and the resistive material B outside the range covered by the first photoresist D are removed by the money to remove the first photoresist D. Forming a second photoresist E having a window opening E1 on the metal layer c, the length l of the window opening m is a predetermined length of the resistor, and removing the metal layer c corresponding to the opening of the window E1 to expose Corresponding to the resistive material B at the E1 position, the second photoresist e is removed to form a circuit board G having a resistance ρ. In the process, when the metal layer C and the resistive material B outside the range covered by the side-light-resistance D are 'the metal-like resistive material stacked by the wire-cut phase, the thickness of the button is thicker' often causes the lower-layer resistive material to be inexhaustible. In the boundary of the resistive material: the contact area is convenient to produce the residual foot (four) problem, and the subsequent need to add a paste process, square. 201103384 can remove the residual force as much as possible. In addition, please refer to the third E diagram. From the second photoresist, the width of the bottom metal layer is in the middle of the money. When the metal layer is removed, the rotting liquid will penetrate in addition to the side of the metal layer corresponding to the window opening position. To the gap between the gold and the light resistive material and the resistive material B, the corners of the (4) position of the metal layer c behind the side are arcuate. Both of the above problems cause the difficulty of controlling the correct size of the resistor. Therefore, in the process of fabricating the side film resistors, avoiding the problem of residual feet and avoiding the secrets of the metal layer, and the size of the front side resistors has become an urgent problem to be overcome in the industry. [Summary of the Invention], the various defects of the prior art of the present invention, the main purpose of the present invention is to provide a method for the production of a film resistor circuit board, which is known to be carried out in the process of (four) hybrid resistance production. Resistance problem. For the above purpose, the present invention provides a method for fabricating a thin film resistor circuit board, which comprises the following steps: (1) providing a substrate on which a metal layer and a resistive material are stacked; (2) forming on the metal layer - First—take the first photoresist of the pattern; (3) implement the first remnant to pattern the metal layer of the current Lishui, so that the resistive material is exposed corresponding to a first width; ~ (4) remove the first light Resistor; 201103384 (5) forming a second photoresist of the second predetermined pattern; (4) realizing the first etching 'to remove the first-width resistance material exposed by the patterned metal layer and the resistive material side to the second width One (7) removes the second photoresist; to form a circuit board having a resistance. The production method of this case is in the well-known process, because the thickness of the first paste is not 3 thickness of the resistive layer, H knows the technology - the thickness of the metal layer and the electric material is started to be thin, so that the method The edge of the resistance layer that is not covered by the metal layer on the wire _ occupational resistance circuit board occurs _ no (9) the problem of material residue. In addition, in the preferred embodiment of the present invention, when the first pass is implemented, although the lack of money engraving liquid will also penetrate into the gap between the metal layer fresh-resistance and the resistive material, causing the metal layer behind the side to be etched. The falling edge is curved, but the subsequent second photoresist is shielded in the middle of the first-width resistive material. Therefore, when the second pass is engraved, the residual liquid will follow the flat boundary of the second photoresist. The metal layer and the resistive material are removed, so that the first-width resistive material is removed to the second width in this section, that is, the arc-shaped corners are removed, and a resistor having a complete boundary is obtained. [Embodiment] The embodiments of the present invention will be described in more detail below with reference to the drawings and the reference numerals. Referring to the first figure, a flow chart illustrating a specific embodiment of an etched thin film resistor circuit board process 100 of the present invention is shown. The second A to the second G maps show the state diagrams of the respective processes of the 201103384 in the first figure. As shown in step 110 and FIG. 2A, a substrate 1 is first provided; the substrate 1 can be a double panel that can be applied on both sides, or a double panel is a core and a dielectric layer, a line, and a stack are externally stacked. A multilayer board having a structure such as a conductive layer; in the embodiment of the present invention, a resistive material 2 and a metal layer 3 are stacked on at least one side of the substrate 1. The resistive material 2 can be nickel-chromium (NiCr), recorded in the chrome chain (10) to (5)), recorded ^
或鉻石夕氧(CrSiO)、.·等合金電阻；該金屬層可為銅、錄或金、.. 等金屬。接續如步驟120及第二8圖所示，於該金屬層3上以微 鲁影技術(包含光阻劑塗佈、預烤、曝光、顯影、硬烤，由於微影技 術為習知技術，容不詳細說明)形成一第一預定圖樣之第一光阻 4，此第一預定圖樣定義了最後所形成之電阻的長度。接續如步 驟130及第二C圖所示’實行第一道蝕刻，以圖樣化該金屬層3 , 使電阻材料2對應一第一寬度霤丨露出，其中第一寬度貨〗大於 最後所形成的電阻的寬度。本發明不對蝕刻方式加以限定，可以 為濕蝕刻或乾蝕刻。接續如步驟14〇及第二D圖所示，移除第 _ 一光阻；可利用曝光、顯影或化學剝離的方式移除第一光阻。接 續如步驟150及第二E圖所示，於部分的金屬層3與部份的電阻 材料2上施以微影製程，形成一第二預定圖樣之第二光阻5，此 第二預定圖樣定義了最後所形成的電阻的寬度，第二光阻5遮蔽 在第一寬度電阻材料的中心部分。接續如步驟及第二F圖所 示，實行第二道触刻，以圖樣化金屬層3及電阻材料2，使因第 道餘刻所露出之第一寬度電阻材料移除至第二寬度W2，其中 第二寬度W2即為電阻的最後寬度。接續如步驟17〇及第二G 201103384 圖所示’可利用曝光、顯影或化學剝離的方式移除第二光阻，便 形成具有電阻6之電路板7。 本實施例之製作方法，由於第一道钱刻厚度僅包含金屬層厚 度，並未同時钱刻電阻材料，蝕刻厚度較薄，不易發生蝕刻不盡 而產生電阻材料殘足的問題。 此外，本實施例在第一道蝕刻時，雖然蝕刻液也會滲透至金 屬層與第-光阻及電阻材料之間的間隙’造成輸刻後的金屬層 各角落被蝕刻成圓弧狀，但由於後續的第二光阻是遮蔽在第一寬 度電阻材料的中間部位’因此第二道_時，侧液會沿著第二 光阻之平整邊界’移除金屬層及電阻材料，使第一寬度電阻材料 在此階段被移除至第二寬度，意即移除了各圓弧狀角落，而得到 具有完整邊界的電阻，故本實施例之製作方法可以㈣成型出正 確的電阻尺寸，即絲被金顧覆朗電阻層尺寸。 以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據 以對本發明做任何形式上之限制，是以，凡有在相同之發明精神 下所作有關本發明之任何修都或變更，皆仍應包括在本發明意圖 保護之範。 201103384 【圖式簡單說明】 第一圖為本發明蝕刻薄膜電阻電路板製程之具體實施例說明流程 圖。 第一 A至第二g圖，係顯示第一圖中各說明流程之狀態圖。 第二A至第三g圖，為習知一種蝕刻薄膜電阻製作流程示意圖。 【主要元件符號說明】 • 1·基板 2. 電阻材料 3. 金屬層 4. 第一光阻 5. 第二光阻 6. 電阻 7. 電路板 • ι〇0.蝕刻薄膜電阻製程 110.提供一堆疊有金屬層及電阻材料之基板 120.形成—第一預定圖樣之第一光阻 130.實行第一道蝕刻 140,移除第一光阻 150.形成一第二預定圖樣之第二光阻 160.實行第二道蝕刻 170.移除第二光阻 201103384 A. 基板 B. 電阻材料 C. 金屬層 D. 第一光阻 E. 第二光阻 E1.開窗 F. 電阻 φ G.電路板 L.開窗長度 W.第一光阻寬度 W1.第一寬度 W2.第二寬度Or alloy resistance such as chrome oxide (CrSiO), etc.; the metal layer may be copper, gold or gold, or the like. The lithography is as shown in steps 120 and 2, and the micro-picture technology (including photoresist coating, pre-baking, exposure, development, and hard baking) is applied to the metal layer 3, and the lithography technology is a conventional technique. The first photoresist pattern 4 of a first predetermined pattern is formed, which defines the length of the last formed resistor. Subsequently, as shown in step 130 and FIG. 2C, the first etching is performed to pattern the metal layer 3, so that the resistive material 2 is exposed corresponding to a first width, wherein the first width is larger than the last formed. The width of the resistor. The etching mode is not limited in the present invention, and may be wet etching or dry etching. Subsequently, as shown in steps 14A and 2D, the first photoresist is removed; the first photoresist can be removed by exposure, development or chemical peeling. The lithography process is performed on the portion of the metal layer 3 and the portion of the resistive material 2 to form a second predetermined pattern of the second photoresist 5, the second predetermined pattern. The width of the last formed resistor is defined, and the second photoresist 5 is shielded at the central portion of the first width resistive material. Following the steps and the second F diagram, a second touch is performed to pattern the metal layer 3 and the resistive material 2 to remove the first width resistive material exposed by the first pass to the second width W2. Where the second width W2 is the last width of the resistor. Following the removal of the second photoresist by exposure, development or chemical stripping as shown in steps 17 and 2G 201103384, a circuit board 7 having a resistor 6 is formed. In the manufacturing method of the embodiment, since the thickness of the first pass includes only the thickness of the metal layer, the resistive material is not engraved at the same time, the etching thickness is thin, and the problem that the etching material is not enough to cause the residual of the resistive material is less likely to occur. In addition, in the first etching of the embodiment, although the etching liquid penetrates into the gap between the metal layer and the first photoresist and the resistive material, the corners of the inscribed metal layer are etched into an arc shape. However, since the subsequent second photoresist is shielded in the middle portion of the first width resistive material, the second layer _, the side liquid will remove the metal layer and the resistive material along the flat boundary of the second photoresist. A width resistive material is removed to the second width at this stage, that is, the arcuate corners are removed, and a resistor having a complete boundary is obtained, so that the manufacturing method of the embodiment can (4) form the correct resistance size. That is, the wire is covered with gold to measure the size of the resistance layer. The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, so that any modifications relating to the present invention may be made in the spirit of the same invention. Changes are still to be included in the intended protection of the present invention. 201103384 [Simple description of the drawings] The first figure is a flow chart showing a specific embodiment of the process for etching a thin film resistor circuit board of the present invention. The first to second g diagrams show the state diagrams of the various illustrated flows in the first figure. The second A to third g diagrams are schematic diagrams of a conventional etching film resistance manufacturing process. [Main component symbol description] • 1·substrate 2. Resistive material 3. Metal layer 4. First photoresist 5. Second photoresist 6. Resistor 7. Circuit board • ι〇0. Etched film resistor process 110. Provide one a substrate 120 having a metal layer and a resistive material stacked. Forming a first photoresist pattern of a first predetermined pattern 130. Performing a first etching 140, removing the first photoresist 150. Forming a second photoresist of a second predetermined pattern 160. Perform a second etching 170. Remove the second photoresist 201103384 A. Substrate B. Resistive material C. Metal layer D. First photoresist E. Second photoresist E1. Open window F. Resistance φ G. Plate L. window length W. first photoresist width W1. first width W2. second width